1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/systm.h> 28 #include <sys/archsystm.h> 29 #include <sys/t_lock.h> 30 #include <sys/uadmin.h> 31 #include <sys/panic.h> 32 #include <sys/reboot.h> 33 #include <sys/autoconf.h> 34 #include <sys/machsystm.h> 35 #include <sys/promif.h> 36 #include <sys/membar.h> 37 #include <vm/hat_sfmmu.h> 38 #include <sys/cpu_module.h> 39 #include <sys/cpu_sgnblk_defs.h> 40 #include <sys/intreg.h> 41 #include <sys/consdev.h> 42 #include <sys/kdi_impl.h> 43 #include <sys/traptrace.h> 44 #include <sys/hypervisor_api.h> 45 #include <sys/vmsystm.h> 46 #include <sys/dtrace.h> 47 #include <sys/xc_impl.h> 48 #include <sys/callb.h> 49 #include <sys/mdesc.h> 50 #include <sys/mach_descrip.h> 51 #include <sys/wdt.h> 52 #include <sys/soft_state.h> 53 #include <sys/promimpl.h> 54 #include <sys/hsvc.h> 55 #include <sys/ldoms.h> 56 #include <sys/kldc.h> 57 #include <sys/clock_impl.h> 58 #include <sys/suspend.h> 59 #include <sys/dumphdr.h> 60 61 /* 62 * hvdump_buf_va is a pointer to the currently-configured hvdump_buf. 63 * A value of NULL indicates that this area is not configured. 64 * hvdump_buf_sz is tunable but will be clamped to HVDUMP_SIZE_MAX. 65 */ 66 67 caddr_t hvdump_buf_va; 68 uint64_t hvdump_buf_sz = HVDUMP_SIZE_DEFAULT; 69 static uint64_t hvdump_buf_pa; 70 71 u_longlong_t panic_tick; 72 73 extern u_longlong_t gettick(); 74 static void reboot_machine(char *); 75 static void update_hvdump_buffer(void); 76 77 /* 78 * For xt_sync synchronization. 79 */ 80 extern uint64_t xc_tick_limit; 81 extern uint64_t xc_tick_jump_limit; 82 extern uint64_t xc_sync_tick_limit; 83 84 /* 85 * We keep our own copies, used for cache flushing, because we can be called 86 * before cpu_fiximpl(). 87 */ 88 static int kdi_dcache_size; 89 static int kdi_dcache_linesize; 90 static int kdi_icache_size; 91 static int kdi_icache_linesize; 92 93 /* 94 * Assembly support for generic modules in sun4v/ml/mach_xc.s 95 */ 96 extern void init_mondo_nocheck(xcfunc_t *func, uint64_t arg1, uint64_t arg2); 97 extern void kdi_flush_idcache(int, int, int, int); 98 extern uint64_t get_cpuaddr(uint64_t, uint64_t); 99 100 101 #define BOOT_CMD_MAX_LEN 256 102 #define BOOT_CMD_BASE "boot " 103 104 /* 105 * In an LDoms system we do not save the user's boot args in NVRAM 106 * as is done on legacy systems. Instead, we format and send a 107 * 'reboot-command' variable to the variable service. The contents 108 * of the variable are retrieved by OBP and used verbatim for 109 * the next boot. 110 */ 111 static void 112 store_boot_cmd(char *args, boolean_t add_boot_str, boolean_t invoke_cb) 113 { 114 static char cmd_buf[BOOT_CMD_MAX_LEN]; 115 size_t len = 1; 116 pnode_t node; 117 size_t base_len = 0; 118 size_t args_len; 119 size_t args_max; 120 uint64_t majornum; 121 uint64_t minornum; 122 uint64_t buf_pa; 123 uint64_t status; 124 125 status = hsvc_version(HSVC_GROUP_REBOOT_DATA, &majornum, &minornum); 126 127 /* 128 * invoke_cb is set to true when we are in a normal shutdown sequence 129 * (interrupts are not blocked, the system is not panicking or being 130 * suspended). In that case, we can use any method to store the boot 131 * command. Otherwise storing the boot command can not be done using 132 * a domain service because it can not be safely used in that context. 133 */ 134 if ((status != H_EOK) && (invoke_cb == B_FALSE)) 135 return; 136 137 if (add_boot_str) { 138 (void) strcpy(cmd_buf, BOOT_CMD_BASE); 139 140 base_len = strlen(BOOT_CMD_BASE); 141 len = base_len + 1; 142 } 143 144 if (args != NULL) { 145 args_len = strlen(args); 146 args_max = BOOT_CMD_MAX_LEN - len; 147 148 if (args_len > args_max) { 149 cmn_err(CE_WARN, "Reboot command too long (%ld), " 150 "truncating command arguments", len + args_len); 151 152 args_len = args_max; 153 } 154 155 len += args_len; 156 (void) strncpy(&cmd_buf[base_len], args, args_len); 157 } 158 159 /* 160 * Save the reboot-command with HV, if reboot data group is 161 * negotiated. Else save the reboot-command via vars-config domain 162 * services on the SP. 163 */ 164 if (status == H_EOK) { 165 buf_pa = va_to_pa(cmd_buf); 166 status = hv_reboot_data_set(buf_pa, len); 167 if (status != H_EOK) { 168 cmn_err(CE_WARN, "Unable to store boot command for " 169 "use on reboot with HV: error = 0x%lx", status); 170 } 171 } else { 172 node = prom_optionsnode(); 173 if ((node == OBP_NONODE) || (node == OBP_BADNODE) || 174 prom_setprop(node, "reboot-command", cmd_buf, len) == -1) 175 cmn_err(CE_WARN, "Unable to store boot command for " 176 "use on reboot"); 177 } 178 } 179 180 181 /* 182 * Machine dependent code to reboot. 183 * 184 * "bootstr", when non-null, points to a string to be used as the 185 * argument string when rebooting. 186 * 187 * "invoke_cb" is a boolean. It is set to true when mdboot() can safely 188 * invoke CB_CL_MDBOOT callbacks before shutting the system down, i.e. when 189 * we are in a normal shutdown sequence (interrupts are not blocked, the 190 * system is not panic'ing or being suspended). 191 */ 192 /*ARGSUSED*/ 193 void 194 mdboot(int cmd, int fcn, char *bootstr, boolean_t invoke_cb) 195 { 196 extern void pm_cfb_check_and_powerup(void); 197 198 /* 199 * XXX - rconsvp is set to NULL to ensure that output messages 200 * are sent to the underlying "hardware" device using the 201 * monitor's printf routine since we are in the process of 202 * either rebooting or halting the machine. 203 */ 204 rconsvp = NULL; 205 206 switch (fcn) { 207 case AD_HALT: 208 /* 209 * LDoms: By storing a no-op command 210 * in the 'reboot-command' variable we cause OBP 211 * to ignore the setting of 'auto-boot?' after 212 * it completes the reset. This causes the system 213 * to stop at the ok prompt. 214 */ 215 if (domaining_enabled()) 216 store_boot_cmd("noop", B_FALSE, invoke_cb); 217 break; 218 219 case AD_POWEROFF: 220 break; 221 222 default: 223 if (bootstr == NULL) { 224 switch (fcn) { 225 226 case AD_FASTREBOOT: 227 case AD_BOOT: 228 bootstr = ""; 229 break; 230 231 case AD_IBOOT: 232 bootstr = "-a"; 233 break; 234 235 case AD_SBOOT: 236 bootstr = "-s"; 237 break; 238 239 case AD_SIBOOT: 240 bootstr = "-sa"; 241 break; 242 default: 243 cmn_err(CE_WARN, 244 "mdboot: invalid function %d", fcn); 245 bootstr = ""; 246 break; 247 } 248 } 249 250 /* 251 * If LDoms is running, we must save the boot string 252 * before we enter restricted mode. This is possible 253 * only if we are not being called from panic. 254 */ 255 if (domaining_enabled()) 256 store_boot_cmd(bootstr, B_TRUE, invoke_cb); 257 } 258 259 /* 260 * At a high interrupt level we can't: 261 * 1) bring up the console 262 * or 263 * 2) wait for pending interrupts prior to redistribution 264 * to the current CPU 265 * 266 * so we do them now. 267 */ 268 pm_cfb_check_and_powerup(); 269 270 /* make sure there are no more changes to the device tree */ 271 devtree_freeze(); 272 273 if (invoke_cb) 274 (void) callb_execute_class(CB_CL_MDBOOT, NULL); 275 276 /* 277 * Clear any unresolved UEs from memory. 278 */ 279 page_retire_mdboot(); 280 281 /* 282 * stop other cpus which also raise our priority. since there is only 283 * one active cpu after this, and our priority will be too high 284 * for us to be preempted, we're essentially single threaded 285 * from here on out. 286 */ 287 stop_other_cpus(); 288 289 /* 290 * try and reset leaf devices. reset_leaves() should only 291 * be called when there are no other threads that could be 292 * accessing devices 293 */ 294 reset_leaves(); 295 296 watchdog_clear(); 297 298 if (fcn == AD_HALT) { 299 mach_set_soft_state(SIS_TRANSITION, 300 &SOLARIS_SOFT_STATE_HALT_MSG); 301 halt((char *)NULL); 302 } else if (fcn == AD_POWEROFF) { 303 mach_set_soft_state(SIS_TRANSITION, 304 &SOLARIS_SOFT_STATE_POWER_MSG); 305 power_down(NULL); 306 } else { 307 mach_set_soft_state(SIS_TRANSITION, 308 &SOLARIS_SOFT_STATE_REBOOT_MSG); 309 reboot_machine(bootstr); 310 } 311 /* MAYBE REACHED */ 312 } 313 314 /* mdpreboot - may be called prior to mdboot while root fs still mounted */ 315 /*ARGSUSED*/ 316 void 317 mdpreboot(int cmd, int fcn, char *bootstr) 318 { 319 } 320 321 /* 322 * Halt the machine and then reboot with the device 323 * and arguments specified in bootstr. 324 */ 325 static void 326 reboot_machine(char *bootstr) 327 { 328 flush_windows(); 329 stop_other_cpus(); /* send stop signal to other CPUs */ 330 prom_printf("rebooting...\n"); 331 /* 332 * For platforms that use CPU signatures, we 333 * need to set the signature block to OS and 334 * the state to exiting for all the processors. 335 */ 336 CPU_SIGNATURE(OS_SIG, SIGST_EXIT, SIGSUBST_REBOOT, -1); 337 prom_reboot(bootstr); 338 /*NOTREACHED*/ 339 } 340 341 /* 342 * We use the x-trap mechanism and idle_stop_xcall() to stop the other CPUs. 343 * Once in panic_idle() they raise spl, record their location, and spin. 344 */ 345 static void 346 panic_idle(void) 347 { 348 (void) spl7(); 349 350 debug_flush_windows(); 351 (void) setjmp(&curthread->t_pcb); 352 353 CPU->cpu_m.in_prom = 1; 354 membar_stld(); 355 356 dumpsys_helper(); 357 358 for (;;) 359 ; 360 } 361 362 /* 363 * Force the other CPUs to trap into panic_idle(), and then remove them 364 * from the cpu_ready_set so they will no longer receive cross-calls. 365 */ 366 /*ARGSUSED*/ 367 void 368 panic_stopcpus(cpu_t *cp, kthread_t *t, int spl) 369 { 370 cpuset_t cps; 371 int i; 372 373 (void) splzs(); 374 CPUSET_ALL_BUT(cps, cp->cpu_id); 375 xt_some(cps, (xcfunc_t *)idle_stop_xcall, (uint64_t)&panic_idle, NULL); 376 377 for (i = 0; i < NCPU; i++) { 378 if (i != cp->cpu_id && CPU_XCALL_READY(i)) { 379 int ntries = 0x10000; 380 381 while (!cpu[i]->cpu_m.in_prom && ntries) { 382 DELAY(50); 383 ntries--; 384 } 385 386 if (!cpu[i]->cpu_m.in_prom) 387 printf("panic: failed to stop cpu%d\n", i); 388 389 cpu[i]->cpu_flags &= ~CPU_READY; 390 cpu[i]->cpu_flags |= CPU_QUIESCED; 391 CPUSET_DEL(cpu_ready_set, cpu[i]->cpu_id); 392 } 393 } 394 } 395 396 /* 397 * Platform callback following each entry to panicsys(). If we've panicked at 398 * level 14, we examine t_panic_trap to see if a fatal trap occurred. If so, 399 * we disable further %tick_cmpr interrupts. If not, an explicit call to panic 400 * was made and so we re-enqueue an interrupt request structure to allow 401 * further level 14 interrupts to be processed once we lower PIL. This allows 402 * us to handle panics from the deadman() CY_HIGH_LEVEL cyclic. 403 */ 404 void 405 panic_enter_hw(int spl) 406 { 407 if (!panic_tick) { 408 panic_tick = gettick(); 409 if (mach_htraptrace_enable) { 410 uint64_t prev_freeze; 411 412 /* there are no possible error codes for this hcall */ 413 (void) hv_ttrace_freeze((uint64_t)TRAP_TFREEZE_ALL, 414 &prev_freeze); 415 } 416 #ifdef TRAPTRACE 417 TRAPTRACE_FREEZE; 418 #endif 419 } 420 421 mach_set_soft_state(SIS_TRANSITION, &SOLARIS_SOFT_STATE_PANIC_MSG); 422 423 if (spl == ipltospl(PIL_14)) { 424 uint_t opstate = disable_vec_intr(); 425 426 if (curthread->t_panic_trap != NULL) { 427 tickcmpr_disable(); 428 intr_dequeue_req(PIL_14, cbe_level14_inum); 429 } else { 430 if (!tickcmpr_disabled()) 431 intr_enqueue_req(PIL_14, cbe_level14_inum); 432 /* 433 * Clear SOFTINT<14>, SOFTINT<0> (TICK_INT) 434 * and SOFTINT<16> (STICK_INT) to indicate 435 * that the current level 14 has been serviced. 436 */ 437 wr_clr_softint((1 << PIL_14) | 438 TICK_INT_MASK | STICK_INT_MASK); 439 } 440 441 enable_vec_intr(opstate); 442 } 443 } 444 445 /* 446 * Miscellaneous hardware-specific code to execute after panicstr is set 447 * by the panic code: we also print and record PTL1 panic information here. 448 */ 449 /*ARGSUSED*/ 450 void 451 panic_quiesce_hw(panic_data_t *pdp) 452 { 453 extern uint_t getpstate(void); 454 extern void setpstate(uint_t); 455 456 /* 457 * Turn off TRAPTRACE and save the current %tick value in panic_tick. 458 */ 459 if (!panic_tick) { 460 panic_tick = gettick(); 461 if (mach_htraptrace_enable) { 462 uint64_t prev_freeze; 463 464 /* there are no possible error codes for this hcall */ 465 (void) hv_ttrace_freeze((uint64_t)TRAP_TFREEZE_ALL, 466 &prev_freeze); 467 } 468 #ifdef TRAPTRACE 469 TRAPTRACE_FREEZE; 470 #endif 471 } 472 /* 473 * For Platforms that use CPU signatures, we 474 * need to set the signature block to OS, the state to 475 * exiting, and the substate to panic for all the processors. 476 */ 477 CPU_SIGNATURE(OS_SIG, SIGST_EXIT, SIGSUBST_PANIC, -1); 478 479 update_hvdump_buffer(); 480 481 /* 482 * Disable further ECC errors from the bus nexus. 483 */ 484 (void) bus_func_invoke(BF_TYPE_ERRDIS); 485 486 /* 487 * Redirect all interrupts to the current CPU. 488 */ 489 intr_redist_all_cpus_shutdown(); 490 491 /* 492 * This call exists solely to support dumps to network 493 * devices after sync from OBP. 494 * 495 * If we came here via the sync callback, then on some 496 * platforms, interrupts may have arrived while we were 497 * stopped in OBP. OBP will arrange for those interrupts to 498 * be redelivered if you say "go", but not if you invoke a 499 * client callback like 'sync'. For some dump devices 500 * (network swap devices), we need interrupts to be 501 * delivered in order to dump, so we have to call the bus 502 * nexus driver to reset the interrupt state machines. 503 */ 504 (void) bus_func_invoke(BF_TYPE_RESINTR); 505 506 setpstate(getpstate() | PSTATE_IE); 507 } 508 509 /* 510 * Platforms that use CPU signatures need to set the signature block to OS and 511 * the state to exiting for all CPUs. PANIC_CONT indicates that we're about to 512 * write the crash dump, which tells the SSP/SMS to begin a timeout routine to 513 * reboot the machine if the dump never completes. 514 */ 515 /*ARGSUSED*/ 516 void 517 panic_dump_hw(int spl) 518 { 519 CPU_SIGNATURE(OS_SIG, SIGST_EXIT, SIGSUBST_DUMP, -1); 520 } 521 522 /* 523 * for ptl1_panic 524 */ 525 void 526 ptl1_init_cpu(struct cpu *cpu) 527 { 528 ptl1_state_t *pstate = &cpu->cpu_m.ptl1_state; 529 530 /*CONSTCOND*/ 531 if (sizeof (struct cpu) + PTL1_SSIZE > CPU_ALLOC_SIZE) { 532 panic("ptl1_init_cpu: not enough space left for ptl1_panic " 533 "stack, sizeof (struct cpu) = %lu", 534 (unsigned long)sizeof (struct cpu)); 535 } 536 537 pstate->ptl1_stktop = (uintptr_t)cpu + CPU_ALLOC_SIZE; 538 cpu_pa[cpu->cpu_id] = va_to_pa(cpu); 539 } 540 541 void 542 ptl1_panic_handler(ptl1_state_t *pstate) 543 { 544 static const char *ptl1_reasons[] = { 545 #ifdef PTL1_PANIC_DEBUG 546 "trap for debug purpose", /* PTL1_BAD_DEBUG */ 547 #else 548 "unknown trap", /* PTL1_BAD_DEBUG */ 549 #endif 550 "register window trap", /* PTL1_BAD_WTRAP */ 551 "kernel MMU miss", /* PTL1_BAD_KMISS */ 552 "kernel protection fault", /* PTL1_BAD_KPROT_FAULT */ 553 "ISM MMU miss", /* PTL1_BAD_ISM */ 554 "kernel MMU trap", /* PTL1_BAD_MMUTRAP */ 555 "kernel trap handler state", /* PTL1_BAD_TRAP */ 556 "floating point trap", /* PTL1_BAD_FPTRAP */ 557 #ifdef DEBUG 558 "pointer to intr_vec", /* PTL1_BAD_INTR_VEC */ 559 #else 560 "unknown trap", /* PTL1_BAD_INTR_VEC */ 561 #endif 562 #ifdef TRAPTRACE 563 "TRACE_PTR state", /* PTL1_BAD_TRACE_PTR */ 564 #else 565 "unknown trap", /* PTL1_BAD_TRACE_PTR */ 566 #endif 567 "stack overflow", /* PTL1_BAD_STACK */ 568 "DTrace flags", /* PTL1_BAD_DTRACE_FLAGS */ 569 "attempt to steal locked ctx", /* PTL1_BAD_CTX_STEAL */ 570 "CPU ECC error loop", /* PTL1_BAD_ECC */ 571 "unexpected error from hypervisor call", /* PTL1_BAD_HCALL */ 572 "unexpected global level(%gl)", /* PTL1_BAD_GL */ 573 "Watchdog Reset", /* PTL1_BAD_WATCHDOG */ 574 "unexpected RED mode trap", /* PTL1_BAD_RED */ 575 "return value EINVAL from hcall: "\ 576 "UNMAP_PERM_ADDR", /* PTL1_BAD_HCALL_UNMAP_PERM_EINVAL */ 577 "return value ENOMAP from hcall: "\ 578 "UNMAP_PERM_ADDR", /* PTL1_BAD_HCALL_UNMAP_PERM_ENOMAP */ 579 "error raising a TSB exception", /* PTL1_BAD_RAISE_TSBEXCP */ 580 "missing shared TSB" /* PTL1_NO_SCDTSB8K */ 581 }; 582 583 uint_t reason = pstate->ptl1_regs.ptl1_gregs[0].ptl1_g1; 584 uint_t tl = pstate->ptl1_regs.ptl1_trap_regs[0].ptl1_tl; 585 struct panic_trap_info ti = { 0 }; 586 587 /* 588 * Use trap_info for a place holder to call panic_savetrap() and 589 * panic_showtrap() to save and print out ptl1_panic information. 590 */ 591 if (curthread->t_panic_trap == NULL) 592 curthread->t_panic_trap = &ti; 593 594 if (reason < sizeof (ptl1_reasons) / sizeof (ptl1_reasons[0])) 595 panic("bad %s at TL %u", ptl1_reasons[reason], tl); 596 else 597 panic("ptl1_panic reason 0x%x at TL %u", reason, tl); 598 } 599 600 void 601 clear_watchdog_on_exit(void) 602 { 603 if (watchdog_enabled && watchdog_activated) { 604 prom_printf("Debugging requested; hardware watchdog " 605 "suspended.\n"); 606 (void) watchdog_suspend(); 607 } 608 } 609 610 /* 611 * Restore the watchdog timer when returning from a debugger 612 * after a panic or L1-A and resume watchdog pat. 613 */ 614 void 615 restore_watchdog_on_entry() 616 { 617 watchdog_resume(); 618 } 619 620 int 621 kdi_watchdog_disable(void) 622 { 623 watchdog_suspend(); 624 625 return (0); 626 } 627 628 void 629 kdi_watchdog_restore(void) 630 { 631 watchdog_resume(); 632 } 633 634 void 635 mach_dump_buffer_init(void) 636 { 637 uint64_t ret, minsize = 0; 638 639 if (hvdump_buf_sz > HVDUMP_SIZE_MAX) 640 hvdump_buf_sz = HVDUMP_SIZE_MAX; 641 642 hvdump_buf_va = contig_mem_alloc_align(hvdump_buf_sz, PAGESIZE); 643 if (hvdump_buf_va == NULL) 644 return; 645 646 hvdump_buf_pa = va_to_pa(hvdump_buf_va); 647 648 ret = hv_dump_buf_update(hvdump_buf_pa, hvdump_buf_sz, 649 &minsize); 650 651 if (ret != H_EOK) { 652 contig_mem_free(hvdump_buf_va, hvdump_buf_sz); 653 hvdump_buf_va = NULL; 654 cmn_err(CE_NOTE, "!Error in setting up hvstate" 655 "dump buffer. Error = 0x%lx, size = 0x%lx," 656 "buf_pa = 0x%lx", ret, hvdump_buf_sz, 657 hvdump_buf_pa); 658 659 if (ret == H_EINVAL) { 660 cmn_err(CE_NOTE, "!Buffer size too small." 661 "Available buffer size = 0x%lx," 662 "Minimum buffer size required = 0x%lx", 663 hvdump_buf_sz, minsize); 664 } 665 } 666 } 667 668 669 static void 670 update_hvdump_buffer(void) 671 { 672 uint64_t ret, dummy_val; 673 674 if (hvdump_buf_va == NULL) 675 return; 676 677 ret = hv_dump_buf_update(hvdump_buf_pa, hvdump_buf_sz, 678 &dummy_val); 679 if (ret != H_EOK) { 680 cmn_err(CE_NOTE, "!Cannot update hvstate dump" 681 "buffer. Error = 0x%lx", ret); 682 } 683 } 684 685 686 static int 687 getintprop(pnode_t node, char *name, int deflt) 688 { 689 int value; 690 691 switch (prom_getproplen(node, name)) { 692 case 0: 693 value = 1; /* boolean properties */ 694 break; 695 696 case sizeof (int): 697 (void) prom_getprop(node, name, (caddr_t)&value); 698 break; 699 700 default: 701 value = deflt; 702 break; 703 } 704 705 return (value); 706 } 707 708 /* 709 * Called by setcpudelay 710 */ 711 void 712 cpu_init_tick_freq(void) 713 { 714 md_t *mdp; 715 mde_cookie_t rootnode; 716 int listsz; 717 mde_cookie_t *listp = NULL; 718 int num_nodes; 719 uint64_t stick_prop; 720 721 if (broken_md_flag) { 722 sys_tick_freq = cpunodes[CPU->cpu_id].clock_freq; 723 return; 724 } 725 726 if ((mdp = md_get_handle()) == NULL) 727 panic("stick_frequency property not found in MD"); 728 729 rootnode = md_root_node(mdp); 730 ASSERT(rootnode != MDE_INVAL_ELEM_COOKIE); 731 732 num_nodes = md_node_count(mdp); 733 734 ASSERT(num_nodes > 0); 735 listsz = num_nodes * sizeof (mde_cookie_t); 736 listp = (mde_cookie_t *)prom_alloc((caddr_t)0, listsz, 0); 737 738 if (listp == NULL) 739 panic("cannot allocate list for MD properties"); 740 741 num_nodes = md_scan_dag(mdp, rootnode, md_find_name(mdp, "platform"), 742 md_find_name(mdp, "fwd"), listp); 743 744 ASSERT(num_nodes == 1); 745 746 if (md_get_prop_val(mdp, *listp, "stick-frequency", &stick_prop) != 0) 747 panic("stick_frequency property not found in MD"); 748 749 sys_tick_freq = stick_prop; 750 751 prom_free((caddr_t)listp, listsz); 752 (void) md_fini_handle(mdp); 753 } 754 755 int shipit(int n, uint64_t cpu_list_ra); 756 757 #ifdef DEBUG 758 #define SEND_MONDO_STATS 1 759 #endif 760 761 #ifdef SEND_MONDO_STATS 762 uint32_t x_one_stimes[64]; 763 uint32_t x_one_ltimes[16]; 764 uint32_t x_set_stimes[64]; 765 uint32_t x_set_ltimes[16]; 766 uint32_t x_set_cpus[NCPU]; 767 #endif 768 769 void 770 send_one_mondo(int cpuid) 771 { 772 int retries, stat; 773 uint64_t starttick, endtick, tick, lasttick; 774 struct machcpu *mcpup = &(CPU->cpu_m); 775 776 CPU_STATS_ADDQ(CPU, sys, xcalls, 1); 777 starttick = lasttick = gettick(); 778 mcpup->cpu_list[0] = (uint16_t)cpuid; 779 stat = shipit(1, mcpup->cpu_list_ra); 780 endtick = starttick + xc_tick_limit; 781 retries = 0; 782 while (stat != H_EOK) { 783 if (stat != H_EWOULDBLOCK) { 784 if (panic_quiesce) 785 return; 786 if (stat == H_ECPUERROR) 787 cmn_err(CE_PANIC, "send_one_mondo: " 788 "cpuid: 0x%x has been marked in " 789 "error", cpuid); 790 else 791 cmn_err(CE_PANIC, "send_one_mondo: " 792 "unexpected hypervisor error 0x%x " 793 "while sending a mondo to cpuid: " 794 "0x%x", stat, cpuid); 795 } 796 tick = gettick(); 797 /* 798 * If there is a big jump between the current tick 799 * count and lasttick, we have probably hit a break 800 * point. Adjust endtick accordingly to avoid panic. 801 */ 802 if (tick > (lasttick + xc_tick_jump_limit)) 803 endtick += (tick - lasttick); 804 lasttick = tick; 805 if (tick > endtick) { 806 if (panic_quiesce) 807 return; 808 cmn_err(CE_PANIC, "send mondo timeout " 809 "(target 0x%x) [retries: 0x%x hvstat: 0x%x]", 810 cpuid, retries, stat); 811 } 812 drv_usecwait(1); 813 stat = shipit(1, mcpup->cpu_list_ra); 814 retries++; 815 } 816 #ifdef SEND_MONDO_STATS 817 { 818 uint64_t n = gettick() - starttick; 819 if (n < 8192) 820 x_one_stimes[n >> 7]++; 821 else if (n < 15*8192) 822 x_one_ltimes[n >> 13]++; 823 else 824 x_one_ltimes[0xf]++; 825 } 826 #endif 827 } 828 829 void 830 send_mondo_set(cpuset_t set) 831 { 832 uint64_t starttick, endtick, tick, lasttick; 833 uint_t largestid, smallestid; 834 int i, j; 835 int ncpuids = 0; 836 int shipped = 0; 837 int retries = 0; 838 struct machcpu *mcpup = &(CPU->cpu_m); 839 840 ASSERT(!CPUSET_ISNULL(set)); 841 CPUSET_BOUNDS(set, smallestid, largestid); 842 if (smallestid == CPUSET_NOTINSET) { 843 return; 844 } 845 846 starttick = lasttick = gettick(); 847 endtick = starttick + xc_tick_limit; 848 849 /* 850 * Assemble CPU list for HV argument. We already know 851 * smallestid and largestid are members of set. 852 */ 853 mcpup->cpu_list[ncpuids++] = (uint16_t)smallestid; 854 if (largestid != smallestid) { 855 for (i = smallestid+1; i <= largestid-1; i++) { 856 if (CPU_IN_SET(set, i)) { 857 mcpup->cpu_list[ncpuids++] = (uint16_t)i; 858 } 859 } 860 mcpup->cpu_list[ncpuids++] = (uint16_t)largestid; 861 } 862 863 do { 864 int stat; 865 866 stat = shipit(ncpuids, mcpup->cpu_list_ra); 867 if (stat == H_EOK) { 868 shipped += ncpuids; 869 break; 870 } 871 872 /* 873 * Either not all CPU mondos were sent, or an 874 * error occurred. CPUs that were sent mondos 875 * have their CPU IDs overwritten in cpu_list. 876 * Reset cpu_list so that it only holds those 877 * CPU IDs that still need to be sent. 878 */ 879 for (i = 0, j = 0; i < ncpuids; i++) { 880 if (mcpup->cpu_list[i] == HV_SEND_MONDO_ENTRYDONE) { 881 shipped++; 882 } else { 883 mcpup->cpu_list[j++] = mcpup->cpu_list[i]; 884 } 885 } 886 ncpuids = j; 887 888 /* 889 * Now handle possible errors returned 890 * from hypervisor. 891 */ 892 if (stat == H_ECPUERROR) { 893 int errorcpus; 894 895 if (!panic_quiesce) 896 cmn_err(CE_CONT, "send_mondo_set: cpuid(s) "); 897 898 /* 899 * Remove any CPUs in the error state from 900 * cpu_list. At this point cpu_list only 901 * contains the CPU IDs for mondos not 902 * succesfully sent. 903 */ 904 for (i = 0, errorcpus = 0; i < ncpuids; i++) { 905 uint64_t state = CPU_STATE_INVALID; 906 uint16_t id = mcpup->cpu_list[i]; 907 908 (void) hv_cpu_state(id, &state); 909 if (state == CPU_STATE_ERROR) { 910 if (!panic_quiesce) 911 cmn_err(CE_CONT, "0x%x ", id); 912 errorcpus++; 913 } else if (errorcpus > 0) { 914 mcpup->cpu_list[i - errorcpus] = 915 mcpup->cpu_list[i]; 916 } 917 } 918 ncpuids -= errorcpus; 919 920 if (!panic_quiesce) { 921 if (errorcpus == 0) { 922 cmn_err(CE_CONT, "<none> have been " 923 "marked in error\n"); 924 cmn_err(CE_PANIC, "send_mondo_set: " 925 "hypervisor returned " 926 "H_ECPUERROR but no CPU in " 927 "cpu_list in error state"); 928 } else { 929 cmn_err(CE_CONT, "have been marked in " 930 "error\n"); 931 cmn_err(CE_PANIC, "send_mondo_set: " 932 "CPU(s) in error state"); 933 } 934 } 935 } else if (stat != H_EWOULDBLOCK) { 936 if (panic_quiesce) 937 return; 938 /* 939 * For all other errors, panic. 940 */ 941 cmn_err(CE_CONT, "send_mondo_set: unexpected " 942 "hypervisor error 0x%x while sending a " 943 "mondo to cpuid(s):", stat); 944 for (i = 0; i < ncpuids; i++) { 945 cmn_err(CE_CONT, " 0x%x", mcpup->cpu_list[i]); 946 } 947 cmn_err(CE_CONT, "\n"); 948 cmn_err(CE_PANIC, "send_mondo_set: unexpected " 949 "hypervisor error"); 950 } 951 952 tick = gettick(); 953 /* 954 * If there is a big jump between the current tick 955 * count and lasttick, we have probably hit a break 956 * point. Adjust endtick accordingly to avoid panic. 957 */ 958 if (tick > (lasttick + xc_tick_jump_limit)) 959 endtick += (tick - lasttick); 960 lasttick = tick; 961 if (tick > endtick) { 962 if (panic_quiesce) 963 return; 964 cmn_err(CE_CONT, "send mondo timeout " 965 "[retries: 0x%x] cpuids: ", retries); 966 for (i = 0; i < ncpuids; i++) 967 cmn_err(CE_CONT, " 0x%x", mcpup->cpu_list[i]); 968 cmn_err(CE_CONT, "\n"); 969 cmn_err(CE_PANIC, "send_mondo_set: timeout"); 970 } 971 972 while (gettick() < (tick + sys_clock_mhz)) 973 ; 974 retries++; 975 } while (ncpuids > 0); 976 977 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped); 978 979 #ifdef SEND_MONDO_STATS 980 { 981 uint64_t n = gettick() - starttick; 982 if (n < 8192) 983 x_set_stimes[n >> 7]++; 984 else if (n < 15*8192) 985 x_set_ltimes[n >> 13]++; 986 else 987 x_set_ltimes[0xf]++; 988 } 989 x_set_cpus[shipped]++; 990 #endif 991 } 992 993 void 994 syncfpu(void) 995 { 996 } 997 998 void 999 sticksync_slave(void) 1000 { 1001 suspend_sync_tick_stick_npt(); 1002 } 1003 1004 void 1005 sticksync_master(void) 1006 {} 1007 1008 void 1009 cpu_init_cache_scrub(void) 1010 { 1011 mach_set_soft_state(SIS_NORMAL, &SOLARIS_SOFT_STATE_RUN_MSG); 1012 } 1013 1014 int 1015 dtrace_blksuword32_err(uintptr_t addr, uint32_t *data) 1016 { 1017 int ret, watched; 1018 1019 watched = watch_disable_addr((void *)addr, 4, S_WRITE); 1020 ret = dtrace_blksuword32(addr, data, 0); 1021 if (watched) 1022 watch_enable_addr((void *)addr, 4, S_WRITE); 1023 1024 return (ret); 1025 } 1026 1027 int 1028 dtrace_blksuword32(uintptr_t addr, uint32_t *data, int tryagain) 1029 { 1030 if (suword32((void *)addr, *data) == -1) 1031 return (tryagain ? dtrace_blksuword32_err(addr, data) : -1); 1032 dtrace_flush_sec(addr); 1033 1034 return (0); 1035 } 1036 1037 /*ARGSUSED*/ 1038 void 1039 cpu_faulted_enter(struct cpu *cp) 1040 { 1041 } 1042 1043 /*ARGSUSED*/ 1044 void 1045 cpu_faulted_exit(struct cpu *cp) 1046 { 1047 } 1048 1049 static int 1050 kdi_cpu_ready_iter(int (*cb)(int, void *), void *arg) 1051 { 1052 int rc, i; 1053 1054 for (rc = 0, i = 0; i < NCPU; i++) { 1055 if (CPU_IN_SET(cpu_ready_set, i)) 1056 rc += cb(i, arg); 1057 } 1058 1059 return (rc); 1060 } 1061 1062 /* 1063 * Sends a cross-call to a specified processor. The caller assumes 1064 * responsibility for repetition of cross-calls, as appropriate (MARSA for 1065 * debugging). 1066 */ 1067 static int 1068 kdi_xc_one(int cpuid, void (*func)(uintptr_t, uintptr_t), uintptr_t arg1, 1069 uintptr_t arg2) 1070 { 1071 int stat; 1072 struct machcpu *mcpup; 1073 uint64_t cpuaddr_reg = 0, cpuaddr_scr = 0; 1074 1075 mcpup = &(((cpu_t *)get_cpuaddr(cpuaddr_reg, cpuaddr_scr))->cpu_m); 1076 1077 /* 1078 * if (idsr_busy()) 1079 * return (KDI_XC_RES_ERR); 1080 */ 1081 1082 init_mondo_nocheck((xcfunc_t *)func, arg1, arg2); 1083 1084 mcpup->cpu_list[0] = (uint16_t)cpuid; 1085 stat = shipit(1, mcpup->cpu_list_ra); 1086 1087 if (stat == 0) 1088 return (KDI_XC_RES_OK); 1089 else 1090 return (KDI_XC_RES_NACK); 1091 } 1092 1093 static void 1094 kdi_tickwait(clock_t nticks) 1095 { 1096 clock_t endtick = gettick() + nticks; 1097 1098 while (gettick() < endtick) 1099 ; 1100 } 1101 1102 static void 1103 kdi_cpu_init(int dcache_size, int dcache_linesize, int icache_size, 1104 int icache_linesize) 1105 { 1106 kdi_dcache_size = dcache_size; 1107 kdi_dcache_linesize = dcache_linesize; 1108 kdi_icache_size = icache_size; 1109 kdi_icache_linesize = icache_linesize; 1110 } 1111 1112 /* used directly by kdi_read/write_phys */ 1113 void 1114 kdi_flush_caches(void) 1115 { 1116 /* Not required on sun4v architecture. */ 1117 } 1118 1119 /*ARGSUSED*/ 1120 int 1121 kdi_get_stick(uint64_t *stickp) 1122 { 1123 return (-1); 1124 } 1125 1126 void 1127 cpu_kdi_init(kdi_t *kdi) 1128 { 1129 kdi->kdi_flush_caches = kdi_flush_caches; 1130 kdi->mkdi_cpu_init = kdi_cpu_init; 1131 kdi->mkdi_cpu_ready_iter = kdi_cpu_ready_iter; 1132 kdi->mkdi_xc_one = kdi_xc_one; 1133 kdi->mkdi_tickwait = kdi_tickwait; 1134 kdi->mkdi_get_stick = kdi_get_stick; 1135 } 1136 1137 uint64_t soft_state_message_ra[SOLARIS_SOFT_STATE_MSG_CNT]; 1138 static uint64_t soft_state_saved_state = (uint64_t)-1; 1139 static int soft_state_initialized = 0; 1140 static uint64_t soft_state_sup_minor; /* Supported minor number */ 1141 static hsvc_info_t soft_state_hsvc = { 1142 HSVC_REV_1, NULL, HSVC_GROUP_SOFT_STATE, 1, 0, NULL }; 1143 1144 1145 static void 1146 sun4v_system_claim(void) 1147 { 1148 lbolt_debug_entry(); 1149 1150 watchdog_suspend(); 1151 kldc_debug_enter(); 1152 /* 1153 * For "mdb -K", set soft state to debugging 1154 */ 1155 if (soft_state_saved_state == -1) { 1156 mach_get_soft_state(&soft_state_saved_state, 1157 &SOLARIS_SOFT_STATE_SAVED_MSG); 1158 } 1159 /* 1160 * check again as the read above may or may not have worked and if 1161 * it didn't then soft state will still be -1 1162 */ 1163 if (soft_state_saved_state != -1) { 1164 mach_set_soft_state(SIS_TRANSITION, 1165 &SOLARIS_SOFT_STATE_DEBUG_MSG); 1166 } 1167 } 1168 1169 static void 1170 sun4v_system_release(void) 1171 { 1172 watchdog_resume(); 1173 /* 1174 * For "mdb -K", set soft_state state back to original state on exit 1175 */ 1176 if (soft_state_saved_state != -1) { 1177 mach_set_soft_state(soft_state_saved_state, 1178 &SOLARIS_SOFT_STATE_SAVED_MSG); 1179 soft_state_saved_state = -1; 1180 } 1181 1182 lbolt_debug_return(); 1183 } 1184 1185 void 1186 plat_kdi_init(kdi_t *kdi) 1187 { 1188 kdi->pkdi_system_claim = sun4v_system_claim; 1189 kdi->pkdi_system_release = sun4v_system_release; 1190 } 1191 1192 /* 1193 * Routine to return memory information associated 1194 * with a physical address and syndrome. 1195 */ 1196 /* ARGSUSED */ 1197 int 1198 cpu_get_mem_info(uint64_t synd, uint64_t afar, 1199 uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep, 1200 int *segsp, int *banksp, int *mcidp) 1201 { 1202 return (ENOTSUP); 1203 } 1204 1205 /* 1206 * This routine returns the size of the kernel's FRU name buffer. 1207 */ 1208 size_t 1209 cpu_get_name_bufsize() 1210 { 1211 return (UNUM_NAMLEN); 1212 } 1213 1214 /* 1215 * This routine is a more generic interface to cpu_get_mem_unum(), 1216 * that may be used by other modules (e.g. mm). 1217 */ 1218 /* ARGSUSED */ 1219 int 1220 cpu_get_mem_name(uint64_t synd, uint64_t *afsr, uint64_t afar, 1221 char *buf, int buflen, int *lenp) 1222 { 1223 return (ENOTSUP); 1224 } 1225 1226 /* ARGSUSED */ 1227 int 1228 cpu_get_mem_sid(char *unum, char *buf, int buflen, int *lenp) 1229 { 1230 return (ENOTSUP); 1231 } 1232 1233 /* ARGSUSED */ 1234 int 1235 cpu_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *addrp) 1236 { 1237 return (ENOTSUP); 1238 } 1239 1240 /* 1241 * xt_sync - wait for previous x-traps to finish 1242 */ 1243 void 1244 xt_sync(cpuset_t cpuset) 1245 { 1246 union { 1247 uint8_t volatile byte[NCPU]; 1248 uint64_t volatile xword[NCPU / 8]; 1249 } cpu_sync; 1250 uint64_t starttick, endtick, tick, lasttick, traptrace_id; 1251 uint_t largestid, smallestid; 1252 int i, j; 1253 1254 kpreempt_disable(); 1255 CPUSET_DEL(cpuset, CPU->cpu_id); 1256 CPUSET_AND(cpuset, cpu_ready_set); 1257 1258 CPUSET_BOUNDS(cpuset, smallestid, largestid); 1259 if (smallestid == CPUSET_NOTINSET) 1260 goto out; 1261 1262 /* 1263 * Sun4v uses a queue for receiving mondos. Successful 1264 * transmission of a mondo only indicates that the mondo 1265 * has been written into the queue. 1266 * 1267 * We use an array of bytes to let each cpu to signal back 1268 * to the cross trap sender that the cross trap has been 1269 * executed. Set the byte to 1 before sending the cross trap 1270 * and wait until other cpus reset it to 0. 1271 */ 1272 bzero((void *)&cpu_sync, NCPU); 1273 cpu_sync.byte[smallestid] = 1; 1274 if (largestid != smallestid) { 1275 for (i = (smallestid + 1); i <= (largestid - 1); i++) 1276 if (CPU_IN_SET(cpuset, i)) 1277 cpu_sync.byte[i] = 1; 1278 cpu_sync.byte[largestid] = 1; 1279 } 1280 1281 /* 1282 * To help debug xt_sync panic, each mondo is uniquely identified 1283 * by passing the tick value, traptrace_id as the second mondo 1284 * argument to xt_some which is logged in CPU's mondo queue, 1285 * traptrace buffer and the panic message. 1286 */ 1287 traptrace_id = gettick(); 1288 xt_some(cpuset, (xcfunc_t *)xt_sync_tl1, 1289 (uint64_t)cpu_sync.byte, traptrace_id); 1290 1291 starttick = lasttick = gettick(); 1292 endtick = starttick + xc_sync_tick_limit; 1293 1294 for (i = (smallestid / 8); i <= (largestid / 8); i++) { 1295 while (cpu_sync.xword[i] != 0) { 1296 tick = gettick(); 1297 /* 1298 * If there is a big jump between the current tick 1299 * count and lasttick, we have probably hit a break 1300 * point. Adjust endtick accordingly to avoid panic. 1301 */ 1302 if (tick > (lasttick + xc_tick_jump_limit)) { 1303 endtick += (tick - lasttick); 1304 } 1305 lasttick = tick; 1306 if (tick > endtick) { 1307 if (panic_quiesce) 1308 goto out; 1309 cmn_err(CE_CONT, "Cross trap sync timeout: " 1310 "at cpu_sync.xword[%d]: 0x%lx " 1311 "cpu_sync.byte: 0x%lx " 1312 "starttick: 0x%lx endtick: 0x%lx " 1313 "traptrace_id = 0x%lx\n", 1314 i, cpu_sync.xword[i], 1315 (uint64_t)cpu_sync.byte, 1316 starttick, endtick, traptrace_id); 1317 cmn_err(CE_CONT, "CPUIDs:"); 1318 for (j = (i * 8); j <= largestid; j++) { 1319 if (cpu_sync.byte[j] != 0) 1320 cmn_err(CE_CONT, " 0x%x", j); 1321 } 1322 cmn_err(CE_PANIC, "xt_sync: timeout"); 1323 } 1324 } 1325 } 1326 1327 out: 1328 kpreempt_enable(); 1329 } 1330 1331 #define QFACTOR 200 1332 /* 1333 * Recalculate the values of the cross-call timeout variables based 1334 * on the value of the 'inter-cpu-latency' property of the platform node. 1335 * The property sets the number of nanosec to wait for a cross-call 1336 * to be acknowledged. Other timeout variables are derived from it. 1337 * 1338 * N.B. This implementation is aware of the internals of xc_init() 1339 * and updates many of the same variables. 1340 */ 1341 void 1342 recalc_xc_timeouts(void) 1343 { 1344 typedef union { 1345 uint64_t whole; 1346 struct { 1347 uint_t high; 1348 uint_t low; 1349 } half; 1350 } u_number; 1351 1352 /* See x_call.c for descriptions of these extern variables. */ 1353 extern uint64_t xc_tick_limit_scale; 1354 extern uint64_t xc_mondo_time_limit; 1355 extern uint64_t xc_func_time_limit; 1356 extern uint64_t xc_scale; 1357 extern uint64_t xc_mondo_multiplier; 1358 extern uint_t nsec_shift; 1359 1360 /* Temp versions of the target variables */ 1361 uint64_t tick_limit; 1362 uint64_t tick_jump_limit; 1363 uint64_t mondo_time_limit; 1364 uint64_t func_time_limit; 1365 uint64_t scale; 1366 1367 uint64_t latency; /* nanoseconds */ 1368 uint64_t maxfreq; 1369 uint64_t tick_limit_save = xc_tick_limit; 1370 uint64_t sync_tick_limit_save = xc_sync_tick_limit; 1371 uint_t tick_scale; 1372 uint64_t top; 1373 uint64_t bottom; 1374 u_number tk; 1375 1376 md_t *mdp; 1377 int nrnode; 1378 mde_cookie_t *platlist; 1379 1380 /* 1381 * Look up the 'inter-cpu-latency' (optional) property in the 1382 * platform node of the MD. The units are nanoseconds. 1383 */ 1384 if ((mdp = md_get_handle()) == NULL) { 1385 cmn_err(CE_WARN, "recalc_xc_timeouts: " 1386 "Unable to initialize machine description"); 1387 return; 1388 } 1389 1390 nrnode = md_alloc_scan_dag(mdp, 1391 md_root_node(mdp), "platform", "fwd", &platlist); 1392 1393 ASSERT(nrnode == 1); 1394 if (nrnode < 1) { 1395 cmn_err(CE_WARN, "recalc_xc_timeouts: platform node missing"); 1396 goto done; 1397 } 1398 if (md_get_prop_val(mdp, platlist[0], 1399 "inter-cpu-latency", &latency) == -1) 1400 goto done; 1401 1402 /* 1403 * clock.h defines an assembly-language macro 1404 * (NATIVE_TIME_TO_NSEC_SCALE) to convert from %stick 1405 * units to nanoseconds. Since the inter-cpu-latency 1406 * units are nanoseconds and the xc_* variables require 1407 * %stick units, we need the inverse of that function. 1408 * The trick is to perform the calculation without 1409 * floating point, but also without integer truncation 1410 * or overflow. To understand the calculation below, 1411 * please read the discussion of the macro in clock.h. 1412 * Since this new code will be invoked infrequently, 1413 * we can afford to implement it in C. 1414 * 1415 * tick_scale is the reciprocal of nsec_scale which is 1416 * calculated at startup in setcpudelay(). The calc 1417 * of tick_limit parallels that of NATIVE_TIME_TO_NSEC_SCALE 1418 * except we use tick_scale instead of nsec_scale and 1419 * C instead of assembler. 1420 */ 1421 tick_scale = (uint_t)(((u_longlong_t)sys_tick_freq 1422 << (32 - nsec_shift)) / NANOSEC); 1423 1424 tk.whole = latency; 1425 top = ((uint64_t)tk.half.high << 4) * tick_scale; 1426 bottom = (((uint64_t)tk.half.low << 4) * (uint64_t)tick_scale) >> 32; 1427 tick_limit = top + bottom; 1428 1429 /* 1430 * xc_init() calculated 'maxfreq' by looking at all the cpus, 1431 * and used it to derive some of the timeout variables that we 1432 * recalculate below. We can back into the original value by 1433 * using the inverse of one of those calculations. 1434 */ 1435 maxfreq = xc_mondo_time_limit / xc_scale; 1436 1437 /* 1438 * Don't allow the new timeout (xc_tick_limit) to fall below 1439 * the system tick frequency (stick). Allowing the timeout 1440 * to be set more tightly than this empirically determined 1441 * value may cause panics. 1442 */ 1443 tick_limit = tick_limit < sys_tick_freq ? sys_tick_freq : tick_limit; 1444 1445 tick_jump_limit = tick_limit / 32; 1446 tick_limit *= xc_tick_limit_scale; 1447 1448 /* 1449 * Recalculate xc_scale since it is used in a callback function 1450 * (xc_func_timeout_adj) to adjust two of the timeouts dynamically. 1451 * Make the change in xc_scale proportional to the change in 1452 * xc_tick_limit. 1453 */ 1454 scale = (xc_scale * tick_limit + sys_tick_freq / 2) / tick_limit_save; 1455 if (scale == 0) 1456 scale = 1; 1457 1458 mondo_time_limit = maxfreq * scale; 1459 func_time_limit = mondo_time_limit * xc_mondo_multiplier; 1460 1461 /* 1462 * Don't modify the timeouts if nothing has changed. Else, 1463 * stuff the variables with the freshly calculated (temp) 1464 * variables. This minimizes the window where the set of 1465 * values could be inconsistent. 1466 */ 1467 if (tick_limit != xc_tick_limit) { 1468 xc_tick_limit = tick_limit; 1469 xc_tick_jump_limit = tick_jump_limit; 1470 xc_scale = scale; 1471 xc_mondo_time_limit = mondo_time_limit; 1472 xc_func_time_limit = func_time_limit; 1473 } 1474 1475 done: 1476 /* 1477 * Increase the timeout limit for xt_sync() cross calls. 1478 */ 1479 xc_sync_tick_limit = xc_tick_limit * (cpu_q_entries / QFACTOR); 1480 xc_sync_tick_limit = xc_sync_tick_limit < xc_tick_limit ? 1481 xc_tick_limit : xc_sync_tick_limit; 1482 1483 /* 1484 * Force the new values to be used for future cross calls. 1485 * This is necessary only when we increase the timeouts. 1486 */ 1487 if ((xc_tick_limit > tick_limit_save) || (xc_sync_tick_limit > 1488 sync_tick_limit_save)) { 1489 cpuset_t cpuset = cpu_ready_set; 1490 xt_sync(cpuset); 1491 } 1492 1493 if (nrnode > 0) 1494 md_free_scan_dag(mdp, &platlist); 1495 (void) md_fini_handle(mdp); 1496 } 1497 1498 void 1499 mach_soft_state_init(void) 1500 { 1501 int i; 1502 uint64_t ra; 1503 1504 /* 1505 * Try to register soft_state api. If it fails, soft_state api has not 1506 * been implemented in the firmware, so do not bother to setup 1507 * soft_state in the kernel. 1508 */ 1509 if ((i = hsvc_register(&soft_state_hsvc, &soft_state_sup_minor)) != 0) { 1510 return; 1511 } 1512 for (i = 0; i < SOLARIS_SOFT_STATE_MSG_CNT; i++) { 1513 ASSERT(strlen((const char *)(void *) 1514 soft_state_message_strings + i) < SSM_SIZE); 1515 if ((ra = va_to_pa( 1516 (void *)(soft_state_message_strings + i))) == -1ll) { 1517 return; 1518 } 1519 soft_state_message_ra[i] = ra; 1520 } 1521 /* 1522 * Tell OBP that we are supporting Guest State 1523 */ 1524 prom_sun4v_soft_state_supported(); 1525 soft_state_initialized = 1; 1526 } 1527 1528 void 1529 mach_set_soft_state(uint64_t state, uint64_t *string_ra) 1530 { 1531 uint64_t rc; 1532 1533 if (soft_state_initialized && *string_ra) { 1534 rc = hv_soft_state_set(state, *string_ra); 1535 if (rc != H_EOK) { 1536 cmn_err(CE_WARN, 1537 "hv_soft_state_set returned %ld\n", rc); 1538 } 1539 } 1540 } 1541 1542 void 1543 mach_get_soft_state(uint64_t *state, uint64_t *string_ra) 1544 { 1545 uint64_t rc; 1546 1547 if (soft_state_initialized && *string_ra) { 1548 rc = hv_soft_state_get(*string_ra, state); 1549 if (rc != H_EOK) { 1550 cmn_err(CE_WARN, 1551 "hv_soft_state_get returned %ld\n", rc); 1552 *state = -1; 1553 } 1554 } 1555 } 1556