1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/machsystm.h> 31 #include <sys/cmp.h> 32 #include <sys/chip.h> 33 34 /* 35 * Note: For now assume the chip ID as 0 for all the cpus until additional 36 * information is available via machine description table 37 */ 38 39 /* 40 * Returns 1 if cpuid is CMP-capable, 0 otherwise. 41 */ 42 /*ARGSUSED*/ 43 int 44 cmp_cpu_is_cmp(processorid_t cpuid) 45 { 46 return (0); 47 } 48 49 /* 50 * Indicate that this core (cpuid) resides on the chip indicated by chipid. 51 * Called during boot and DR add. 52 */ 53 /*ARGSUSED*/ 54 void 55 cmp_add_cpu(chipid_t chipid, processorid_t cpuid) 56 { 57 } 58 59 /* 60 * Indicate that this core (cpuid) is being DR removed. 61 */ 62 /*ARGSUSED*/ 63 void 64 cmp_delete_cpu(processorid_t cpuid) 65 { 66 } 67 68 /* 69 * Called when cpuid is being onlined or offlined. If the offlined 70 * processor is CMP-capable then current target of the CMP Error Steering 71 * Register is set to either the lowest numbered on-line sibling core, if 72 * one exists, or else to this core. 73 */ 74 /*ARGSUSED*/ 75 void 76 cmp_error_resteer(processorid_t cpuid) 77 { 78 } 79 80 /* 81 * Return 0, shortterm workaround until MD table is updated 82 * to provide cpu-chip mapping 83 */ 84 85 /*ARGSUSED*/ 86 chipid_t 87 cmp_cpu_to_chip(processorid_t cpuid) 88 { 89 return (0); 90 } 91 92 /* 93 * Return a chip "id" for the given cpu_t 94 * cpu_t's residing on the same physical processor 95 * should map to the same "id" 96 */ 97 chipid_t 98 chip_plat_get_chipid(cpu_t *cp) 99 { 100 return (cmp_cpu_to_chip(cp->cpu_id)); 101 } 102 103 /*ARGSUSED*/ 104 void 105 chip_plat_define_chip(cpu_t *cp, chip_def_t *cd) 106 { 107 cd->chipd_type = CHIP_CMT; 108 109 /* 110 * Define any needed adjustment of rechoose_interval 111 * For now, all chips use the default. This 112 * will change with future processors. 113 */ 114 cd->chipd_rechoose_adj = 0; 115 cd->chipd_nosteal = 0; 116 } 117 118 /* 119 * Return a pipeline "id" for the given cpu_t 120 * cpu_t's sharing the same instruction pipeline 121 * should map to the same "id" 122 */ 123 124 id_t 125 chip_plat_get_coreid(cpu_t *cp) 126 { 127 return (cp->cpu_m.cpu_ipipe); 128 } 129