1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29#if !defined(lint) 30#include "assym.h" 31#endif /* !lint */ 32#include <sys/asm_linkage.h> 33#include <sys/privregs.h> 34#include <sys/sun4asi.h> 35#include <sys/machasi.h> 36#include <sys/hypervisor_api.h> 37#include <sys/machtrap.h> 38#include <sys/machthread.h> 39#include <sys/pcb.h> 40#include <sys/pte.h> 41#include <sys/mmu.h> 42#include <sys/machpcb.h> 43#include <sys/async.h> 44#include <sys/intreg.h> 45#include <sys/scb.h> 46#include <sys/psr_compat.h> 47#include <sys/syscall.h> 48#include <sys/machparam.h> 49#include <sys/traptrace.h> 50#include <vm/hat_sfmmu.h> 51#include <sys/archsystm.h> 52#include <sys/utrap.h> 53#include <sys/clock.h> 54#include <sys/intr.h> 55#include <sys/fpu/fpu_simulator.h> 56#include <vm/seg_spt.h> 57 58/* 59 * WARNING: If you add a fast trap handler which can be invoked by a 60 * non-privileged user, you may have to use the FAST_TRAP_DONE macro 61 * instead of "done" instruction to return back to the user mode. See 62 * comments for the "fast_trap_done" entry point for more information. 63 * 64 * An alternate FAST_TRAP_DONE_CHK_INTR macro should be used for the 65 * cases where you always want to process any pending interrupts before 66 * returning back to the user mode. 67 */ 68#define FAST_TRAP_DONE \ 69 ba,a fast_trap_done 70 71#define FAST_TRAP_DONE_CHK_INTR \ 72 ba,a fast_trap_done_chk_intr 73 74/* 75 * SPARC V9 Trap Table 76 * 77 * Most of the trap handlers are made from common building 78 * blocks, and some are instantiated multiple times within 79 * the trap table. So, I build a bunch of macros, then 80 * populate the table using only the macros. 81 * 82 * Many macros branch to sys_trap. Its calling convention is: 83 * %g1 kernel trap handler 84 * %g2, %g3 args for above 85 * %g4 desire %pil 86 */ 87 88#ifdef TRAPTRACE 89 90/* 91 * Tracing macro. Adds two instructions if TRAPTRACE is defined. 92 */ 93#define TT_TRACE(label) \ 94 ba label ;\ 95 rd %pc, %g7 96#define TT_TRACE_INS 2 97 98#define TT_TRACE_L(label) \ 99 ba label ;\ 100 rd %pc, %l4 ;\ 101 clr %l4 102#define TT_TRACE_L_INS 3 103 104#else 105 106#define TT_TRACE(label) 107#define TT_TRACE_INS 0 108 109#define TT_TRACE_L(label) 110#define TT_TRACE_L_INS 0 111 112#endif 113 114/* 115 * This macro is used to update per cpu mmu stats in perf critical 116 * paths. It is only enabled in debug kernels or if SFMMU_STAT_GATHER 117 * is defined. 118 */ 119#if defined(DEBUG) || defined(SFMMU_STAT_GATHER) 120#define HAT_PERCPU_DBSTAT(stat) \ 121 mov stat, %g1 ;\ 122 ba stat_mmu ;\ 123 rd %pc, %g7 124#else 125#define HAT_PERCPU_DBSTAT(stat) 126#endif /* DEBUG || SFMMU_STAT_GATHER */ 127 128/* 129 * This first set are funneled to trap() with %tt as the type. 130 * Trap will then either panic or send the user a signal. 131 */ 132/* 133 * NOT is used for traps that just shouldn't happen. 134 * It comes in both single and quadruple flavors. 135 */ 136#if !defined(lint) 137 .global trap 138#endif /* !lint */ 139#define NOT \ 140 TT_TRACE(trace_gen) ;\ 141 set trap, %g1 ;\ 142 rdpr %tt, %g3 ;\ 143 ba,pt %xcc, sys_trap ;\ 144 sub %g0, 1, %g4 ;\ 145 .align 32 146#define NOT4 NOT; NOT; NOT; NOT 147 148#define NOTP \ 149 TT_TRACE(trace_gen) ;\ 150 ba,pt %xcc, ptl1_panic ;\ 151 mov PTL1_BAD_TRAP, %g1 ;\ 152 .align 32 153#define NOTP4 NOTP; NOTP; NOTP; NOTP 154 155 156/* 157 * BAD is used for trap vectors we don't have a kernel 158 * handler for. 159 * It also comes in single and quadruple versions. 160 */ 161#define BAD NOT 162#define BAD4 NOT4 163 164#define DONE \ 165 done; \ 166 .align 32 167 168/* 169 * TRAP vectors to the trap() function. 170 * It's main use is for user errors. 171 */ 172#if !defined(lint) 173 .global trap 174#endif /* !lint */ 175#define TRAP(arg) \ 176 TT_TRACE(trace_gen) ;\ 177 set trap, %g1 ;\ 178 mov arg, %g3 ;\ 179 ba,pt %xcc, sys_trap ;\ 180 sub %g0, 1, %g4 ;\ 181 .align 32 182 183/* 184 * SYSCALL is used for system calls on both ILP32 and LP64 kernels 185 * depending on the "which" parameter (should be syscall_trap, 186 * syscall_trap32, or nosys for unused system call traps). 187 */ 188#define SYSCALL(which) \ 189 TT_TRACE(trace_gen) ;\ 190 set (which), %g1 ;\ 191 ba,pt %xcc, sys_trap ;\ 192 sub %g0, 1, %g4 ;\ 193 .align 32 194 195/* 196 * GOTO just jumps to a label. 197 * It's used for things that can be fixed without going thru sys_trap. 198 */ 199#define GOTO(label) \ 200 .global label ;\ 201 ba,a label ;\ 202 .empty ;\ 203 .align 32 204 205/* 206 * GOTO_TT just jumps to a label. 207 * correctable ECC error traps at level 0 and 1 will use this macro. 208 * It's used for things that can be fixed without going thru sys_trap. 209 */ 210#define GOTO_TT(label, ttlabel) \ 211 .global label ;\ 212 TT_TRACE(ttlabel) ;\ 213 ba,a label ;\ 214 .empty ;\ 215 .align 32 216 217/* 218 * Privileged traps 219 * Takes breakpoint if privileged, calls trap() if not. 220 */ 221#define PRIV(label) \ 222 rdpr %tstate, %g1 ;\ 223 btst TSTATE_PRIV, %g1 ;\ 224 bnz label ;\ 225 rdpr %tt, %g3 ;\ 226 set trap, %g1 ;\ 227 ba,pt %xcc, sys_trap ;\ 228 sub %g0, 1, %g4 ;\ 229 .align 32 230 231 232/* 233 * DTrace traps. 234 */ 235#define DTRACE_PID \ 236 .global dtrace_pid_probe ;\ 237 set dtrace_pid_probe, %g1 ;\ 238 ba,pt %xcc, user_trap ;\ 239 sub %g0, 1, %g4 ;\ 240 .align 32 241 242#define DTRACE_RETURN \ 243 .global dtrace_return_probe ;\ 244 set dtrace_return_probe, %g1 ;\ 245 ba,pt %xcc, user_trap ;\ 246 sub %g0, 1, %g4 ;\ 247 .align 32 248 249/* 250 * REGISTER WINDOW MANAGEMENT MACROS 251 */ 252 253/* 254 * various convenient units of padding 255 */ 256#define SKIP(n) .skip 4*(n) 257 258/* 259 * CLEAN_WINDOW is the simple handler for cleaning a register window. 260 */ 261#define CLEAN_WINDOW \ 262 TT_TRACE_L(trace_win) ;\ 263 rdpr %cleanwin, %l0; inc %l0; wrpr %l0, %cleanwin ;\ 264 clr %l0; clr %l1; clr %l2; clr %l3 ;\ 265 clr %l4; clr %l5; clr %l6; clr %l7 ;\ 266 clr %o0; clr %o1; clr %o2; clr %o3 ;\ 267 clr %o4; clr %o5; clr %o6; clr %o7 ;\ 268 retry; .align 128 269 270#if !defined(lint) 271 272/* 273 * If we get an unresolved tlb miss while in a window handler, the fault 274 * handler will resume execution at the last instruction of the window 275 * hander, instead of delivering the fault to the kernel. Spill handlers 276 * use this to spill windows into the wbuf. 277 * 278 * The mixed handler works by checking %sp, and branching to the correct 279 * handler. This is done by branching back to label 1: for 32b frames, 280 * or label 2: for 64b frames; which implies the handler order is: 32b, 281 * 64b, mixed. The 1: and 2: labels are offset into the routines to 282 * allow the branchs' delay slots to contain useful instructions. 283 */ 284 285/* 286 * SPILL_32bit spills a 32-bit-wide kernel register window. It 287 * assumes that the kernel context and the nucleus context are the 288 * same. The stack pointer is required to be eight-byte aligned even 289 * though this code only needs it to be four-byte aligned. 290 */ 291#define SPILL_32bit(tail) \ 292 srl %sp, 0, %sp ;\ 2931: st %l0, [%sp + 0] ;\ 294 st %l1, [%sp + 4] ;\ 295 st %l2, [%sp + 8] ;\ 296 st %l3, [%sp + 12] ;\ 297 st %l4, [%sp + 16] ;\ 298 st %l5, [%sp + 20] ;\ 299 st %l6, [%sp + 24] ;\ 300 st %l7, [%sp + 28] ;\ 301 st %i0, [%sp + 32] ;\ 302 st %i1, [%sp + 36] ;\ 303 st %i2, [%sp + 40] ;\ 304 st %i3, [%sp + 44] ;\ 305 st %i4, [%sp + 48] ;\ 306 st %i5, [%sp + 52] ;\ 307 st %i6, [%sp + 56] ;\ 308 st %i7, [%sp + 60] ;\ 309 TT_TRACE_L(trace_win) ;\ 310 saved ;\ 311 retry ;\ 312 SKIP(31-19-TT_TRACE_L_INS) ;\ 313 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 314 .empty 315 316/* 317 * SPILL_32bit_asi spills a 32-bit-wide register window into a 32-bit 318 * wide address space via the designated asi. It is used to spill 319 * non-kernel windows. The stack pointer is required to be eight-byte 320 * aligned even though this code only needs it to be four-byte 321 * aligned. 322 */ 323#define SPILL_32bit_asi(asi_num, tail) \ 324 srl %sp, 0, %sp ;\ 3251: sta %l0, [%sp + %g0]asi_num ;\ 326 mov 4, %g1 ;\ 327 sta %l1, [%sp + %g1]asi_num ;\ 328 mov 8, %g2 ;\ 329 sta %l2, [%sp + %g2]asi_num ;\ 330 mov 12, %g3 ;\ 331 sta %l3, [%sp + %g3]asi_num ;\ 332 add %sp, 16, %g4 ;\ 333 sta %l4, [%g4 + %g0]asi_num ;\ 334 sta %l5, [%g4 + %g1]asi_num ;\ 335 sta %l6, [%g4 + %g2]asi_num ;\ 336 sta %l7, [%g4 + %g3]asi_num ;\ 337 add %g4, 16, %g4 ;\ 338 sta %i0, [%g4 + %g0]asi_num ;\ 339 sta %i1, [%g4 + %g1]asi_num ;\ 340 sta %i2, [%g4 + %g2]asi_num ;\ 341 sta %i3, [%g4 + %g3]asi_num ;\ 342 add %g4, 16, %g4 ;\ 343 sta %i4, [%g4 + %g0]asi_num ;\ 344 sta %i5, [%g4 + %g1]asi_num ;\ 345 sta %i6, [%g4 + %g2]asi_num ;\ 346 sta %i7, [%g4 + %g3]asi_num ;\ 347 TT_TRACE_L(trace_win) ;\ 348 saved ;\ 349 retry ;\ 350 SKIP(31-25-TT_TRACE_L_INS) ;\ 351 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 352 .empty 353 354#define SPILL_32bit_tt1(asi_num, tail) \ 355 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 356 .empty ;\ 357 .align 128 358 359 360/* 361 * FILL_32bit fills a 32-bit-wide kernel register window. It assumes 362 * that the kernel context and the nucleus context are the same. The 363 * stack pointer is required to be eight-byte aligned even though this 364 * code only needs it to be four-byte aligned. 365 */ 366#define FILL_32bit(tail) \ 367 srl %sp, 0, %sp ;\ 3681: TT_TRACE_L(trace_win) ;\ 369 ld [%sp + 0], %l0 ;\ 370 ld [%sp + 4], %l1 ;\ 371 ld [%sp + 8], %l2 ;\ 372 ld [%sp + 12], %l3 ;\ 373 ld [%sp + 16], %l4 ;\ 374 ld [%sp + 20], %l5 ;\ 375 ld [%sp + 24], %l6 ;\ 376 ld [%sp + 28], %l7 ;\ 377 ld [%sp + 32], %i0 ;\ 378 ld [%sp + 36], %i1 ;\ 379 ld [%sp + 40], %i2 ;\ 380 ld [%sp + 44], %i3 ;\ 381 ld [%sp + 48], %i4 ;\ 382 ld [%sp + 52], %i5 ;\ 383 ld [%sp + 56], %i6 ;\ 384 ld [%sp + 60], %i7 ;\ 385 restored ;\ 386 retry ;\ 387 SKIP(31-19-TT_TRACE_L_INS) ;\ 388 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 389 .empty 390 391/* 392 * FILL_32bit_asi fills a 32-bit-wide register window from a 32-bit 393 * wide address space via the designated asi. It is used to fill 394 * non-kernel windows. The stack pointer is required to be eight-byte 395 * aligned even though this code only needs it to be four-byte 396 * aligned. 397 */ 398#define FILL_32bit_asi(asi_num, tail) \ 399 srl %sp, 0, %sp ;\ 4001: TT_TRACE_L(trace_win) ;\ 401 mov 4, %g1 ;\ 402 lda [%sp + %g0]asi_num, %l0 ;\ 403 mov 8, %g2 ;\ 404 lda [%sp + %g1]asi_num, %l1 ;\ 405 mov 12, %g3 ;\ 406 lda [%sp + %g2]asi_num, %l2 ;\ 407 lda [%sp + %g3]asi_num, %l3 ;\ 408 add %sp, 16, %g4 ;\ 409 lda [%g4 + %g0]asi_num, %l4 ;\ 410 lda [%g4 + %g1]asi_num, %l5 ;\ 411 lda [%g4 + %g2]asi_num, %l6 ;\ 412 lda [%g4 + %g3]asi_num, %l7 ;\ 413 add %g4, 16, %g4 ;\ 414 lda [%g4 + %g0]asi_num, %i0 ;\ 415 lda [%g4 + %g1]asi_num, %i1 ;\ 416 lda [%g4 + %g2]asi_num, %i2 ;\ 417 lda [%g4 + %g3]asi_num, %i3 ;\ 418 add %g4, 16, %g4 ;\ 419 lda [%g4 + %g0]asi_num, %i4 ;\ 420 lda [%g4 + %g1]asi_num, %i5 ;\ 421 lda [%g4 + %g2]asi_num, %i6 ;\ 422 lda [%g4 + %g3]asi_num, %i7 ;\ 423 restored ;\ 424 retry ;\ 425 SKIP(31-25-TT_TRACE_L_INS) ;\ 426 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 427 .empty 428 429 430/* 431 * SPILL_64bit spills a 64-bit-wide kernel register window. It 432 * assumes that the kernel context and the nucleus context are the 433 * same. The stack pointer is required to be eight-byte aligned. 434 */ 435#define SPILL_64bit(tail) \ 4362: stx %l0, [%sp + V9BIAS64 + 0] ;\ 437 stx %l1, [%sp + V9BIAS64 + 8] ;\ 438 stx %l2, [%sp + V9BIAS64 + 16] ;\ 439 stx %l3, [%sp + V9BIAS64 + 24] ;\ 440 stx %l4, [%sp + V9BIAS64 + 32] ;\ 441 stx %l5, [%sp + V9BIAS64 + 40] ;\ 442 stx %l6, [%sp + V9BIAS64 + 48] ;\ 443 stx %l7, [%sp + V9BIAS64 + 56] ;\ 444 stx %i0, [%sp + V9BIAS64 + 64] ;\ 445 stx %i1, [%sp + V9BIAS64 + 72] ;\ 446 stx %i2, [%sp + V9BIAS64 + 80] ;\ 447 stx %i3, [%sp + V9BIAS64 + 88] ;\ 448 stx %i4, [%sp + V9BIAS64 + 96] ;\ 449 stx %i5, [%sp + V9BIAS64 + 104] ;\ 450 stx %i6, [%sp + V9BIAS64 + 112] ;\ 451 stx %i7, [%sp + V9BIAS64 + 120] ;\ 452 TT_TRACE_L(trace_win) ;\ 453 saved ;\ 454 retry ;\ 455 SKIP(31-18-TT_TRACE_L_INS) ;\ 456 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 457 .empty 458 459#define SPILL_64bit_ktt1(tail) \ 460 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 461 .empty ;\ 462 .align 128 463 464#define SPILL_mixed_ktt1(tail) \ 465 btst 1, %sp ;\ 466 bz,a,pt %xcc, fault_32bit_/**/tail ;\ 467 srl %sp, 0, %sp ;\ 468 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 469 .empty ;\ 470 .align 128 471 472/* 473 * SPILL_64bit_asi spills a 64-bit-wide register window into a 64-bit 474 * wide address space via the designated asi. It is used to spill 475 * non-kernel windows. The stack pointer is required to be eight-byte 476 * aligned. 477 */ 478#define SPILL_64bit_asi(asi_num, tail) \ 479 mov 0 + V9BIAS64, %g1 ;\ 4802: stxa %l0, [%sp + %g1]asi_num ;\ 481 mov 8 + V9BIAS64, %g2 ;\ 482 stxa %l1, [%sp + %g2]asi_num ;\ 483 mov 16 + V9BIAS64, %g3 ;\ 484 stxa %l2, [%sp + %g3]asi_num ;\ 485 mov 24 + V9BIAS64, %g4 ;\ 486 stxa %l3, [%sp + %g4]asi_num ;\ 487 add %sp, 32, %g5 ;\ 488 stxa %l4, [%g5 + %g1]asi_num ;\ 489 stxa %l5, [%g5 + %g2]asi_num ;\ 490 stxa %l6, [%g5 + %g3]asi_num ;\ 491 stxa %l7, [%g5 + %g4]asi_num ;\ 492 add %g5, 32, %g5 ;\ 493 stxa %i0, [%g5 + %g1]asi_num ;\ 494 stxa %i1, [%g5 + %g2]asi_num ;\ 495 stxa %i2, [%g5 + %g3]asi_num ;\ 496 stxa %i3, [%g5 + %g4]asi_num ;\ 497 add %g5, 32, %g5 ;\ 498 stxa %i4, [%g5 + %g1]asi_num ;\ 499 stxa %i5, [%g5 + %g2]asi_num ;\ 500 stxa %i6, [%g5 + %g3]asi_num ;\ 501 stxa %i7, [%g5 + %g4]asi_num ;\ 502 TT_TRACE_L(trace_win) ;\ 503 saved ;\ 504 retry ;\ 505 SKIP(31-25-TT_TRACE_L_INS) ;\ 506 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 507 .empty 508 509#define SPILL_64bit_tt1(asi_num, tail) \ 510 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 511 .empty ;\ 512 .align 128 513 514/* 515 * FILL_64bit fills a 64-bit-wide kernel register window. It assumes 516 * that the kernel context and the nucleus context are the same. The 517 * stack pointer is required to be eight-byte aligned. 518 */ 519#define FILL_64bit(tail) \ 5202: TT_TRACE_L(trace_win) ;\ 521 ldx [%sp + V9BIAS64 + 0], %l0 ;\ 522 ldx [%sp + V9BIAS64 + 8], %l1 ;\ 523 ldx [%sp + V9BIAS64 + 16], %l2 ;\ 524 ldx [%sp + V9BIAS64 + 24], %l3 ;\ 525 ldx [%sp + V9BIAS64 + 32], %l4 ;\ 526 ldx [%sp + V9BIAS64 + 40], %l5 ;\ 527 ldx [%sp + V9BIAS64 + 48], %l6 ;\ 528 ldx [%sp + V9BIAS64 + 56], %l7 ;\ 529 ldx [%sp + V9BIAS64 + 64], %i0 ;\ 530 ldx [%sp + V9BIAS64 + 72], %i1 ;\ 531 ldx [%sp + V9BIAS64 + 80], %i2 ;\ 532 ldx [%sp + V9BIAS64 + 88], %i3 ;\ 533 ldx [%sp + V9BIAS64 + 96], %i4 ;\ 534 ldx [%sp + V9BIAS64 + 104], %i5 ;\ 535 ldx [%sp + V9BIAS64 + 112], %i6 ;\ 536 ldx [%sp + V9BIAS64 + 120], %i7 ;\ 537 restored ;\ 538 retry ;\ 539 SKIP(31-18-TT_TRACE_L_INS) ;\ 540 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 541 .empty 542 543/* 544 * FILL_64bit_asi fills a 64-bit-wide register window from a 64-bit 545 * wide address space via the designated asi. It is used to fill 546 * non-kernel windows. The stack pointer is required to be eight-byte 547 * aligned. 548 */ 549#define FILL_64bit_asi(asi_num, tail) \ 550 mov V9BIAS64 + 0, %g1 ;\ 5512: TT_TRACE_L(trace_win) ;\ 552 ldxa [%sp + %g1]asi_num, %l0 ;\ 553 mov V9BIAS64 + 8, %g2 ;\ 554 ldxa [%sp + %g2]asi_num, %l1 ;\ 555 mov V9BIAS64 + 16, %g3 ;\ 556 ldxa [%sp + %g3]asi_num, %l2 ;\ 557 mov V9BIAS64 + 24, %g4 ;\ 558 ldxa [%sp + %g4]asi_num, %l3 ;\ 559 add %sp, 32, %g5 ;\ 560 ldxa [%g5 + %g1]asi_num, %l4 ;\ 561 ldxa [%g5 + %g2]asi_num, %l5 ;\ 562 ldxa [%g5 + %g3]asi_num, %l6 ;\ 563 ldxa [%g5 + %g4]asi_num, %l7 ;\ 564 add %g5, 32, %g5 ;\ 565 ldxa [%g5 + %g1]asi_num, %i0 ;\ 566 ldxa [%g5 + %g2]asi_num, %i1 ;\ 567 ldxa [%g5 + %g3]asi_num, %i2 ;\ 568 ldxa [%g5 + %g4]asi_num, %i3 ;\ 569 add %g5, 32, %g5 ;\ 570 ldxa [%g5 + %g1]asi_num, %i4 ;\ 571 ldxa [%g5 + %g2]asi_num, %i5 ;\ 572 ldxa [%g5 + %g3]asi_num, %i6 ;\ 573 ldxa [%g5 + %g4]asi_num, %i7 ;\ 574 restored ;\ 575 retry ;\ 576 SKIP(31-25-TT_TRACE_L_INS) ;\ 577 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 578 .empty 579 580 581#endif /* !lint */ 582 583/* 584 * SPILL_mixed spills either size window, depending on 585 * whether %sp is even or odd, to a 32-bit address space. 586 * This may only be used in conjunction with SPILL_32bit/ 587 * FILL_64bit. 588 * Clear upper 32 bits of %sp if it is odd. 589 * We won't need to clear them in 64 bit kernel. 590 */ 591#define SPILL_mixed \ 592 btst 1, %sp ;\ 593 bz,a,pt %xcc, 1b ;\ 594 srl %sp, 0, %sp ;\ 595 ba,pt %xcc, 2b ;\ 596 nop ;\ 597 .align 128 598 599/* 600 * FILL_mixed(ASI) fills either size window, depending on 601 * whether %sp is even or odd, from a 32-bit address space. 602 * This may only be used in conjunction with FILL_32bit/ 603 * FILL_64bit. New versions of FILL_mixed_{tt1,asi} would be 604 * needed for use with FILL_{32,64}bit_{tt1,asi}. Particular 605 * attention should be paid to the instructions that belong 606 * in the delay slots of the branches depending on the type 607 * of fill handler being branched to. 608 * Clear upper 32 bits of %sp if it is odd. 609 * We won't need to clear them in 64 bit kernel. 610 */ 611#define FILL_mixed \ 612 btst 1, %sp ;\ 613 bz,a,pt %xcc, 1b ;\ 614 srl %sp, 0, %sp ;\ 615 ba,pt %xcc, 2b ;\ 616 nop ;\ 617 .align 128 618 619 620/* 621 * SPILL_32clean/SPILL_64clean spill 32-bit and 64-bit register windows, 622 * respectively, into the address space via the designated asi. The 623 * unbiased stack pointer is required to be eight-byte aligned (even for 624 * the 32-bit case even though this code does not require such strict 625 * alignment). 626 * 627 * With SPARC v9 the spill trap takes precedence over the cleanwin trap 628 * so when cansave == 0, canrestore == 6, and cleanwin == 6 the next save 629 * will cause cwp + 2 to be spilled but will not clean cwp + 1. That 630 * window may contain kernel data so in user_rtt we set wstate to call 631 * these spill handlers on the first user spill trap. These handler then 632 * spill the appropriate window but also back up a window and clean the 633 * window that didn't get a cleanwin trap. 634 */ 635#define SPILL_32clean(asi_num, tail) \ 636 srl %sp, 0, %sp ;\ 637 sta %l0, [%sp + %g0]asi_num ;\ 638 mov 4, %g1 ;\ 639 sta %l1, [%sp + %g1]asi_num ;\ 640 mov 8, %g2 ;\ 641 sta %l2, [%sp + %g2]asi_num ;\ 642 mov 12, %g3 ;\ 643 sta %l3, [%sp + %g3]asi_num ;\ 644 add %sp, 16, %g4 ;\ 645 sta %l4, [%g4 + %g0]asi_num ;\ 646 sta %l5, [%g4 + %g1]asi_num ;\ 647 sta %l6, [%g4 + %g2]asi_num ;\ 648 sta %l7, [%g4 + %g3]asi_num ;\ 649 add %g4, 16, %g4 ;\ 650 sta %i0, [%g4 + %g0]asi_num ;\ 651 sta %i1, [%g4 + %g1]asi_num ;\ 652 sta %i2, [%g4 + %g2]asi_num ;\ 653 sta %i3, [%g4 + %g3]asi_num ;\ 654 add %g4, 16, %g4 ;\ 655 sta %i4, [%g4 + %g0]asi_num ;\ 656 sta %i5, [%g4 + %g1]asi_num ;\ 657 sta %i6, [%g4 + %g2]asi_num ;\ 658 sta %i7, [%g4 + %g3]asi_num ;\ 659 TT_TRACE_L(trace_win) ;\ 660 b .spill_clean ;\ 661 mov WSTATE_USER32, %g7 ;\ 662 SKIP(31-25-TT_TRACE_L_INS) ;\ 663 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 664 .empty 665 666#define SPILL_64clean(asi_num, tail) \ 667 mov 0 + V9BIAS64, %g1 ;\ 668 stxa %l0, [%sp + %g1]asi_num ;\ 669 mov 8 + V9BIAS64, %g2 ;\ 670 stxa %l1, [%sp + %g2]asi_num ;\ 671 mov 16 + V9BIAS64, %g3 ;\ 672 stxa %l2, [%sp + %g3]asi_num ;\ 673 mov 24 + V9BIAS64, %g4 ;\ 674 stxa %l3, [%sp + %g4]asi_num ;\ 675 add %sp, 32, %g5 ;\ 676 stxa %l4, [%g5 + %g1]asi_num ;\ 677 stxa %l5, [%g5 + %g2]asi_num ;\ 678 stxa %l6, [%g5 + %g3]asi_num ;\ 679 stxa %l7, [%g5 + %g4]asi_num ;\ 680 add %g5, 32, %g5 ;\ 681 stxa %i0, [%g5 + %g1]asi_num ;\ 682 stxa %i1, [%g5 + %g2]asi_num ;\ 683 stxa %i2, [%g5 + %g3]asi_num ;\ 684 stxa %i3, [%g5 + %g4]asi_num ;\ 685 add %g5, 32, %g5 ;\ 686 stxa %i4, [%g5 + %g1]asi_num ;\ 687 stxa %i5, [%g5 + %g2]asi_num ;\ 688 stxa %i6, [%g5 + %g3]asi_num ;\ 689 stxa %i7, [%g5 + %g4]asi_num ;\ 690 TT_TRACE_L(trace_win) ;\ 691 b .spill_clean ;\ 692 mov WSTATE_USER64, %g7 ;\ 693 SKIP(31-25-TT_TRACE_L_INS) ;\ 694 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 695 .empty 696 697 698/* 699 * Floating point disabled. 700 */ 701#define FP_DISABLED_TRAP \ 702 TT_TRACE(trace_gen) ;\ 703 ba,pt %xcc,.fp_disabled ;\ 704 nop ;\ 705 .align 32 706 707/* 708 * Floating point exceptions. 709 */ 710#define FP_IEEE_TRAP \ 711 TT_TRACE(trace_gen) ;\ 712 ba,pt %xcc,.fp_ieee_exception ;\ 713 nop ;\ 714 .align 32 715 716#define FP_TRAP \ 717 TT_TRACE(trace_gen) ;\ 718 ba,pt %xcc,.fp_exception ;\ 719 nop ;\ 720 .align 32 721 722#if !defined(lint) 723 724/* 725 * ECACHE_ECC error traps at level 0 and level 1 726 */ 727#define ECACHE_ECC(table_name) \ 728 .global table_name ;\ 729table_name: ;\ 730 membar #Sync ;\ 731 set trap, %g1 ;\ 732 rdpr %tt, %g3 ;\ 733 ba,pt %xcc, sys_trap ;\ 734 sub %g0, 1, %g4 ;\ 735 .align 32 736 737#endif /* !lint */ 738 739/* 740 * illegal instruction trap 741 */ 742#define ILLTRAP_INSTR \ 743 membar #Sync ;\ 744 TT_TRACE(trace_gen) ;\ 745 or %g0, P_UTRAP4, %g2 ;\ 746 or %g0, T_UNIMP_INSTR, %g3 ;\ 747 sethi %hi(.check_v9utrap), %g4 ;\ 748 jmp %g4 + %lo(.check_v9utrap) ;\ 749 nop ;\ 750 .align 32 751 752/* 753 * tag overflow trap 754 */ 755#define TAG_OVERFLOW \ 756 TT_TRACE(trace_gen) ;\ 757 or %g0, P_UTRAP10, %g2 ;\ 758 or %g0, T_TAG_OVERFLOW, %g3 ;\ 759 sethi %hi(.check_v9utrap), %g4 ;\ 760 jmp %g4 + %lo(.check_v9utrap) ;\ 761 nop ;\ 762 .align 32 763 764/* 765 * divide by zero trap 766 */ 767#define DIV_BY_ZERO \ 768 TT_TRACE(trace_gen) ;\ 769 or %g0, P_UTRAP11, %g2 ;\ 770 or %g0, T_IDIV0, %g3 ;\ 771 sethi %hi(.check_v9utrap), %g4 ;\ 772 jmp %g4 + %lo(.check_v9utrap) ;\ 773 nop ;\ 774 .align 32 775 776/* 777 * trap instruction for V9 user trap handlers 778 */ 779#define TRAP_INSTR \ 780 TT_TRACE(trace_gen) ;\ 781 or %g0, T_SOFTWARE_TRAP, %g3 ;\ 782 sethi %hi(.check_v9utrap), %g4 ;\ 783 jmp %g4 + %lo(.check_v9utrap) ;\ 784 nop ;\ 785 .align 32 786#define TRP4 TRAP_INSTR; TRAP_INSTR; TRAP_INSTR; TRAP_INSTR 787 788/* 789 * LEVEL_INTERRUPT is for level N interrupts. 790 * VECTOR_INTERRUPT is for the vector trap. 791 */ 792#define LEVEL_INTERRUPT(level) \ 793 .global tt_pil/**/level ;\ 794tt_pil/**/level: ;\ 795 ba,pt %xcc, pil_interrupt ;\ 796 mov level, %g4 ;\ 797 .align 32 798 799#define LEVEL14_INTERRUPT \ 800 ba pil14_interrupt ;\ 801 mov PIL_14, %g4 ;\ 802 .align 32 803 804#define CPU_MONDO \ 805 ba,a,pt %xcc, cpu_mondo ;\ 806 .align 32 807 808#define DEV_MONDO \ 809 ba,a,pt %xcc, dev_mondo ;\ 810 .align 32 811 812/* 813 * We take over the rtba after we set our trap table and 814 * fault status area. The watchdog reset trap is now handled by the OS. 815 */ 816#define WATCHDOG_RESET \ 817 mov PTL1_BAD_WATCHDOG, %g1 ;\ 818 ba,a,pt %xcc, .watchdog_trap ;\ 819 .align 32 820 821/* 822 * RED is for traps that use the red mode handler. 823 * We should never see these either. 824 */ 825#define RED \ 826 mov PTL1_BAD_RED, %g1 ;\ 827 ba,a,pt %xcc, .watchdog_trap ;\ 828 .align 32 829 830 831/* 832 * MMU Trap Handlers. 833 */ 834 835/* 836 * synthesize for trap(): SFSR in %g3 837 */ 838#define IMMU_EXCEPTION \ 839 MMU_FAULT_STATUS_AREA(%g3) ;\ 840 rdpr %tpc, %g2 ;\ 841 ldx [%g3 + MMFSA_I_TYPE], %g1 ;\ 842 ldx [%g3 + MMFSA_I_CTX], %g3 ;\ 843 sllx %g3, SFSR_CTX_SHIFT, %g3 ;\ 844 or %g3, %g1, %g3 ;\ 845 ba,pt %xcc, .mmu_exception_end ;\ 846 mov T_INSTR_EXCEPTION, %g1 ;\ 847 .align 32 848 849/* 850 * synthesize for trap(): TAG_ACCESS in %g2, SFSR in %g3 851 */ 852#define DMMU_EXCEPTION \ 853 ba,a,pt %xcc, .dmmu_exception ;\ 854 .align 32 855 856/* 857 * synthesize for trap(): SFAR in %g2, SFSR in %g3 858 */ 859#define DMMU_EXC_AG_PRIV \ 860 MMU_FAULT_STATUS_AREA(%g3) ;\ 861 ldx [%g3 + MMFSA_D_ADDR], %g2 ;\ 862 /* Fault type not available in MMU fault status area */ ;\ 863 mov MMFSA_F_PRVACT, %g1 ;\ 864 ldx [%g3 + MMFSA_D_CTX], %g3 ;\ 865 sllx %g3, SFSR_CTX_SHIFT, %g3 ;\ 866 ba,pt %xcc, .mmu_priv_exception ;\ 867 or %g3, %g1, %g3 ;\ 868 .align 32 869 870/* 871 * synthesize for trap(): SFAR in %g2, SFSR in %g3 872 */ 873#define DMMU_EXC_AG_NOT_ALIGNED \ 874 MMU_FAULT_STATUS_AREA(%g3) ;\ 875 ldx [%g3 + MMFSA_D_ADDR], %g2 ;\ 876 /* Fault type not available in MMU fault status area */ ;\ 877 mov MMFSA_F_UNALIGN, %g1 ;\ 878 ldx [%g3 + MMFSA_D_CTX], %g3 ;\ 879 sllx %g3, SFSR_CTX_SHIFT, %g3 ;\ 880 ba,pt %xcc, .mmu_exception_not_aligned ;\ 881 or %g3, %g1, %g3 /* SFSR */ ;\ 882 .align 32 883/* 884 * SPARC V9 IMPL. DEP. #109(1) and (2) and #110(1) and (2) 885 */ 886 887/* 888 * synthesize for trap(): SFAR in %g2, SFSR in %g3 889 */ 890#define DMMU_EXC_LDDF_NOT_ALIGNED \ 891 ba,a,pt %xcc, .dmmu_exc_lddf_not_aligned ;\ 892 .align 32 893/* 894 * synthesize for trap(): SFAR in %g2, SFSR in %g3 895 */ 896#define DMMU_EXC_STDF_NOT_ALIGNED \ 897 ba,a,pt %xcc, .dmmu_exc_stdf_not_aligned ;\ 898 .align 32 899 900#if TAGACC_CTX_MASK != CTXREG_CTX_MASK 901#error "TAGACC_CTX_MASK != CTXREG_CTX_MASK" 902#endif 903 904#if defined(cscope) 905/* 906 * Define labels to direct cscope quickly to labels that 907 * are generated by macro expansion of DTLB_MISS(). 908 */ 909 .global tt0_dtlbmiss 910tt0_dtlbmiss: 911 .global tt1_dtlbmiss 912tt1_dtlbmiss: 913 nop 914#endif 915 916/* 917 * Data miss handler (must be exactly 32 instructions) 918 * 919 * This handler is invoked only if the hypervisor has been instructed 920 * not to do any TSB walk. 921 * 922 * Kernel and invalid context cases are handled by the sfmmu_kdtlb_miss 923 * handler. 924 * 925 * User TLB miss handling depends upon whether a user process has one or 926 * two TSBs. User TSB information (physical base and size code) is kept 927 * in two dedicated scratchpad registers. Absence of a user TSB (primarily 928 * second TSB) is indicated by a negative value (-1) in that register. 929 */ 930 931/* 932 * synthesize for miss handler: TAG_ACCESS in %g2 933 */ 934#define DTLB_MISS(table_name) ;\ 935 .global table_name/**/_dtlbmiss ;\ 936table_name/**/_dtlbmiss: ;\ 937 HAT_PERCPU_DBSTAT(TSBMISS_DTLBMISS) /* 3 instr ifdef DEBUG */ ;\ 938 MMU_FAULT_STATUS_AREA(%g7) ;\ 939 ldx [%g7 + MMFSA_D_ADDR], %g2 /* address */ ;\ 940 ldx [%g7 + MMFSA_D_CTX], %g3 /* g3 = ctx */ ;\ 941 srlx %g2, MMU_PAGESHIFT, %g2 /* align address */ ;\ 942 sllx %g2, MMU_PAGESHIFT, %g2 ;\ 943 or %g2, %g3, %g2 /* TAG_ACCESS */ ;\ 944 cmp %g3, INVALID_CONTEXT ;\ 945 ble,pn %xcc, sfmmu_kdtlb_miss ;\ 946 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 947 mov SCRATCHPAD_UTSBREG2, %g1 ;\ 948 ldxa [%g1]ASI_SCRATCHPAD, %g1 /* get 2nd tsbreg */ ;\ 949 brgez,pn %g1, sfmmu_udtlb_slowpath /* brnach if 2 TSBs */ ;\ 950 nop ;\ 951 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5) /* 11 instr */ ;\ 952 ba,pt %xcc, sfmmu_udtlb_fastpath /* no 4M TSB, miss */ ;\ 953 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 954 .align 128 955 956 957#if defined(cscope) 958/* 959 * Define labels to direct cscope quickly to labels that 960 * are generated by macro expansion of ITLB_MISS(). 961 */ 962 .global tt0_itlbmiss 963tt0_itlbmiss: 964 .global tt1_itlbmiss 965tt1_itlbmiss: 966 nop 967#endif 968 969/* 970 * Instruction miss handler. 971 * 972 * This handler is invoked only if the hypervisor has been instructed 973 * not to do any TSB walk. 974 * 975 * ldda instructions will have their ASI patched 976 * by sfmmu_patch_ktsb at runtime. 977 * MUST be EXACTLY 32 instructions or we'll break. 978 */ 979 980/* 981 * synthesize for miss handler: TAG_ACCESS in %g2 982 */ 983#define ITLB_MISS(table_name) \ 984 .global table_name/**/_itlbmiss ;\ 985table_name/**/_itlbmiss: ;\ 986 HAT_PERCPU_DBSTAT(TSBMISS_ITLBMISS) /* 3 instr ifdef DEBUG */ ;\ 987 MMU_FAULT_STATUS_AREA(%g7) ;\ 988 ldx [%g7 + MMFSA_I_ADDR], %g2 /* g2 = address */ ;\ 989 ldx [%g7 + MMFSA_I_CTX], %g3 /* g3 = ctx */ ;\ 990 srlx %g2, MMU_PAGESHIFT, %g2 /* align address */ ;\ 991 sllx %g2, MMU_PAGESHIFT, %g2 ;\ 992 or %g2, %g3, %g2 /* TAG_ACCESS */ ;\ 993 cmp %g3, INVALID_CONTEXT ;\ 994 ble,pn %xcc, sfmmu_kitlb_miss ;\ 995 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 996 mov SCRATCHPAD_UTSBREG2, %g1 ;\ 997 ldxa [%g1]ASI_SCRATCHPAD, %g1 /* get 2nd tsbreg */ ;\ 998 brgez,pn %g1, sfmmu_uitlb_slowpath /* branch if 2 TSBS */ ;\ 999 nop ;\ 1000 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5) /* 11 instr */ ;\ 1001 ba,pt %xcc, sfmmu_uitlb_fastpath /* no 4M TSB, miss */ ;\ 1002 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 1003 .align 128 1004 1005#define DTSB_MISS \ 1006 GOTO_TT(sfmmu_slow_dmmu_miss,trace_dmmu) 1007 1008#define ITSB_MISS \ 1009 GOTO_TT(sfmmu_slow_immu_miss,trace_immu) 1010 1011/* 1012 * This macro is the first level handler for fast protection faults. 1013 * It first demaps the tlb entry which generated the fault and then 1014 * attempts to set the modify bit on the hash. It needs to be 1015 * exactly 32 instructions. 1016 */ 1017/* 1018 * synthesize for miss handler: TAG_ACCESS in %g2 1019 */ 1020#define DTLB_PROT \ 1021 MMU_FAULT_STATUS_AREA(%g7) ;\ 1022 ldx [%g7 + MMFSA_D_ADDR], %g2 /* address */ ;\ 1023 ldx [%g7 + MMFSA_D_CTX], %g3 /* %g3 = ctx */ ;\ 1024 srlx %g2, MMU_PAGESHIFT, %g2 /* align address */ ;\ 1025 sllx %g2, MMU_PAGESHIFT, %g2 ;\ 1026 or %g2, %g3, %g2 /* TAG_ACCESS */ ;\ 1027 /* ;\ 1028 * g2 = tag access register ;\ 1029 * g3 = ctx number ;\ 1030 */ ;\ 1031 TT_TRACE(trace_dataprot) /* 2 instr ifdef TRAPTRACE */ ;\ 1032 /* clobbers g1 and g6 XXXQ? */ ;\ 1033 brnz,pt %g3, sfmmu_uprot_trap /* user trap */ ;\ 1034 nop ;\ 1035 ba,a,pt %xcc, sfmmu_kprot_trap /* kernel trap */ ;\ 1036 .align 128 1037 1038#define DMMU_EXCEPTION_TL1 ;\ 1039 ba,a,pt %xcc, mmu_trap_tl1 ;\ 1040 .align 32 1041 1042#define MISALIGN_ADDR_TL1 ;\ 1043 ba,a,pt %xcc, mmu_trap_tl1 ;\ 1044 .align 32 1045 1046/* 1047 * Trace a tsb hit 1048 * g1 = tsbe pointer (in/clobbered) 1049 * g2 = tag access register (in) 1050 * g3 - g4 = scratch (clobbered) 1051 * g5 = tsbe data (in) 1052 * g6 = scratch (clobbered) 1053 * g7 = pc we jumped here from (in) 1054 * ttextra = value to OR in to trap type (%tt) (in) 1055 */ 1056#ifdef TRAPTRACE 1057#define TRACE_TSBHIT(ttextra) \ 1058 membar #Sync ;\ 1059 sethi %hi(FLUSH_ADDR), %g6 ;\ 1060 flush %g6 ;\ 1061 TRACE_PTR(%g3, %g6) ;\ 1062 GET_TRACE_TICK(%g6) ;\ 1063 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi ;\ 1064 stna %g2, [%g3 + TRAP_ENT_SP]%asi /* tag access */ ;\ 1065 stna %g5, [%g3 + TRAP_ENT_F1]%asi /* tsb data */ ;\ 1066 rdpr %tnpc, %g6 ;\ 1067 stna %g6, [%g3 + TRAP_ENT_F2]%asi ;\ 1068 stna %g1, [%g3 + TRAP_ENT_F3]%asi /* tsb pointer */ ;\ 1069 stna %g0, [%g3 + TRAP_ENT_F4]%asi ;\ 1070 rdpr %tpc, %g6 ;\ 1071 stna %g6, [%g3 + TRAP_ENT_TPC]%asi ;\ 1072 TRACE_SAVE_TL_GL_REGS(%g3, %g6) ;\ 1073 rdpr %tt, %g6 ;\ 1074 or %g6, (ttextra), %g1 ;\ 1075 stha %g1, [%g3 + TRAP_ENT_TT]%asi ;\ 1076 MMU_FAULT_STATUS_AREA(%g4) ;\ 1077 mov MMFSA_D_ADDR, %g1 ;\ 1078 cmp %g6, FAST_IMMU_MISS_TT ;\ 1079 move %xcc, MMFSA_I_ADDR, %g1 ;\ 1080 cmp %g6, T_INSTR_MMU_MISS ;\ 1081 move %xcc, MMFSA_I_ADDR, %g1 ;\ 1082 ldx [%g4 + %g1], %g1 ;\ 1083 stxa %g1, [%g3 + TRAP_ENT_TSTATE]%asi /* fault addr */ ;\ 1084 mov MMFSA_D_CTX, %g1 ;\ 1085 cmp %g6, FAST_IMMU_MISS_TT ;\ 1086 move %xcc, MMFSA_I_CTX, %g1 ;\ 1087 cmp %g6, T_INSTR_MMU_MISS ;\ 1088 move %xcc, MMFSA_I_CTX, %g1 ;\ 1089 ldx [%g4 + %g1], %g1 ;\ 1090 stna %g1, [%g3 + TRAP_ENT_TR]%asi ;\ 1091 TRACE_NEXT(%g3, %g4, %g6) 1092#else 1093#define TRACE_TSBHIT(ttextra) 1094#endif 1095 1096 1097#if defined(lint) 1098 1099struct scb trap_table; 1100struct scb scb; /* trap_table/scb are the same object */ 1101 1102#else /* lint */ 1103 1104/* 1105 * ======================================================================= 1106 * SPARC V9 TRAP TABLE 1107 * 1108 * The trap table is divided into two halves: the first half is used when 1109 * taking traps when TL=0; the second half is used when taking traps from 1110 * TL>0. Note that handlers in the second half of the table might not be able 1111 * to make the same assumptions as handlers in the first half of the table. 1112 * 1113 * Worst case trap nesting so far: 1114 * 1115 * at TL=0 client issues software trap requesting service 1116 * at TL=1 nucleus wants a register window 1117 * at TL=2 register window clean/spill/fill takes a TLB miss 1118 * at TL=3 processing TLB miss 1119 * at TL=4 handle asynchronous error 1120 * 1121 * Note that a trap from TL=4 to TL=5 places Spitfire in "RED mode". 1122 * 1123 * ======================================================================= 1124 */ 1125 .section ".text" 1126 .align 4 1127 .global trap_table, scb, trap_table0, trap_table1, etrap_table 1128 .type trap_table, #object 1129 .type trap_table0, #object 1130 .type trap_table1, #object 1131 .type scb, #object 1132trap_table: 1133scb: 1134trap_table0: 1135 /* hardware traps */ 1136 NOT; /* 000 reserved */ 1137 RED; /* 001 power on reset */ 1138 WATCHDOG_RESET; /* 002 watchdog reset */ 1139 RED; /* 003 externally initiated reset */ 1140 RED; /* 004 software initiated reset */ 1141 RED; /* 005 red mode exception */ 1142 NOT; NOT; /* 006 - 007 reserved */ 1143 IMMU_EXCEPTION; /* 008 instruction access exception */ 1144 ITSB_MISS; /* 009 instruction access MMU miss */ 1145 NOT; /* 00A reserved */ 1146 NOT; NOT4; /* 00B - 00F reserved */ 1147 ILLTRAP_INSTR; /* 010 illegal instruction */ 1148 TRAP(T_PRIV_INSTR); /* 011 privileged opcode */ 1149 TRAP(T_UNIMP_LDD); /* 012 unimplemented LDD */ 1150 TRAP(T_UNIMP_STD); /* 013 unimplemented STD */ 1151 NOT4; NOT4; NOT4; /* 014 - 01F reserved */ 1152 FP_DISABLED_TRAP; /* 020 fp disabled */ 1153 FP_IEEE_TRAP; /* 021 fp exception ieee 754 */ 1154 FP_TRAP; /* 022 fp exception other */ 1155 TAG_OVERFLOW; /* 023 tag overflow */ 1156 CLEAN_WINDOW; /* 024 - 027 clean window */ 1157 DIV_BY_ZERO; /* 028 division by zero */ 1158 NOT; /* 029 internal processor error */ 1159 NOT; NOT; NOT4; /* 02A - 02F reserved */ 1160 DMMU_EXCEPTION; /* 030 data access exception */ 1161 DTSB_MISS; /* 031 data access MMU miss */ 1162 NOT; /* 032 reserved */ 1163 NOT; /* 033 data access protection */ 1164 DMMU_EXC_AG_NOT_ALIGNED; /* 034 mem address not aligned */ 1165 DMMU_EXC_LDDF_NOT_ALIGNED; /* 035 LDDF mem address not aligned */ 1166 DMMU_EXC_STDF_NOT_ALIGNED; /* 036 STDF mem address not aligned */ 1167 DMMU_EXC_AG_PRIV; /* 037 privileged action */ 1168 NOT; /* 038 LDQF mem address not aligned */ 1169 NOT; /* 039 STQF mem address not aligned */ 1170 NOT; NOT; NOT4; /* 03A - 03F reserved */ 1171 NOT; /* 040 async data error */ 1172 LEVEL_INTERRUPT(1); /* 041 interrupt level 1 */ 1173 LEVEL_INTERRUPT(2); /* 042 interrupt level 2 */ 1174 LEVEL_INTERRUPT(3); /* 043 interrupt level 3 */ 1175 LEVEL_INTERRUPT(4); /* 044 interrupt level 4 */ 1176 LEVEL_INTERRUPT(5); /* 045 interrupt level 5 */ 1177 LEVEL_INTERRUPT(6); /* 046 interrupt level 6 */ 1178 LEVEL_INTERRUPT(7); /* 047 interrupt level 7 */ 1179 LEVEL_INTERRUPT(8); /* 048 interrupt level 8 */ 1180 LEVEL_INTERRUPT(9); /* 049 interrupt level 9 */ 1181 LEVEL_INTERRUPT(10); /* 04A interrupt level 10 */ 1182 LEVEL_INTERRUPT(11); /* 04B interrupt level 11 */ 1183 LEVEL_INTERRUPT(12); /* 04C interrupt level 12 */ 1184 LEVEL_INTERRUPT(13); /* 04D interrupt level 13 */ 1185 LEVEL14_INTERRUPT; /* 04E interrupt level 14 */ 1186 LEVEL_INTERRUPT(15); /* 04F interrupt level 15 */ 1187 NOT4; NOT4; NOT4; NOT4; /* 050 - 05F reserved */ 1188 NOT; /* 060 interrupt vector */ 1189 GOTO(kmdb_trap); /* 061 PA watchpoint */ 1190 GOTO(kmdb_trap); /* 062 VA watchpoint */ 1191 NOT; /* 063 reserved */ 1192 ITLB_MISS(tt0); /* 064 instruction access MMU miss */ 1193 DTLB_MISS(tt0); /* 068 data access MMU miss */ 1194 DTLB_PROT; /* 06C data access protection */ 1195 NOT; /* 070 reserved */ 1196 NOT; /* 071 reserved */ 1197 NOT; /* 072 reserved */ 1198 NOT; /* 073 reserved */ 1199 NOT4; NOT4 /* 074 - 07B reserved */ 1200 CPU_MONDO; /* 07C cpu_mondo */ 1201 DEV_MONDO; /* 07D dev_mondo */ 1202 GOTO_TT(resumable_error, trace_gen); /* 07E resumable error */ 1203 GOTO_TT(nonresumable_error, trace_gen); /* 07F non-reasumable error */ 1204 NOT4; /* 080 spill 0 normal */ 1205 SPILL_32bit_asi(ASI_AIUP,sn0); /* 084 spill 1 normal */ 1206 SPILL_64bit_asi(ASI_AIUP,sn0); /* 088 spill 2 normal */ 1207 SPILL_32clean(ASI_AIUP,sn0); /* 08C spill 3 normal */ 1208 SPILL_64clean(ASI_AIUP,sn0); /* 090 spill 4 normal */ 1209 SPILL_32bit(not); /* 094 spill 5 normal */ 1210 SPILL_64bit(not); /* 098 spill 6 normal */ 1211 SPILL_mixed; /* 09C spill 7 normal */ 1212 NOT4; /* 0A0 spill 0 other */ 1213 SPILL_32bit_asi(ASI_AIUS,so0); /* 0A4 spill 1 other */ 1214 SPILL_64bit_asi(ASI_AIUS,so0); /* 0A8 spill 2 other */ 1215 SPILL_32bit_asi(ASI_AIUS,so0); /* 0AC spill 3 other */ 1216 SPILL_64bit_asi(ASI_AIUS,so0); /* 0B0 spill 4 other */ 1217 NOT4; /* 0B4 spill 5 other */ 1218 NOT4; /* 0B8 spill 6 other */ 1219 NOT4; /* 0BC spill 7 other */ 1220 NOT4; /* 0C0 fill 0 normal */ 1221 FILL_32bit_asi(ASI_AIUP,fn0); /* 0C4 fill 1 normal */ 1222 FILL_64bit_asi(ASI_AIUP,fn0); /* 0C8 fill 2 normal */ 1223 FILL_32bit_asi(ASI_AIUP,fn0); /* 0CC fill 3 normal */ 1224 FILL_64bit_asi(ASI_AIUP,fn0); /* 0D0 fill 4 normal */ 1225 FILL_32bit(not); /* 0D4 fill 5 normal */ 1226 FILL_64bit(not); /* 0D8 fill 6 normal */ 1227 FILL_mixed; /* 0DC fill 7 normal */ 1228 NOT4; /* 0E0 fill 0 other */ 1229 NOT4; /* 0E4 fill 1 other */ 1230 NOT4; /* 0E8 fill 2 other */ 1231 NOT4; /* 0EC fill 3 other */ 1232 NOT4; /* 0F0 fill 4 other */ 1233 NOT4; /* 0F4 fill 5 other */ 1234 NOT4; /* 0F8 fill 6 other */ 1235 NOT4; /* 0FC fill 7 other */ 1236 /* user traps */ 1237 GOTO(syscall_trap_4x); /* 100 old system call */ 1238 TRAP(T_BREAKPOINT); /* 101 user breakpoint */ 1239 TRAP(T_DIV0); /* 102 user divide by zero */ 1240 GOTO(.flushw); /* 103 flush windows */ 1241 GOTO(.clean_windows); /* 104 clean windows */ 1242 BAD; /* 105 range check ?? */ 1243 GOTO(.fix_alignment); /* 106 do unaligned references */ 1244 BAD; /* 107 unused */ 1245 SYSCALL(syscall_trap32); /* 108 ILP32 system call on LP64 */ 1246 GOTO(set_trap0_addr); /* 109 set trap0 address */ 1247 BAD; BAD; BAD4; /* 10A - 10F unused */ 1248 TRP4; TRP4; TRP4; TRP4; /* 110 - 11F V9 user trap handlers */ 1249 GOTO(.getcc); /* 120 get condition codes */ 1250 GOTO(.setcc); /* 121 set condition codes */ 1251 GOTO(.getpsr); /* 122 get psr */ 1252 GOTO(.setpsr); /* 123 set psr (some fields) */ 1253 GOTO(get_timestamp); /* 124 get timestamp */ 1254 GOTO(get_virtime); /* 125 get lwp virtual time */ 1255 PRIV(self_xcall); /* 126 self xcall */ 1256 GOTO(get_hrestime); /* 127 get hrestime */ 1257 BAD; /* 128 ST_SETV9STACK */ 1258 GOTO(.getlgrp); /* 129 get lgrpid */ 1259 BAD; BAD; BAD4; /* 12A - 12F unused */ 1260 BAD4; BAD4; /* 130 - 137 unused */ 1261 DTRACE_PID; /* 138 dtrace pid tracing provider */ 1262 BAD; /* 139 unused */ 1263 DTRACE_RETURN; /* 13A dtrace pid return probe */ 1264 BAD; BAD4; /* 13B - 13F unused */ 1265 SYSCALL(syscall_trap) /* 140 LP64 system call */ 1266 SYSCALL(nosys); /* 141 unused system call trap */ 1267#ifdef DEBUG_USER_TRAPTRACECTL 1268 GOTO(.traptrace_freeze); /* 142 freeze traptrace */ 1269 GOTO(.traptrace_unfreeze); /* 143 unfreeze traptrace */ 1270#else 1271 SYSCALL(nosys); /* 142 unused system call trap */ 1272 SYSCALL(nosys); /* 143 unused system call trap */ 1273#endif 1274 BAD4; BAD4; BAD4; /* 144 - 14F unused */ 1275 BAD4; BAD4; BAD4; BAD4; /* 150 - 15F unused */ 1276 BAD4; BAD4; BAD4; BAD4; /* 160 - 16F unused */ 1277 BAD; /* 170 - unused */ 1278 BAD; /* 171 - unused */ 1279 BAD; BAD; /* 172 - 173 unused */ 1280 BAD4; BAD4; /* 174 - 17B unused */ 1281#ifdef PTL1_PANIC_DEBUG 1282 mov PTL1_BAD_DEBUG, %g1; GOTO(ptl1_panic); 1283 /* 17C test ptl1_panic */ 1284#else 1285 BAD; /* 17C unused */ 1286#endif /* PTL1_PANIC_DEBUG */ 1287 PRIV(kmdb_trap); /* 17D kmdb enter (L1-A) */ 1288 PRIV(kmdb_trap); /* 17E kmdb breakpoint */ 1289 PRIV(obp_bpt); /* 17F obp breakpoint */ 1290 /* reserved */ 1291 NOT4; NOT4; NOT4; NOT4; /* 180 - 18F reserved */ 1292 NOT4; NOT4; NOT4; NOT4; /* 190 - 19F reserved */ 1293 NOT4; NOT4; NOT4; NOT4; /* 1A0 - 1AF reserved */ 1294 NOT4; NOT4; NOT4; NOT4; /* 1B0 - 1BF reserved */ 1295 NOT4; NOT4; NOT4; NOT4; /* 1C0 - 1CF reserved */ 1296 NOT4; NOT4; NOT4; NOT4; /* 1D0 - 1DF reserved */ 1297 NOT4; NOT4; NOT4; NOT4; /* 1E0 - 1EF reserved */ 1298 NOT4; NOT4; NOT4; NOT4; /* 1F0 - 1FF reserved */ 1299 .size trap_table0, (.-trap_table0) 1300trap_table1: 1301 NOT4; NOT4; /* 000 - 007 unused */ 1302 NOT; /* 008 instruction access exception */ 1303 ITSB_MISS; /* 009 instruction access MMU miss */ 1304 NOT; /* 00A reserved */ 1305 NOT; NOT4; /* 00B - 00F unused */ 1306 NOT4; NOT4; NOT4; NOT4; /* 010 - 01F unused */ 1307 NOT4; /* 020 - 023 unused */ 1308 CLEAN_WINDOW; /* 024 - 027 clean window */ 1309 NOT4; NOT4; /* 028 - 02F unused */ 1310 DMMU_EXCEPTION_TL1; /* 030 data access exception */ 1311 DTSB_MISS; /* 031 data access MMU miss */ 1312 NOT; /* 032 reserved */ 1313 NOT; /* 033 unused */ 1314 MISALIGN_ADDR_TL1; /* 034 mem address not aligned */ 1315 NOT; NOT; NOT; NOT4; NOT4 /* 035 - 03F unused */ 1316 NOT4; NOT4; NOT4; NOT4; /* 040 - 04F unused */ 1317 NOT4; NOT4; NOT4; NOT4; /* 050 - 05F unused */ 1318 NOT; /* 060 unused */ 1319 GOTO(kmdb_trap_tl1); /* 061 PA watchpoint */ 1320 GOTO(kmdb_trap_tl1); /* 062 VA watchpoint */ 1321 NOT; /* 063 reserved */ 1322 ITLB_MISS(tt1); /* 064 instruction access MMU miss */ 1323 DTLB_MISS(tt1); /* 068 data access MMU miss */ 1324 DTLB_PROT; /* 06C data access protection */ 1325 NOT; /* 070 reserved */ 1326 NOT; /* 071 reserved */ 1327 NOT; /* 072 reserved */ 1328 NOT; /* 073 reserved */ 1329 NOT4; NOT4; /* 074 - 07B reserved */ 1330 NOT; /* 07C reserved */ 1331 NOT; /* 07D reserved */ 1332 NOT; /* 07E resumable error */ 1333 GOTO_TT(nonresumable_error, trace_gen); /* 07F nonresumable error */ 1334 NOTP4; /* 080 spill 0 normal */ 1335 SPILL_32bit_tt1(ASI_AIUP,sn1); /* 084 spill 1 normal */ 1336 SPILL_64bit_tt1(ASI_AIUP,sn1); /* 088 spill 2 normal */ 1337 SPILL_32bit_tt1(ASI_AIUP,sn1); /* 08C spill 3 normal */ 1338 SPILL_64bit_tt1(ASI_AIUP,sn1); /* 090 spill 4 normal */ 1339 NOTP4; /* 094 spill 5 normal */ 1340 SPILL_64bit_ktt1(sk); /* 098 spill 6 normal */ 1341 SPILL_mixed_ktt1(sk); /* 09C spill 7 normal */ 1342 NOTP4; /* 0A0 spill 0 other */ 1343 SPILL_32bit_tt1(ASI_AIUS,so1); /* 0A4 spill 1 other */ 1344 SPILL_64bit_tt1(ASI_AIUS,so1); /* 0A8 spill 2 other */ 1345 SPILL_32bit_tt1(ASI_AIUS,so1); /* 0AC spill 3 other */ 1346 SPILL_64bit_tt1(ASI_AIUS,so1); /* 0B0 spill 4 other */ 1347 NOTP4; /* 0B4 spill 5 other */ 1348 NOTP4; /* 0B8 spill 6 other */ 1349 NOTP4; /* 0BC spill 7 other */ 1350 NOT4; /* 0C0 fill 0 normal */ 1351 NOT4; /* 0C4 fill 1 normal */ 1352 NOT4; /* 0C8 fill 2 normal */ 1353 NOT4; /* 0CC fill 3 normal */ 1354 NOT4; /* 0D0 fill 4 normal */ 1355 NOT4; /* 0D4 fill 5 normal */ 1356 NOT4; /* 0D8 fill 6 normal */ 1357 NOT4; /* 0DC fill 7 normal */ 1358 NOT4; NOT4; NOT4; NOT4; /* 0E0 - 0EF unused */ 1359 NOT4; NOT4; NOT4; NOT4; /* 0F0 - 0FF unused */ 1360/* 1361 * Code running at TL>0 does not use soft traps, so 1362 * we can truncate the table here. 1363 * However: 1364 * sun4v uses (hypervisor) ta instructions at TL > 0, so 1365 * provide a safety net for now. 1366 */ 1367 /* soft traps */ 1368 BAD4; BAD4; BAD4; BAD4; /* 100 - 10F unused */ 1369 BAD4; BAD4; BAD4; BAD4; /* 110 - 11F unused */ 1370 BAD4; BAD4; BAD4; BAD4; /* 120 - 12F unused */ 1371 BAD4; BAD4; BAD4; BAD4; /* 130 - 13F unused */ 1372 BAD4; BAD4; BAD4; BAD4; /* 140 - 14F unused */ 1373 BAD4; BAD4; BAD4; BAD4; /* 150 - 15F unused */ 1374 BAD4; BAD4; BAD4; BAD4; /* 160 - 16F unused */ 1375 BAD4; BAD4; BAD4; BAD4; /* 170 - 17F unused */ 1376 /* reserved */ 1377 NOT4; NOT4; NOT4; NOT4; /* 180 - 18F reserved */ 1378 NOT4; NOT4; NOT4; NOT4; /* 190 - 19F reserved */ 1379 NOT4; NOT4; NOT4; NOT4; /* 1A0 - 1AF reserved */ 1380 NOT4; NOT4; NOT4; NOT4; /* 1B0 - 1BF reserved */ 1381 NOT4; NOT4; NOT4; NOT4; /* 1C0 - 1CF reserved */ 1382 NOT4; NOT4; NOT4; NOT4; /* 1D0 - 1DF reserved */ 1383 NOT4; NOT4; NOT4; NOT4; /* 1E0 - 1EF reserved */ 1384 NOT4; NOT4; NOT4; NOT4; /* 1F0 - 1FF reserved */ 1385etrap_table: 1386 .size trap_table1, (.-trap_table1) 1387 .size trap_table, (.-trap_table) 1388 .size scb, (.-scb) 1389 1390/* 1391 * We get to exec_fault in the case of an instruction miss and tte 1392 * has no execute bit set. We go to tl0 to handle it. 1393 * 1394 * g1 = tsbe pointer (in/clobbered) 1395 * g2 = tag access register (in) 1396 * g3 - g4 = scratch (clobbered) 1397 * g5 = tsbe data (in) 1398 * g6 = scratch (clobbered) 1399 * g7 = pc we jumped here from (in) 1400 */ 1401/* 1402 * synthesize for trap(): TAG_ACCESS in %g2 1403 */ 1404 ALTENTRY(exec_fault) 1405 TRACE_TSBHIT(TT_MMU_EXEC) 1406 MMU_FAULT_STATUS_AREA(%g4) 1407 ldx [%g4 + MMFSA_I_ADDR], %g2 /* g2 = address */ 1408 ldx [%g4 + MMFSA_I_CTX], %g3 /* g3 = ctx */ 1409 srlx %g2, MMU_PAGESHIFT, %g2 ! align address to page boundry 1410 sllx %g2, MMU_PAGESHIFT, %g2 1411 or %g2, %g3, %g2 /* TAG_ACCESS */ 1412 mov T_INSTR_MMU_MISS, %g3 ! arg2 = traptype 1413 set trap, %g1 1414 ba,pt %xcc, sys_trap 1415 mov -1, %g4 1416 1417.mmu_exception_not_aligned: 1418 /* %g2 = sfar, %g3 = sfsr */ 1419 rdpr %tstate, %g1 1420 btst TSTATE_PRIV, %g1 1421 bnz,pn %icc, 2f 1422 nop 1423 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1424 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1425 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1426 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1427 brz,pt %g5, 2f 1428 nop 1429 ldn [%g5 + P_UTRAP15], %g5 ! unaligned utrap? 1430 brz,pn %g5, 2f 1431 nop 1432 btst 1, %sp 1433 bz,pt %xcc, 1f ! 32 bit user program 1434 nop 1435 ba,pt %xcc, .setup_v9utrap ! 64 bit user program 1436 nop 14371: 1438 ba,pt %xcc, .setup_utrap 1439 or %g2, %g0, %g7 14402: 1441 ba,pt %xcc, .mmu_exception_end 1442 mov T_ALIGNMENT, %g1 1443 1444.mmu_priv_exception: 1445 rdpr %tstate, %g1 1446 btst TSTATE_PRIV, %g1 1447 bnz,pn %icc, 1f 1448 nop 1449 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1450 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1451 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1452 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1453 brz,pt %g5, 1f 1454 nop 1455 ldn [%g5 + P_UTRAP16], %g5 1456 brnz,pt %g5, .setup_v9utrap 1457 nop 14581: 1459 mov T_PRIV_INSTR, %g1 1460 1461.mmu_exception_end: 1462 CPU_INDEX(%g4, %g5) 1463 set cpu_core, %g5 1464 sllx %g4, CPU_CORE_SHIFT, %g4 1465 add %g4, %g5, %g4 1466 lduh [%g4 + CPUC_DTRACE_FLAGS], %g5 1467 andcc %g5, CPU_DTRACE_NOFAULT, %g0 1468 bz 1f 1469 or %g5, CPU_DTRACE_BADADDR, %g5 1470 stuh %g5, [%g4 + CPUC_DTRACE_FLAGS] 1471 done 1472 14731: 1474 sllx %g3, 32, %g3 1475 or %g3, %g1, %g3 1476 set trap, %g1 1477 ba,pt %xcc, sys_trap 1478 sub %g0, 1, %g4 1479 1480.fp_disabled: 1481 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1482 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1483 rdpr %tstate, %g4 1484 btst TSTATE_PRIV, %g4 1485 bnz,a,pn %icc, ptl1_panic 1486 mov PTL1_BAD_FPTRAP, %g1 1487 1488 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1489 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1490 brz,a,pt %g5, 2f 1491 nop 1492 ldn [%g5 + P_UTRAP7], %g5 ! fp_disabled utrap? 1493 brz,a,pn %g5, 2f 1494 nop 1495 btst 1, %sp 1496 bz,a,pt %xcc, 1f ! 32 bit user program 1497 nop 1498 ba,a,pt %xcc, .setup_v9utrap ! 64 bit user program 1499 nop 15001: 1501 ba,pt %xcc, .setup_utrap 1502 or %g0, %g0, %g7 15032: 1504 set fp_disabled, %g1 1505 ba,pt %xcc, sys_trap 1506 sub %g0, 1, %g4 1507 1508.fp_ieee_exception: 1509 rdpr %tstate, %g1 1510 btst TSTATE_PRIV, %g1 1511 bnz,a,pn %icc, ptl1_panic 1512 mov PTL1_BAD_FPTRAP, %g1 1513 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1514 stx %fsr, [%g1 + CPU_TMP1] 1515 ldx [%g1 + CPU_TMP1], %g2 1516 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1517 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1518 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1519 brz,a,pt %g5, 1f 1520 nop 1521 ldn [%g5 + P_UTRAP8], %g5 1522 brnz,a,pt %g5, .setup_v9utrap 1523 nop 15241: 1525 set _fp_ieee_exception, %g1 1526 ba,pt %xcc, sys_trap 1527 sub %g0, 1, %g4 1528 1529/* 1530 * Register Inputs: 1531 * %g5 user trap handler 1532 * %g7 misaligned addr - for alignment traps only 1533 */ 1534.setup_utrap: 1535 set trap, %g1 ! setup in case we go 1536 mov T_FLUSH_PCB, %g3 ! through sys_trap on 1537 sub %g0, 1, %g4 ! the save instruction below 1538 1539 /* 1540 * If the DTrace pid provider is single stepping a copied-out 1541 * instruction, t->t_dtrace_step will be set. In that case we need 1542 * to abort the single-stepping (since execution of the instruction 1543 * was interrupted) and use the value of t->t_dtrace_npc as the %npc. 1544 */ 1545 save %sp, -SA(MINFRAME32), %sp ! window for trap handler 1546 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1547 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1548 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step 1549 rdpr %tnpc, %l2 ! arg1 == tnpc 1550 brz,pt %g2, 1f 1551 rdpr %tpc, %l1 ! arg0 == tpc 1552 1553 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast 1554 ldn [%g1 + T_DTRACE_NPC], %l2 ! arg1 = t->t_dtrace_npc (step) 1555 brz,pt %g2, 1f 1556 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags 1557 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast 15581: 1559 mov %g7, %l3 ! arg2 == misaligned address 1560 1561 rdpr %tstate, %g1 ! cwp for trap handler 1562 rdpr %cwp, %g4 1563 bclr TSTATE_CWP_MASK, %g1 1564 wrpr %g1, %g4, %tstate 1565 wrpr %g0, %g5, %tnpc ! trap handler address 1566 FAST_TRAP_DONE 1567 /* NOTREACHED */ 1568 1569.check_v9utrap: 1570 rdpr %tstate, %g1 1571 btst TSTATE_PRIV, %g1 1572 bnz,a,pn %icc, 3f 1573 nop 1574 CPU_ADDR(%g4, %g1) ! load CPU struct addr 1575 ldn [%g4 + CPU_THREAD], %g5 ! load thread pointer 1576 ldn [%g5 + T_PROCP], %g5 ! load proc pointer 1577 ldn [%g5 + P_UTRAPS], %g5 ! are there utraps? 1578 1579 cmp %g3, T_SOFTWARE_TRAP 1580 bne,a,pt %icc, 1f 1581 nop 1582 1583 brz,pt %g5, 3f ! if p_utraps == NULL goto trap() 1584 rdpr %tt, %g3 ! delay - get actual hw trap type 1585 1586 sub %g3, 254, %g1 ! UT_TRAP_INSTRUCTION_16 = p_utraps[18] 1587 ba,pt %icc, 2f 1588 smul %g1, CPTRSIZE, %g2 15891: 1590 brz,a,pt %g5, 3f ! if p_utraps == NULL goto trap() 1591 nop 1592 1593 cmp %g3, T_UNIMP_INSTR 1594 bne,a,pt %icc, 2f 1595 nop 1596 1597 mov 1, %g1 1598 st %g1, [%g4 + CPU_TL1_HDLR] ! set CPU_TL1_HDLR 1599 rdpr %tpc, %g1 ! ld trapping instruction using 1600 lduwa [%g1]ASI_AIUP, %g1 ! "AS IF USER" ASI which could fault 1601 st %g0, [%g4 + CPU_TL1_HDLR] ! clr CPU_TL1_HDLR 1602 1603 sethi %hi(0xc1c00000), %g4 ! setup mask for illtrap instruction 1604 andcc %g1, %g4, %g4 ! and instruction with mask 1605 bnz,a,pt %icc, 3f ! if %g4 == zero, %g1 is an ILLTRAP 1606 nop ! fall thru to setup 16072: 1608 ldn [%g5 + %g2], %g5 1609 brnz,a,pt %g5, .setup_v9utrap 1610 nop 16113: 1612 set trap, %g1 1613 ba,pt %xcc, sys_trap 1614 sub %g0, 1, %g4 1615 /* NOTREACHED */ 1616 1617/* 1618 * Register Inputs: 1619 * %g5 user trap handler 1620 */ 1621.setup_v9utrap: 1622 set trap, %g1 ! setup in case we go 1623 mov T_FLUSH_PCB, %g3 ! through sys_trap on 1624 sub %g0, 1, %g4 ! the save instruction below 1625 1626 /* 1627 * If the DTrace pid provider is single stepping a copied-out 1628 * instruction, t->t_dtrace_step will be set. In that case we need 1629 * to abort the single-stepping (since execution of the instruction 1630 * was interrupted) and use the value of t->t_dtrace_npc as the %npc. 1631 */ 1632 save %sp, -SA(MINFRAME64), %sp ! window for trap handler 1633 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1634 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1635 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step 1636 rdpr %tnpc, %l7 ! arg1 == tnpc 1637 brz,pt %g2, 1f 1638 rdpr %tpc, %l6 ! arg0 == tpc 1639 1640 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast 1641 ldn [%g1 + T_DTRACE_NPC], %l7 ! arg1 == t->t_dtrace_npc (step) 1642 brz,pt %g2, 1f 1643 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags 1644 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast 16451: 1646 rdpr %tstate, %g2 ! cwp for trap handler 1647 rdpr %cwp, %g4 1648 bclr TSTATE_CWP_MASK, %g2 1649 wrpr %g2, %g4, %tstate 1650 1651 ldn [%g1 + T_PROCP], %g4 ! load proc pointer 1652 ldn [%g4 + P_AS], %g4 ! load as pointer 1653 ldn [%g4 + A_USERLIMIT], %g4 ! load as userlimit 1654 cmp %l7, %g4 ! check for single-step set 1655 bne,pt %xcc, 4f 1656 nop 1657 ldn [%g1 + T_LWP], %g1 ! load klwp pointer 1658 ld [%g1 + PCB_STEP], %g4 ! load single-step flag 1659 cmp %g4, STEP_ACTIVE ! step flags set in pcb? 1660 bne,pt %icc, 4f 1661 nop 1662 stn %g5, [%g1 + PCB_TRACEPC] ! save trap handler addr in pcb 1663 mov %l7, %g4 ! on entry to precise user trap 1664 add %l6, 4, %l7 ! handler, %l6 == pc, %l7 == npc 1665 ! at time of trap 1666 wrpr %g0, %g4, %tnpc ! generate FLTBOUNDS, 1667 ! %g4 == userlimit 1668 FAST_TRAP_DONE 1669 /* NOTREACHED */ 16704: 1671 wrpr %g0, %g5, %tnpc ! trap handler address 1672 FAST_TRAP_DONE_CHK_INTR 1673 /* NOTREACHED */ 1674 1675.fp_exception: 1676 CPU_ADDR(%g1, %g4) 1677 stx %fsr, [%g1 + CPU_TMP1] 1678 ldx [%g1 + CPU_TMP1], %g2 1679 1680 /* 1681 * Cheetah takes unfinished_FPop trap for certain range of operands 1682 * to the "fitos" instruction. Instead of going through the slow 1683 * software emulation path, we try to simulate the "fitos" instruction 1684 * via "fitod" and "fdtos" provided the following conditions are met: 1685 * 1686 * fpu_exists is set (if DEBUG) 1687 * not in privileged mode 1688 * ftt is unfinished_FPop 1689 * NXM IEEE trap is not enabled 1690 * instruction at %tpc is "fitos" 1691 * 1692 * Usage: 1693 * %g1 per cpu address 1694 * %g2 %fsr 1695 * %g6 user instruction 1696 * 1697 * Note that we can take a memory access related trap while trying 1698 * to fetch the user instruction. Therefore, we set CPU_TL1_HDLR 1699 * flag to catch those traps and let the SFMMU code deal with page 1700 * fault and data access exception. 1701 */ 1702#if defined(DEBUG) || defined(NEED_FPU_EXISTS) 1703 sethi %hi(fpu_exists), %g7 1704 ld [%g7 + %lo(fpu_exists)], %g7 1705 brz,pn %g7, .fp_exception_cont 1706 nop 1707#endif 1708 rdpr %tstate, %g7 ! branch if in privileged mode 1709 btst TSTATE_PRIV, %g7 1710 bnz,pn %xcc, .fp_exception_cont 1711 srl %g2, FSR_FTT_SHIFT, %g7 ! extract ftt from %fsr 1712 and %g7, (FSR_FTT>>FSR_FTT_SHIFT), %g7 1713 cmp %g7, FTT_UNFIN 1714 set FSR_TEM_NX, %g5 1715 bne,pn %xcc, .fp_exception_cont ! branch if NOT unfinished_FPop 1716 andcc %g2, %g5, %g0 1717 bne,pn %xcc, .fp_exception_cont ! branch if FSR_TEM_NX enabled 1718 rdpr %tpc, %g5 ! get faulting PC 1719 1720 or %g0, 1, %g7 1721 st %g7, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag 1722 lda [%g5]ASI_USER, %g6 ! get user's instruction 1723 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 1724 1725 set FITOS_INSTR_MASK, %g7 1726 and %g6, %g7, %g7 1727 set FITOS_INSTR, %g5 1728 cmp %g7, %g5 1729 bne,pn %xcc, .fp_exception_cont ! branch if not FITOS_INSTR 1730 nop 1731 1732 /* 1733 * This is unfinished FPops trap for "fitos" instruction. We 1734 * need to simulate "fitos" via "fitod" and "fdtos" instruction 1735 * sequence. 1736 * 1737 * We need a temporary FP register to do the conversion. Since 1738 * both source and destination operands for the "fitos" instruction 1739 * have to be within %f0-%f31, we use an FP register from the upper 1740 * half to guarantee that it won't collide with the source or the 1741 * dest operand. However, we do have to save and restore its value. 1742 * 1743 * We use %d62 as a temporary FP register for the conversion and 1744 * branch to appropriate instruction within the conversion tables 1745 * based upon the rs2 and rd values. 1746 */ 1747 1748 std %d62, [%g1 + CPU_TMP1] ! save original value 1749 1750 srl %g6, FITOS_RS2_SHIFT, %g7 1751 and %g7, FITOS_REG_MASK, %g7 1752 set _fitos_fitod_table, %g4 1753 sllx %g7, 2, %g7 1754 jmp %g4 + %g7 1755 ba,pt %xcc, _fitos_fitod_done 1756 .empty 1757 1758_fitos_fitod_table: 1759 fitod %f0, %d62 1760 fitod %f1, %d62 1761 fitod %f2, %d62 1762 fitod %f3, %d62 1763 fitod %f4, %d62 1764 fitod %f5, %d62 1765 fitod %f6, %d62 1766 fitod %f7, %d62 1767 fitod %f8, %d62 1768 fitod %f9, %d62 1769 fitod %f10, %d62 1770 fitod %f11, %d62 1771 fitod %f12, %d62 1772 fitod %f13, %d62 1773 fitod %f14, %d62 1774 fitod %f15, %d62 1775 fitod %f16, %d62 1776 fitod %f17, %d62 1777 fitod %f18, %d62 1778 fitod %f19, %d62 1779 fitod %f20, %d62 1780 fitod %f21, %d62 1781 fitod %f22, %d62 1782 fitod %f23, %d62 1783 fitod %f24, %d62 1784 fitod %f25, %d62 1785 fitod %f26, %d62 1786 fitod %f27, %d62 1787 fitod %f28, %d62 1788 fitod %f29, %d62 1789 fitod %f30, %d62 1790 fitod %f31, %d62 1791_fitos_fitod_done: 1792 1793 /* 1794 * Now convert data back into single precision 1795 */ 1796 srl %g6, FITOS_RD_SHIFT, %g7 1797 and %g7, FITOS_REG_MASK, %g7 1798 set _fitos_fdtos_table, %g4 1799 sllx %g7, 2, %g7 1800 jmp %g4 + %g7 1801 ba,pt %xcc, _fitos_fdtos_done 1802 .empty 1803 1804_fitos_fdtos_table: 1805 fdtos %d62, %f0 1806 fdtos %d62, %f1 1807 fdtos %d62, %f2 1808 fdtos %d62, %f3 1809 fdtos %d62, %f4 1810 fdtos %d62, %f5 1811 fdtos %d62, %f6 1812 fdtos %d62, %f7 1813 fdtos %d62, %f8 1814 fdtos %d62, %f9 1815 fdtos %d62, %f10 1816 fdtos %d62, %f11 1817 fdtos %d62, %f12 1818 fdtos %d62, %f13 1819 fdtos %d62, %f14 1820 fdtos %d62, %f15 1821 fdtos %d62, %f16 1822 fdtos %d62, %f17 1823 fdtos %d62, %f18 1824 fdtos %d62, %f19 1825 fdtos %d62, %f20 1826 fdtos %d62, %f21 1827 fdtos %d62, %f22 1828 fdtos %d62, %f23 1829 fdtos %d62, %f24 1830 fdtos %d62, %f25 1831 fdtos %d62, %f26 1832 fdtos %d62, %f27 1833 fdtos %d62, %f28 1834 fdtos %d62, %f29 1835 fdtos %d62, %f30 1836 fdtos %d62, %f31 1837_fitos_fdtos_done: 1838 1839 ldd [%g1 + CPU_TMP1], %d62 ! restore %d62 1840 1841#if DEBUG 1842 /* 1843 * Update FPop_unfinished trap kstat 1844 */ 1845 set fpustat+FPUSTAT_UNFIN_KSTAT, %g7 1846 ldx [%g7], %g5 18471: 1848 add %g5, 1, %g6 1849 1850 casxa [%g7] ASI_N, %g5, %g6 1851 cmp %g5, %g6 1852 bne,a,pn %xcc, 1b 1853 or %g0, %g6, %g5 1854 1855 /* 1856 * Update fpu_sim_fitos kstat 1857 */ 1858 set fpuinfo+FPUINFO_FITOS_KSTAT, %g7 1859 ldx [%g7], %g5 18601: 1861 add %g5, 1, %g6 1862 1863 casxa [%g7] ASI_N, %g5, %g6 1864 cmp %g5, %g6 1865 bne,a,pn %xcc, 1b 1866 or %g0, %g6, %g5 1867#endif /* DEBUG */ 1868 1869 FAST_TRAP_DONE 1870 1871.fp_exception_cont: 1872 /* 1873 * Let _fp_exception deal with simulating FPop instruction. 1874 * Note that we need to pass %fsr in %g2 (already read above). 1875 */ 1876 1877 set _fp_exception, %g1 1878 ba,pt %xcc, sys_trap 1879 sub %g0, 1, %g4 1880 1881 1882/* 1883 * Register windows 1884 */ 1885.flushw: 1886.clean_windows: 1887 rdpr %tnpc, %g1 1888 wrpr %g1, %tpc 1889 add %g1, 4, %g1 1890 wrpr %g1, %tnpc 1891 set trap, %g1 1892 mov T_FLUSH_PCB, %g3 1893 ba,pt %xcc, sys_trap 1894 sub %g0, 1, %g4 1895 1896/* 1897 * .spill_clean: clean the previous window, restore the wstate, and 1898 * "done". 1899 * 1900 * Entry: %g7 contains new wstate 1901 */ 1902.spill_clean: 1903 sethi %hi(nwin_minus_one), %g5 1904 ld [%g5 + %lo(nwin_minus_one)], %g5 ! %g5 = nwin - 1 1905 rdpr %cwp, %g6 ! %g6 = %cwp 1906 deccc %g6 ! %g6-- 1907 movneg %xcc, %g5, %g6 ! if (%g6<0) %g6 = nwin-1 1908 wrpr %g6, %cwp 1909 TT_TRACE_L(trace_win) 1910 clr %l0 1911 clr %l1 1912 clr %l2 1913 clr %l3 1914 clr %l4 1915 clr %l5 1916 clr %l6 1917 clr %l7 1918 wrpr %g0, %g7, %wstate 1919 saved 1920 retry ! restores correct %cwp 1921 1922.fix_alignment: 1923 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 1924 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1925 ldn [%g1 + T_PROCP], %g1 1926 mov 1, %g2 1927 stb %g2, [%g1 + P_FIXALIGNMENT] 1928 FAST_TRAP_DONE 1929 1930#define STDF_REG(REG, ADDR, TMP) \ 1931 sll REG, 3, REG ;\ 1932mark1: set start1, TMP ;\ 1933 jmp REG + TMP ;\ 1934 nop ;\ 1935start1: ba,pt %xcc, done1 ;\ 1936 std %f0, [ADDR + CPU_TMP1] ;\ 1937 ba,pt %xcc, done1 ;\ 1938 std %f32, [ADDR + CPU_TMP1] ;\ 1939 ba,pt %xcc, done1 ;\ 1940 std %f2, [ADDR + CPU_TMP1] ;\ 1941 ba,pt %xcc, done1 ;\ 1942 std %f34, [ADDR + CPU_TMP1] ;\ 1943 ba,pt %xcc, done1 ;\ 1944 std %f4, [ADDR + CPU_TMP1] ;\ 1945 ba,pt %xcc, done1 ;\ 1946 std %f36, [ADDR + CPU_TMP1] ;\ 1947 ba,pt %xcc, done1 ;\ 1948 std %f6, [ADDR + CPU_TMP1] ;\ 1949 ba,pt %xcc, done1 ;\ 1950 std %f38, [ADDR + CPU_TMP1] ;\ 1951 ba,pt %xcc, done1 ;\ 1952 std %f8, [ADDR + CPU_TMP1] ;\ 1953 ba,pt %xcc, done1 ;\ 1954 std %f40, [ADDR + CPU_TMP1] ;\ 1955 ba,pt %xcc, done1 ;\ 1956 std %f10, [ADDR + CPU_TMP1] ;\ 1957 ba,pt %xcc, done1 ;\ 1958 std %f42, [ADDR + CPU_TMP1] ;\ 1959 ba,pt %xcc, done1 ;\ 1960 std %f12, [ADDR + CPU_TMP1] ;\ 1961 ba,pt %xcc, done1 ;\ 1962 std %f44, [ADDR + CPU_TMP1] ;\ 1963 ba,pt %xcc, done1 ;\ 1964 std %f14, [ADDR + CPU_TMP1] ;\ 1965 ba,pt %xcc, done1 ;\ 1966 std %f46, [ADDR + CPU_TMP1] ;\ 1967 ba,pt %xcc, done1 ;\ 1968 std %f16, [ADDR + CPU_TMP1] ;\ 1969 ba,pt %xcc, done1 ;\ 1970 std %f48, [ADDR + CPU_TMP1] ;\ 1971 ba,pt %xcc, done1 ;\ 1972 std %f18, [ADDR + CPU_TMP1] ;\ 1973 ba,pt %xcc, done1 ;\ 1974 std %f50, [ADDR + CPU_TMP1] ;\ 1975 ba,pt %xcc, done1 ;\ 1976 std %f20, [ADDR + CPU_TMP1] ;\ 1977 ba,pt %xcc, done1 ;\ 1978 std %f52, [ADDR + CPU_TMP1] ;\ 1979 ba,pt %xcc, done1 ;\ 1980 std %f22, [ADDR + CPU_TMP1] ;\ 1981 ba,pt %xcc, done1 ;\ 1982 std %f54, [ADDR + CPU_TMP1] ;\ 1983 ba,pt %xcc, done1 ;\ 1984 std %f24, [ADDR + CPU_TMP1] ;\ 1985 ba,pt %xcc, done1 ;\ 1986 std %f56, [ADDR + CPU_TMP1] ;\ 1987 ba,pt %xcc, done1 ;\ 1988 std %f26, [ADDR + CPU_TMP1] ;\ 1989 ba,pt %xcc, done1 ;\ 1990 std %f58, [ADDR + CPU_TMP1] ;\ 1991 ba,pt %xcc, done1 ;\ 1992 std %f28, [ADDR + CPU_TMP1] ;\ 1993 ba,pt %xcc, done1 ;\ 1994 std %f60, [ADDR + CPU_TMP1] ;\ 1995 ba,pt %xcc, done1 ;\ 1996 std %f30, [ADDR + CPU_TMP1] ;\ 1997 ba,pt %xcc, done1 ;\ 1998 std %f62, [ADDR + CPU_TMP1] ;\ 1999done1: 2000 2001#define LDDF_REG(REG, ADDR, TMP) \ 2002 sll REG, 3, REG ;\ 2003mark2: set start2, TMP ;\ 2004 jmp REG + TMP ;\ 2005 nop ;\ 2006start2: ba,pt %xcc, done2 ;\ 2007 ldd [ADDR + CPU_TMP1], %f0 ;\ 2008 ba,pt %xcc, done2 ;\ 2009 ldd [ADDR + CPU_TMP1], %f32 ;\ 2010 ba,pt %xcc, done2 ;\ 2011 ldd [ADDR + CPU_TMP1], %f2 ;\ 2012 ba,pt %xcc, done2 ;\ 2013 ldd [ADDR + CPU_TMP1], %f34 ;\ 2014 ba,pt %xcc, done2 ;\ 2015 ldd [ADDR + CPU_TMP1], %f4 ;\ 2016 ba,pt %xcc, done2 ;\ 2017 ldd [ADDR + CPU_TMP1], %f36 ;\ 2018 ba,pt %xcc, done2 ;\ 2019 ldd [ADDR + CPU_TMP1], %f6 ;\ 2020 ba,pt %xcc, done2 ;\ 2021 ldd [ADDR + CPU_TMP1], %f38 ;\ 2022 ba,pt %xcc, done2 ;\ 2023 ldd [ADDR + CPU_TMP1], %f8 ;\ 2024 ba,pt %xcc, done2 ;\ 2025 ldd [ADDR + CPU_TMP1], %f40 ;\ 2026 ba,pt %xcc, done2 ;\ 2027 ldd [ADDR + CPU_TMP1], %f10 ;\ 2028 ba,pt %xcc, done2 ;\ 2029 ldd [ADDR + CPU_TMP1], %f42 ;\ 2030 ba,pt %xcc, done2 ;\ 2031 ldd [ADDR + CPU_TMP1], %f12 ;\ 2032 ba,pt %xcc, done2 ;\ 2033 ldd [ADDR + CPU_TMP1], %f44 ;\ 2034 ba,pt %xcc, done2 ;\ 2035 ldd [ADDR + CPU_TMP1], %f14 ;\ 2036 ba,pt %xcc, done2 ;\ 2037 ldd [ADDR + CPU_TMP1], %f46 ;\ 2038 ba,pt %xcc, done2 ;\ 2039 ldd [ADDR + CPU_TMP1], %f16 ;\ 2040 ba,pt %xcc, done2 ;\ 2041 ldd [ADDR + CPU_TMP1], %f48 ;\ 2042 ba,pt %xcc, done2 ;\ 2043 ldd [ADDR + CPU_TMP1], %f18 ;\ 2044 ba,pt %xcc, done2 ;\ 2045 ldd [ADDR + CPU_TMP1], %f50 ;\ 2046 ba,pt %xcc, done2 ;\ 2047 ldd [ADDR + CPU_TMP1], %f20 ;\ 2048 ba,pt %xcc, done2 ;\ 2049 ldd [ADDR + CPU_TMP1], %f52 ;\ 2050 ba,pt %xcc, done2 ;\ 2051 ldd [ADDR + CPU_TMP1], %f22 ;\ 2052 ba,pt %xcc, done2 ;\ 2053 ldd [ADDR + CPU_TMP1], %f54 ;\ 2054 ba,pt %xcc, done2 ;\ 2055 ldd [ADDR + CPU_TMP1], %f24 ;\ 2056 ba,pt %xcc, done2 ;\ 2057 ldd [ADDR + CPU_TMP1], %f56 ;\ 2058 ba,pt %xcc, done2 ;\ 2059 ldd [ADDR + CPU_TMP1], %f26 ;\ 2060 ba,pt %xcc, done2 ;\ 2061 ldd [ADDR + CPU_TMP1], %f58 ;\ 2062 ba,pt %xcc, done2 ;\ 2063 ldd [ADDR + CPU_TMP1], %f28 ;\ 2064 ba,pt %xcc, done2 ;\ 2065 ldd [ADDR + CPU_TMP1], %f60 ;\ 2066 ba,pt %xcc, done2 ;\ 2067 ldd [ADDR + CPU_TMP1], %f30 ;\ 2068 ba,pt %xcc, done2 ;\ 2069 ldd [ADDR + CPU_TMP1], %f62 ;\ 2070done2: 2071 2072.lddf_exception_not_aligned: 2073 /* %g2 = sfar, %g3 = sfsr */ 2074 mov %g2, %g5 ! stash sfar 2075#if defined(DEBUG) || defined(NEED_FPU_EXISTS) 2076 sethi %hi(fpu_exists), %g2 ! check fpu_exists 2077 ld [%g2 + %lo(fpu_exists)], %g2 2078 brz,a,pn %g2, 4f 2079 nop 2080#endif 2081 CPU_ADDR(%g1, %g4) 2082 or %g0, 1, %g4 2083 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag 2084 2085 rdpr %tpc, %g2 2086 lda [%g2]ASI_AIUP, %g6 ! get the user's lddf instruction 2087 srl %g6, 23, %g1 ! using ldda or not? 2088 and %g1, 1, %g1 2089 brz,a,pt %g1, 2f ! check for ldda instruction 2090 nop 2091 srl %g6, 13, %g1 ! check immflag 2092 and %g1, 1, %g1 2093 rdpr %tstate, %g2 ! %tstate in %g2 2094 brnz,a,pn %g1, 1f 2095 srl %g2, 31, %g1 ! get asi from %tstate 2096 srl %g6, 5, %g1 ! get asi from instruction 2097 and %g1, 0xFF, %g1 ! imm_asi field 20981: 2099 cmp %g1, ASI_P ! primary address space 2100 be,a,pt %icc, 2f 2101 nop 2102 cmp %g1, ASI_PNF ! primary no fault address space 2103 be,a,pt %icc, 2f 2104 nop 2105 cmp %g1, ASI_S ! secondary address space 2106 be,a,pt %icc, 2f 2107 nop 2108 cmp %g1, ASI_SNF ! secondary no fault address space 2109 bne,a,pn %icc, 3f 2110 nop 21112: 2112 lduwa [%g5]ASI_USER, %g7 ! get first half of misaligned data 2113 add %g5, 4, %g5 ! increment misaligned data address 2114 lduwa [%g5]ASI_USER, %g5 ! get second half of misaligned data 2115 2116 sllx %g7, 32, %g7 2117 or %g5, %g7, %g5 ! combine data 2118 CPU_ADDR(%g7, %g1) ! save data on a per-cpu basis 2119 stx %g5, [%g7 + CPU_TMP1] ! save in cpu_tmp1 2120 2121 srl %g6, 25, %g3 ! %g6 has the instruction 2122 and %g3, 0x1F, %g3 ! %g3 has rd 2123 LDDF_REG(%g3, %g7, %g4) 2124 2125 CPU_ADDR(%g1, %g4) 2126 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 2127 FAST_TRAP_DONE 21283: 2129 CPU_ADDR(%g1, %g4) 2130 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 21314: 2132 set T_USER, %g3 ! trap type in %g3 2133 or %g3, T_LDDF_ALIGN, %g3 2134 mov %g5, %g2 ! misaligned vaddr in %g2 2135 set fpu_trap, %g1 ! goto C for the little and 2136 ba,pt %xcc, sys_trap ! no fault little asi's 2137 sub %g0, 1, %g4 2138 2139.stdf_exception_not_aligned: 2140 /* %g2 = sfar, %g3 = sfsr */ 2141 mov %g2, %g5 2142 2143#if defined(DEBUG) || defined(NEED_FPU_EXISTS) 2144 sethi %hi(fpu_exists), %g7 ! check fpu_exists 2145 ld [%g7 + %lo(fpu_exists)], %g3 2146 brz,a,pn %g3, 4f 2147 nop 2148#endif 2149 CPU_ADDR(%g1, %g4) 2150 or %g0, 1, %g4 2151 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag 2152 2153 rdpr %tpc, %g2 2154 lda [%g2]ASI_AIUP, %g6 ! get the user's stdf instruction 2155 2156 srl %g6, 23, %g1 ! using stda or not? 2157 and %g1, 1, %g1 2158 brz,a,pt %g1, 2f ! check for stda instruction 2159 nop 2160 srl %g6, 13, %g1 ! check immflag 2161 and %g1, 1, %g1 2162 rdpr %tstate, %g2 ! %tstate in %g2 2163 brnz,a,pn %g1, 1f 2164 srl %g2, 31, %g1 ! get asi from %tstate 2165 srl %g6, 5, %g1 ! get asi from instruction 2166 and %g1, 0xff, %g1 ! imm_asi field 21671: 2168 cmp %g1, ASI_P ! primary address space 2169 be,a,pt %icc, 2f 2170 nop 2171 cmp %g1, ASI_S ! secondary address space 2172 bne,a,pn %icc, 3f 2173 nop 21742: 2175 srl %g6, 25, %g6 2176 and %g6, 0x1F, %g6 ! %g6 has rd 2177 CPU_ADDR(%g7, %g1) 2178 STDF_REG(%g6, %g7, %g4) ! STDF_REG(REG, ADDR, TMP) 2179 2180 ldx [%g7 + CPU_TMP1], %g6 2181 srlx %g6, 32, %g7 2182 stuwa %g7, [%g5]ASI_USER ! first half 2183 add %g5, 4, %g5 ! increment misaligned data address 2184 stuwa %g6, [%g5]ASI_USER ! second half 2185 2186 CPU_ADDR(%g1, %g4) 2187 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 2188 FAST_TRAP_DONE 21893: 2190 CPU_ADDR(%g1, %g4) 2191 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 21924: 2193 set T_USER, %g3 ! trap type in %g3 2194 or %g3, T_STDF_ALIGN, %g3 2195 mov %g5, %g2 ! misaligned vaddr in %g2 2196 set fpu_trap, %g1 ! goto C for the little and 2197 ba,pt %xcc, sys_trap ! nofault little asi's 2198 sub %g0, 1, %g4 2199 2200#ifdef DEBUG_USER_TRAPTRACECTL 2201 2202.traptrace_freeze: 2203 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4 2204 TT_TRACE_L(trace_win) 2205 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0 2206 set trap_freeze, %g1 2207 mov 1, %g2 2208 st %g2, [%g1] 2209 FAST_TRAP_DONE 2210 2211.traptrace_unfreeze: 2212 set trap_freeze, %g1 2213 st %g0, [%g1] 2214 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4 2215 TT_TRACE_L(trace_win) 2216 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0 2217 FAST_TRAP_DONE 2218 2219#endif /* DEBUG_USER_TRAPTRACECTL */ 2220 2221.getcc: 2222 CPU_ADDR(%g1, %g2) 2223 stx %o0, [%g1 + CPU_TMP1] ! save %o0 2224 rdpr %tstate, %g3 ! get tstate 2225 srlx %g3, PSR_TSTATE_CC_SHIFT, %o0 ! shift ccr to V8 psr 2226 set PSR_ICC, %g2 2227 and %o0, %g2, %o0 ! mask out the rest 2228 srl %o0, PSR_ICC_SHIFT, %o0 ! right justify 2229 wrpr %g0, 0, %gl 2230 mov %o0, %g1 ! move ccr to normal %g1 2231 wrpr %g0, 1, %gl 2232 ! cannot assume globals retained their values after increasing %gl 2233 CPU_ADDR(%g1, %g2) 2234 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0 2235 FAST_TRAP_DONE 2236 2237.setcc: 2238 CPU_ADDR(%g1, %g2) 2239 stx %o0, [%g1 + CPU_TMP1] ! save %o0 2240 wrpr %g0, 0, %gl 2241 mov %g1, %o0 2242 wrpr %g0, 1, %gl 2243 ! cannot assume globals retained their values after increasing %gl 2244 CPU_ADDR(%g1, %g2) 2245 sll %o0, PSR_ICC_SHIFT, %g2 2246 set PSR_ICC, %g3 2247 and %g2, %g3, %g2 ! mask out rest 2248 sllx %g2, PSR_TSTATE_CC_SHIFT, %g2 2249 rdpr %tstate, %g3 ! get tstate 2250 srl %g3, 0, %g3 ! clear upper word 2251 or %g3, %g2, %g3 ! or in new bits 2252 wrpr %g3, %tstate 2253 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0 2254 FAST_TRAP_DONE 2255 2256/* 2257 * getpsr(void) 2258 * Note that the xcc part of the ccr is not provided. 2259 * The V8 code shows why the V9 trap is not faster: 2260 * #define GETPSR_TRAP() \ 2261 * mov %psr, %i0; jmp %l2; rett %l2+4; nop; 2262 */ 2263 2264 .type .getpsr, #function 2265.getpsr: 2266 rdpr %tstate, %g1 ! get tstate 2267 srlx %g1, PSR_TSTATE_CC_SHIFT, %o0 ! shift ccr to V8 psr 2268 set PSR_ICC, %g2 2269 and %o0, %g2, %o0 ! mask out the rest 2270 2271 rd %fprs, %g1 ! get fprs 2272 and %g1, FPRS_FEF, %g2 ! mask out dirty upper/lower 2273 sllx %g2, PSR_FPRS_FEF_SHIFT, %g2 ! shift fef to V8 psr.ef 2274 or %o0, %g2, %o0 ! or result into psr.ef 2275 2276 set V9_PSR_IMPLVER, %g2 ! SI assigned impl/ver: 0xef 2277 or %o0, %g2, %o0 ! or psr.impl/ver 2278 FAST_TRAP_DONE 2279 SET_SIZE(.getpsr) 2280 2281/* 2282 * setpsr(newpsr) 2283 * Note that there is no support for ccr.xcc in the V9 code. 2284 */ 2285 2286 .type .setpsr, #function 2287.setpsr: 2288 rdpr %tstate, %g1 ! get tstate 2289! setx TSTATE_V8_UBITS, %g2 2290 or %g0, CCR_ICC, %g3 2291 sllx %g3, TSTATE_CCR_SHIFT, %g2 2292 2293 andn %g1, %g2, %g1 ! zero current user bits 2294 set PSR_ICC, %g2 2295 and %g2, %o0, %g2 ! clear all but psr.icc bits 2296 sllx %g2, PSR_TSTATE_CC_SHIFT, %g3 ! shift to tstate.ccr.icc 2297 wrpr %g1, %g3, %tstate ! write tstate 2298 2299 set PSR_EF, %g2 2300 and %g2, %o0, %g2 ! clear all but fp enable bit 2301 srlx %g2, PSR_FPRS_FEF_SHIFT, %g4 ! shift ef to V9 fprs.fef 2302 wr %g0, %g4, %fprs ! write fprs 2303 2304 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 2305 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2306 ldn [%g2 + T_LWP], %g3 ! load klwp pointer 2307 ldn [%g3 + LWP_FPU], %g2 ! get lwp_fpu pointer 2308 stuw %g4, [%g2 + FPU_FPRS] ! write fef value to fpu_fprs 2309 srlx %g4, 2, %g4 ! shift fef value to bit 0 2310 stub %g4, [%g2 + FPU_EN] ! write fef value to fpu_en 2311 FAST_TRAP_DONE 2312 SET_SIZE(.setpsr) 2313 2314/* 2315 * getlgrp 2316 * get home lgrpid on which the calling thread is currently executing. 2317 */ 2318 .type .getlgrp, #function 2319.getlgrp: 2320 ! Thanks for the incredibly helpful comments 2321 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2322 ld [%g1 + CPU_ID], %o0 ! load cpu_id 2323 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2324 ldn [%g2 + T_LPL], %g2 ! load lpl pointer 2325 ld [%g2 + LPL_LGRPID], %g1 ! load lpl_lgrpid 2326 sra %g1, 0, %o1 2327 FAST_TRAP_DONE 2328 SET_SIZE(.getlgrp) 2329 2330/* 2331 * Entry for old 4.x trap (trap 0). 2332 */ 2333 ENTRY_NP(syscall_trap_4x) 2334 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2335 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2336 ldn [%g2 + T_LWP], %g2 ! load klwp pointer 2337 ld [%g2 + PCB_TRAP0], %g2 ! lwp->lwp_pcb.pcb_trap0addr 2338 brz,pn %g2, 1f ! has it been set? 2339 st %l0, [%g1 + CPU_TMP1] ! delay - save some locals 2340 st %l1, [%g1 + CPU_TMP2] 2341 rdpr %tnpc, %l1 ! save old tnpc 2342 wrpr %g0, %g2, %tnpc ! setup tnpc 2343 2344 mov %g1, %l0 ! save CPU struct addr 2345 wrpr %g0, 0, %gl 2346 mov %l1, %g6 ! pass tnpc to user code in %g6 2347 wrpr %g0, 1, %gl 2348 ld [%l0 + CPU_TMP2], %l1 ! restore locals 2349 ld [%l0 + CPU_TMP1], %l0 2350 FAST_TRAP_DONE_CHK_INTR 23511: 2352 ! 2353 ! check for old syscall mmap which is the only different one which 2354 ! must be the same. Others are handled in the compatibility library. 2355 ! 2356 mov %g1, %l0 ! save CPU struct addr 2357 wrpr %g0, 0, %gl 2358 cmp %g1, OSYS_mmap ! compare to old 4.x mmap 2359 movz %icc, SYS_mmap, %g1 2360 wrpr %g0, 1, %gl 2361 ld [%l0 + CPU_TMP1], %l0 2362 SYSCALL(syscall_trap32) 2363 SET_SIZE(syscall_trap_4x) 2364 2365/* 2366 * Handler for software trap 9. 2367 * Set trap0 emulation address for old 4.x system call trap. 2368 * XXX - this should be a system call. 2369 */ 2370 ENTRY_NP(set_trap0_addr) 2371 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2372 st %l0, [%g1 + CPU_TMP1] ! save some locals 2373 st %l1, [%g1 + CPU_TMP2] 2374 mov %g1, %l0 ! preserve CPU addr 2375 wrpr %g0, 0, %gl 2376 mov %g1, %l1 2377 wrpr %g0, 1, %gl 2378 ! cannot assume globals retained their values after increasing %gl 2379 ldn [%l0 + CPU_THREAD], %g2 ! load thread pointer 2380 ldn [%g2 + T_LWP], %g2 ! load klwp pointer 2381 andn %l1, 3, %l1 ! force alignment 2382 st %l1, [%g2 + PCB_TRAP0] ! lwp->lwp_pcb.pcb_trap0addr 2383 ld [%l0 + CPU_TMP2], %l1 ! restore locals 2384 ld [%l0 + CPU_TMP1], %l0 2385 FAST_TRAP_DONE 2386 SET_SIZE(set_trap0_addr) 2387 2388/* 2389 * mmu_trap_tl1 2390 * trap handler for unexpected mmu traps. 2391 * simply checks if the trap was a user lddf/stdf alignment trap, in which 2392 * case we go to fpu_trap or a user trap from the window handler, in which 2393 * case we go save the state on the pcb. Otherwise, we go to ptl1_panic. 2394 */ 2395 .type mmu_trap_tl1, #function 2396mmu_trap_tl1: 2397#ifdef TRAPTRACE 2398 TRACE_PTR(%g5, %g6) 2399 GET_TRACE_TICK(%g6) 2400 stxa %g6, [%g5 + TRAP_ENT_TICK]%asi 2401 TRACE_SAVE_TL_GL_REGS(%g5, %g6) 2402 rdpr %tt, %g6 2403 stha %g6, [%g5 + TRAP_ENT_TT]%asi 2404 rdpr %tstate, %g6 2405 stxa %g6, [%g5 + TRAP_ENT_TSTATE]%asi 2406 stna %sp, [%g5 + TRAP_ENT_SP]%asi 2407 stna %g0, [%g5 + TRAP_ENT_TR]%asi 2408 rdpr %tpc, %g6 2409 stna %g6, [%g5 + TRAP_ENT_TPC]%asi 2410 MMU_FAULT_STATUS_AREA(%g6) 2411 ldx [%g6 + MMFSA_D_ADDR], %g6 2412 stna %g6, [%g5 + TRAP_ENT_F1]%asi ! MMU fault address 2413 CPU_PADDR(%g7, %g6); 2414 add %g7, CPU_TL1_HDLR, %g7 2415 lda [%g7]ASI_MEM, %g6 2416 stna %g6, [%g5 + TRAP_ENT_F2]%asi 2417 MMU_FAULT_STATUS_AREA(%g6) 2418 ldx [%g6 + MMFSA_D_TYPE], %g7 ! XXXQ should be a MMFSA_F_ constant? 2419 ldx [%g6 + MMFSA_D_CTX], %g6 2420 sllx %g6, SFSR_CTX_SHIFT, %g6 2421 or %g6, %g7, %g6 2422 stna %g6, [%g5 + TRAP_ENT_F3]%asi ! MMU context/type 2423 set 0xdeadbeef, %g6 2424 stna %g6, [%g5 + TRAP_ENT_F4]%asi 2425 TRACE_NEXT(%g5, %g6, %g7) 2426#endif /* TRAPTRACE */ 2427 CPU_PADDR(%g7, %g6); 2428 add %g7, CPU_TL1_HDLR, %g7 ! %g7 = &cpu_m.tl1_hdlr (PA) 2429 lda [%g7]ASI_MEM, %g6 2430 brz,a,pt %g6, 1f 2431 nop 2432 sta %g0, [%g7]ASI_MEM 2433 ! XXXQ need to setup registers for sfmmu_mmu_trap? 2434 ba,a,pt %xcc, sfmmu_mmu_trap ! handle page faults 24351: 2436 rdpr %tpc, %g7 2437 /* in user_rtt? */ 2438 set rtt_fill_start, %g6 2439 cmp %g7, %g6 2440 blu,pn %xcc, 6f 2441 .empty 2442 set rtt_fill_end, %g6 2443 cmp %g7, %g6 2444 bgeu,pn %xcc, 6f 2445 nop 2446 set fault_rtt_fn1, %g7 2447 ba,a 7f 24486: 2449 ! check to see if the trap pc is in a window spill/fill handling 2450 rdpr %tpc, %g7 2451 /* tpc should be in the trap table */ 2452 set trap_table, %g6 2453 cmp %g7, %g6 2454 blu,a,pn %xcc, ptl1_panic 2455 mov PTL1_BAD_MMUTRAP, %g1 2456 set etrap_table, %g6 2457 cmp %g7, %g6 2458 bgeu,a,pn %xcc, ptl1_panic 2459 mov PTL1_BAD_MMUTRAP, %g1 2460 ! pc is inside the trap table, convert to trap type 2461 srl %g7, 5, %g6 ! XXXQ need #define 2462 and %g6, 0x1ff, %g6 ! XXXQ need #define 2463 ! and check for a window trap type 2464 and %g6, WTRAP_TTMASK, %g6 2465 cmp %g6, WTRAP_TYPE 2466 bne,a,pn %xcc, ptl1_panic 2467 mov PTL1_BAD_MMUTRAP, %g1 2468 andn %g7, WTRAP_ALIGN, %g7 /* 128 byte aligned */ 2469 add %g7, WTRAP_FAULTOFF, %g7 2470 24717: 2472 ! Arguments are passed in the global set active after the 2473 ! 'done' instruction. Before switching sets, must save 2474 ! the calculated next pc 2475 wrpr %g0, %g7, %tnpc 2476 wrpr %g0, 1, %gl 2477 rdpr %tt, %g5 2478 MMU_FAULT_STATUS_AREA(%g7) 2479 cmp %g5, T_ALIGNMENT 2480 be,pn %xcc, 1f 2481 ldx [%g7 + MMFSA_D_ADDR], %g6 2482 ldx [%g7 + MMFSA_D_CTX], %g7 2483 srlx %g6, MMU_PAGESHIFT, %g6 /* align address */ 2484 sllx %g6, MMU_PAGESHIFT, %g6 2485 or %g6, %g7, %g6 /* TAG_ACCESS */ 24861: 2487 done 2488 SET_SIZE(mmu_trap_tl1) 2489 2490/* 2491 * Several traps use kmdb_trap and kmdb_trap_tl1 as their handlers. These 2492 * traps are valid only when kmdb is loaded. When the debugger is active, 2493 * the code below is rewritten to transfer control to the appropriate 2494 * debugger entry points. 2495 */ 2496 .global kmdb_trap 2497 .align 8 2498kmdb_trap: 2499 ba,a trap_table0 2500 jmp %g1 + 0 2501 nop 2502 2503 .global kmdb_trap_tl1 2504 .align 8 2505kmdb_trap_tl1: 2506 ba,a trap_table0 2507 jmp %g1 + 0 2508 nop 2509 2510/* 2511 * This entry is copied from OBP's trap table during boot. 2512 */ 2513 .global obp_bpt 2514 .align 8 2515obp_bpt: 2516 NOT 2517 2518 2519 2520#ifdef TRAPTRACE 2521/* 2522 * TRAPTRACE support. 2523 * labels here are branched to with "rd %pc, %g7" in the delay slot. 2524 * Return is done by "jmp %g7 + 4". 2525 */ 2526 2527trace_dmmu: 2528 TRACE_PTR(%g3, %g6) 2529 GET_TRACE_TICK(%g6) 2530 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi 2531 TRACE_SAVE_TL_GL_REGS(%g3, %g6) 2532 rdpr %tt, %g6 2533 stha %g6, [%g3 + TRAP_ENT_TT]%asi 2534 rdpr %tstate, %g6 2535 stxa %g6, [%g3 + TRAP_ENT_TSTATE]%asi 2536 stna %sp, [%g3 + TRAP_ENT_SP]%asi 2537 rdpr %tpc, %g6 2538 stna %g6, [%g3 + TRAP_ENT_TPC]%asi 2539 MMU_FAULT_STATUS_AREA(%g6) 2540 ldx [%g6 + MMFSA_D_ADDR], %g4 2541 stxa %g4, [%g3 + TRAP_ENT_TR]%asi 2542 ldx [%g6 + MMFSA_D_CTX], %g4 2543 stxa %g4, [%g3 + TRAP_ENT_F1]%asi 2544 ldx [%g6 + MMFSA_D_TYPE], %g4 2545 stxa %g4, [%g3 + TRAP_ENT_F2]%asi 2546 stxa %g6, [%g3 + TRAP_ENT_F3]%asi 2547 stna %g0, [%g3 + TRAP_ENT_F4]%asi 2548 TRACE_NEXT(%g3, %g4, %g5) 2549 jmp %g7 + 4 2550 nop 2551 2552trace_immu: 2553 TRACE_PTR(%g3, %g6) 2554 GET_TRACE_TICK(%g6) 2555 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi 2556 TRACE_SAVE_TL_GL_REGS(%g3, %g6) 2557 rdpr %tt, %g6 2558 stha %g6, [%g3 + TRAP_ENT_TT]%asi 2559 rdpr %tstate, %g6 2560 stxa %g6, [%g3 + TRAP_ENT_TSTATE]%asi 2561 stna %sp, [%g3 + TRAP_ENT_SP]%asi 2562 rdpr %tpc, %g6 2563 stna %g6, [%g3 + TRAP_ENT_TPC]%asi 2564 MMU_FAULT_STATUS_AREA(%g6) 2565 ldx [%g6 + MMFSA_I_ADDR], %g4 2566 stxa %g4, [%g3 + TRAP_ENT_TR]%asi 2567 ldx [%g6 + MMFSA_I_CTX], %g4 2568 stxa %g4, [%g3 + TRAP_ENT_F1]%asi 2569 ldx [%g6 + MMFSA_I_TYPE], %g4 2570 stxa %g4, [%g3 + TRAP_ENT_F2]%asi 2571 stxa %g6, [%g3 + TRAP_ENT_F3]%asi 2572 stna %g0, [%g3 + TRAP_ENT_F4]%asi 2573 TRACE_NEXT(%g3, %g4, %g5) 2574 jmp %g7 + 4 2575 nop 2576 2577trace_gen: 2578 TRACE_PTR(%g3, %g6) 2579 GET_TRACE_TICK(%g6) 2580 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi 2581 TRACE_SAVE_TL_GL_REGS(%g3, %g6) 2582 rdpr %tt, %g6 2583 stha %g6, [%g3 + TRAP_ENT_TT]%asi 2584 rdpr %tstate, %g6 2585 stxa %g6, [%g3 + TRAP_ENT_TSTATE]%asi 2586 stna %sp, [%g3 + TRAP_ENT_SP]%asi 2587 rdpr %tpc, %g6 2588 stna %g6, [%g3 + TRAP_ENT_TPC]%asi 2589 stna %g0, [%g3 + TRAP_ENT_TR]%asi 2590 stna %g0, [%g3 + TRAP_ENT_F1]%asi 2591 stna %g0, [%g3 + TRAP_ENT_F2]%asi 2592 stna %g0, [%g3 + TRAP_ENT_F3]%asi 2593 stna %g0, [%g3 + TRAP_ENT_F4]%asi 2594 TRACE_NEXT(%g3, %g4, %g5) 2595 jmp %g7 + 4 2596 nop 2597 2598trace_win: 2599 TRACE_WIN_INFO(0, %l0, %l1, %l2) 2600 ! Keep the locals as clean as possible, caller cleans %l4 2601 clr %l2 2602 clr %l1 2603 jmp %l4 + 4 2604 clr %l0 2605 2606/* 2607 * Trace a tsb hit 2608 * g1 = tsbe pointer (in/clobbered) 2609 * g2 = tag access register (in) 2610 * g3 - g4 = scratch (clobbered) 2611 * g5 = tsbe data (in) 2612 * g6 = scratch (clobbered) 2613 * g7 = pc we jumped here from (in) 2614 */ 2615 2616 ! Do not disturb %g5, it will be used after the trace 2617 ALTENTRY(trace_tsbhit) 2618 TRACE_TSBHIT(0) 2619 jmp %g7 + 4 2620 nop 2621 2622/* 2623 * Trace a TSB miss 2624 * 2625 * g1 = tsb8k pointer (in) 2626 * g2 = tag access register (in) 2627 * g3 = tsb4m pointer (in) 2628 * g4 = tsbe tag (in/clobbered) 2629 * g5 - g6 = scratch (clobbered) 2630 * g7 = pc we jumped here from (in) 2631 */ 2632 .global trace_tsbmiss 2633trace_tsbmiss: 2634 membar #Sync 2635 sethi %hi(FLUSH_ADDR), %g6 2636 flush %g6 2637 TRACE_PTR(%g5, %g6) 2638 GET_TRACE_TICK(%g6) 2639 stxa %g6, [%g5 + TRAP_ENT_TICK]%asi 2640 stna %g2, [%g5 + TRAP_ENT_SP]%asi ! tag access 2641 stna %g4, [%g5 + TRAP_ENT_F1]%asi ! XXX? tsb tag 2642 rdpr %tnpc, %g6 2643 stna %g6, [%g5 + TRAP_ENT_F2]%asi 2644 stna %g1, [%g5 + TRAP_ENT_F3]%asi ! tsb8k pointer 2645 srlx %g1, 32, %g6 2646 stna %g6, [%g5 + TRAP_ENT_F4]%asi ! huh? 2647 rdpr %tpc, %g6 2648 stna %g6, [%g5 + TRAP_ENT_TPC]%asi 2649 TRACE_SAVE_TL_GL_REGS(%g5, %g6) 2650 rdpr %tt, %g6 2651 or %g6, TT_MMU_MISS, %g4 2652 stha %g4, [%g5 + TRAP_ENT_TT]%asi 2653 mov MMFSA_D_ADDR, %g4 2654 cmp %g6, FAST_IMMU_MISS_TT 2655 move %xcc, MMFSA_I_ADDR, %g4 2656 cmp %g6, T_INSTR_MMU_MISS 2657 move %xcc, MMFSA_I_ADDR, %g4 2658 MMU_FAULT_STATUS_AREA(%g6) 2659 ldx [%g6 + %g4], %g6 2660 stxa %g6, [%g5 + TRAP_ENT_TSTATE]%asi ! tag target 2661 stna %g3, [%g5 + TRAP_ENT_TR]%asi ! tsb4m pointer 2662 TRACE_NEXT(%g5, %g4, %g6) 2663 jmp %g7 + 4 2664 nop 2665 2666/* 2667 * g2 = tag access register (in) 2668 * g3 = ctx number (in) 2669 */ 2670trace_dataprot: 2671 membar #Sync 2672 sethi %hi(FLUSH_ADDR), %g6 2673 flush %g6 2674 TRACE_PTR(%g1, %g6) 2675 GET_TRACE_TICK(%g6) 2676 stxa %g6, [%g1 + TRAP_ENT_TICK]%asi 2677 rdpr %tpc, %g6 2678 stna %g6, [%g1 + TRAP_ENT_TPC]%asi 2679 rdpr %tstate, %g6 2680 stxa %g6, [%g1 + TRAP_ENT_TSTATE]%asi 2681 stna %g2, [%g1 + TRAP_ENT_SP]%asi ! tag access reg 2682 stna %g0, [%g1 + TRAP_ENT_TR]%asi 2683 stna %g0, [%g1 + TRAP_ENT_F1]%asi 2684 stna %g0, [%g1 + TRAP_ENT_F2]%asi 2685 stna %g0, [%g1 + TRAP_ENT_F3]%asi 2686 stna %g0, [%g1 + TRAP_ENT_F4]%asi 2687 TRACE_SAVE_TL_GL_REGS(%g1, %g6) 2688 rdpr %tt, %g6 2689 stha %g6, [%g1 + TRAP_ENT_TT]%asi 2690 TRACE_NEXT(%g1, %g4, %g5) 2691 jmp %g7 + 4 2692 nop 2693 2694#endif /* TRAPTRACE */ 2695 2696/* 2697 * Handle watchdog reset trap. Enable the MMU using the MMU_ENABLE 2698 * HV service, which requires the return target to be specified as a VA 2699 * since we are enabling the MMU. We set the target to ptl1_panic. 2700 */ 2701 2702 .type .watchdog_trap, #function 2703.watchdog_trap: 2704 mov 1, %o0 2705 setx ptl1_panic, %g2, %o1 2706 mov MMU_ENABLE, %o5 2707 ta FAST_TRAP 2708 done 2709 SET_SIZE(.watchdog_trap) 2710/* 2711 * synthesize for trap(): SFAR in %g2, SFSR in %g3 2712 */ 2713 .type .dmmu_exc_lddf_not_aligned, #function 2714.dmmu_exc_lddf_not_aligned: 2715 MMU_FAULT_STATUS_AREA(%g3) 2716 ldx [%g3 + MMFSA_D_ADDR], %g2 2717 /* Fault type not available in MMU fault status area */ 2718 mov MMFSA_F_UNALIGN, %g1 2719 ldx [%g3 + MMFSA_D_CTX], %g3 2720 sllx %g3, SFSR_CTX_SHIFT, %g3 2721 btst 1, %sp 2722 bnz,pt %xcc, .lddf_exception_not_aligned 2723 or %g3, %g1, %g3 /* SFSR */ 2724 ba,a,pt %xcc, .mmu_exception_not_aligned 2725 SET_SIZE(.dmmu_exc_lddf_not_aligned) 2726 2727/* 2728 * synthesize for trap(): SFAR in %g2, SFSR in %g3 2729 */ 2730 .type .dmmu_exc_stdf_not_aligned, #function 2731.dmmu_exc_stdf_not_aligned: 2732 MMU_FAULT_STATUS_AREA(%g3) 2733 ldx [%g3 + MMFSA_D_ADDR], %g2 2734 /* Fault type not available in MMU fault status area */ 2735 mov MMFSA_F_UNALIGN, %g1 2736 ldx [%g3 + MMFSA_D_CTX], %g3 2737 sllx %g3, SFSR_CTX_SHIFT, %g3 2738 btst 1, %sp 2739 bnz,pt %xcc, .stdf_exception_not_aligned 2740 or %g3, %g1, %g3 /* SFSR */ 2741 ba,a,pt %xcc, .mmu_exception_not_aligned 2742 SET_SIZE(.dmmu_exc_stdf_not_aligned) 2743 2744 .type .dmmu_exception, #function 2745.dmmu_exception: 2746 MMU_FAULT_STATUS_AREA(%g3) 2747 ldx [%g3 + MMFSA_D_ADDR], %g2 2748 ldx [%g3 + MMFSA_D_TYPE], %g1 2749 ldx [%g3 + MMFSA_D_CTX], %g3 2750 srlx %g2, MMU_PAGESHIFT, %g2 /* align address */ 2751 sllx %g2, MMU_PAGESHIFT, %g2 2752 or %g2, %g3, %g2 /* TAG_ACCESS */ 2753 sllx %g3, SFSR_CTX_SHIFT, %g3 2754 or %g3, %g1, %g3 /* SFSR */ 2755 ba,pt %xcc, .mmu_exception_end 2756 mov T_DATA_EXCEPTION, %g1 2757 SET_SIZE(.dmmu_exception) 2758/* 2759 * expects offset into tsbmiss area in %g1 and return pc in %g7 2760 */ 2761stat_mmu: 2762 CPU_INDEX(%g5, %g6) 2763 sethi %hi(tsbmiss_area), %g6 2764 sllx %g5, TSBMISS_SHIFT, %g5 2765 or %g6, %lo(tsbmiss_area), %g6 2766 add %g6, %g5, %g6 /* g6 = tsbmiss area */ 2767 ld [%g6 + %g1], %g5 2768 add %g5, 1, %g5 2769 jmp %g7 + 4 2770 st %g5, [%g6 + %g1] 2771 2772 2773/* 2774 * fast_trap_done, fast_trap_done_chk_intr: 2775 * 2776 * Due to the design of UltraSPARC pipeline, pending interrupts are not 2777 * taken immediately after a RETRY or DONE instruction which causes IE to 2778 * go from 0 to 1. Instead, the instruction at %tpc or %tnpc is allowed 2779 * to execute first before taking any interrupts. If that instruction 2780 * results in other traps, and if the corresponding trap handler runs 2781 * entirely at TL=1 with interrupts disabled, then pending interrupts 2782 * won't be taken until after yet another instruction following the %tpc 2783 * or %tnpc. 2784 * 2785 * A malicious user program can use this feature to block out interrupts 2786 * for extended durations, which can result in send_mondo_timeout kernel 2787 * panic. 2788 * 2789 * This problem is addressed by servicing any pending interrupts via 2790 * sys_trap before returning back to the user mode from a fast trap 2791 * handler. The "done" instruction within a fast trap handler, which 2792 * runs entirely at TL=1 with interrupts disabled, is replaced with the 2793 * FAST_TRAP_DONE macro, which branches control to this fast_trap_done 2794 * entry point. 2795 * 2796 * We check for any pending interrupts here and force a sys_trap to 2797 * service those interrupts, if any. To minimize overhead, pending 2798 * interrupts are checked if the %tpc happens to be at 16K boundary, 2799 * which allows a malicious program to execute at most 4K consecutive 2800 * instructions before we service any pending interrupts. If a worst 2801 * case fast trap handler takes about 2 usec, then interrupts will be 2802 * blocked for at most 8 msec, less than a clock tick. 2803 * 2804 * For the cases where we don't know if the %tpc will cross a 16K 2805 * boundary, we can't use the above optimization and always process 2806 * any pending interrupts via fast_frap_done_chk_intr entry point. 2807 * 2808 * Entry Conditions: 2809 * %pstate am:0 priv:1 ie:0 2810 * globals are AG (not normal globals) 2811 */ 2812 2813 .global fast_trap_done, fast_trap_done_chk_intr 2814fast_trap_done: 2815 rdpr %tpc, %g5 2816 sethi %hi(0xffffc000), %g6 ! 1's complement of 0x3fff 2817 andncc %g5, %g6, %g0 ! check lower 14 bits of %tpc 2818 bz,pn %icc, 1f ! branch if zero (lower 32 bits only) 2819 nop 2820 done 2821 2822fast_trap_done_chk_intr: 28231: rd SOFTINT, %g6 2824 brnz,pn %g6, 2f ! branch if any pending intr 2825 nop 2826 done 2827 28282: 2829 /* 2830 * We get here if there are any pending interrupts. 2831 * Adjust %tpc/%tnpc as we'll be resuming via "retry" 2832 * instruction. 2833 */ 2834 rdpr %tnpc, %g5 2835 wrpr %g0, %g5, %tpc 2836 add %g5, 4, %g5 2837 wrpr %g0, %g5, %tnpc 2838 2839 /* 2840 * Force a dummy sys_trap call so that interrupts can be serviced. 2841 */ 2842 set fast_trap_dummy_call, %g1 2843 ba,pt %xcc, sys_trap 2844 mov -1, %g4 2845 2846fast_trap_dummy_call: 2847 retl 2848 nop 2849 2850#endif /* lint */ 2851