1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29/* 30 * Hypervisor calls 31 */ 32 33#include <sys/asm_linkage.h> 34#include <sys/machasi.h> 35#include <sys/machparam.h> 36#include <sys/hypervisor_api.h> 37 38#if defined(lint) || defined(__lint) 39 40/*ARGSUSED*/ 41uint64_t 42hv_mach_exit(uint64_t exit_code) 43{ return (0); } 44 45uint64_t 46hv_mach_sir(void) 47{ return (0); } 48 49/*ARGSUSED*/ 50uint64_t 51hv_cpu_start(uint64_t cpuid, uint64_t pc, uint64_t rtba, uint64_t arg) 52{ return (0); } 53 54/*ARGSUSED*/ 55uint64_t 56hv_cpu_stop(uint64_t cpuid) 57{ return (0); } 58 59/*ARGSUSED*/ 60uint64_t 61hv_cpu_set_rtba(uint64_t *rtba) 62{ return (0); } 63 64/*ARGSUSED*/ 65int64_t 66hv_cnputchar(uint8_t ch) 67{ return (0); } 68 69/*ARGSUSED*/ 70int64_t 71hv_cngetchar(uint8_t *ch) 72{ return (0); } 73 74/*ARGSUSED*/ 75uint64_t 76hv_tod_get(uint64_t *seconds) 77{ return (0); } 78 79/*ARGSUSED*/ 80uint64_t 81hv_tod_set(uint64_t seconds) 82{ return (0);} 83 84/*ARGSUSED*/ 85uint64_t 86hv_mmu_map_perm_addr(void *vaddr, int ctx, uint64_t tte, int flags) 87{ return (0); } 88 89/*ARGSUSED */ 90uint64_t 91hv_mmu_fault_area_conf(void *raddr) 92{ return (0); } 93 94/*ARGSUSED*/ 95uint64_t 96hv_mmu_unmap_perm_addr(void *vaddr, int ctx, int flags) 97{ return (0); } 98 99/*ARGSUSED*/ 100uint64_t 101hv_set_ctx0(uint64_t ntsb_descriptor, uint64_t desc_ra) 102{ return (0); } 103 104/*ARGSUSED*/ 105uint64_t 106hv_set_ctxnon0(uint64_t ntsb_descriptor, uint64_t desc_ra) 107{ return (0); } 108 109#ifdef SET_MMU_STATS 110/*ARGSUSED*/ 111uint64_t 112hv_mmu_set_stat_area(uint64_t rstatarea, uint64_t size) 113{ return (0); } 114#endif /* SET_MMU_STATS */ 115 116/*ARGSUSED*/ 117uint64_t 118hv_cpu_qconf(int queue, uint64_t paddr, int size) 119{ return (0); } 120 121/*ARGSUSED*/ 122uint64_t 123hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino) 124{ return (0); } 125 126/*ARGSUSED*/ 127uint64_t 128hvio_intr_getvalid(uint64_t sysino, int *intr_valid_state) 129{ return (0); } 130 131/*ARGSUSED*/ 132uint64_t 133hvio_intr_setvalid(uint64_t sysino, int intr_valid_state) 134{ return (0); } 135 136/*ARGSUSED*/ 137uint64_t 138hvio_intr_getstate(uint64_t sysino, int *intr_state) 139{ return (0); } 140 141/*ARGSUSED*/ 142uint64_t 143hvio_intr_setstate(uint64_t sysino, int intr_state) 144{ return (0); } 145 146/*ARGSUSED*/ 147uint64_t 148hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid) 149{ return (0); } 150 151/*ARGSUSED*/ 152uint64_t 153hvio_intr_settarget(uint64_t sysino, uint32_t cpuid) 154{ return (0); } 155 156uint64_t 157hv_cpu_yield(void) 158{ return (0); } 159 160/*ARGSUSED*/ 161uint64_t 162hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state) 163{ return (0); } 164 165/*ARGSUSED*/ 166uint64_t 167hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *minsize) 168{ return (0); } 169 170/*ARGSUSED*/ 171uint64_t 172hv_mem_scrub(uint64_t real_addr, uint64_t length, uint64_t *scrubbed_len) 173{ return (0); } 174 175/*ARGSUSED*/ 176uint64_t 177hv_mem_sync(uint64_t real_addr, uint64_t length, uint64_t *flushed_len) 178{ return (0); } 179 180/*ARGSUSED*/ 181uint64_t 182hv_ttrace_buf_conf(uint64_t paddr, uint64_t size, uint64_t *size1) 183{ return (0); } 184 185/*ARGSUSED*/ 186uint64_t 187hv_ttrace_buf_info(uint64_t *paddr, uint64_t *size) 188{ return (0); } 189 190/*ARGSUSED*/ 191uint64_t 192hv_ttrace_enable(uint64_t enable, uint64_t *prev_enable) 193{ return (0); } 194 195/*ARGSUSED*/ 196uint64_t 197hv_ttrace_freeze(uint64_t freeze, uint64_t *prev_freeze) 198{ return (0); } 199 200/*ARGSUSED*/ 201uint64_t 202hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep) 203{ return (0); } 204 205/*ARGSUSED*/ 206uint64_t 207hv_ra2pa(uint64_t ra) 208{ return (0); } 209 210/*ARGSUSED*/ 211uint64_t 212hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 213{ return (0); } 214 215/*ARGSUSED*/ 216uint64_t 217hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 218{ return (0); } 219 220/*ARGSUSED*/ 221uint64_t 222hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 223{ return (0); } 224 225/*ARGSUSED*/ 226uint64_t 227hv_ldc_tx_get_state(uint64_t channel, 228 uint64_t *headp, uint64_t *tailp, uint64_t *state) 229{ return (0); } 230 231/*ARGSUSED*/ 232uint64_t 233hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 234{ return (0); } 235 236/*ARGSUSED*/ 237uint64_t 238hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 239{ return (0); } 240 241/*ARGSUSED*/ 242uint64_t 243hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 244{ return (0); } 245 246/*ARGSUSED*/ 247uint64_t 248hv_ldc_rx_get_state(uint64_t channel, 249 uint64_t *headp, uint64_t *tailp, uint64_t *state) 250{ return (0); } 251 252/*ARGSUSED*/ 253uint64_t 254hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 255{ return (0); } 256 257/*ARGSUSED*/ 258uint64_t 259hv_ldc_send_msg(uint64_t channel, uint64_t msg_ra) 260{ return (0); } 261 262/*ARGSUSED*/ 263uint64_t 264hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, uint64_t tbl_entries) 265{ return (0); } 266 267/*ARGSUSED*/ 268uint64_t 269hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 270 uint64_t raddr, uint64_t length, uint64_t *lengthp) 271{ return (0); } 272 273/*ARGSUSED*/ 274uint64_t 275hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, uint64_t *cookie) 276{ return (0); } 277 278/*ARGSUSED*/ 279uint64_t 280hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, uint64_t cookie) 281{ return (0); } 282 283/*ARGSUSED*/ 284uint64_t 285hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, int *intr_valid_state) 286{ return (0); } 287 288/*ARGSUSED*/ 289uint64_t 290hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, int intr_valid_state) 291{ return (0); } 292 293/*ARGSUSED*/ 294uint64_t 295hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, int *intr_state) 296{ return (0); } 297 298/*ARGSUSED*/ 299uint64_t 300hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, int intr_state) 301{ return (0); } 302 303/*ARGSUSED*/ 304uint64_t 305hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, uint32_t *cpuid) 306{ return (0); } 307 308/*ARGSUSED*/ 309uint64_t 310hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, uint32_t cpuid) 311{ return (0); } 312 313/*ARGSUSED*/ 314uint64_t 315hv_api_get_version(uint64_t api_group, uint64_t *majorp, uint64_t *minorp) 316{ return (0); } 317 318/*ARGSUSED*/ 319uint64_t 320hv_api_set_version(uint64_t api_group, uint64_t major, uint64_t minor, 321 uint64_t *supported_minor) 322{ return (0); } 323 324/*ARGSUSED*/ 325uint64_t 326hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 327{ return (0); } 328 329/*ARGSUSED*/ 330int64_t 331hv_cnwrite(uint64_t buf_ra, uint64_t count, uint64_t *retcount) 332{ return (0); } 333 334/*ARGSUSED*/ 335int64_t 336hv_cnread(uint64_t buf_ra, uint64_t count, int64_t *retcount) 337{ return (0); } 338 339#else /* lint || __lint */ 340 341 /* 342 * int hv_mach_exit(uint64_t exit_code) 343 */ 344 ENTRY(hv_mach_exit) 345 mov HV_MACH_EXIT, %o5 346 ta FAST_TRAP 347 retl 348 nop 349 SET_SIZE(hv_mach_exit) 350 351 /* 352 * uint64_t hv_mach_sir(void) 353 */ 354 ENTRY(hv_mach_sir) 355 mov HV_MACH_SIR, %o5 356 ta FAST_TRAP 357 retl 358 nop 359 SET_SIZE(hv_mach_sir) 360 361 /* 362 * hv_cpu_start(uint64_t cpuid, uint64_t pc, ui64_t rtba, 363 * uint64_t arg) 364 */ 365 ENTRY(hv_cpu_start) 366 mov HV_CPU_START, %o5 367 ta FAST_TRAP 368 retl 369 nop 370 SET_SIZE(hv_cpu_start) 371 372 /* 373 * hv_cpu_stop(uint64_t cpuid) 374 */ 375 ENTRY(hv_cpu_stop) 376 mov HV_CPU_STOP, %o5 377 ta FAST_TRAP 378 retl 379 nop 380 SET_SIZE(hv_cpu_stop) 381 382 /* 383 * hv_cpu_set_rtba(uint64_t *rtba) 384 */ 385 ENTRY(hv_cpu_set_rtba) 386 mov %o0, %o2 387 ldx [%o2], %o0 388 mov HV_CPU_SET_RTBA, %o5 389 ta FAST_TRAP 390 stx %o1, [%o2] 391 retl 392 nop 393 SET_SIZE(hv_cpu_set_rtba) 394 395 /* 396 * int64_t hv_cnputchar(uint8_t ch) 397 */ 398 ENTRY(hv_cnputchar) 399 mov CONS_PUTCHAR, %o5 400 ta FAST_TRAP 401 retl 402 nop 403 SET_SIZE(hv_cnputchar) 404 405 /* 406 * int64_t hv_cngetchar(uint8_t *ch) 407 */ 408 ENTRY(hv_cngetchar) 409 mov %o0, %o2 410 mov CONS_GETCHAR, %o5 411 ta FAST_TRAP 412 brnz,a %o0, 1f ! failure, just return error 413 nop 414 415 cmp %o1, H_BREAK 416 be 1f 417 mov %o1, %o0 418 419 cmp %o1, H_HUP 420 be 1f 421 mov %o1, %o0 422 423 stb %o1, [%o2] ! success, save character and return 0 424 mov 0, %o0 4251: 426 retl 427 nop 428 SET_SIZE(hv_cngetchar) 429 430 ENTRY(hv_tod_get) 431 mov %o0, %o4 432 mov TOD_GET, %o5 433 ta FAST_TRAP 434 retl 435 stx %o1, [%o4] 436 SET_SIZE(hv_tod_get) 437 438 ENTRY(hv_tod_set) 439 mov TOD_SET, %o5 440 ta FAST_TRAP 441 retl 442 nop 443 SET_SIZE(hv_tod_set) 444 445 /* 446 * Map permanent address 447 * arg0 vaddr (%o0) 448 * arg1 context (%o1) 449 * arg2 tte (%o2) 450 * arg3 flags (%o3) 0x1=d 0x2=i 451 */ 452 ENTRY(hv_mmu_map_perm_addr) 453 mov MAP_PERM_ADDR, %o5 454 ta FAST_TRAP 455 retl 456 nop 457 SET_SIZE(hv_mmu_map_perm_addr) 458 459 /* 460 * hv_mmu_fault_area_conf(void *raddr) 461 */ 462 ENTRY(hv_mmu_fault_area_conf) 463 mov %o0, %o2 464 ldx [%o2], %o0 465 mov MMU_SET_INFOPTR, %o5 466 ta FAST_TRAP 467 stx %o1, [%o2] 468 retl 469 nop 470 SET_SIZE(hv_mmu_fault_area_conf) 471 472 /* 473 * Unmap permanent address 474 * arg0 vaddr (%o0) 475 * arg1 context (%o1) 476 * arg2 flags (%o2) 0x1=d 0x2=i 477 */ 478 ENTRY(hv_mmu_unmap_perm_addr) 479 mov UNMAP_PERM_ADDR, %o5 480 ta FAST_TRAP 481 retl 482 nop 483 SET_SIZE(hv_mmu_unmap_perm_addr) 484 485 /* 486 * Set TSB for context 0 487 * arg0 ntsb_descriptor (%o0) 488 * arg1 desc_ra (%o1) 489 */ 490 ENTRY(hv_set_ctx0) 491 mov MMU_TSB_CTX0, %o5 492 ta FAST_TRAP 493 retl 494 nop 495 SET_SIZE(hv_set_ctx0) 496 497 /* 498 * Set TSB for context non0 499 * arg0 ntsb_descriptor (%o0) 500 * arg1 desc_ra (%o1) 501 */ 502 ENTRY(hv_set_ctxnon0) 503 mov MMU_TSB_CTXNON0, %o5 504 ta FAST_TRAP 505 retl 506 nop 507 SET_SIZE(hv_set_ctxnon0) 508 509#ifdef SET_MMU_STATS 510 /* 511 * Returns old stat area on success 512 */ 513 ENTRY(hv_mmu_set_stat_area) 514 mov MMU_STAT_AREA, %o5 515 ta FAST_TRAP 516 retl 517 nop 518 SET_SIZE(hv_mmu_set_stat_area) 519#endif /* SET_MMU_STATS */ 520 521 /* 522 * CPU Q Configure 523 * arg0 queue (%o0) 524 * arg1 Base address RA (%o1) 525 * arg2 Size (%o2) 526 */ 527 ENTRY(hv_cpu_qconf) 528 mov HV_CPU_QCONF, %o5 529 ta FAST_TRAP 530 retl 531 nop 532 SET_SIZE(hv_cpu_qconf) 533 534 /* 535 * arg0 - devhandle 536 * arg1 - devino 537 * 538 * ret0 - status 539 * ret1 - sysino 540 */ 541 ENTRY(hvio_intr_devino_to_sysino) 542 mov HVIO_INTR_DEVINO2SYSINO, %o5 543 ta FAST_TRAP 544 brz,a %o0, 1f 545 stx %o1, [%o2] 5461: retl 547 nop 548 SET_SIZE(hvio_intr_devino_to_sysino) 549 550 /* 551 * arg0 - sysino 552 * 553 * ret0 - status 554 * ret1 - intr_valid_state 555 */ 556 ENTRY(hvio_intr_getvalid) 557 mov %o1, %o2 558 mov HVIO_INTR_GETVALID, %o5 559 ta FAST_TRAP 560 brz,a %o0, 1f 561 stuw %o1, [%o2] 5621: retl 563 nop 564 SET_SIZE(hvio_intr_getvalid) 565 566 /* 567 * arg0 - sysino 568 * arg1 - intr_valid_state 569 * 570 * ret0 - status 571 */ 572 ENTRY(hvio_intr_setvalid) 573 mov HVIO_INTR_SETVALID, %o5 574 ta FAST_TRAP 575 retl 576 nop 577 SET_SIZE(hvio_intr_setvalid) 578 579 /* 580 * arg0 - sysino 581 * 582 * ret0 - status 583 * ret1 - intr_state 584 */ 585 ENTRY(hvio_intr_getstate) 586 mov %o1, %o2 587 mov HVIO_INTR_GETSTATE, %o5 588 ta FAST_TRAP 589 brz,a %o0, 1f 590 stuw %o1, [%o2] 5911: retl 592 nop 593 SET_SIZE(hvio_intr_getstate) 594 595 /* 596 * arg0 - sysino 597 * arg1 - intr_state 598 * 599 * ret0 - status 600 */ 601 ENTRY(hvio_intr_setstate) 602 mov HVIO_INTR_SETSTATE, %o5 603 ta FAST_TRAP 604 retl 605 nop 606 SET_SIZE(hvio_intr_setstate) 607 608 /* 609 * arg0 - sysino 610 * 611 * ret0 - status 612 * ret1 - cpu_id 613 */ 614 ENTRY(hvio_intr_gettarget) 615 mov %o1, %o2 616 mov HVIO_INTR_GETTARGET, %o5 617 ta FAST_TRAP 618 brz,a %o0, 1f 619 stuw %o1, [%o2] 6201: retl 621 nop 622 SET_SIZE(hvio_intr_gettarget) 623 624 /* 625 * arg0 - sysino 626 * arg1 - cpu_id 627 * 628 * ret0 - status 629 */ 630 ENTRY(hvio_intr_settarget) 631 mov HVIO_INTR_SETTARGET, %o5 632 ta FAST_TRAP 633 retl 634 nop 635 SET_SIZE(hvio_intr_settarget) 636 637 /* 638 * hv_cpu_yield(void) 639 */ 640 ENTRY(hv_cpu_yield) 641 mov HV_CPU_YIELD, %o5 642 ta FAST_TRAP 643 retl 644 nop 645 SET_SIZE(hv_cpu_yield) 646 647 /* 648 * int hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 649 */ 650 ENTRY(hv_cpu_state) 651 mov %o1, %o4 ! save datap 652 mov HV_CPU_STATE, %o5 653 ta FAST_TRAP 654 brz,a %o0, 1f 655 stx %o1, [%o4] 6561: 657 retl 658 nop 659 SET_SIZE(hv_cpu_state) 660 661 /* 662 * HV state dump zone Configure 663 * arg0 real adrs of dump buffer (%o0) 664 * arg1 size of dump buffer (%o1) 665 * ret0 status (%o0) 666 * ret1 size of buffer on success and min size on EINVAL (%o1) 667 * hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *ret_size) 668 */ 669 ENTRY(hv_dump_buf_update) 670 mov DUMP_BUF_UPDATE, %o5 671 ta FAST_TRAP 672 retl 673 stx %o1, [%o2] 674 SET_SIZE(hv_dump_buf_update) 675 676 /* 677 * arg0 - timeout value (%o0) 678 * 679 * ret0 - status (%o0) 680 * ret1 - time_remaining (%o1) 681 * hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 682 */ 683 ENTRY(hv_mach_set_watchdog) 684 mov %o1, %o2 685 mov MACH_SET_WATCHDOG, %o5 686 ta FAST_TRAP 687 retl 688 stx %o1, [%o2] 689 SET_SIZE(hv_mach_set_watchdog) 690 691 /* 692 * For memory scrub 693 * int hv_mem_scrub(uint64_t real_addr, uint64_t length, 694 * uint64_t *scrubbed_len); 695 * Retun %o0 -- status 696 * %o1 -- bytes scrubbed 697 */ 698 ENTRY(hv_mem_scrub) 699 mov %o2, %o4 700 mov HV_MEM_SCRUB, %o5 701 ta FAST_TRAP 702 retl 703 stx %o1, [%o4] 704 SET_SIZE(hv_mem_scrub) 705 706 /* 707 * Flush ecache 708 * int hv_mem_sync(uint64_t real_addr, uint64_t length, 709 * uint64_t *flushed_len); 710 * Retun %o0 -- status 711 * %o1 -- bytes flushed 712 */ 713 ENTRY(hv_mem_sync) 714 mov %o2, %o4 715 mov HV_MEM_SYNC, %o5 716 ta FAST_TRAP 717 retl 718 stx %o1, [%o4] 719 SET_SIZE(hv_mem_sync) 720 721 /* 722 * TTRACE_BUF_CONF Configure 723 * arg0 RA base of buffer (%o0) 724 * arg1 buf size in no. of entries (%o1) 725 * ret0 status (%o0) 726 * ret1 minimum size in no. of entries on failure, 727 * actual size in no. of entries on success (%o1) 728 */ 729 ENTRY(hv_ttrace_buf_conf) 730 mov TTRACE_BUF_CONF, %o5 731 ta FAST_TRAP 732 retl 733 stx %o1, [%o2] 734 SET_SIZE(hv_ttrace_buf_conf) 735 736 /* 737 * TTRACE_BUF_INFO 738 * ret0 status (%o0) 739 * ret1 RA base of buffer (%o1) 740 * ret2 size in no. of entries (%o2) 741 */ 742 ENTRY(hv_ttrace_buf_info) 743 mov %o0, %o3 744 mov %o1, %o4 745 mov TTRACE_BUF_INFO, %o5 746 ta FAST_TRAP 747 stx %o1, [%o3] 748 retl 749 stx %o2, [%o4] 750 SET_SIZE(hv_ttrace_buf_info) 751 752 /* 753 * TTRACE_ENABLE 754 * arg0 enable/ disable (%o0) 755 * ret0 status (%o0) 756 * ret1 previous enable state (%o1) 757 */ 758 ENTRY(hv_ttrace_enable) 759 mov %o1, %o2 760 mov TTRACE_ENABLE, %o5 761 ta FAST_TRAP 762 retl 763 stx %o1, [%o2] 764 SET_SIZE(hv_ttrace_enable) 765 766 /* 767 * TTRACE_FREEZE 768 * arg0 enable/ freeze (%o0) 769 * ret0 status (%o0) 770 * ret1 previous freeze state (%o1) 771 */ 772 ENTRY(hv_ttrace_freeze) 773 mov %o1, %o2 774 mov TTRACE_FREEZE, %o5 775 ta FAST_TRAP 776 retl 777 stx %o1, [%o2] 778 SET_SIZE(hv_ttrace_freeze) 779 780 /* 781 * MACH_DESC 782 * arg0 buffer real address 783 * arg1 pointer to uint64_t for size of buffer 784 * ret0 status 785 * ret1 return required size of buffer / returned data size 786 */ 787 ENTRY(hv_mach_desc) 788 mov %o1, %o4 ! save datap 789 ldx [%o1], %o1 790 mov HV_MACH_DESC, %o5 791 ta FAST_TRAP 792 retl 793 stx %o1, [%o4] 794 SET_SIZE(hv_mach_desc) 795 796 /* 797 * hv_ra2pa(uint64_t ra) 798 * 799 * MACH_DESC 800 * arg0 Real address to convert 801 * ret0 Returned physical address or -1 on error 802 */ 803 ENTRY(hv_ra2pa) 804 mov HV_RA2PA, %o5 805 ta FAST_TRAP 806 cmp %o0, 0 807 move %xcc, %o1, %o0 808 movne %xcc, -1, %o0 809 retl 810 nop 811 SET_SIZE(hv_ra2pa) 812 813 /* 814 * hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 815 * 816 * MACH_DESC 817 * arg0 OS function to call 818 * arg1 First arg to OS function 819 * arg2 Second arg to OS function 820 * arg3 Third arg to OS function 821 * ret0 Returned value from function 822 */ 823 824 ENTRY(hv_hpriv) 825 mov HV_HPRIV, %o5 826 ta FAST_TRAP 827 retl 828 nop 829 SET_SIZE(hv_hpriv) 830 831 /* 832 * hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, 833 * uint64_t nentries); 834 */ 835 ENTRY(hv_ldc_tx_qconf) 836 mov LDC_TX_QCONF, %o5 837 ta FAST_TRAP 838 retl 839 nop 840 SET_SIZE(hv_ldc_tx_qconf) 841 842 843 /* 844 * hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, 845 * uint64_t *nentries); 846 */ 847 ENTRY(hv_ldc_tx_qinfo) 848 mov %o1, %g1 849 mov %o2, %g2 850 mov LDC_TX_QINFO, %o5 851 ta FAST_TRAP 852 stx %o1, [%g1] 853 retl 854 stx %o2, [%g2] 855 SET_SIZE(hv_ldc_tx_qinfo) 856 857 858 /* 859 * hv_ldc_tx_get_state(uint64_t channel, 860 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 861 */ 862 ENTRY(hv_ldc_tx_get_state) 863 mov LDC_TX_GET_STATE, %o5 864 mov %o1, %g1 865 mov %o2, %g2 866 mov %o3, %g3 867 ta FAST_TRAP 868 stx %o1, [%g1] 869 stx %o2, [%g2] 870 retl 871 stx %o3, [%g3] 872 SET_SIZE(hv_ldc_tx_get_state) 873 874 875 /* 876 * hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 877 */ 878 ENTRY(hv_ldc_tx_set_qtail) 879 mov LDC_TX_SET_QTAIL, %o5 880 ta FAST_TRAP 881 retl 882 SET_SIZE(hv_ldc_tx_set_qtail) 883 884 885 /* 886 * hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, 887 * uint64_t nentries); 888 */ 889 ENTRY(hv_ldc_rx_qconf) 890 mov LDC_RX_QCONF, %o5 891 ta FAST_TRAP 892 retl 893 nop 894 SET_SIZE(hv_ldc_rx_qconf) 895 896 897 /* 898 * hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, 899 * uint64_t *nentries); 900 */ 901 ENTRY(hv_ldc_rx_qinfo) 902 mov %o1, %g1 903 mov %o2, %g2 904 mov LDC_RX_QINFO, %o5 905 ta FAST_TRAP 906 stx %o1, [%g1] 907 retl 908 stx %o2, [%g2] 909 SET_SIZE(hv_ldc_rx_qinfo) 910 911 912 /* 913 * hv_ldc_rx_get_state(uint64_t channel, 914 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 915 */ 916 ENTRY(hv_ldc_rx_get_state) 917 mov LDC_RX_GET_STATE, %o5 918 mov %o1, %g1 919 mov %o2, %g2 920 mov %o3, %g3 921 ta FAST_TRAP 922 stx %o1, [%g1] 923 stx %o2, [%g2] 924 retl 925 stx %o3, [%g3] 926 SET_SIZE(hv_ldc_rx_get_state) 927 928 929 /* 930 * hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 931 */ 932 ENTRY(hv_ldc_rx_set_qhead) 933 mov LDC_RX_SET_QHEAD, %o5 934 ta FAST_TRAP 935 retl 936 SET_SIZE(hv_ldc_rx_set_qhead) 937 938 /* 939 * hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, 940 * uint64_t tbl_entries) 941 */ 942 ENTRY(hv_ldc_set_map_table) 943 mov LDC_SET_MAP_TABLE, %o5 944 ta FAST_TRAP 945 retl 946 nop 947 SET_SIZE(hv_ldc_set_map_table) 948 949 950 /* 951 * hv_ldc_get_map_table(uint64_t channel, uint64_t *tbl_ra, 952 * uint64_t *tbl_entries) 953 */ 954 ENTRY(hv_ldc_get_map_table) 955 mov %o1, %g1 956 mov %o2, %g2 957 mov LDC_GET_MAP_TABLE, %o5 958 ta FAST_TRAP 959 stx %o1, [%g1] 960 retl 961 stx %o2, [%g2] 962 SET_SIZE(hv_ldc_get_map_table) 963 964 965 /* 966 * hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 967 * uint64_t raddr, uint64_t length, uint64_t *lengthp); 968 */ 969 ENTRY(hv_ldc_copy) 970 mov %o5, %g1 971 mov LDC_COPY, %o5 972 ta FAST_TRAP 973 retl 974 stx %o1, [%g1] 975 SET_SIZE(hv_ldc_copy) 976 977 978 /* 979 * hv_ldc_mapin(uint64_t channel, uint64_t cookie, uint64_t *raddr, 980 * uint64_t *perm) 981 */ 982 ENTRY(hv_ldc_mapin) 983 mov %o2, %g1 984 mov %o3, %g2 985 mov LDC_MAPIN, %o5 986 ta FAST_TRAP 987 stx %o1, [%g1] 988 retl 989 stx %o2, [%g2] 990 SET_SIZE(hv_ldc_mapin) 991 992 993 /* 994 * hv_ldc_unmap(uint64_t raddr) 995 */ 996 ENTRY(hv_ldc_unmap) 997 mov LDC_UNMAP, %o5 998 ta FAST_TRAP 999 retl 1000 nop 1001 SET_SIZE(hv_ldc_unmap) 1002 1003 1004 /* 1005 * hv_ldc_revoke(uint64_t channel, uint64_t cookie, 1006 * uint64_t revoke_cookie 1007 */ 1008 ENTRY(hv_ldc_revoke) 1009 mov LDC_REVOKE, %o5 1010 ta FAST_TRAP 1011 retl 1012 nop 1013 SET_SIZE(hv_ldc_revoke) 1014 1015 1016 /* 1017 * hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, 1018 * uint64_t *cookie); 1019 */ 1020 ENTRY(hvldc_intr_getcookie) 1021 mov %o2, %g1 1022 mov VINTR_GET_COOKIE, %o5 1023 ta FAST_TRAP 1024 retl 1025 stx %o1, [%g1] 1026 SET_SIZE(hvldc_intr_getcookie) 1027 1028 /* 1029 * hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, 1030 * uint64_t cookie); 1031 */ 1032 ENTRY(hvldc_intr_setcookie) 1033 mov VINTR_SET_COOKIE, %o5 1034 ta FAST_TRAP 1035 retl 1036 nop 1037 SET_SIZE(hvldc_intr_setcookie) 1038 1039 1040 /* 1041 * hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, 1042 * int *intr_valid_state); 1043 */ 1044 ENTRY(hvldc_intr_getvalid) 1045 mov %o2, %g1 1046 mov VINTR_GET_VALID, %o5 1047 ta FAST_TRAP 1048 retl 1049 stuw %o1, [%g1] 1050 SET_SIZE(hvldc_intr_getvalid) 1051 1052 /* 1053 * hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, 1054 * int intr_valid_state); 1055 */ 1056 ENTRY(hvldc_intr_setvalid) 1057 mov VINTR_SET_VALID, %o5 1058 ta FAST_TRAP 1059 retl 1060 nop 1061 SET_SIZE(hvldc_intr_setvalid) 1062 1063 /* 1064 * hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, 1065 * int *intr_state); 1066 */ 1067 ENTRY(hvldc_intr_getstate) 1068 mov %o2, %g1 1069 mov VINTR_GET_STATE, %o5 1070 ta FAST_TRAP 1071 retl 1072 stuw %o1, [%g1] 1073 SET_SIZE(hvldc_intr_getstate) 1074 1075 /* 1076 * hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, 1077 * int intr_state); 1078 */ 1079 ENTRY(hvldc_intr_setstate) 1080 mov VINTR_SET_STATE, %o5 1081 ta FAST_TRAP 1082 retl 1083 nop 1084 SET_SIZE(hvldc_intr_setstate) 1085 1086 /* 1087 * hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, 1088 * uint32_t *cpuid); 1089 */ 1090 ENTRY(hvldc_intr_gettarget) 1091 mov %o2, %g1 1092 mov VINTR_GET_TARGET, %o5 1093 ta FAST_TRAP 1094 retl 1095 stuw %o1, [%g1] 1096 SET_SIZE(hvldc_intr_gettarget) 1097 1098 /* 1099 * hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, 1100 * uint32_t cpuid); 1101 */ 1102 ENTRY(hvldc_intr_settarget) 1103 mov VINTR_SET_TARGET, %o5 1104 ta FAST_TRAP 1105 retl 1106 nop 1107 SET_SIZE(hvldc_intr_settarget) 1108 1109 /* 1110 * hv_api_get_version(uint64_t api_group, uint64_t *majorp, 1111 * uint64_t *minorp) 1112 * 1113 * API_GET_VERSION 1114 * arg0 API group 1115 * ret0 status 1116 * ret1 major number 1117 * ret2 minor number 1118 */ 1119 ENTRY(hv_api_get_version) 1120 mov %o1, %o3 1121 mov %o2, %o4 1122 mov API_GET_VERSION, %o5 1123 ta CORE_TRAP 1124 stx %o1, [%o3] 1125 retl 1126 stx %o2, [%o4] 1127 SET_SIZE(hv_api_get_version) 1128 1129 /* 1130 * hv_api_set_version(uint64_t api_group, uint64_t major, 1131 * uint64_t minor, uint64_t *supported_minor) 1132 * 1133 * API_SET_VERSION 1134 * arg0 API group 1135 * arg1 major number 1136 * arg2 requested minor number 1137 * ret0 status 1138 * ret1 actual minor number 1139 */ 1140 ENTRY(hv_api_set_version) 1141 mov %o3, %o4 1142 mov API_SET_VERSION, %o5 1143 ta CORE_TRAP 1144 retl 1145 stx %o1, [%o4] 1146 SET_SIZE(hv_api_set_version) 1147 1148 /* 1149 * %o0 - buffer real address 1150 * %o1 - buffer size 1151 * %o2 - &characters written 1152 * returns 1153 * status 1154 */ 1155 ENTRY(hv_cnwrite) 1156 mov CONS_WRITE, %o5 1157 ta FAST_TRAP 1158 retl 1159 stx %o1, [%o2] 1160 SET_SIZE(hv_cnwrite) 1161 1162 /* 1163 * %o0 character buffer ra 1164 * %o1 buffer size 1165 * %o2 pointer to returned size 1166 * return values: 1167 * 0 success 1168 * hv_errno failure 1169 */ 1170 ENTRY(hv_cnread) 1171 mov CONS_READ, %o5 1172 ta FAST_TRAP 1173 brnz,a %o0, 1f ! failure, just return error 1174 nop 1175 1176 cmp %o1, H_BREAK 1177 be 1f 1178 mov %o1, %o0 1179 1180 cmp %o1, H_HUP 1181 be 1f 1182 mov %o1, %o0 1183 1184 stx %o1, [%o2] ! success, save count and return 0 1185 mov 0, %o0 11861: 1187 retl 1188 nop 1189 SET_SIZE(hv_cnread) 1190 1191#endif /* lint || __lint */ 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