xref: /titanic_52/usr/src/uts/sun4v/io/vnet_dds_hcall.s (revision 678453a8ed49104d8adad58f3ba591bdc39883e8)
1*678453a8Sspeer/*
2*678453a8Sspeer * CDDL HEADER START
3*678453a8Sspeer *
4*678453a8Sspeer * The contents of this file are subject to the terms of the
5*678453a8Sspeer * Common Development and Distribution License (the "License").
6*678453a8Sspeer * You may not use this file except in compliance with the License.
7*678453a8Sspeer *
8*678453a8Sspeer * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*678453a8Sspeer * or http://www.opensolaris.org/os/licensing.
10*678453a8Sspeer * See the License for the specific language governing permissions
11*678453a8Sspeer * and limitations under the License.
12*678453a8Sspeer *
13*678453a8Sspeer * When distributing Covered Code, include this CDDL HEADER in each
14*678453a8Sspeer * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*678453a8Sspeer * If applicable, add the following below this CDDL HEADER, with the
16*678453a8Sspeer * fields enclosed by brackets "[]" replaced with your own identifying
17*678453a8Sspeer * information: Portions Copyright [yyyy] [name of copyright owner]
18*678453a8Sspeer *
19*678453a8Sspeer * CDDL HEADER END
20*678453a8Sspeer */
21*678453a8Sspeer
22*678453a8Sspeer/*
23*678453a8Sspeer * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
24*678453a8Sspeer * Use is subject to license terms.
25*678453a8Sspeer */
26*678453a8Sspeer
27*678453a8Sspeer#pragma ident	"%Z%%M%	%I%	%E% SMI"
28*678453a8Sspeer
29*678453a8Sspeer/*
30*678453a8Sspeer * Hypervisor calls called by niu leaf driver.
31*678453a8Sspeer*/
32*678453a8Sspeer
33*678453a8Sspeer#include <sys/asm_linkage.h>
34*678453a8Sspeer#include <sys/hypervisor_api.h>
35*678453a8Sspeer
36*678453a8Sspeer/*
37*678453a8Sspeer * NIU HV API v1.1 definitions
38*678453a8Sspeer */
39*678453a8Sspeer#define	N2NIU_VR_GETINFO	0x148
40*678453a8Sspeer#define	N2NIU_VR_GET_RX_MAP	0x14d
41*678453a8Sspeer#define	N2NIU_VR_GET_TX_MAP	0x14e
42*678453a8Sspeer#define N2NIU_VRRX_SET_INO	0x150
43*678453a8Sspeer#define N2NIU_VRTX_SET_INO	0x151
44*678453a8Sspeer
45*678453a8Sspeer
46*678453a8Sspeer#if defined(lint) || defined(__lint)
47*678453a8Sspeer
48*678453a8Sspeer/*ARGSUSED*/
49*678453a8Sspeeruint64_t
50*678453a8Sspeervdds_hv_niu_vr_getinfo(uint32_t cookie, uint64_t *real_start, uint64_t *size)
51*678453a8Sspeer{ return (0); }
52*678453a8Sspeer
53*678453a8Sspeer/*ARGSUSED*/
54*678453a8Sspeeruint64_t
55*678453a8Sspeervdds_hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map)
56*678453a8Sspeer{ return (0); }
57*678453a8Sspeer
58*678453a8Sspeer/*ARGSUSED*/
59*678453a8Sspeeruint64_t
60*678453a8Sspeervdds_hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map)
61*678453a8Sspeer{ return (0); }
62*678453a8Sspeer
63*678453a8Sspeer/*ARGSUSED*/
64*678453a8Sspeeruint64_t
65*678453a8Sspeervdds_hv_niu_vrtx_set_ino(uint32_t cookie, uint64_t vch_idx, uint32_t ino)
66*678453a8Sspeer{ return (0); }
67*678453a8Sspeer
68*678453a8Sspeer/*ARGSUSED*/
69*678453a8Sspeeruint64_t
70*678453a8Sspeervdds_hv_niu_vrrx_set_ino(uint32_t cookie, uint64_t vch_idx, uint32_t ino)
71*678453a8Sspeer{ return (0); }
72*678453a8Sspeer
73*678453a8Sspeer#else	/* lint || __lint */
74*678453a8Sspeer
75*678453a8Sspeer	/*
76*678453a8Sspeer	 * vdds_hv_niu_vr_getinfo(uint32_t cookie, uint64_t &real_start,
77*678453a8Sspeer	 *     uint64_t &size)
78*678453a8Sspeer	 */
79*678453a8Sspeer	ENTRY(vdds_hv_niu_vr_getinfo)
80*678453a8Sspeer	mov	%o1, %g1
81*678453a8Sspeer	mov	%o2, %g2
82*678453a8Sspeer	mov	N2NIU_VR_GETINFO, %o5
83*678453a8Sspeer	ta	FAST_TRAP
84*678453a8Sspeer	stx	%o1, [%g1]
85*678453a8Sspeer	retl
86*678453a8Sspeer	stx	%o2, [%g2]
87*678453a8Sspeer	SET_SIZE(vdds_hv_niu_vr_getinfo)
88*678453a8Sspeer
89*678453a8Sspeer	/*
90*678453a8Sspeer	 * vdds_hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map)
91*678453a8Sspeer	 */
92*678453a8Sspeer	ENTRY(vdds_hv_niu_vr_get_rxmap)
93*678453a8Sspeer	mov	%o1, %g1
94*678453a8Sspeer	mov	N2NIU_VR_GET_RX_MAP, %o5
95*678453a8Sspeer	ta	FAST_TRAP
96*678453a8Sspeer	retl
97*678453a8Sspeer	stx	%o1, [%g1]
98*678453a8Sspeer	SET_SIZE(vdds_hv_niu_vr_get_rxmap)
99*678453a8Sspeer
100*678453a8Sspeer	/*
101*678453a8Sspeer	 * vdds_hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map)
102*678453a8Sspeer	 */
103*678453a8Sspeer	ENTRY(vdds_hv_niu_vr_get_txmap)
104*678453a8Sspeer	mov	%o1, %g1
105*678453a8Sspeer	mov	N2NIU_VR_GET_TX_MAP, %o5
106*678453a8Sspeer	ta	FAST_TRAP
107*678453a8Sspeer	retl
108*678453a8Sspeer	stx	%o1, [%g1]
109*678453a8Sspeer	SET_SIZE(vdds_hv_niu_vr_get_txmap)
110*678453a8Sspeer
111*678453a8Sspeer	/*
112*678453a8Sspeer	 * vdds_hv_niu_vrrx_set_ino(uint32_t cookie, uint64_t vch_idx, uint32_t ino)
113*678453a8Sspeer	 */
114*678453a8Sspeer	ENTRY(vdds_hv_niu_vrrx_set_ino)
115*678453a8Sspeer	mov	N2NIU_VRRX_SET_INO, %o5
116*678453a8Sspeer	ta	FAST_TRAP
117*678453a8Sspeer	retl
118*678453a8Sspeer	nop
119*678453a8Sspeer	SET_SIZE(vdds_hv_niu_vrrx_set_ino)
120*678453a8Sspeer
121*678453a8Sspeer	/*
122*678453a8Sspeer	 * vdds_hv_niu_vrtx_set_ino(uint32_t cookie, uint64_t vch_idx, uint32_t ino)
123*678453a8Sspeer	 */
124*678453a8Sspeer	ENTRY(vdds_hv_niu_vrtx_set_ino)
125*678453a8Sspeer	mov	N2NIU_VRTX_SET_INO, %o5
126*678453a8Sspeer	ta	FAST_TRAP
127*678453a8Sspeer	retl
128*678453a8Sspeer	nop
129*678453a8Sspeer	SET_SIZE(vdds_hv_niu_vrtx_set_ino)
130*678453a8Sspeer
131*678453a8Sspeer#endif	/* lint || __lint */
132