1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/sysmacros.h> 30 #include <sys/ddi.h> 31 #include <sys/async.h> 32 #include <sys/sunddi.h> 33 #include <sys/ddifm.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/vmem.h> 36 #include <sys/intr.h> 37 #include <sys/ivintr.h> 38 #include <sys/errno.h> 39 #include <sys/hypervisor_api.h> 40 #include <sys/hsvc.h> 41 #include <px_obj.h> 42 #include <sys/machsystm.h> 43 #include <sys/hotplug/pci/pcihp.h> 44 #include "px_lib4v.h" 45 #include "px_err.h" 46 47 /* mask for the ranges property in calculating the real PFN range */ 48 uint_t px_ranges_phi_mask = ((1 << 28) -1); 49 50 /* 51 * Hypervisor VPCI services information for the px nexus driver. 52 */ 53 static uint64_t px_vpci_min_ver; /* Negotiated VPCI API minor version */ 54 static uint_t px_vpci_users = 0; /* VPCI API users */ 55 56 static hsvc_info_t px_hsvc = { 57 HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER, 58 PX_VPCI_MINOR_VER, "PX" 59 }; 60 61 int 62 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 63 { 64 px_nexus_regspec_t *rp; 65 uint_t reglen; 66 int ret; 67 68 uint64_t mjrnum; 69 uint64_t mnrnum; 70 71 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 72 73 /* 74 * Check HV intr group api versioning. 75 * This driver uses the old interrupt routines which are supported 76 * in old firmware in the CORE API group and in newer firmware in 77 * the INTR API group. Support for these calls will be dropped 78 * once the INTR API group major goes to 2. 79 */ 80 if ((hsvc_version(HSVC_GROUP_INTR, &mjrnum, &mnrnum) == 0) && 81 (mjrnum > 1)) { 82 cmn_err(CE_WARN, "niumx: unsupported intr api group: " 83 "maj:0x%lx, min:0x%lx", mjrnum, mnrnum); 84 return (ENOTSUP); 85 } 86 87 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 88 "reg", (uchar_t **)&rp, ®len); 89 if (ret != DDI_PROP_SUCCESS) { 90 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 91 return (DDI_FAILURE); 92 } 93 94 /* 95 * Initilize device handle. The device handle uniquely identifies 96 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 97 * of the first entry of the SUN4V device's "reg" property as 98 * defined by the SUN4V Bus Binding to Open Firmware. 99 */ 100 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 101 ddi_prop_free(rp); 102 103 /* 104 * hotplug implementation requires this property to be associated with 105 * any indirect PCI config access services 106 */ 107 (void) ddi_prop_update_int(makedevice(ddi_driver_major(dip), 108 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 109 PCI_BUS_CONF_MAP_PROP, 1); 110 111 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 112 113 /* 114 * Negotiate the API version for VPCI hypervisor services. 115 */ 116 if (px_vpci_users++) 117 return (DDI_SUCCESS); 118 119 if ((ret = hsvc_register(&px_hsvc, &px_vpci_min_ver)) != 0) { 120 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 121 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 122 px_hsvc.hsvc_modname, px_hsvc.hsvc_group, 123 px_hsvc.hsvc_major, px_hsvc.hsvc_minor, ret); 124 125 return (DDI_FAILURE); 126 } 127 128 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " 129 "major 0x%lx minor 0x%lx\n", px_hsvc.hsvc_major, px_vpci_min_ver); 130 131 return (DDI_SUCCESS); 132 } 133 134 /*ARGSUSED*/ 135 int 136 px_lib_dev_fini(dev_info_t *dip) 137 { 138 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 139 140 (void) ddi_prop_remove(makedevice(ddi_driver_major(dip), 141 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 142 PCI_BUS_CONF_MAP_PROP); 143 144 if (--px_vpci_users == 0) 145 (void) hsvc_unregister(&px_hsvc); 146 147 return (DDI_SUCCESS); 148 } 149 150 /*ARGSUSED*/ 151 int 152 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 153 sysino_t *sysino) 154 { 155 uint64_t ret; 156 157 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 158 "devino 0x%x\n", dip, devino); 159 160 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 161 devino, sysino)) != H_EOK) { 162 DBG(DBG_LIB_INT, dip, 163 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 164 return (DDI_FAILURE); 165 } 166 167 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 168 *sysino); 169 170 return (DDI_SUCCESS); 171 } 172 173 /*ARGSUSED*/ 174 int 175 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 176 intr_valid_state_t *intr_valid_state) 177 { 178 uint64_t ret; 179 180 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 181 dip, sysino); 182 183 if ((ret = hvio_intr_getvalid(sysino, 184 (int *)intr_valid_state)) != H_EOK) { 185 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 186 ret); 187 return (DDI_FAILURE); 188 } 189 190 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 191 *intr_valid_state); 192 193 return (DDI_SUCCESS); 194 } 195 196 /*ARGSUSED*/ 197 int 198 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 199 intr_valid_state_t intr_valid_state) 200 { 201 uint64_t ret; 202 203 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 204 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 205 206 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 207 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 208 ret); 209 return (DDI_FAILURE); 210 } 211 212 return (DDI_SUCCESS); 213 } 214 215 /*ARGSUSED*/ 216 int 217 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 218 intr_state_t *intr_state) 219 { 220 uint64_t ret; 221 222 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 223 dip, sysino); 224 225 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 226 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 227 ret); 228 return (DDI_FAILURE); 229 } 230 231 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 232 *intr_state); 233 234 return (DDI_SUCCESS); 235 } 236 237 /*ARGSUSED*/ 238 int 239 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 240 intr_state_t intr_state) 241 { 242 uint64_t ret; 243 244 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 245 "intr_state 0x%x\n", dip, sysino, intr_state); 246 247 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 248 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 249 ret); 250 return (DDI_FAILURE); 251 } 252 253 return (DDI_SUCCESS); 254 } 255 256 /*ARGSUSED*/ 257 int 258 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 259 { 260 uint64_t ret; 261 262 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 263 dip, sysino); 264 265 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 266 DBG(DBG_LIB_INT, dip, 267 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 268 return (DDI_FAILURE); 269 } 270 271 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 272 273 return (DDI_SUCCESS); 274 } 275 276 /*ARGSUSED*/ 277 int 278 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 279 { 280 uint64_t ret; 281 282 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 283 "cpuid 0x%x\n", dip, sysino, cpuid); 284 285 ret = hvio_intr_settarget(sysino, cpuid); 286 if (ret == H_ECPUERROR) { 287 cmn_err(CE_PANIC, 288 "px_lib_intr_settarget: hvio_intr_settarget failed, " 289 "ret = 0x%lx, cpuid = 0x%x, sysino = 0x%lx\n", ret, 290 cpuid, sysino); 291 } else if (ret != H_EOK) { 292 DBG(DBG_LIB_INT, dip, 293 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 294 return (DDI_FAILURE); 295 } 296 297 return (DDI_SUCCESS); 298 } 299 300 /*ARGSUSED*/ 301 int 302 px_lib_intr_reset(dev_info_t *dip) 303 { 304 px_t *px_p = DIP_TO_STATE(dip); 305 px_ib_t *ib_p = px_p->px_ib_p; 306 px_ino_t *ino_p; 307 308 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 309 310 mutex_enter(&ib_p->ib_ino_lst_mutex); 311 312 /* Reset all Interrupts */ 313 for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next_p) { 314 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 315 INTR_IDLE_STATE) != DDI_SUCCESS) 316 return (BF_FATAL); 317 } 318 319 mutex_exit(&ib_p->ib_ino_lst_mutex); 320 321 return (BF_NONE); 322 } 323 324 /*ARGSUSED*/ 325 int 326 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 327 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 328 { 329 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 330 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 331 io_page_list_t *pfns, *pfn_p; 332 pages_t ttes_mapped = 0; 333 int i, err = DDI_SUCCESS; 334 335 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 336 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 337 dip, tsbid, pages, attr, addr, pfn_index, flags); 338 339 if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), 340 KM_NOSLEEP)) == NULL) { 341 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 342 return (DDI_FAILURE); 343 } 344 345 for (i = 0; i < pages; i++) 346 pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i)); 347 348 /* 349 * If HV VPCI version is 1.1 and higher, pass BDF, phantom function, 350 * and relaxed ordering attributes. Otherwise, pass only read or write 351 * attribute. 352 */ 353 if (px_vpci_min_ver == PX_VPCI_MINOR_VER_0) 354 attr = attr & (PCI_MAP_ATTR_READ | PCI_MAP_ATTR_WRITE); 355 356 while ((ttes_mapped = pfn_p - pfns) < pages) { 357 uintptr_t ra = va_to_pa(pfn_p); 358 pages_t ttes2map; 359 uint64_t ret; 360 361 ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3; 362 ra = MMU_PTOB(MMU_BTOP(ra)); 363 364 for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map; 365 ttes2map -= ttes_mapped, pfn_p += ttes_mapped) { 366 367 ttes_mapped = 0; 368 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 369 PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), 370 ttes2map, attr, (io_page_list_t *)(ra | 371 ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), 372 &ttes_mapped)) != H_EOK) { 373 DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " 374 "ret 0x%lx\n", ret); 375 376 ttes_mapped = pfn_p - pfns; 377 err = DDI_FAILURE; 378 goto cleanup; 379 } 380 381 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " 382 "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%x " 383 "ra 0x%p ttes_mapped 0x%x\n", tsb_num, 384 tsb_index + (pfn_p - pfns), ttes2map, attr, 385 ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), 386 ttes_mapped); 387 } 388 } 389 390 cleanup: 391 if ((err == DDI_FAILURE) && ttes_mapped) 392 (void) px_lib_iommu_demap(dip, tsbid, ttes_mapped); 393 394 kmem_free(pfns, pages * sizeof (io_page_list_t)); 395 return (err); 396 } 397 398 /*ARGSUSED*/ 399 int 400 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 401 { 402 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 403 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 404 pages_t ttes2demap, ttes_demapped = 0; 405 uint64_t ret; 406 407 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 408 "pages 0x%x\n", dip, tsbid, pages); 409 410 for (ttes2demap = pages; ttes2demap; 411 ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) { 412 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 413 PCI_TSBID(tsb_num, tsb_index), ttes2demap, 414 &ttes_demapped)) != H_EOK) { 415 DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, " 416 "ret 0x%lx\n", ret); 417 418 return (DDI_FAILURE); 419 } 420 421 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x " 422 "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n", 423 tsb_num, tsb_index, ttes2demap, ttes_demapped); 424 } 425 426 return (DDI_SUCCESS); 427 } 428 429 /*ARGSUSED*/ 430 int 431 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 432 r_addr_t *r_addr_p) 433 { 434 uint64_t ret; 435 436 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 437 dip, tsbid); 438 439 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 440 attr_p, r_addr_p)) != H_EOK) { 441 DBG(DBG_LIB_DMA, dip, 442 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 443 444 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 445 } 446 447 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 448 *attr_p, *r_addr_p); 449 450 return (DDI_SUCCESS); 451 } 452 453 /*ARGSUSED*/ 454 uint64_t 455 px_get_rng_parent_hi_mask(px_t *px_p) 456 { 457 return (PX_RANGE_PROP_MASK); 458 } 459 460 /* 461 * Checks dma attributes against system bypass ranges 462 * A sun4v device must be capable of generating the entire 64-bit 463 * address in order to perform bypass DMA. 464 */ 465 /*ARGSUSED*/ 466 int 467 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 468 uint64_t *lo_p, uint64_t *hi_p) 469 { 470 if ((attr_p->dma_attr_addr_lo != 0ull) || 471 (attr_p->dma_attr_addr_hi != UINT64_MAX)) { 472 473 return (DDI_DMA_BADATTR); 474 } 475 476 *lo_p = 0ull; 477 *hi_p = UINT64_MAX; 478 479 return (DDI_SUCCESS); 480 } 481 482 483 /*ARGSUSED*/ 484 int 485 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 486 io_addr_t *io_addr_p) 487 { 488 uint64_t ret; 489 490 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 491 "attr 0x%x\n", dip, ra, attr); 492 493 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 494 attr, io_addr_p)) != H_EOK) { 495 DBG(DBG_LIB_DMA, dip, 496 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 497 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 498 } 499 500 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 501 *io_addr_p); 502 503 return (DDI_SUCCESS); 504 } 505 506 /*ARGSUSED*/ 507 int 508 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 509 off_t off, size_t len, uint_t cache_flags) 510 { 511 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 512 uint64_t sync_dir; 513 size_t bytes_synced; 514 int end, idx; 515 off_t pg_off; 516 devhandle_t hdl = DIP_TO_HANDLE(dip); /* need to cache hdl */ 517 518 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 519 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 520 dip, rdip, handle, off, len, cache_flags); 521 522 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 523 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 524 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 525 return (DDI_FAILURE); 526 } 527 528 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 529 return (DDI_SUCCESS); 530 531 if (!len) 532 len = mp->dmai_size; 533 534 if (mp->dmai_rflags & DDI_DMA_READ) 535 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 536 else 537 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 538 539 off += mp->dmai_offset; 540 pg_off = off & MMU_PAGEOFFSET; 541 542 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: page offset %x size %x\n", 543 pg_off, len); 544 545 /* sync on page basis */ 546 end = MMU_BTOPR(off + len - 1); 547 for (idx = MMU_BTOP(off); idx < end; idx++, 548 len -= bytes_synced, pg_off = 0) { 549 size_t bytes_to_sync = bytes_to_sync = 550 MIN(len, MMU_PAGESIZE - pg_off); 551 552 if (hvio_dma_sync(hdl, MMU_PTOB(PX_GET_MP_PFN(mp, idx)) + 553 pg_off, bytes_to_sync, sync_dir, &bytes_synced) != H_EOK) 554 break; 555 556 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: Called hvio_dma_sync " 557 "ra = %p bytes to sync = %x bytes synced %x\n", 558 MMU_PTOB(PX_GET_MP_PFN(mp, idx)) + pg_off, bytes_to_sync, 559 bytes_synced); 560 561 if (bytes_to_sync != bytes_synced) 562 break; 563 } 564 565 return (len ? DDI_FAILURE : DDI_SUCCESS); 566 } 567 568 569 /* 570 * MSIQ Functions: 571 */ 572 573 /*ARGSUSED*/ 574 int 575 px_lib_msiq_init(dev_info_t *dip) 576 { 577 px_t *px_p = DIP_TO_STATE(dip); 578 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 579 r_addr_t ra; 580 size_t msiq_size; 581 uint_t rec_cnt; 582 int i, err = DDI_SUCCESS; 583 uint64_t ret; 584 585 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 586 587 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 588 589 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 590 ra = (r_addr_t)va_to_pa((caddr_t)msiq_state_p->msiq_buf_p + 591 (i * msiq_size)); 592 593 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 594 (i + msiq_state_p->msiq_1st_msiq_id), 595 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 596 DBG(DBG_LIB_MSIQ, dip, 597 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 598 err = DDI_FAILURE; 599 break; 600 } 601 602 if ((err = px_lib_msiq_info(dip, 603 (i + msiq_state_p->msiq_1st_msiq_id), 604 &ra, &rec_cnt)) != DDI_SUCCESS) { 605 DBG(DBG_LIB_MSIQ, dip, 606 "px_lib_msiq_info failed, ret 0x%x\n", err); 607 err = DDI_FAILURE; 608 break; 609 } 610 611 DBG(DBG_LIB_MSIQ, dip, 612 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 613 } 614 615 return (err); 616 } 617 618 /*ARGSUSED*/ 619 int 620 px_lib_msiq_fini(dev_info_t *dip) 621 { 622 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 623 624 return (DDI_SUCCESS); 625 } 626 627 /*ARGSUSED*/ 628 int 629 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 630 uint_t *msiq_rec_cnt_p) 631 { 632 uint64_t ret; 633 634 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 635 dip, msiq_id); 636 637 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 638 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 639 DBG(DBG_LIB_MSIQ, dip, 640 "hvio_msiq_info failed, ret 0x%lx\n", ret); 641 return (DDI_FAILURE); 642 } 643 644 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 645 ra_p, *msiq_rec_cnt_p); 646 647 return (DDI_SUCCESS); 648 } 649 650 /*ARGSUSED*/ 651 int 652 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 653 pci_msiq_valid_state_t *msiq_valid_state) 654 { 655 uint64_t ret; 656 657 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 658 dip, msiq_id); 659 660 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 661 msiq_id, msiq_valid_state)) != H_EOK) { 662 DBG(DBG_LIB_MSIQ, dip, 663 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 664 return (DDI_FAILURE); 665 } 666 667 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 668 *msiq_valid_state); 669 670 return (DDI_SUCCESS); 671 } 672 673 /*ARGSUSED*/ 674 int 675 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 676 pci_msiq_valid_state_t msiq_valid_state) 677 { 678 uint64_t ret; 679 680 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 681 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 682 683 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 684 msiq_id, msiq_valid_state)) != H_EOK) { 685 DBG(DBG_LIB_MSIQ, dip, 686 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 687 return (DDI_FAILURE); 688 } 689 690 return (DDI_SUCCESS); 691 } 692 693 /*ARGSUSED*/ 694 int 695 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 696 pci_msiq_state_t *msiq_state) 697 { 698 uint64_t ret; 699 700 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 701 dip, msiq_id); 702 703 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 704 msiq_id, msiq_state)) != H_EOK) { 705 DBG(DBG_LIB_MSIQ, dip, 706 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 707 return (DDI_FAILURE); 708 } 709 710 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 711 *msiq_state); 712 713 return (DDI_SUCCESS); 714 } 715 716 /*ARGSUSED*/ 717 int 718 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 719 pci_msiq_state_t msiq_state) 720 { 721 uint64_t ret; 722 723 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 724 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 725 726 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 727 msiq_id, msiq_state)) != H_EOK) { 728 DBG(DBG_LIB_MSIQ, dip, 729 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 730 return (DDI_FAILURE); 731 } 732 733 return (DDI_SUCCESS); 734 } 735 736 /*ARGSUSED*/ 737 int 738 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 739 msiqhead_t *msiq_head_p) 740 { 741 uint64_t ret; 742 743 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 744 dip, msiq_id); 745 746 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 747 msiq_id, msiq_head_p)) != H_EOK) { 748 DBG(DBG_LIB_MSIQ, dip, 749 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 750 return (DDI_FAILURE); 751 } 752 753 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 754 755 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 756 *msiq_head_p); 757 758 return (DDI_SUCCESS); 759 } 760 761 /*ARGSUSED*/ 762 int 763 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 764 msiqhead_t msiq_head) 765 { 766 uint64_t ret; 767 768 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 769 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 770 771 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 772 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 773 DBG(DBG_LIB_MSIQ, dip, 774 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 775 return (DDI_FAILURE); 776 } 777 778 return (DDI_SUCCESS); 779 } 780 781 /*ARGSUSED*/ 782 int 783 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 784 msiqtail_t *msiq_tail_p) 785 { 786 uint64_t ret; 787 788 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 789 dip, msiq_id); 790 791 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 792 msiq_id, msiq_tail_p)) != H_EOK) { 793 DBG(DBG_LIB_MSIQ, dip, 794 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 795 return (DDI_FAILURE); 796 } 797 798 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 799 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 800 *msiq_tail_p); 801 802 return (DDI_SUCCESS); 803 } 804 805 /*ARGSUSED*/ 806 void 807 px_lib_get_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p, 808 msiq_rec_t *msiq_rec_p) 809 { 810 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 811 812 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 813 814 if (!curr_msiq_rec_p->msiq_rec_type) { 815 /* Set msiq_rec_type to zero */ 816 msiq_rec_p->msiq_rec_type = 0; 817 818 return; 819 } 820 821 *msiq_rec_p = *curr_msiq_rec_p; 822 } 823 824 /*ARGSUSED*/ 825 void 826 px_lib_clr_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p) 827 { 828 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 829 830 DBG(DBG_LIB_MSIQ, dip, "px_lib_clr_msiq_rec: dip 0x%p\n", dip); 831 832 /* Zero out msiq_rec_type field */ 833 curr_msiq_rec_p->msiq_rec_type = 0; 834 } 835 836 /* 837 * MSI Functions: 838 */ 839 840 /*ARGSUSED*/ 841 int 842 px_lib_msi_init(dev_info_t *dip) 843 { 844 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 845 846 /* Noop */ 847 return (DDI_SUCCESS); 848 } 849 850 /*ARGSUSED*/ 851 int 852 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 853 msiqid_t *msiq_id) 854 { 855 uint64_t ret; 856 857 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 858 dip, msi_num); 859 860 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 861 msi_num, msiq_id)) != H_EOK) { 862 DBG(DBG_LIB_MSI, dip, 863 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 864 return (DDI_FAILURE); 865 } 866 867 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 868 *msiq_id); 869 870 return (DDI_SUCCESS); 871 } 872 873 /*ARGSUSED*/ 874 int 875 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 876 msiqid_t msiq_id, msi_type_t msitype) 877 { 878 uint64_t ret; 879 880 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 881 "msq_id 0x%x\n", dip, msi_num, msiq_id); 882 883 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 884 msi_num, msiq_id, msitype)) != H_EOK) { 885 DBG(DBG_LIB_MSI, dip, 886 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 887 return (DDI_FAILURE); 888 } 889 890 return (DDI_SUCCESS); 891 } 892 893 /*ARGSUSED*/ 894 int 895 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 896 pci_msi_valid_state_t *msi_valid_state) 897 { 898 uint64_t ret; 899 900 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 901 dip, msi_num); 902 903 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 904 msi_num, msi_valid_state)) != H_EOK) { 905 DBG(DBG_LIB_MSI, dip, 906 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 907 return (DDI_FAILURE); 908 } 909 910 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 911 *msi_valid_state); 912 913 return (DDI_SUCCESS); 914 } 915 916 /*ARGSUSED*/ 917 int 918 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 919 pci_msi_valid_state_t msi_valid_state) 920 { 921 uint64_t ret; 922 923 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 924 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 925 926 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 927 msi_num, msi_valid_state)) != H_EOK) { 928 DBG(DBG_LIB_MSI, dip, 929 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 930 return (DDI_FAILURE); 931 } 932 933 return (DDI_SUCCESS); 934 } 935 936 /*ARGSUSED*/ 937 int 938 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 939 pci_msi_state_t *msi_state) 940 { 941 uint64_t ret; 942 943 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 944 dip, msi_num); 945 946 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 947 msi_num, msi_state)) != H_EOK) { 948 DBG(DBG_LIB_MSI, dip, 949 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 950 return (DDI_FAILURE); 951 } 952 953 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 954 *msi_state); 955 956 return (DDI_SUCCESS); 957 } 958 959 /*ARGSUSED*/ 960 int 961 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 962 pci_msi_state_t msi_state) 963 { 964 uint64_t ret; 965 966 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 967 "msi_state 0x%x\n", dip, msi_num, msi_state); 968 969 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 970 msi_num, msi_state)) != H_EOK) { 971 DBG(DBG_LIB_MSI, dip, 972 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 973 return (DDI_FAILURE); 974 } 975 976 return (DDI_SUCCESS); 977 } 978 979 /* 980 * MSG Functions: 981 */ 982 983 /*ARGSUSED*/ 984 int 985 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 986 msiqid_t *msiq_id) 987 { 988 uint64_t ret; 989 990 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 991 dip, msg_type); 992 993 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 994 msg_type, msiq_id)) != H_EOK) { 995 DBG(DBG_LIB_MSG, dip, 996 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 997 return (DDI_FAILURE); 998 } 999 1000 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 1001 *msiq_id); 1002 1003 return (DDI_SUCCESS); 1004 } 1005 1006 /*ARGSUSED*/ 1007 int 1008 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1009 msiqid_t msiq_id) 1010 { 1011 uint64_t ret; 1012 1013 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 1014 "msq_id 0x%x\n", dip, msg_type, msiq_id); 1015 1016 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 1017 msg_type, msiq_id)) != H_EOK) { 1018 DBG(DBG_LIB_MSG, dip, 1019 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 1020 return (DDI_FAILURE); 1021 } 1022 1023 return (DDI_SUCCESS); 1024 } 1025 1026 /*ARGSUSED*/ 1027 int 1028 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1029 pcie_msg_valid_state_t *msg_valid_state) 1030 { 1031 uint64_t ret; 1032 1033 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 1034 dip, msg_type); 1035 1036 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 1037 msg_valid_state)) != H_EOK) { 1038 DBG(DBG_LIB_MSG, dip, 1039 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 1040 return (DDI_FAILURE); 1041 } 1042 1043 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1044 *msg_valid_state); 1045 1046 return (DDI_SUCCESS); 1047 } 1048 1049 /*ARGSUSED*/ 1050 int 1051 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1052 pcie_msg_valid_state_t msg_valid_state) 1053 { 1054 uint64_t ret; 1055 1056 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1057 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1058 1059 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1060 msg_valid_state)) != H_EOK) { 1061 DBG(DBG_LIB_MSG, dip, 1062 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1063 return (DDI_FAILURE); 1064 } 1065 1066 return (DDI_SUCCESS); 1067 } 1068 1069 /* 1070 * Suspend/Resume Functions: 1071 * Currently unsupported by hypervisor and all functions are noops. 1072 */ 1073 /*ARGSUSED*/ 1074 int 1075 px_lib_suspend(dev_info_t *dip) 1076 { 1077 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 1078 1079 /* Not supported */ 1080 return (DDI_FAILURE); 1081 } 1082 1083 /*ARGSUSED*/ 1084 void 1085 px_lib_resume(dev_info_t *dip) 1086 { 1087 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 1088 1089 /* Noop */ 1090 } 1091 1092 /* 1093 * Misc Functions: 1094 * Currently unsupported by hypervisor and all functions are noops. 1095 */ 1096 /*ARGSUSED*/ 1097 static int 1098 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1099 uint8_t size, pci_cfg_data_t *data_p) 1100 { 1101 uint64_t ret; 1102 1103 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1104 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1105 1106 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1107 size, data_p)) != H_EOK) { 1108 DBG(DBG_LIB_CFG, dip, 1109 "hvio_config_get failed, ret 0x%lx\n", ret); 1110 return (DDI_FAILURE); 1111 } 1112 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1113 1114 return (DDI_SUCCESS); 1115 } 1116 1117 /*ARGSUSED*/ 1118 static int 1119 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1120 uint8_t size, pci_cfg_data_t data) 1121 { 1122 uint64_t ret; 1123 1124 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1125 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1126 1127 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1128 size, data)) != H_EOK) { 1129 DBG(DBG_LIB_CFG, dip, 1130 "hvio_config_put failed, ret 0x%lx\n", ret); 1131 return (DDI_FAILURE); 1132 } 1133 1134 return (DDI_SUCCESS); 1135 } 1136 1137 static uint32_t 1138 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1139 { 1140 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1141 handle->ahi_common.ah_bus_private; 1142 uint32_t pci_dev_addr = px_pvt->raddr; 1143 uint32_t vaddr = px_pvt->vaddr; 1144 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1145 uint32_t rdata = 0; 1146 1147 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1148 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1149 /* XXX update error kstats */ 1150 return (0xffffffff); 1151 return (rdata); 1152 } 1153 1154 static void 1155 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1156 int size, pci_cfg_data_t wdata) 1157 { 1158 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1159 handle->ahi_common.ah_bus_private; 1160 uint32_t pci_dev_addr = px_pvt->raddr; 1161 uint32_t vaddr = px_pvt->vaddr; 1162 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1163 1164 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1165 size, wdata) != DDI_SUCCESS) { 1166 /*EMPTY*/ 1167 /* XXX update error kstats */ 1168 } 1169 } 1170 1171 static uint8_t 1172 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1173 { 1174 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1175 } 1176 1177 static uint16_t 1178 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1179 { 1180 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1181 } 1182 1183 static uint32_t 1184 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1185 { 1186 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1187 } 1188 1189 static uint64_t 1190 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1191 { 1192 uint32_t rdatah, rdatal; 1193 1194 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1195 rdatah = (uint32_t)px_pci_config_get(handle, 1196 (uint32_t *)((char *)addr+4), 4); 1197 return (((uint64_t)rdatah << 32) | rdatal); 1198 } 1199 1200 static void 1201 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1202 { 1203 pci_cfg_data_t wdata = { 0 }; 1204 1205 wdata.qw = (uint8_t)data; 1206 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1207 } 1208 1209 static void 1210 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1211 { 1212 pci_cfg_data_t wdata = { 0 }; 1213 1214 wdata.qw = (uint16_t)data; 1215 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1216 } 1217 1218 static void 1219 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1220 { 1221 pci_cfg_data_t wdata = { 0 }; 1222 1223 wdata.qw = (uint32_t)data; 1224 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1225 } 1226 1227 static void 1228 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1229 { 1230 pci_cfg_data_t wdata = { 0 }; 1231 1232 wdata.qw = (uint32_t)(data & 0xffffffff); 1233 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1234 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1235 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1236 } 1237 1238 static void 1239 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1240 uint8_t *dev_addr, size_t repcount, uint_t flags) 1241 { 1242 if (flags == DDI_DEV_AUTOINCR) 1243 for (; repcount; repcount--) 1244 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1245 else 1246 for (; repcount; repcount--) 1247 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1248 } 1249 1250 /* 1251 * Function to rep read 16 bit data off the PCI configuration space behind 1252 * the 21554's host interface. 1253 */ 1254 static void 1255 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1256 uint16_t *dev_addr, size_t repcount, uint_t flags) 1257 { 1258 if (flags == DDI_DEV_AUTOINCR) 1259 for (; repcount; repcount--) 1260 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1261 else 1262 for (; repcount; repcount--) 1263 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1264 } 1265 1266 /* 1267 * Function to rep read 32 bit data off the PCI configuration space behind 1268 * the 21554's host interface. 1269 */ 1270 static void 1271 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1272 uint32_t *dev_addr, size_t repcount, uint_t flags) 1273 { 1274 if (flags == DDI_DEV_AUTOINCR) 1275 for (; repcount; repcount--) 1276 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1277 else 1278 for (; repcount; repcount--) 1279 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1280 } 1281 1282 /* 1283 * Function to rep read 64 bit data off the PCI configuration space behind 1284 * the 21554's host interface. 1285 */ 1286 static void 1287 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1288 uint64_t *dev_addr, size_t repcount, uint_t flags) 1289 { 1290 if (flags == DDI_DEV_AUTOINCR) 1291 for (; repcount; repcount--) 1292 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1293 else 1294 for (; repcount; repcount--) 1295 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1296 } 1297 1298 /* 1299 * Function to rep write 8 bit data into the PCI configuration space behind 1300 * the 21554's host interface. 1301 */ 1302 static void 1303 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1304 uint8_t *dev_addr, size_t repcount, uint_t flags) 1305 { 1306 if (flags == DDI_DEV_AUTOINCR) 1307 for (; repcount; repcount--) 1308 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1309 else 1310 for (; repcount; repcount--) 1311 px_pci_config_put8(handle, dev_addr, *host_addr++); 1312 } 1313 1314 /* 1315 * Function to rep write 16 bit data into the PCI configuration space behind 1316 * the 21554's host interface. 1317 */ 1318 static void 1319 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1320 uint16_t *dev_addr, size_t repcount, uint_t flags) 1321 { 1322 if (flags == DDI_DEV_AUTOINCR) 1323 for (; repcount; repcount--) 1324 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1325 else 1326 for (; repcount; repcount--) 1327 px_pci_config_put16(handle, dev_addr, *host_addr++); 1328 } 1329 1330 /* 1331 * Function to rep write 32 bit data into the PCI configuration space behind 1332 * the 21554's host interface. 1333 */ 1334 static void 1335 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1336 uint32_t *dev_addr, size_t repcount, uint_t flags) 1337 { 1338 if (flags == DDI_DEV_AUTOINCR) 1339 for (; repcount; repcount--) 1340 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1341 else 1342 for (; repcount; repcount--) 1343 px_pci_config_put32(handle, dev_addr, *host_addr++); 1344 } 1345 1346 /* 1347 * Function to rep write 64 bit data into the PCI configuration space behind 1348 * the 21554's host interface. 1349 */ 1350 static void 1351 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1352 uint64_t *dev_addr, size_t repcount, uint_t flags) 1353 { 1354 if (flags == DDI_DEV_AUTOINCR) 1355 for (; repcount; repcount--) 1356 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1357 else 1358 for (; repcount; repcount--) 1359 px_pci_config_put64(handle, dev_addr, *host_addr++); 1360 } 1361 1362 /* 1363 * Provide a private access handle to route config access calls to Hypervisor. 1364 * Beware: Do all error checking for config space accesses before calling 1365 * this function. ie. do error checking from the calling function. 1366 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1367 * DDI_SUCCESS from here makes the code organization readable/easier from 1368 * the generic code. 1369 */ 1370 /*ARGSUSED*/ 1371 int 1372 px_lib_map_vconfig(dev_info_t *dip, 1373 ddi_map_req_t *mp, pci_config_offset_t off, 1374 pci_regspec_t *rp, caddr_t *addrp) 1375 { 1376 int fmcap; 1377 ndi_err_t *errp; 1378 on_trap_data_t *otp; 1379 ddi_acc_hdl_t *hp; 1380 ddi_acc_impl_t *ap; 1381 uchar_t busnum; /* bus number */ 1382 uchar_t devnum; /* device number */ 1383 uchar_t funcnum; /* function number */ 1384 px_config_acc_pvt_t *px_pvt; 1385 1386 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1387 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1388 1389 /* Check for mapping teardown operation */ 1390 if ((mp->map_op == DDI_MO_UNMAP) || 1391 (mp->map_op == DDI_MO_UNLOCK)) { 1392 /* free up memory allocated for the private access handle. */ 1393 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1394 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1395 1396 /* unmap operation of PCI IO/config space. */ 1397 return (DDI_SUCCESS); 1398 } 1399 1400 fmcap = ddi_fm_capable(dip); 1401 if (DDI_FM_ACC_ERR_CAP(fmcap)) { 1402 errp = ((ddi_acc_impl_t *)hp)->ahi_err; 1403 otp = (on_trap_data_t *)errp->err_ontrap; 1404 otp->ot_handle = (void *)(hp); 1405 otp->ot_prot = OT_DATA_ACCESS; 1406 errp->err_status = DDI_FM_OK; 1407 errp->err_expected = DDI_FM_ERR_UNEXPECTED; 1408 errp->err_cf = px_err_cfg_hdl_check; 1409 } 1410 1411 ap->ahi_get8 = px_pci_config_get8; 1412 ap->ahi_get16 = px_pci_config_get16; 1413 ap->ahi_get32 = px_pci_config_get32; 1414 ap->ahi_get64 = px_pci_config_get64; 1415 ap->ahi_put8 = px_pci_config_put8; 1416 ap->ahi_put16 = px_pci_config_put16; 1417 ap->ahi_put32 = px_pci_config_put32; 1418 ap->ahi_put64 = px_pci_config_put64; 1419 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1420 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1421 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1422 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1423 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1424 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1425 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1426 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1427 1428 /* Initialize to default check/notify functions */ 1429 ap->ahi_fault = 0; 1430 ap->ahi_fault_check = i_ddi_acc_fault_check; 1431 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1432 1433 /* allocate memory for our private handle */ 1434 px_pvt = (px_config_acc_pvt_t *) 1435 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1436 hp->ah_bus_private = (void *)px_pvt; 1437 1438 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1439 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1440 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1441 1442 /* set up private data for use during IO routines */ 1443 1444 /* addr needed by the HV APIs */ 1445 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1446 /* 1447 * Address that specifies the actual offset into the 256MB 1448 * memory mapped configuration space, 4K per device. 1449 * First 12bits form the offset into 4K config space. 1450 * This address is only used during the IO routines to calculate 1451 * the offset at which the transaction must be performed. 1452 * Drivers bypassing DDI functions to access PCI config space will 1453 * panic the system since the following is a bogus virtual address. 1454 */ 1455 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1456 px_pvt->dip = dip; 1457 1458 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1459 px_pvt->raddr, px_pvt->vaddr); 1460 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1461 return (DDI_SUCCESS); 1462 } 1463 1464 /*ARGSUSED*/ 1465 void 1466 px_lib_map_attr_check(ddi_map_req_t *mp) 1467 { 1468 } 1469 1470 /* 1471 * px_lib_log_safeacc_err: 1472 * Imitate a cpu/mem trap call when a peek/poke fails. 1473 * This will initiate something similar to px_fm_callback. 1474 */ 1475 static void 1476 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag, 1477 r_addr_t addr) 1478 { 1479 uint32_t addr_high, addr_low; 1480 pcie_req_id_t bdf; 1481 px_ranges_t *ranges_p; 1482 int range_len, i; 1483 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1484 ddi_fm_error_t derr; 1485 1486 derr.fme_status = DDI_FM_NONFATAL; 1487 derr.fme_version = DDI_FME_VERSION; 1488 derr.fme_flag = fme_flag; 1489 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1490 derr.fme_acc_handle = handle; 1491 if (hp) 1492 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1493 1494 addr_high = (uint32_t)(addr >> 32); 1495 addr_low = (uint32_t)addr; 1496 1497 /* 1498 * Make sure this failed load came from this PCIe port. Check by 1499 * matching the upper 32 bits of the address with the ranges property. 1500 */ 1501 range_len = px_p->px_ranges_length / sizeof (px_ranges_t); 1502 i = 0; 1503 for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) { 1504 if (ranges_p->parent_high == addr_high) { 1505 switch (ranges_p->child_high & PCI_ADDR_MASK) { 1506 case PCI_ADDR_CONFIG: 1507 bdf = (pcie_req_id_t)(addr_low >> 12); 1508 break; 1509 default: 1510 bdf = NULL; 1511 break; 1512 } 1513 break; 1514 } 1515 } 1516 1517 px_rp_en_q(px_p, bdf, addr, NULL); 1518 1519 if (px_fm_enter(px_p) == DDI_SUCCESS) { 1520 (void) px_scan_fabric(px_p, px_p->px_dip, &derr); 1521 px_fm_exit(px_p); 1522 } 1523 } 1524 1525 1526 #ifdef DEBUG 1527 int px_peekfault_cnt = 0; 1528 int px_pokefault_cnt = 0; 1529 #endif /* DEBUG */ 1530 1531 /* 1532 * Do a safe write to a device. 1533 * 1534 * When this function is given a handle (cautious access), all errors are 1535 * suppressed. 1536 * 1537 * When this function is not given a handle (poke), only Unsupported Request 1538 * and Completer Abort errors are suppressed. 1539 * 1540 * In all cases, all errors are returned in the function return status. 1541 */ 1542 1543 int 1544 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1545 peekpoke_ctlops_t *in_args) 1546 { 1547 px_t *px_p = DIP_TO_STATE(dip); 1548 px_pec_t *pec_p = px_p->px_pec_p; 1549 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1550 1551 size_t repcount = in_args->repcount; 1552 size_t size = in_args->size; 1553 uintptr_t dev_addr = in_args->dev_addr; 1554 uintptr_t host_addr = in_args->host_addr; 1555 1556 int err = DDI_SUCCESS; 1557 uint64_t hvio_poke_status; 1558 uint32_t wrt_stat; 1559 1560 r_addr_t ra; 1561 uint64_t pokeval; 1562 pcie_req_id_t bdf; 1563 1564 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1565 for (; repcount; repcount--) { 1566 1567 switch (size) { 1568 case sizeof (uint8_t): 1569 pokeval = *(uint8_t *)host_addr; 1570 break; 1571 case sizeof (uint16_t): 1572 pokeval = *(uint16_t *)host_addr; 1573 break; 1574 case sizeof (uint32_t): 1575 pokeval = *(uint32_t *)host_addr; 1576 break; 1577 case sizeof (uint64_t): 1578 pokeval = *(uint64_t *)host_addr; 1579 break; 1580 default: 1581 DBG(DBG_MAP, px_p->px_dip, 1582 "poke: invalid size %d passed\n", size); 1583 err = DDI_FAILURE; 1584 goto done; 1585 } 1586 1587 /* 1588 * Grab pokefault mutex since hypervisor does not guarantee 1589 * poke serialization. 1590 */ 1591 if (hp) { 1592 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1593 (ddi_acc_handle_t)hp); 1594 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1595 } else { 1596 mutex_enter(&pec_p->pec_pokefault_mutex); 1597 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1598 } 1599 1600 if (pcie_get_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1601 err = DDI_FAILURE; 1602 goto done; 1603 } 1604 1605 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1606 pokeval, bdf << 8, &wrt_stat); 1607 1608 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1609 err = DDI_FAILURE; 1610 #ifdef DEBUG 1611 px_pokefault_cnt++; 1612 #endif 1613 /* 1614 * For CAUTIOUS and POKE access, notify FMA to 1615 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1616 */ 1617 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1618 (hp ? DDI_FM_ERR_EXPECTED : 1619 DDI_FM_ERR_POKE), ra); 1620 1621 pec_p->pec_ontrap_data = NULL; 1622 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1623 if (hp) { 1624 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1625 (ddi_acc_handle_t)hp); 1626 } else { 1627 mutex_exit(&pec_p->pec_pokefault_mutex); 1628 } 1629 goto done; 1630 } 1631 1632 pec_p->pec_ontrap_data = NULL; 1633 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1634 if (hp) { 1635 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1636 (ddi_acc_handle_t)hp); 1637 } else { 1638 mutex_exit(&pec_p->pec_pokefault_mutex); 1639 } 1640 1641 host_addr += size; 1642 1643 if (in_args->flags == DDI_DEV_AUTOINCR) { 1644 dev_addr += size; 1645 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1646 } 1647 } 1648 1649 done: 1650 return (err); 1651 } 1652 1653 1654 /*ARGSUSED*/ 1655 int 1656 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1657 peekpoke_ctlops_t *in_args, void *result) 1658 { 1659 px_t *px_p = DIP_TO_STATE(dip); 1660 px_pec_t *pec_p = px_p->px_pec_p; 1661 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1662 1663 size_t repcount = in_args->repcount; 1664 uintptr_t dev_addr = in_args->dev_addr; 1665 uintptr_t host_addr = in_args->host_addr; 1666 1667 r_addr_t ra; 1668 uint32_t read_status; 1669 uint64_t hvio_peek_status; 1670 uint64_t peekval; 1671 int err = DDI_SUCCESS; 1672 1673 result = (void *)in_args->host_addr; 1674 1675 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1676 for (; repcount; repcount--) { 1677 1678 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1679 if (hp) { 1680 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1681 (ddi_acc_handle_t)hp); 1682 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1683 } else { 1684 mutex_enter(&pec_p->pec_pokefault_mutex); 1685 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1686 } 1687 1688 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1689 in_args->size, &read_status, &peekval); 1690 1691 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1692 err = DDI_FAILURE; 1693 1694 /* 1695 * For CAUTIOUS and PEEK access, notify FMA to 1696 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1697 */ 1698 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1699 (hp ? DDI_FM_ERR_EXPECTED : 1700 DDI_FM_ERR_PEEK), ra); 1701 1702 /* Stuff FFs in host addr if peek. */ 1703 if (hp == NULL) { 1704 int i; 1705 uint8_t *ff_addr = (uint8_t *)host_addr; 1706 for (i = 0; i < in_args->size; i++) 1707 *ff_addr++ = 0xff; 1708 } 1709 #ifdef DEBUG 1710 px_peekfault_cnt++; 1711 #endif 1712 pec_p->pec_ontrap_data = NULL; 1713 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1714 if (hp) { 1715 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1716 (ddi_acc_handle_t)hp); 1717 } else { 1718 mutex_exit(&pec_p->pec_pokefault_mutex); 1719 } 1720 goto done; 1721 1722 } 1723 pec_p->pec_ontrap_data = NULL; 1724 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1725 if (hp) { 1726 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1727 (ddi_acc_handle_t)hp); 1728 } else { 1729 mutex_exit(&pec_p->pec_pokefault_mutex); 1730 } 1731 1732 switch (in_args->size) { 1733 case sizeof (uint8_t): 1734 *(uint8_t *)host_addr = (uint8_t)peekval; 1735 break; 1736 case sizeof (uint16_t): 1737 *(uint16_t *)host_addr = (uint16_t)peekval; 1738 break; 1739 case sizeof (uint32_t): 1740 *(uint32_t *)host_addr = (uint32_t)peekval; 1741 break; 1742 case sizeof (uint64_t): 1743 *(uint64_t *)host_addr = (uint64_t)peekval; 1744 break; 1745 default: 1746 DBG(DBG_MAP, px_p->px_dip, 1747 "peek: invalid size %d passed\n", 1748 in_args->size); 1749 err = DDI_FAILURE; 1750 goto done; 1751 } 1752 1753 host_addr += in_args->size; 1754 1755 if (in_args->flags == DDI_DEV_AUTOINCR) { 1756 dev_addr += in_args->size; 1757 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1758 } 1759 } 1760 done: 1761 return (err); 1762 } 1763 1764 1765 /* add interrupt vector */ 1766 int 1767 px_err_add_intr(px_fault_t *px_fault_p) 1768 { 1769 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1770 1771 DBG(DBG_LIB_INT, px_p->px_dip, 1772 "px_err_add_intr: calling add_ivintr"); 1773 1774 VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1775 (intrfunc)px_fault_p->px_err_func, (caddr_t)px_fault_p, NULL, 1776 (caddr_t)&px_fault_p->px_intr_payload[0]) == 0); 1777 1778 DBG(DBG_LIB_INT, px_p->px_dip, 1779 "px_err_add_intr: ib_intr_enable "); 1780 1781 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1782 1783 return (DDI_SUCCESS); 1784 } 1785 1786 /* remove interrupt vector */ 1787 void 1788 px_err_rem_intr(px_fault_t *px_fault_p) 1789 { 1790 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1791 1792 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1793 IB_INTR_WAIT); 1794 1795 VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0); 1796 } 1797 1798 void 1799 px_cb_intr_redist(void *arg) 1800 { 1801 px_t *px_p = (px_t *)arg; 1802 px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(), 1803 px_p->px_inos[PX_INTR_XBC], B_FALSE); 1804 } 1805 1806 int 1807 px_cb_add_intr(px_fault_t *f_p) 1808 { 1809 px_t *px_p = DIP_TO_STATE(f_p->px_fh_dip); 1810 1811 DBG(DBG_LIB_INT, px_p->px_dip, 1812 "px_err_add_intr: calling add_ivintr"); 1813 1814 VERIFY(add_ivintr(f_p->px_fh_sysino, PX_ERR_PIL, 1815 (intrfunc)f_p->px_err_func, (caddr_t)f_p, NULL, 1816 (caddr_t)&f_p->px_intr_payload[0]) == 0); 1817 1818 intr_dist_add(px_cb_intr_redist, px_p); 1819 1820 DBG(DBG_LIB_INT, px_p->px_dip, 1821 "px_err_add_intr: ib_intr_enable "); 1822 1823 px_ib_intr_enable(px_p, intr_dist_cpuid(), f_p->px_intr_ino); 1824 1825 return (DDI_SUCCESS); 1826 } 1827 1828 void 1829 px_cb_rem_intr(px_fault_t *f_p) 1830 { 1831 intr_dist_rem(px_cb_intr_redist, DIP_TO_STATE(f_p->px_fh_dip)); 1832 px_err_rem_intr(f_p); 1833 } 1834 1835 #ifdef FMA 1836 void 1837 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1838 { 1839 px_pec_err_t *err_pkt; 1840 1841 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1842 1843 /* initialise all the structure members */ 1844 rc_status->status_valid = 0; 1845 1846 if (err_pkt->pec_descr.P) { 1847 /* PCI Status Register */ 1848 rc_status->pci_err_status = err_pkt->pci_err_status; 1849 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1850 } 1851 1852 if (err_pkt->pec_descr.E) { 1853 /* PCIe Status Register */ 1854 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1855 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1856 } 1857 1858 if (err_pkt->pec_descr.U) { 1859 rc_status->ue_status = err_pkt->ue_reg_status; 1860 rc_status->status_valid |= UE_STATUS_VALID; 1861 } 1862 1863 if (err_pkt->pec_descr.H) { 1864 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1865 rc_status->status_valid |= UE_HDR1_VALID; 1866 } 1867 1868 if (err_pkt->pec_descr.I) { 1869 rc_status->ue_hdr2 = err_pkt->hdr[1]; 1870 rc_status->status_valid |= UE_HDR2_VALID; 1871 } 1872 1873 /* ue_fst_err_ptr - not available for sun4v?? */ 1874 1875 1876 if (err_pkt->pec_descr.S) { 1877 rc_status->source_id = err_pkt->err_src_reg; 1878 rc_status->status_valid |= SOURCE_ID_VALID; 1879 } 1880 1881 if (err_pkt->pec_descr.R) { 1882 rc_status->root_err_status = err_pkt->root_err_status; 1883 rc_status->status_valid |= CE_STATUS_VALID; 1884 } 1885 } 1886 #endif 1887 1888 /*ARGSUSED*/ 1889 int 1890 px_lib_pmctl(int cmd, px_t *px_p) 1891 { 1892 return (DDI_FAILURE); 1893 } 1894 1895 /*ARGSUSED*/ 1896 uint_t 1897 px_pmeq_intr(caddr_t arg) 1898 { 1899 return (DDI_INTR_CLAIMED); 1900 } 1901 1902 /* 1903 * Unprotected raw reads/writes of fabric device's config space. 1904 * Only used for temporary PCI-E Fabric Error Handling. 1905 */ 1906 uint32_t 1907 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) { 1908 uint32_t data = 0; 1909 1910 (void) hvio_config_get(px_p->px_dev_hdl, 1911 (bdf << PX_RA_BDF_SHIFT), offset, 4, 1912 (pci_cfg_data_t *)&data); 1913 1914 return (data); 1915 } 1916 1917 void 1918 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 1919 uint32_t val) { 1920 pci_cfg_data_t wdata = { 0 }; 1921 1922 wdata.qw = (uint32_t)val; 1923 (void) hvio_config_put(px_p->px_dev_hdl, 1924 (bdf << PX_RA_BDF_SHIFT), offset, 4, wdata); 1925 } 1926 1927 /*ARGSUSED*/ 1928 int 1929 px_lib_hotplug_init(dev_info_t *dip, void *arg) 1930 { 1931 return (DDI_ENOTSUP); 1932 } 1933 1934 /*ARGSUSED*/ 1935 void 1936 px_lib_hotplug_uninit(dev_info_t *dip) 1937 { 1938 } 1939 1940 /*ARGSUSED*/ 1941 void 1942 px_hp_intr_redist(px_t *px_p) 1943 { 1944 } 1945 1946 /* Dummy cpr add callback */ 1947 /*ARGSUSED*/ 1948 void 1949 px_cpr_add_callb(px_t *px_p) 1950 { 1951 } 1952 1953 /* Dummy cpr rem callback */ 1954 /*ARGSUSED*/ 1955 void 1956 px_cpr_rem_callb(px_t *px_p) 1957 { 1958 } 1959 1960 /*ARGSUSED*/ 1961 boolean_t 1962 px_lib_is_in_drain_state(px_t *px_p) 1963 { 1964 return (B_FALSE); 1965 } 1966 1967 /* 1968 * There is no IOAPI to get the BDF of the pcie root port nexus at this moment. 1969 * Assume it is 0x0000, until otherwise noted. For now, all sun4v platforms 1970 * have programmed the BDF to be 0x0000. 1971 */ 1972 /*ARGSUSED*/ 1973 pcie_req_id_t 1974 px_lib_get_bdf(px_t *px_p) 1975 { 1976 return (0x0000); 1977 } 1978