1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _RFIOSPC_TABLES_H 28 #define _RFIOSPC_TABLES_H 29 30 /* 31 * Table definitions for the RF IOS performance counters. 32 * 33 * Each table consists of one or more groups of counters. 34 * 35 * A counter group will have a name (used by busstat as the kstat "module" 36 * name), have its own set of kstats, and a common event select register. 37 * A group is represented as an iospc_grp_t. 38 * 39 * Each counter is represented by an iospc_cntr_t. Each has its own register 40 * offset (or address), bits for the data it represents, plus an associated 41 * register for zeroing it. 42 * 43 * All registers for iospc are 64 bit, but a size field can be entered into this 44 * structure if registers sizes vary for other implementations (as if this code 45 * is leveraged for a future driver). 46 * 47 * A select register is represented by an iospc_regsel_t. This defines the 48 * offset or address, and an array of fields which define the events for each 49 * counter it services. All counters need to have an entry in the fields array 50 * even if they don't have any representation in a select register. Please see 51 * the explanation of the events array (below) for more information. Counters 52 * without representation in a select register can specify their (non-existant) 53 * select register field with mask NONPROG_DUMMY_MASK and offset 54 * NONPROG_DUMMY_OFF. 55 * 56 * This implementation supports only one select register per group. If more 57 * are needed (e.g. if this implementation is used as a template for another 58 * device which has multiple select registers per group) the data structures can 59 * easily be changed to support an array of them. Add an array index in the 60 * counter structure to associate that counter with a particular select 61 * register, and add a field for the number of select registers in the group 62 * structure. 63 * 64 * Each counter has an array of programmable events associated with it, even if 65 * it is not programmable. This array is a series of name/value pairs defined 66 * by iospc_event_t. The value is the event value loaded into the select 67 * register to select that event for that counter. The last entry in the array 68 * is always an entry with a bitmask of LSB-aligned bits of that counter's 69 * select register's field's width; it is usually called the CLEAR_PIC entry. 70 * CLEAR_PIC entries are not shown to the user. 71 * 72 * Note that counters without programmable events still need to define a 73 * (small) events array with at least CLEAR_PIC and a single event, so that 74 * event's name can display in busstat output. The CLEAR_PIC entry of 75 * nonprogrammable counters can have a value of NONPROG_DUMMY_MASK. 76 */ 77 78 #ifdef __cplusplus 79 extern "C" { 80 #endif 81 82 #include <sys/types.h> 83 #include <sys/kstat.h> 84 85 /* RF IOS specific definitions. */ 86 87 /* 88 * Event bitmask definitions for all groups. 89 */ 90 #define RFIOS_IMU_CTR_EVT_MASK 0xffull 91 #define RFIOS_IMU_CTR_0_EVT_OFF 0 92 #define RFIOS_IMU_CTR_1_EVT_OFF 8 93 94 #define RFIOS_ATU_CTR_EVT_MASK 0xffull 95 #define RFIOS_ATU_CTR_0_EVT_OFF 0 96 #define RFIOS_ATU_CTR_1_EVT_OFF 8 97 98 #define RFIOS_NPU_CTR_EVT_MASK 0xffull 99 #define RFIOS_NPU_CTR_0_EVT_OFF 0 100 #define RFIOS_NPU_CTR_1_EVT_OFF 8 101 102 #define RFIOS_PEX_CTR_EVT_MASK 0xffull 103 #define RFIOS_PEX_CTR_0_EVT_OFF 0 104 #define RFIOS_PEX_CTR_1_EVT_OFF 8 105 106 #define RFIOS_PEU_CTR_EVT_MASK 0x7full 107 #define RFIOS_PEU_CTR_0_EVT_OFF 0 108 #define RFIOS_PEU_CTR_1_EVT_OFF 32 109 110 /* 111 * Definitions of the different types of events. 112 * 113 * The first part says which registers these events are for. 114 * For example, IMU01 means the IMU performance counters 0 and 1 115 */ 116 117 /* String sought by busstat to locate the event field width "event" entry. */ 118 #define COMMON_S_CLEAR_PIC "clear_pic" 119 120 #define RFIOS_IMU01_S_EVT_NONE "event_none" 121 #define RFIOS_IMU01_S_EVT_CLK "clock_cyc" 122 #define RFIOS_IMU01_S_EVT_TOTAL_MSIX "total_msix" 123 #define RFIOS_IMU01_S_EVT_IOS_MSI "ios_msi" 124 #define RFIOS_IMU01_S_EVT_PCIE_MSIX "pcie_msix" 125 #define RFIOS_IMU01_S_EVT_PCIE_MSGS "pcie_msgs" 126 #define RFIOS_IMU01_S_EVT_FILTERED_MSIX "filtered_msix" 127 #define RFIOS_IMU01_S_EVT_EQ_WR "eq_write" 128 #define RFIOS_IMU01_S_EVT_MONDOS "mondos" 129 130 #define RFIOS_IMU01_EVT_NONE 0x0 131 #define RFIOS_IMU01_EVT_CLK 0x1 132 #define RFIOS_IMU01_EVT_TOTAL_MSIX 0x2 133 #define RFIOS_IMU01_EVT_IOS_MSI 0x3 134 #define RFIOS_IMU01_EVT_PCIE_MSIX 0x4 135 #define RFIOS_IMU01_EVT_PCIE_MSGS 0x5 136 #define RFIOS_IMU01_EVT_FILTERED_MSIX 0x6 137 #define RFIOS_IMU01_EVT_EQ_WR 0x7 138 #define RFIOS_IMU01_EVT_MONDOS 0x8 139 140 #define RFIOS_ATU01_S_EVT_NONE "event_none" 141 #define RFIOS_ATU01_S_EVT_CLK "clock_cyc" 142 #define RFIOS_ATU01_S_EVT_FLOW_CTRL_STALL "flow_ctrl_cyc" 143 #define RFIOS_ATU01_S_EVT_CLUMP_ACC "clump_accesses" 144 #define RFIOS_ATU01_S_EVT_CLUMP_MISS "clump_misses" 145 #define RFIOS_ATU01_S_EVT_CLUMP_RESETS "clump_resets" 146 #define RFIOS_ATU01_S_EVT_CLUMP_TBL_WALK "clump_table_walk" 147 #define RFIOS_ATU01_S_EVT_VIRT_ACC "virt_accesses" 148 #define RFIOS_ATU01_S_EVT_VIRT_MISS "virt_misses" 149 #define RFIOS_ATU01_S_EVT_VIRT_RESETS "virt_resets" 150 #define RFIOS_ATU01_S_EVT_VIRT_TBL_WALK "virt_table_walk" 151 #define RFIOS_ATU01_S_EVT_REAL_ACC "real_accesses" 152 #define RFIOS_ATU01_S_EVT_REAL_MISS "real_misses" 153 #define RFIOS_ATU01_S_EVT_REAL_RESETS "real_resets" 154 #define RFIOS_ATU01_S_EVT_REAL_TBL_WALK "real_table_walk" 155 #define RFIOS_ATU01_S_EVT_CMD_ERRORS "cmd_errors" 156 #define RFIOS_ATU01_S_EVT_VIRT_TRANS "virt_trans" 157 #define RFIOS_ATU01_S_EVT_REAL_TRANS "real_trans" 158 #define RFIOS_ATU01_S_EVT_PHYS_TRANS "phys_trans" 159 #define RFIOS_ATU01_S_EVT_STRICT_ORDER_FORCED "str_order_forced" 160 #define RFIOS_ATU01_S_EVT_RELAX_ORDER_FORCED "relax_order_forced" 161 #define RFIOS_ATU01_S_EVT_RELAX_ORDER_TLP "relax_order_tlp" 162 #define RFIOS_ATU01_S_EVT_RELAX_ORDER_TOTAL "relax_order_total" 163 164 #define RFIOS_ATU01_EVT_NONE 0x0 165 #define RFIOS_ATU01_EVT_CLK 0x1 166 #define RFIOS_ATU01_EVT_FLOW_CTRL_STALL 0x3 167 #define RFIOS_ATU01_EVT_CLUMP_ACC 0x4 168 #define RFIOS_ATU01_EVT_CLUMP_MISS 0x5 169 #define RFIOS_ATU01_EVT_CLUMP_RESETS 0x6 170 #define RFIOS_ATU01_EVT_CLUMP_TBL_WALK 0x7 171 #define RFIOS_ATU01_EVT_VIRT_ACC 0x8 172 #define RFIOS_ATU01_EVT_VIRT_MISS 0x9 173 #define RFIOS_ATU01_EVT_VIRT_RESETS 0xa 174 #define RFIOS_ATU01_EVT_VIRT_TBL_WALK 0xb 175 #define RFIOS_ATU01_EVT_REAL_ACC 0xc 176 #define RFIOS_ATU01_EVT_REAL_MISS 0xd 177 #define RFIOS_ATU01_EVT_REAL_RESETS 0xe 178 #define RFIOS_ATU01_EVT_REAL_TBL_WALK 0xf 179 #define RFIOS_ATU01_EVT_CMD_ERRORS 0x10 180 #define RFIOS_ATU01_EVT_VIRT_TRANS 0x11 181 #define RFIOS_ATU01_EVT_REAL_TRANS 0x12 182 #define RFIOS_ATU01_EVT_PHYS_TRANS 0x13 183 #define RFIOS_ATU01_EVT_STRICT_ORDER_FORCED 0x14 184 #define RFIOS_ATU01_EVT_RELAX_ORDER_FORCED 0x15 185 #define RFIOS_ATU01_EVT_RELAX_ORDER_TLP 0x16 186 #define RFIOS_ATU01_EVT_RELAX_ORDER_TOTAL 0x17 187 188 #define RFIOS_NPU01_S_EVT_NONE "event_none" 189 #define RFIOS_NPU01_S_EVT_CLK "clock_cyc" 190 #define RFIOS_NPU01_S_EVT_ZERO_BYTE_READ "zero_byte_reads" 191 #define RFIOS_NPU01_S_EVT_DMA_WRITE_LATENCY "write_latency" 192 #define RFIOS_NPU01_S_EVT_DMA_WRITE_LATENCY_NUM "write_latency_num" 193 #define RFIOS_NPU01_S_EVT_OSB_FULL_CYCLES "osb_full_cyc" 194 #define RFIOS_NPU01_S_EVT_DMA_READ_LATENCY "read_latency" 195 #define RFIOS_NPU01_S_EVT_DMA_READ_LATENCY_NUM "read_latency_num" 196 #define RFIOS_NPU01_S_EVT_PSB_FULL_CYCLES "psb_full_cyc" 197 #define RFIOS_NPU01_S_EVT_ICB_FULL_CYCLES "icb_full_cyc" 198 #define RFIOS_NPU01_S_EVT_ECB_FULL_CYCLES "ecb_full_cyc" 199 #define RFIOS_NPU01_S_EVT_ATU_CSR_CFG_WRITES "atu_csr_cfg_wrs" 200 #define RFIOS_NPU01_S_EVT_ATU_CSR_CFG_READS "atu_csr_cfg_rds" 201 #define RFIOS_NPU01_S_EVT_ATU_CSR_MEM_WRITES "atu_csr_mem_wrs" 202 #define RFIOS_NPU01_S_EVT_ATU_CSR_MEM_READS "atu_csr_mem_rds" 203 #define RFIOS_NPU01_S_EVT_IMU_CSR_CFG_WRITES "imu_csr_cfg_wrs" 204 #define RFIOS_NPU01_S_EVT_IMU_CSR_CFG_READS "imu_csr_cfg_rds" 205 #define RFIOS_NPU01_S_EVT_IMU_CSR_MEM_WRITES "imu_csr_mem_wrs" 206 #define RFIOS_NPU01_S_EVT_IMU_CSR_MEM_READS "imu_csr_mem_rds" 207 #define RFIOS_NPU01_S_EVT_NPU_CSR_CFG_WRITES "npu_csr_cfg_wrs" 208 #define RFIOS_NPU01_S_EVT_NPU_CSR_CFG_READS "npu_csr_cfg_rds" 209 #define RFIOS_NPU01_S_EVT_NPU_CSR_MEM_WRITES "npu_csr_mem_wrs" 210 #define RFIOS_NPU01_S_EVT_NPU_CSR_MEM_READS "npu_csr_mem_rds" 211 #define RFIOS_NPU01_S_EVT_OTHER_CSR_CFG_WRITES "other_csr_cfg_wrs" 212 #define RFIOS_NPU01_S_EVT_OTHER_CSR_CFG_READS "other_csr_cfg_rds" 213 #define RFIOS_NPU01_S_EVT_OTHER_CSR_MEM64_WRITES \ 214 "other_csr_mem64_wrs" 215 #define RFIOS_NPU01_S_EVT_OTHER_CSR_MEM64_READS "other_csr_mem64_rds" 216 #define RFIOS_NPU01_S_EVT_OTHER_CSR_MEM32_WRITES \ 217 "other_csr_mem32_wrs" 218 #define RFIOS_NPU01_S_EVT_OTHER_CSR_MEM32_READS "other_csr_mem32_rds" 219 #define RFIOS_NPU01_S_EVT_IO_SPACE_WRITES "io_space_wrs" 220 #define RFIOS_NPU01_S_EVT_IO_SPACE_READS "io_space_rds" 221 #define RFIOS_NPU01_S_EVT_TOTAL_MSI "total_msi" 222 #define RFIOS_NPU01_S_EVT_ATU_MSI "atu_msi" 223 #define RFIOS_NPU01_S_EVT_IMU_MSI "imu_msi" 224 #define RFIOS_NPU01_S_EVT_NPU_MSI "npu_msi" 225 #define RFIOS_NPU01_S_EVT_RETIRED_TAGS_CTO "retired_tags" 226 #define RFIOS_NPU01_S_EVT_NO_POSTED_TAGS_CYCYLES \ 227 "no_posted_tags_cyc" 228 229 #define RFIOS_NPU01_EVT_NONE 0 230 #define RFIOS_NPU01_EVT_CLK 1 231 #define RFIOS_NPU01_EVT_ZERO_BYTE_READ 2 232 #define RFIOS_NPU01_EVT_DMA_WRITE_LATENCY 3 233 #define RFIOS_NPU01_EVT_DMA_WRITE_LATENCY_NUM 4 234 #define RFIOS_NPU01_EVT_OSB_FULL_CYCLES 5 235 #define RFIOS_NPU01_EVT_DMA_READ_LATENCY 8 236 #define RFIOS_NPU01_EVT_DMA_READ_LATENCY_NUM 9 237 #define RFIOS_NPU01_EVT_PSB_FULL_CYCLES 10 238 #define RFIOS_NPU01_EVT_ICB_FULL_CYCLES 16 239 #define RFIOS_NPU01_EVT_ECB_FULL_CYCLES 24 240 #define RFIOS_NPU01_EVT_ATU_CSR_CFG_WRITES 32 241 #define RFIOS_NPU01_EVT_ATU_CSR_CFG_READS 33 242 #define RFIOS_NPU01_EVT_ATU_CSR_MEM_WRITES 34 243 #define RFIOS_NPU01_EVT_ATU_CSR_MEM_READS 35 244 #define RFIOS_NPU01_EVT_IMU_CSR_CFG_WRITES 36 245 #define RFIOS_NPU01_EVT_IMU_CSR_CFG_READS 37 246 #define RFIOS_NPU01_EVT_IMU_CSR_MEM_WRITES 38 247 #define RFIOS_NPU01_EVT_IMU_CSR_MEM_READS 39 248 #define RFIOS_NPU01_EVT_NPU_CSR_CFG_WRITES 40 249 #define RFIOS_NPU01_EVT_NPU_CSR_CFG_READS 41 250 #define RFIOS_NPU01_EVT_NPU_CSR_MEM_WRITES 42 251 #define RFIOS_NPU01_EVT_NPU_CSR_MEM_READS 43 252 #define RFIOS_NPU01_EVT_OTHER_CSR_CFG_WRITES 44 253 #define RFIOS_NPU01_EVT_OTHER_CSR_CFG_READS 45 254 #define RFIOS_NPU01_EVT_OTHER_CSR_MEM64_WRITES 46 255 #define RFIOS_NPU01_EVT_OTHER_CSR_MEM64_READS 47 256 #define RFIOS_NPU01_EVT_OTHER_CSR_MEM32_WRITES 48 257 #define RFIOS_NPU01_EVT_OTHER_CSR_MEM32_READS 49 258 #define RFIOS_NPU01_EVT_IO_SPACE_WRITES 50 259 #define RFIOS_NPU01_EVT_IO_SPACE_READS 51 260 #define RFIOS_NPU01_EVT_TOTAL_MSI 52 261 #define RFIOS_NPU01_EVT_ATU_MSI 53 262 #define RFIOS_NPU01_EVT_IMU_MSI 54 263 #define RFIOS_NPU01_EVT_NPU_MSI 55 264 #define RFIOS_NPU01_EVT_RETIRED_TAGS_CTO 56 265 #define RFIOS_NPU01_EVT_NO_POSTED_TAGS_CYCYLES 57 266 267 #define RFIOS_PEX01_S_EVT_NONE "event_none" 268 #define RFIOS_PEX01_S_EVT_CLK "clock_cyc" 269 #define RFIOS_PEX01_S_EVT_PEU0_DMA_WR_REC "peu0_dma_wr_received" 270 #define RFIOS_PEX01_S_EVT_PEU0_PIO_RD_REC "peu0_pio_rd_received" 271 #define RFIOS_PEX01_S_EVT_PEU0_DMA_RD_SENT "peu0_dma_rd_sent" 272 #define RFIOS_PEX01_S_EVT_PEU0_TLP_REC "peu0_tlp_recieved" 273 #define RFIOS_PEX01_S_EVT_PEU0_TRP_FULL_CYCLES "peu0_trp_full_cyc" 274 #define RFIOS_PEX01_S_EVT_PEU0_TCH_FULL_CYCLES "peu0_tch_full_cyc" 275 #define RFIOS_PEX01_S_EVT_PEU0_TCD_FULL_CYCLES "peu0_tcd_full_cyc" 276 #define RFIOS_PEX01_S_EVT_NON_POSTED_PIOS_LATENCY \ 277 "non_posted_pios_latency" 278 #define RFIOS_PEX01_S_EVT_NON_POSTED_PIOS_NUM "non_posted_pios_num" 279 #define RFIOS_PEX01_S_EVT_PEX_CFG_WRITE "pex_config_wr" 280 #define RFIOS_PEX01_S_EVT_PEX_CFG_READ "pex_config_rd" 281 #define RFIOS_PEX01_S_EVT_PEX_MEM_WRITE "pex_mem_wr" 282 #define RFIOS_PEX01_S_EVT_PEX_MEM_READ "pex_mem_rd" 283 #define RFIOS_PEX01_S_EVT_PEU1_DMA_WR_REC "peu1_dma_wr_received" 284 #define RFIOS_PEX01_S_EVT_PEU1_PIO_RD_REC "peu1_pio_rd_received" 285 #define RFIOS_PEX01_S_EVT_PEU1_DMA_RD_SENT "peu1_dma_rd_sent" 286 #define RFIOS_PEX01_S_EVT_PEU1_TLP_REC "peu1_tlp_recieved" 287 #define RFIOS_PEX01_S_EVT_PEU1_TRP_FULL_CYCLES "peu1_trp_full_cyc" 288 #define RFIOS_PEX01_S_EVT_PEU1_TCH_FULL_CYCLES "peu1_tch_full_cyc" 289 #define RFIOS_PEX01_S_EVT_PEU1_TCD_FULL_CYCLES "peu1_tcd_full_cyc" 290 291 #define RFIOS_PEX01_EVT_NONE 0x0 292 #define RFIOS_PEX01_EVT_CLK 0x1 293 #define RFIOS_PEX01_EVT_PEU0_DMA_WR_REC 0x2 294 #define RFIOS_PEX01_EVT_PEU0_PIO_RD_REC 0x3 295 #define RFIOS_PEX01_EVT_PEU0_DMA_RD_SENT 0x4 296 #define RFIOS_PEX01_EVT_PEU0_TLP_REC 0x5 297 #define RFIOS_PEX01_EVT_PEU0_TRP_FULL_CYCLES 0x6 298 #define RFIOS_PEX01_EVT_PEU0_TCH_FULL_CYCLES 0x7 299 #define RFIOS_PEX01_EVT_PEU0_TCD_FULL_CYCLES 0x8 300 #define RFIOS_PEX01_EVT_NON_POSTED_PIOS_LATENCY 0x9 301 #define RFIOS_PEX01_EVT_NON_POSTED_PIOS_NUM 0xa 302 #define RFIOS_PEX01_EVT_PEX_CFG_WRITE 0xb 303 #define RFIOS_PEX01_EVT_PEX_CFG_READ 0xc 304 #define RFIOS_PEX01_EVT_PEX_MEM_WRITE 0xd 305 #define RFIOS_PEX01_EVT_PEX_MEM_READ 0xe 306 #define RFIOS_PEX01_EVT_PEU1_DMA_WR_REC 0x20 307 #define RFIOS_PEX01_EVT_PEU1_PIO_RD_REC 0x30 308 #define RFIOS_PEX01_EVT_PEU1_DMA_RD_SENT 0x40 309 #define RFIOS_PEX01_EVT_PEU1_TLP_REC 0x50 310 #define RFIOS_PEX01_EVT_PEU1_TRP_FULL_CYCLES 0x60 311 #define RFIOS_PEX01_EVT_PEU1_TCH_FULL_CYCLES 0x70 312 #define RFIOS_PEX01_EVT_PEU1_TCD_FULL_CYCLES 0x80 313 314 #define RFIOS_PEU01_S_EVT_NONE "event_none" 315 #define RFIOS_PEU01_S_EVT_CLK "clock_cyc" 316 #define RFIOS_PEU01_S_EVT_INT_CFG_WR_RECD "int_config_wr_recd" 317 #define RFIOS_PEU01_S_EVT_INT_CFG_RD_RECD "int_config_rd_recd" 318 #define RFIOS_PEU01_S_EVT_INT_MEM_WR_RECD "int_mem_wr_recd" 319 #define RFIOS_PEU01_S_EVT_INT_MEM_RD_RECD "int_mem_rd_recd" 320 #define RFIOS_PEU01_S_EVT_EXT_CFG_WR_RECD "ext_config_wr_recd" 321 #define RFIOS_PEU01_S_EVT_EXT_CFG_RD_RECD "ext_config_rd_recd" 322 #define RFIOS_PEU01_S_EVT_EXT_MEM_WR_RECD "ext_mem_wr_recd" 323 #define RFIOS_PEU01_S_EVT_EXT_MEM_RD_RECD "ext_mem_rd_recd" 324 #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_ALL "mem_rd_recd_all" 325 #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_1_15DW \ 326 "mem_rd_recd_1_15dw" 327 #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_16_31DW \ 328 "mem_rd_recd_16_31dw" 329 #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_32_63DW \ 330 "mem_rd_recd_32_63dw" 331 #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_64_127DW \ 332 "mem_rd_recd_64_127dw" 333 #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_128_255DW \ 334 "mem_rd_recd_128_255dw" 335 #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_256_511DW \ 336 "mem_rd_recd_256_511dw" 337 #define RFIOS_PEU01_S_EVT_MEM_RD_REQ_RECD_512_1024DW \ 338 "mem_rd_recd_512_1024dw" 339 #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_ALL "mem_wr_recd_all" 340 #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_1_15DW \ 341 "mem_wr_recd_1_15dw" 342 #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_16_31DW \ 343 "mem_wr_recd_16_31dw" 344 #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_32_63DW \ 345 "mem_wr_recd_32_63dw" 346 #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_64_127DW \ 347 "mem_wr_recd_64_127dw" 348 #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_128_255DW \ 349 "mem_wr_recd_128_255dw" 350 #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_256_511DW \ 351 "mem_wr_recd_256_511dw" 352 #define RFIOS_PEU01_S_EVT_MEM_WR_REQ_RECD_512_1024DW \ 353 "mem_wr_recd_512_1024dw" 354 #define RFIOS_PEU01_S_EVT_XMIT_POSTED_HDR_NA_CYC \ 355 "xmit_posted_hdr_na_cyc" 356 #define RFIOS_PEU01_S_EVT_XMIT_POSTED_DATA_NA_CYC \ 357 "xmit_posted_data_na_cyc" 358 #define RFIOS_PEU01_S_EVT_XMIT_NON_POSTED_HDR_NA_CYC \ 359 "xmit_non_posted_hdr_na_cyc" 360 #define RFIOS_PEU01_S_EVT_XMIT_NON_POSTED_DATA_NA_CYC \ 361 "xmit_non_posted_data_na_cyc" 362 #define RFIOS_PEU01_S_EVT_XMIT_COMPL_HDR_NA_CYC "xmit_compl_hdr_na_cyc" 363 #define RFIOS_PEU01_S_EVT_XMIT_COMPL_DATA_NA_CYC \ 364 "xmit_compl_data_na_cyc" 365 #define RFIOS_PEU01_S_EVT_NO_XMIT_CRED_CYC "no_xmit_cred_cyc" 366 #define RFIOS_PEU01_S_EVT_RETRY_BUFF_NA_CYC "retry_buffer_na_cyc" 367 #define RFIOS_PEU01_S_EVT_REC_FLCTRL_COMP_EXST_CYC \ 368 "rec_flw_compl_hdr_exhast_cyc" 369 #define RFIOS_PEU01_S_EVT_REC_FLCTRL_NPOST_EXST_CYC \ 370 "rec_flw_npost_hdr_exhast_cyc" 371 #define RFIOS_PEU01_S_EVT_REC_FLCTRL_PST_DAT_EXST \ 372 "rec_flw_post_data_exhast_cyc" 373 #define RFIOS_PEU01_S_EVT_REC_FLCTRL_PST_DT_CDT_EXST \ 374 "rec_flw_post_data_cred_exh_cyc" 375 #define RFIOS_PEU01_S_EVT_REC_FLCTRL_PST_CDT_EXST \ 376 "rec_flw_post_data_exh_cyc" 377 #define RFIOS_PEU01_S_EVT_REC_FLCTRL_CDT_EXST "rec_flw_cred_exh_cyc" 378 #define RFIOS_PEU01_S_EVT_DLLP_CRC_ERRORS "dllp_crc_errs" 379 #define RFIOS_PEU01_S_EVT_TLP_CRC_ERRORS "tlp_crc_errs" 380 #define RFIOS_PEU01_S_EVT_TLP_RECD_WITH_EDB "tlp_recd_with_edb" 381 #define RFIOS_PEU01_S_EVT_RECD_FC_TIMEOUT_ERROR "recd_fc_to_errs" 382 #define RFIOS_PEU01_S_EVT_REPLAY_NUM_ROLLOVERS "replay_num_ro" 383 #define RFIOS_PEU01_S_EVT_REPLAY_TIMER_TIMEOUTS "replay_timer_to" 384 #define RFIOS_PEU01_S_EVT_REPLAYS_INITIATED "replays_init" 385 #define RFIOS_PEU01_S_EVT_LTSSM_RECOVERY_CYC "ltssm_rec_cyc" 386 #define RFIOS_PEU01_S_EVT_ENTRIES_LTSSM_RECOVERY \ 387 "entries_ltssm_rec" 388 #define RFIOS_PEU01_S_EVT_REC_L0S_STATE_CYC "rec_l0s_state_cyc" 389 #define RFIOS_PEU01_S_EVT_REC_L0S_STATE_TRANS "rec_l0s_state_trans" 390 #define RFIOS_PEU01_S_EVT_XMIT_L0S_STATE_CYC "xmit_l0s_state_cyc" 391 #define RFIOS_PEU01_S_EVT_XMIT_L0S_STATE_TRANS "xmit_l0s_state_trans" 392 393 394 #define RFIOS_PEU01_EVT_NONE 0x0 395 #define RFIOS_PEU01_EVT_CLK 0x1 396 #define RFIOS_PEU01_EVT_INT_CFG_WR_RECD 0x2 397 #define RFIOS_PEU01_EVT_INT_CFG_RD_RECD 0x3 398 #define RFIOS_PEU01_EVT_INT_MEM_WR_RECD 0x4 399 #define RFIOS_PEU01_EVT_INT_MEM_RD_RECD 0x5 400 #define RFIOS_PEU01_EVT_EXT_CFG_WR_RECD 0x6 401 #define RFIOS_PEU01_EVT_EXT_CFG_RD_RECD 0x7 402 #define RFIOS_PEU01_EVT_EXT_MEM_WR_RECD 0x8 403 #define RFIOS_PEU01_EVT_EXT_MEM_RD_RECD 0x9 404 #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_ALL 0x10 405 #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_1_15DW 0x11 406 #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_16_31DW 0x12 407 #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_32_63DW 0x13 408 #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_64_127DW 0x14 409 #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_128_255DW 0x15 410 #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_256_511DW 0x16 411 #define RFIOS_PEU01_EVT_MEM_RD_REQ_RECD_512_1024DW 0x17 412 #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_ALL 0x18 413 #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_1_15DW 0x19 414 #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_16_31DW 0x1a 415 #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_32_63DW 0x1b 416 #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_64_127DW 0x1c 417 #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_128_255DW 0x1d 418 #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_256_511DW 0x1e 419 #define RFIOS_PEU01_EVT_MEM_WR_REQ_RECD_512_1024DW 0x1f 420 #define RFIOS_PEU01_EVT_XMIT_POSTED_HDR_NA_CYC 0x20 421 #define RFIOS_PEU01_EVT_XMIT_POSTED_DATA_NA_CYC 0x21 422 #define RFIOS_PEU01_EVT_XMIT_NON_POSTED_HDR_NA_CYC 0x22 423 #define RFIOS_PEU01_EVT_XMIT_NON_POSTED_DATA_NA_CYC 0x23 424 #define RFIOS_PEU01_EVT_XMIT_COMPL_HDR_NA_CYC 0x24 425 #define RFIOS_PEU01_EVT_XMIT_COMPL_DATA_NA_CYC 0x25 426 #define RFIOS_PEU01_EVT_NO_XMIT_CRED_CYC 0x26 427 #define RFIOS_PEU01_EVT_RETRY_BUFF_NA_CYC 0x27 428 #define RFIOS_PEU01_EVT_REC_FLCTRL_COMP_EXST_CYC 0x28 429 #define RFIOS_PEU01_EVT_REC_FLCTRL_NPOST_EXST_CYC 0x29 430 #define RFIOS_PEU01_EVT_REC_FLCTRL_PST_DAT_EXST 0x2a 431 #define RFIOS_PEU01_EVT_REC_FLCTRL_PST_DT_CDT_EXST 0x2b 432 #define RFIOS_PEU01_EVT_REC_FLCTRL_PST_CDT_EXST 0x2c 433 #define RFIOS_PEU01_EVT_REC_FLCTRL_CDT_EXST 0x2d 434 #define RFIOS_PEU01_EVT_DLLP_CRC_ERRORS 0x30 435 #define RFIOS_PEU01_EVT_TLP_CRC_ERRORS 0x31 436 #define RFIOS_PEU01_EVT_TLP_RECD_WITH_EDB 0x32 437 #define RFIOS_PEU01_EVT_RECD_FC_TIMEOUT_ERROR 0x33 438 #define RFIOS_PEU01_EVT_REPLAY_NUM_ROLLOVERS 0x34 439 #define RFIOS_PEU01_EVT_REPLAY_TIMER_TIMEOUTS 0x35 440 #define RFIOS_PEU01_EVT_REPLAYS_INITIATED 0x36 441 #define RFIOS_PEU01_EVT_LTSSM_RECOVERY_CYC 0x37 442 #define RFIOS_PEU01_EVT_ENTRIES_LTSSM_RECOVERY 0x38 443 #define RFIOS_PEU01_EVT_REC_L0S_STATE_CYC 0x40 444 #define RFIOS_PEU01_EVT_REC_L0S_STATE_TRANS 0x41 445 #define RFIOS_PEU01_EVT_XMIT_L0S_STATE_CYC 0x42 446 #define RFIOS_PEU01_EVT_XMIT_L0S_STATE_TRANS 0x43 447 448 extern int rfiospc_get_perfreg(cntr_handle_t handle, int regid, uint64_t *data); 449 extern int rfiospc_set_perfreg(cntr_handle_t handle, int regid, uint64_t data); 450 451 extern int rfios_access_hv(iospc_t *iospc_p, void *arg, int op, int regid, 452 uint64_t *data); 453 extern int rfios_access_init(iospc_t *iospc_p, iospc_ksinfo_t *ksinfo_p); 454 extern int rfios_access_fini(iospc_t *iospc_p, iospc_ksinfo_t *ksinfo_p); 455 456 #ifdef __cplusplus 457 } 458 #endif 459 460 #endif /* _RFIOSPC_TABLES_H */ 461