17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 51ae08745Sheppo * Common Development and Distribution License (the "License"). 61ae08745Sheppo * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 21459190a5Srsmaeda 227c478bd9Sstevel@tonic-gate /* 23fb2f18f8Sesaxe * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate 277c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate #include <sys/types.h> 307c478bd9Sstevel@tonic-gate #include <sys/systm.h> 317c478bd9Sstevel@tonic-gate #include <sys/archsystm.h> 327c478bd9Sstevel@tonic-gate #include <sys/machparam.h> 337c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> 347c478bd9Sstevel@tonic-gate #include <sys/cpu.h> 357c478bd9Sstevel@tonic-gate #include <sys/elf_SPARC.h> 367c478bd9Sstevel@tonic-gate #include <vm/hat_sfmmu.h> 377c478bd9Sstevel@tonic-gate #include <vm/page.h> 38*ce8eb11aSdp78419 #include <vm/vm_dep.h> 397c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 407c478bd9Sstevel@tonic-gate #include <sys/async.h> 417c478bd9Sstevel@tonic-gate #include <sys/cmn_err.h> 427c478bd9Sstevel@tonic-gate #include <sys/debug.h> 437c478bd9Sstevel@tonic-gate #include <sys/dditypes.h> 447c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 457c478bd9Sstevel@tonic-gate #include <sys/cpu_module.h> 467c478bd9Sstevel@tonic-gate #include <sys/prom_debug.h> 477c478bd9Sstevel@tonic-gate #include <sys/vmsystm.h> 487c478bd9Sstevel@tonic-gate #include <sys/prom_plat.h> 497c478bd9Sstevel@tonic-gate #include <sys/sysmacros.h> 507c478bd9Sstevel@tonic-gate #include <sys/intreg.h> 517c478bd9Sstevel@tonic-gate #include <sys/machtrap.h> 527c478bd9Sstevel@tonic-gate #include <sys/ontrap.h> 537c478bd9Sstevel@tonic-gate #include <sys/ivintr.h> 547c478bd9Sstevel@tonic-gate #include <sys/atomic.h> 557c478bd9Sstevel@tonic-gate #include <sys/panic.h> 567c478bd9Sstevel@tonic-gate #include <sys/dtrace.h> 577c478bd9Sstevel@tonic-gate #include <vm/seg_spt.h> 581ae08745Sheppo #include <sys/simulate.h> 591ae08745Sheppo #include <sys/fault.h> 607c478bd9Sstevel@tonic-gate 617c478bd9Sstevel@tonic-gate 627c478bd9Sstevel@tonic-gate uint_t root_phys_addr_lo_mask = 0xffffffffU; 637c478bd9Sstevel@tonic-gate 647c478bd9Sstevel@tonic-gate void 657c478bd9Sstevel@tonic-gate cpu_setup(void) 667c478bd9Sstevel@tonic-gate { 677c478bd9Sstevel@tonic-gate extern int mmu_exported_pagesize_mask; 681ae08745Sheppo char *generic_isa_set[] = { 691ae08745Sheppo "sparcv9+vis", 701ae08745Sheppo "sparcv8plus+vis", 711ae08745Sheppo NULL 721ae08745Sheppo }; 731ae08745Sheppo 741ae08745Sheppo /* 751ae08745Sheppo * The setup common to all CPU modules is done in cpu_setup_common 761ae08745Sheppo * routine. 771ae08745Sheppo */ 781ae08745Sheppo cpu_setup_common(generic_isa_set); 797c478bd9Sstevel@tonic-gate 807c478bd9Sstevel@tonic-gate cache |= (CACHE_PTAG | CACHE_IOCOHERENT); 817c478bd9Sstevel@tonic-gate 821ae08745Sheppo if (broken_md_flag) { 837c478bd9Sstevel@tonic-gate /* 841ae08745Sheppo * Turn on the missing bits supported by sun4v architecture in 851ae08745Sheppo * MMU pagesize mask returned by MD. 867c478bd9Sstevel@tonic-gate */ 871ae08745Sheppo mmu_exported_pagesize_mask |= DEFAULT_SUN4V_MMU_PAGESIZE_MASK; 881ae08745Sheppo } else { 897c478bd9Sstevel@tonic-gate /* 901ae08745Sheppo * According to sun4v architecture each processor must 911ae08745Sheppo * support 8K, 64K and 4M page sizes. If any of the page 921ae08745Sheppo * size is missing from page size mask, then panic. 937c478bd9Sstevel@tonic-gate */ 941ae08745Sheppo if ((mmu_exported_pagesize_mask & 951ae08745Sheppo DEFAULT_SUN4V_MMU_PAGESIZE_MASK) != 961ae08745Sheppo DEFAULT_SUN4V_MMU_PAGESIZE_MASK) 971ae08745Sheppo cmn_err(CE_PANIC, "machine description" 981ae08745Sheppo " does not have required sun4v page sizes" 991ae08745Sheppo " 8K, 64K and 4M: MD mask is 0x%x", 1001ae08745Sheppo mmu_exported_pagesize_mask); 1017c478bd9Sstevel@tonic-gate } 1027c478bd9Sstevel@tonic-gate 1037c478bd9Sstevel@tonic-gate /* 1041ae08745Sheppo * If processor supports the subset of full 64-bit virtual 1051ae08745Sheppo * address space, then set VA hole accordingly. 1067c478bd9Sstevel@tonic-gate */ 1071ae08745Sheppo if (va_bits < VA_ADDRESS_SPACE_BITS) { 1081ae08745Sheppo hole_start = (caddr_t)(1ull << (va_bits - 1)); 1091ae08745Sheppo hole_end = (caddr_t)(0ull - (1ull << (va_bits - 1))); 1101ae08745Sheppo } else { 1111ae08745Sheppo hole_start = hole_end = 0; 1121ae08745Sheppo } 1137c478bd9Sstevel@tonic-gate } 1147c478bd9Sstevel@tonic-gate 1157c478bd9Sstevel@tonic-gate void 1167c478bd9Sstevel@tonic-gate cpu_fiximp(struct cpu_node *cpunode) 1177c478bd9Sstevel@tonic-gate { 1187c478bd9Sstevel@tonic-gate /* 1191ae08745Sheppo * The Cache node is optional in MD. Therefore in case "Cache" 1201ae08745Sheppo * does not exists in MD, set the default L2 cache associativity, 1211ae08745Sheppo * size, linesize for generic CPU module. 1227c478bd9Sstevel@tonic-gate */ 1231ae08745Sheppo if (cpunode->ecache_size == 0) 1241ae08745Sheppo cpunode->ecache_size = 0x100000; 1251ae08745Sheppo if (cpunode->ecache_linesize == 0) 1261ae08745Sheppo cpunode->ecache_linesize = 64; 1271ae08745Sheppo if (cpunode->ecache_associativity == 0) 1281ae08745Sheppo cpunode->ecache_associativity = 1; 1297c478bd9Sstevel@tonic-gate } 1307c478bd9Sstevel@tonic-gate 1317c478bd9Sstevel@tonic-gate void 1327c478bd9Sstevel@tonic-gate dtrace_flush_sec(uintptr_t addr) 1337c478bd9Sstevel@tonic-gate { 1347c478bd9Sstevel@tonic-gate pfn_t pfn; 1357c478bd9Sstevel@tonic-gate proc_t *procp = ttoproc(curthread); 1367c478bd9Sstevel@tonic-gate page_t *pp; 1377c478bd9Sstevel@tonic-gate caddr_t va; 1387c478bd9Sstevel@tonic-gate 1397c478bd9Sstevel@tonic-gate pfn = hat_getpfnum(procp->p_as->a_hat, (void *)addr); 1407c478bd9Sstevel@tonic-gate if (pfn != -1) { 1417c478bd9Sstevel@tonic-gate ASSERT(pf_is_memory(pfn)); 1427c478bd9Sstevel@tonic-gate pp = page_numtopp_noreclaim(pfn, SE_SHARED); 1437c478bd9Sstevel@tonic-gate if (pp != NULL) { 1447c478bd9Sstevel@tonic-gate va = ppmapin(pp, PROT_READ | PROT_WRITE, (void *)addr); 1457c478bd9Sstevel@tonic-gate /* sparc needs 8-byte align */ 1467c478bd9Sstevel@tonic-gate doflush((caddr_t)((uintptr_t)va & -8l)); 1477c478bd9Sstevel@tonic-gate ppmapout(va); 1487c478bd9Sstevel@tonic-gate page_unlock(pp); 1497c478bd9Sstevel@tonic-gate } 1507c478bd9Sstevel@tonic-gate } 1517c478bd9Sstevel@tonic-gate } 1527c478bd9Sstevel@tonic-gate 1537c478bd9Sstevel@tonic-gate void 154459190a5Srsmaeda cpu_map_exec_units(struct cpu *cp) 1557c478bd9Sstevel@tonic-gate { 156459190a5Srsmaeda ASSERT(MUTEX_HELD(&cpu_lock)); 157459190a5Srsmaeda 15870f54eadSesaxe /* 159fb2f18f8Sesaxe * The cpu_ipipe and cpu_fpu fields are initialized based on 160459190a5Srsmaeda * the execution unit sharing information from the MD. They 161459190a5Srsmaeda * default to the CPU id in the absence of such information. 16270f54eadSesaxe */ 1631ae08745Sheppo cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping; 1641ae08745Sheppo if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND) 16570f54eadSesaxe cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id); 166fb2f18f8Sesaxe 167fb2f18f8Sesaxe cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping; 168fb2f18f8Sesaxe if (cp->cpu_m.cpu_fpu == NO_EU_MAPPING_FOUND) 169fb2f18f8Sesaxe cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id); 170fb2f18f8Sesaxe 171*ce8eb11aSdp78419 cp->cpu_m.cpu_mpipe = cpunodes[cp->cpu_id].l2_cache_mapping; 172*ce8eb11aSdp78419 if (cp->cpu_m.cpu_mpipe == NO_L2_CACHE_MAPPING_FOUND) 173*ce8eb11aSdp78419 cp->cpu_m.cpu_mpipe = CPU_L2_CACHEID_INVALID; 174*ce8eb11aSdp78419 175fb2f18f8Sesaxe cp->cpu_m.cpu_core = (id_t)(cp->cpu_id); 17659ac0c16Sdavemq 17759ac0c16Sdavemq /* 17859ac0c16Sdavemq * The cpu_chip field is set to invalid(unknown) for generic cpu. 17959ac0c16Sdavemq */ 18059ac0c16Sdavemq cp->cpu_m.cpu_chip = CPU_CHIPID_INVALID; 1817c478bd9Sstevel@tonic-gate } 1827c478bd9Sstevel@tonic-gate 1837c478bd9Sstevel@tonic-gate void 184459190a5Srsmaeda cpu_init_private(struct cpu *cp) 1857c478bd9Sstevel@tonic-gate { 186459190a5Srsmaeda cpu_map_exec_units(cp); 1877c478bd9Sstevel@tonic-gate } 1887c478bd9Sstevel@tonic-gate 189459190a5Srsmaeda /*ARGSUSED*/ 190459190a5Srsmaeda void 191459190a5Srsmaeda cpu_uninit_private(struct cpu *cp) 192459190a5Srsmaeda {} 193459190a5Srsmaeda 1947c478bd9Sstevel@tonic-gate /* 1957c478bd9Sstevel@tonic-gate * Invalidate a TSB. Since this needs to work on all sun4v 1967c478bd9Sstevel@tonic-gate * architecture compliant processors, we use the old method of 1977c478bd9Sstevel@tonic-gate * walking the TSB, setting each tag to TSBTAG_INVALID. 1987c478bd9Sstevel@tonic-gate */ 1997c478bd9Sstevel@tonic-gate void 2007c478bd9Sstevel@tonic-gate cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes) 2017c478bd9Sstevel@tonic-gate { 2027c478bd9Sstevel@tonic-gate struct tsbe *tsbaddr; 2037c478bd9Sstevel@tonic-gate 2047c478bd9Sstevel@tonic-gate for (tsbaddr = (struct tsbe *)tsb_base; 2057c478bd9Sstevel@tonic-gate (uintptr_t)tsbaddr < (uintptr_t)(tsb_base + tsb_bytes); 2067c478bd9Sstevel@tonic-gate tsbaddr++) { 2077c478bd9Sstevel@tonic-gate tsbaddr->tte_tag.tag_inthi = TSBTAG_INVALID; 2087c478bd9Sstevel@tonic-gate } 2097c478bd9Sstevel@tonic-gate } 210ce0352ebSgirish 211ce0352ebSgirish /* 2121ae08745Sheppo * Sun4v kernel must emulate code a generic sun4v processor may not support 2131ae08745Sheppo * i.e. VIS1 and VIS2. 2141ae08745Sheppo */ 2151ae08745Sheppo #define IS_FLOAT(i) (((i) & 0x1000000) != 0) 2161ae08745Sheppo #define IS_IBIT_SET(x) (x & 0x2000) 2171ae08745Sheppo #define IS_VIS1(op, op3)(op == 2 && op3 == 0x36) 2181ae08745Sheppo #define IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(op, op3, asi) \ 2191ae08745Sheppo (op == 3 && (op3 == IOP_V8_LDDFA || \ 2201ae08745Sheppo op3 == IOP_V8_STDFA) && asi > ASI_SNFL) 2211ae08745Sheppo int 2221ae08745Sheppo vis1_partial_support(struct regs *rp, k_siginfo_t *siginfo, uint_t *fault) 2231ae08745Sheppo { 2241ae08745Sheppo char *badaddr; 2251ae08745Sheppo int instr; 2261ae08745Sheppo uint_t optype, op3, asi; 2271ae08745Sheppo uint_t rd, ignor; 2281ae08745Sheppo 2291ae08745Sheppo if (!USERMODE(rp->r_tstate)) 2301ae08745Sheppo return (-1); 2311ae08745Sheppo 2321ae08745Sheppo instr = fetch_user_instr((caddr_t)rp->r_pc); 2331ae08745Sheppo 2341ae08745Sheppo rd = (instr >> 25) & 0x1f; 2351ae08745Sheppo optype = (instr >> 30) & 0x3; 2361ae08745Sheppo op3 = (instr >> 19) & 0x3f; 2371ae08745Sheppo ignor = (instr >> 5) & 0xff; 2381ae08745Sheppo if (IS_IBIT_SET(instr)) { 2391ae08745Sheppo asi = (uint32_t)((rp->r_tstate >> TSTATE_ASI_SHIFT) & 2401ae08745Sheppo TSTATE_ASI_MASK); 2411ae08745Sheppo } else { 2421ae08745Sheppo asi = ignor; 2431ae08745Sheppo } 2441ae08745Sheppo 2451ae08745Sheppo if (!IS_VIS1(optype, op3) && 2461ae08745Sheppo !IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(optype, op3, asi)) { 2471ae08745Sheppo return (-1); 2481ae08745Sheppo } 2491ae08745Sheppo switch (simulate_unimp(rp, &badaddr)) { 2501ae08745Sheppo case SIMU_RETRY: 2511ae08745Sheppo break; /* regs are already set up */ 2521ae08745Sheppo /*NOTREACHED*/ 2531ae08745Sheppo 2541ae08745Sheppo case SIMU_SUCCESS: 2551ae08745Sheppo /* 2561ae08745Sheppo * skip the successfully 2571ae08745Sheppo * simulated instruction 2581ae08745Sheppo */ 2591ae08745Sheppo rp->r_pc = rp->r_npc; 2601ae08745Sheppo rp->r_npc += 4; 2611ae08745Sheppo break; 2621ae08745Sheppo /*NOTREACHED*/ 2631ae08745Sheppo 2641ae08745Sheppo case SIMU_FAULT: 2651ae08745Sheppo siginfo->si_signo = SIGSEGV; 2661ae08745Sheppo siginfo->si_code = SEGV_MAPERR; 2671ae08745Sheppo siginfo->si_addr = badaddr; 2681ae08745Sheppo *fault = FLTBOUNDS; 2691ae08745Sheppo break; 2701ae08745Sheppo 2711ae08745Sheppo case SIMU_DZERO: 2721ae08745Sheppo siginfo->si_signo = SIGFPE; 2731ae08745Sheppo siginfo->si_code = FPE_INTDIV; 2741ae08745Sheppo siginfo->si_addr = (caddr_t)rp->r_pc; 2751ae08745Sheppo *fault = FLTIZDIV; 2761ae08745Sheppo break; 2771ae08745Sheppo 2781ae08745Sheppo case SIMU_UNALIGN: 2791ae08745Sheppo siginfo->si_signo = SIGBUS; 2801ae08745Sheppo siginfo->si_code = BUS_ADRALN; 2811ae08745Sheppo siginfo->si_addr = badaddr; 2821ae08745Sheppo *fault = FLTACCESS; 2831ae08745Sheppo break; 2841ae08745Sheppo 2851ae08745Sheppo case SIMU_ILLEGAL: 2861ae08745Sheppo default: 2871ae08745Sheppo siginfo->si_signo = SIGILL; 2881ae08745Sheppo op3 = (instr >> 19) & 0x3F; 2891ae08745Sheppo if ((IS_FLOAT(instr) && (op3 == IOP_V8_STQFA) || 2901ae08745Sheppo (op3 == IOP_V8_STDFA))) 2911ae08745Sheppo siginfo->si_code = ILL_ILLADR; 2921ae08745Sheppo else 2931ae08745Sheppo siginfo->si_code = ILL_ILLOPC; 2941ae08745Sheppo siginfo->si_addr = (caddr_t)rp->r_pc; 2951ae08745Sheppo *fault = FLTILL; 2961ae08745Sheppo break; 2971ae08745Sheppo } 2981ae08745Sheppo return (0); 2991ae08745Sheppo } 3001ae08745Sheppo 3011ae08745Sheppo /* 302ce0352ebSgirish * Trapstat support for generic sun4v processor 303ce0352ebSgirish */ 304ce0352ebSgirish int 305ce0352ebSgirish cpu_trapstat_conf(int cmd) 306ce0352ebSgirish { 307ce0352ebSgirish int status; 308ce0352ebSgirish 309ce0352ebSgirish switch (cmd) { 310ce0352ebSgirish case CPU_TSTATCONF_INIT: 311ce0352ebSgirish case CPU_TSTATCONF_FINI: 312ce0352ebSgirish case CPU_TSTATCONF_ENABLE: 313ce0352ebSgirish case CPU_TSTATCONF_DISABLE: 314ce0352ebSgirish status = ENOTSUP; 315ce0352ebSgirish break; 316ce0352ebSgirish 317ce0352ebSgirish default: 318ce0352ebSgirish status = EINVAL; 319ce0352ebSgirish break; 320ce0352ebSgirish } 321ce0352ebSgirish return (status); 322ce0352ebSgirish } 323ce0352ebSgirish 324ce0352ebSgirish /*ARGSUSED*/ 325ce0352ebSgirish void 326ce0352ebSgirish cpu_trapstat_data(void *buf, uint_t tstat_pgszs) 327ce0352ebSgirish { 328ce0352ebSgirish } 329