1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_US3_MODULE_H 27 #define _SYS_US3_MODULE_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 #include <sys/async.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #ifdef _KERNEL 37 38 /* 39 * Macros to access the "cheetah cpu private" data structure. 40 */ 41 #define CPU_PRIVATE_PTR(cp, x) (&(((cheetah_private_t *)CPU_PRIVATE(cp))->x)) 42 #define CPU_PRIVATE_VAL(cp, x) (((cheetah_private_t *)CPU_PRIVATE(cp))->x) 43 44 #define CHP_WORD_TO_OFF(word, off) (((word) * 8) == off) 45 46 #if defined(JALAPENO) || defined(SERRANO) 47 /* JP J_REQ errors */ 48 #define C_AFSR_JREQ_ERRS (C_AFSR_RUE | C_AFSR_BP | C_AFSR_WBP | \ 49 C_AFSR_RCE | C_AFSR_TO | C_AFSR_BERR | C_AFSR_UMS) 50 /* JP AID errors */ 51 #define C_AFSR_AID_ERRS (C_AFSR_CPU | C_AFSR_FRU | C_AFSR_CPC | \ 52 C_AFSR_FRC) 53 54 #if defined(SERRANO) 55 /* SERRANO AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 56 #define C_AFSR_CECC_ERRS (C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_CPC | \ 57 C_AFSR_CPU | C_AFSR_WDC | C_AFSR_WDU | C_AFSR_EDC | \ 58 C_AFSR_CE | C_AFSR_RCE | C_AFSR_WBP | C_AFSR_FRC | \ 59 C_AFSR_FRU | C_AFSR_EDU | C_AFSR_ETI | C_AFSR_ETC) 60 61 #else /* SERRANO */ 62 /* JP AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 63 #define C_AFSR_CECC_ERRS (C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_CPC | \ 64 C_AFSR_CPU | C_AFSR_WDC | C_AFSR_WDU | C_AFSR_EDC | \ 65 C_AFSR_CE | C_AFSR_RCE | C_AFSR_WBP | C_AFSR_FRC | \ 66 C_AFSR_FRU | C_AFSR_EDU) 67 #endif /* SERRANO */ 68 69 #if defined(SERRANO) 70 /* 71 * SERRANO AFSR bits from {Instruction,Data}_access_error traps 72 * (Traps 0xa, 0x32) 73 */ 74 #define C_AFSR_ASYNC_ERRS (C_AFSR_OM | C_AFSR_TO | C_AFSR_BERR | \ 75 C_AFSR_UE | C_AFSR_RUE | C_AFSR_EDU | C_AFSR_BP | \ 76 C_AFSR_ETU | C_AFSR_ETS) 77 #else /* SERRANO */ 78 /* JP AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */ 79 #define C_AFSR_ASYNC_ERRS (C_AFSR_OM | C_AFSR_TO | C_AFSR_BERR | \ 80 C_AFSR_UE | C_AFSR_RUE | C_AFSR_EDU | C_AFSR_BP) 81 #endif /* SERRANO */ 82 83 #if defined(SERRANO) 84 /* SERRANO AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 85 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_ETI | \ 86 C_AFSR_ETC) 87 88 #else /* SERRANO */ 89 /* JP AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 90 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC) 91 #endif /* SERRANO */ 92 93 #if defined(SERRANO) 94 /* SERRANO AFSR bits from Fatal errors (processor asserts ERROR pin) */ 95 #define C_AFSR_FATAL_ERRS (C_AFSR_JETO | C_AFSR_SCE | C_AFSR_JEIC | \ 96 C_AFSR_JEIT | C_AFSR_JEIS | C_AFSR_IERR | \ 97 C_AFSR_ISAP | C_AFSR_EFES | C_AFSR_ETS | C_AFSR_ETU) 98 99 #else /* SERRANO */ 100 /* JP AFSR bits from Fatal errors (processor asserts ERROR pin) */ 101 #define C_AFSR_FATAL_ERRS (C_AFSR_JETO | C_AFSR_SCE | C_AFSR_JEIC | \ 102 C_AFSR_JEIT | C_AFSR_JEIS | C_AFSR_IERR | \ 103 C_AFSR_ISAP | C_AFSR_ETP) 104 #endif /* SERRANO */ 105 106 /* JP AFSR all valid error status bits */ 107 #define C_AFSR_ALL_ERRS (C_AFSR_FATAL_ERRS | C_AFSR_FECC_ERRS | \ 108 C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME) 109 110 #if defined(SERRANO) 111 /* SERRANO AFSR all ME status bits */ 112 #define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_UCU | \ 113 C_AFSR_EDU | C_AFSR_WDU | C_AFSR_CPU | C_AFSR_UCC | \ 114 C_AFSR_BERR | C_AFSR_TO | C_AFSR_ETU | C_AFSR_OM | \ 115 C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_RUE | C_AFSR_BP | \ 116 C_AFSR_WBP | C_AFSR_FRU | C_AFSR_JETO | C_AFSR_SCE | \ 117 C_AFSR_JEIC | C_AFSR_JEIT | C_AFSR_JEIS | \ 118 C_AFSR_ETC | C_AFSR_ETI) 119 120 #else /* SERRANO */ 121 /* JP AFSR all ME status bits */ 122 #define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_UCU | \ 123 C_AFSR_EDU | C_AFSR_WDU | C_AFSR_CPU | C_AFSR_UCC | \ 124 C_AFSR_BERR | C_AFSR_TO | C_AFSR_ETP | C_AFSR_OM | \ 125 C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_RUE | C_AFSR_BP | \ 126 C_AFSR_WBP | C_AFSR_FRU | C_AFSR_JETO | C_AFSR_SCE | \ 127 C_AFSR_JEIC | C_AFSR_JEIT | C_AFSR_JEIS) 128 #endif /* SERRANO */ 129 130 /* JP AFSR bits due to a Memory error */ 131 #define C_AFSR_MEMORY (C_AFSR_UE | C_AFSR_CE | C_AFSR_FRC | C_AFSR_FRU |\ 132 C_AFSR_RCE | C_AFSR_RUE) 133 134 /* JP AFSR bits due to parity errors and have a valid BSYND */ 135 #define C_AFSR_MSYND_ERRS (C_AFSR_IVPE | C_AFSR_BP | C_AFSR_WBP) 136 137 /* JP AFSR bits with a valid ESYND field */ 138 #define C_AFSR_ESYND_ERRS (C_AFSR_UE | C_AFSR_CE | \ 139 C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 140 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \ 141 C_AFSR_FRC | C_AFSR_FRU) 142 143 /* JP AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */ 144 #define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_RUE | C_AFSR_UCU | C_AFSR_EDU | \ 145 C_AFSR_WDU | C_AFSR_CPU | C_AFSR_IVPE | C_AFSR_TO | \ 146 C_AFSR_BERR | C_AFSR_UMS | C_AFSR_OM | C_AFSR_WBP | \ 147 C_AFSR_FRU | C_AFSR_BP) 148 149 #elif defined(CHEETAH_PLUS) 150 151 /* Ch+ AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 152 #define C_AFSR_CECC_ERRS (C_AFSR_CE | C_AFSR_EMC | C_AFSR_EDU | \ 153 C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \ 154 C_AFSR_CPC | C_AFSR_IVU | C_AFSR_IVC | C_AFSR_DUE | \ 155 C_AFSR_THCE | C_AFSR_DBERR | C_AFSR_DTO | C_AFSR_IMU | \ 156 C_AFSR_IMC) 157 158 /* Ch+ AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */ 159 #define C_AFSR_ASYNC_ERRS (C_AFSR_UE | C_AFSR_EMU | C_AFSR_EDU | \ 160 C_AFSR_TO | C_AFSR_BERR) 161 162 /* Ch+ AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 163 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_TSCE) 164 165 /* Ch+ AFSR bits from Fatal errors (processor asserts ERROR pin) */ 166 #define C_AFSR_FATAL_ERRS (C_AFSR_PERR | C_AFSR_IERR | C_AFSR_ISAP | \ 167 C_AFSR_TUE | C_AFSR_TUE_SH | C_AFSR_IMU | C_AFSR_EMU) 168 169 /* Ch+ AFSR all valid error status bits */ 170 #define C_AFSR_ALL_ERRS (C_AFSR_FATAL_ERRS | C_AFSR_FECC_ERRS | \ 171 C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME) 172 173 /* Ch+ AFSR all errors that set ME bit, in both AFSR and AFSR_EXT */ 174 #define C_AFSR_ALL_ME_ERRS (C_AFSR_TUE_SH | C_AFSR_IMU | C_AFSR_DTO | \ 175 C_AFSR_DBERR | C_AFSR_TSCE | C_AFSR_TUE | C_AFSR_DUE | \ 176 C_AFSR_ISAP | C_AFSR_EMU | C_AFSR_IVU | C_AFSR_TO | \ 177 C_AFSR_BERR | C_AFSR_UCC | C_AFSR_UCU | C_AFSR_CPU | \ 178 C_AFSR_WDU | C_AFSR_EDU | C_AFSR_UE | \ 179 C_AFSR_L3_TUE_SH | C_AFSR_L3_TUE | C_AFSR_L3_EDU | \ 180 C_AFSR_L3_UCC | C_AFSR_L3_UCU | C_AFSR_L3_CPU | \ 181 C_AFSR_L3_WDU) 182 183 /* Ch+ AFSR bits due to an Ecache data error */ 184 #define C_AFSR_EC_DATA_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | \ 185 C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \ 186 C_AFSR_CPC) 187 188 /* Ch+ AFSR bits due to a Memory error */ 189 #define C_AFSR_MEMORY (C_AFSR_UE | C_AFSR_CE | C_AFSR_EMU | C_AFSR_EMC | \ 190 C_AFSR_DUE) 191 192 /* Ch+ AFSR bits due to an Mtag error and have a valid MSYND */ 193 #define C_AFSR_MSYND_ERRS (C_AFSR_EMU | C_AFSR_EMC | C_AFSR_IMU | \ 194 C_AFSR_IMC) 195 196 /* Ch+ AFSR bits with a valid ESYND field */ 197 #define C_AFSR_ESYND_ERRS (C_AFSR_UE | C_AFSR_CE | \ 198 C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 199 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \ 200 C_AFSR_IVU | C_AFSR_IVC | C_AFSR_DUE) 201 202 /* Ch+ AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */ 203 #define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_UCU | C_AFSR_EMU | C_AFSR_EDU | \ 204 C_AFSR_WDU | C_AFSR_CPU | C_AFSR_IVU | C_AFSR_TO | \ 205 C_AFSR_BERR | C_AFSR_DUE | C_AFSR_TUE | C_AFSR_DTO | \ 206 C_AFSR_DBERR | C_AFSR_TUE_SH | C_AFSR_IMU) 207 208 #else /* CHEETAH_PLUS */ 209 210 /* AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 211 #define C_AFSR_CECC_ERRS (C_AFSR_CE | C_AFSR_EMC | C_AFSR_EDU | \ 212 C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \ 213 C_AFSR_CPC | C_AFSR_IVU | C_AFSR_IVC) 214 215 /* AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */ 216 #define C_AFSR_ASYNC_ERRS (C_AFSR_UE | C_AFSR_EMU | C_AFSR_EDU | \ 217 C_AFSR_TO | C_AFSR_BERR) 218 219 /* AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 220 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC) 221 222 /* AFSR bits from Fatal errors (processor asserts ERROR pin) */ 223 #define C_AFSR_FATAL_ERRS (C_AFSR_PERR | C_AFSR_IERR | C_AFSR_ISAP | \ 224 C_AFSR_EMU) 225 226 /* AFSR all valid error status bits */ 227 #define C_AFSR_ALL_ERRS (C_AFSR_FATAL_ERRS | C_AFSR_FECC_ERRS | \ 228 C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME) 229 230 /* AFSR all ME status bits */ 231 #define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_IVU | \ 232 C_AFSR_EMU | C_AFSR_UCU | C_AFSR_EDU | C_AFSR_WDU | \ 233 C_AFSR_CPU | C_AFSR_UCC | C_AFSR_BERR | C_AFSR_TO) 234 235 /* AFSR bits due to an Ecache error */ 236 #define C_AFSR_EC_DATA_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | \ 237 C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \ 238 C_AFSR_CPC) 239 240 /* AFSR bits due to a Memory error */ 241 #define C_AFSR_MEMORY (C_AFSR_UE | C_AFSR_CE | C_AFSR_EMU | C_AFSR_EMC) 242 243 /* AFSR bits due to an Mtag error and have a valid MSYND */ 244 #define C_AFSR_MSYND_ERRS (C_AFSR_EMU | C_AFSR_EMC) 245 246 /* AFSR bits with a valid ESYND field */ 247 #define C_AFSR_ESYND_ERRS (C_AFSR_UE | C_AFSR_CE | \ 248 C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 249 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \ 250 C_AFSR_IVU | C_AFSR_IVC) 251 252 /* AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */ 253 #define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_UCU | C_AFSR_EMU | C_AFSR_EDU | \ 254 C_AFSR_WDU | C_AFSR_CPU | C_AFSR_IVU | C_AFSR_TO | \ 255 C_AFSR_BERR) 256 257 #endif /* CHEETAH_PLUS */ 258 259 #if defined(JALAPENO) || defined(SERRANO) 260 /* AFSR all valid bits (except for ETW) */ 261 #define C_AFSR_MASK (C_AFSR_ALL_ERRS | C_AFSR_PRIV | C_AFSR_B_SYND | \ 262 C_AFSR_E_SYND | C_AFSR_AID | C_AFSR_JREQ) 263 #else /* JALAPENO || SERRANO */ 264 /* AFSR all valid bits */ 265 #define C_AFSR_MASK (C_AFSR_ALL_ERRS | C_AFSR_PRIV | C_AFSR_M_SYND | \ 266 C_AFSR_E_SYND) 267 #endif /* JALAPENO || SERRANO */ 268 269 /* 270 * Panther AFSR_EXT bits from Disrupting (Corrected) ECC error Trap 271 * (Trap 0x63) 272 */ 273 #define C_AFSR_EXT_CECC_ERRS (C_AFSR_L3_EDU | C_AFSR_L3_EDC | \ 274 C_AFSR_L3_WDU | C_AFSR_L3_WDC | C_AFSR_L3_CPU | \ 275 C_AFSR_L3_CPC | C_AFSR_L3_THCE) 276 277 /* 278 * Panther AFSR_EXT bits from {Instruction,Data}_access_error traps 279 * (Traps 0xa, 0x32) 280 */ 281 #define C_AFSR_EXT_ASYNC_ERRS (C_AFSR_L3_EDU) 282 283 /* Panther AFSR_EXT bits from Fast_ECC_error trap (Trap 0x70) */ 284 #define C_AFSR_EXT_FECC_ERRS (C_AFSR_L3_UCU | C_AFSR_L3_UCC) 285 286 /* Panther AFSR_EXT bits from Fatal errors (processor asserts ERROR pin) */ 287 #define C_AFSR_EXT_FATAL_ERRS (C_AFSR_L3_TUE | C_AFSR_L3_TUE_SH | \ 288 C_AFSR_RED_ERR | C_AFSR_EFA_PAR_ERR) 289 290 /* Panther AFSR_EXT all valid error status bits */ 291 #define C_AFSR_EXT_ALL_ERRS (C_AFSR_EXT_FATAL_ERRS | \ 292 C_AFSR_EXT_FECC_ERRS | C_AFSR_EXT_CECC_ERRS | \ 293 C_AFSR_EXT_ASYNC_ERRS | C_AFSR_L3_MECC) 294 295 /* Panther AFSR_EXT bits for errors to report a L3 cache data resource */ 296 #define C_AFSR_EXT_L3_DATA_ERRS (C_AFSR_L3_WDU | C_AFSR_L3_WDC | \ 297 C_AFSR_L3_CPU | C_AFSR_L3_CPC | C_AFSR_L3_UCU | \ 298 C_AFSR_L3_UCC | C_AFSR_L3_EDU | C_AFSR_L3_EDC | \ 299 C_AFSR_L3_MECC) 300 301 /* Panther AFSR_EXT bits with a valid ESYND field */ 302 #define C_AFSR_EXT_ESYND_ERRS (C_AFSR_L3_UCU | C_AFSR_L3_UCC | \ 303 C_AFSR_L3_EDU | C_AFSR_L3_EDC | C_AFSR_L3_WDU | \ 304 C_AFSR_L3_WDC | C_AFSR_L3_CPU | C_AFSR_L3_CPC) 305 306 /* PANTHER AFSR_EXT error bits for AFT Level 1 messages (uncorrected) */ 307 #define C_AFSR_EXT_LEVEL1 (C_AFSR_L3_UCU | C_AFSR_L3_EDU | \ 308 C_AFSR_L3_WDU | C_AFSR_L3_CPU | C_AFSR_L3_TUE | \ 309 C_AFSR_L3_TUE_SH) 310 311 /* 312 * AFSR / AFSR_EXT bits for which we need to panic the system. 313 */ 314 #define C_AFSR_PANIC(errs) (((errs) & (C_AFSR_FATAL_ERRS | \ 315 C_AFSR_EXT_FATAL_ERRS)) != 0) 316 317 /* 318 * For the Fast ECC TL1 handler, we are limited in how many registers 319 * we can use, so we need to store the AFSR_EXT bits within the AFSR 320 * register using some of the AFSR reserved bits. 321 */ 322 #define AFSR_EXT_IN_AFSR_MASK C_AFSR_EXT_ALL_ERRS 323 #define AFSR_EXT_IN_AFSR_SHIFT 20 324 325 /* 326 * Defines for the flag field in the CPU logout structure. See the 327 * definition of ch_cpu_logout_t for further description. 328 */ 329 #define CLO_FLAGS_TT_MASK 0xff000 330 #define CLO_FLAGS_TT_SHIFT 12 331 #define CLO_FLAGS_TL_MASK 0xf00 332 #define CLO_FLAGS_TL_SHIFT 8 333 #define CLO_NESTING_MAX 20 /* Arbitrary maximum value */ 334 335 #define C_M_SYND_SHIFT 16 336 #define GET_M_SYND(afsr) (((afsr) & C_AFSR_M_SYND) >> C_M_SYND_SHIFT) 337 #define GET_E_SYND(afsr) ((afsr) & C_AFSR_E_SYND) 338 339 /* 340 * Bits of Cheetah Asynchronous Fault Address Register 341 */ 342 #define C_AFAR_PA INT64_C(0x000007fffffffff0) /* PA<42:4> physical address */ 343 344 /* 345 * Defines for the different types of dcache_flush 346 * it is stored in dflush_type 347 */ 348 #define FLUSHALL_TYPE 0x0 /* blasts all cache lines */ 349 #define FLUSHMATCH_TYPE 0x1 /* flush entire cache but check each */ 350 /* each line for a match */ 351 #define FLUSHPAGE_TYPE 0x2 /* flush only one page and check */ 352 /* each line for a match */ 353 354 /* 355 * D-Cache Tag Data Register 356 * 357 * +----------+--------+----------+ 358 * | Reserved | DC_Tag | DC_Valid | 359 * +----------+--------+----------+ 360 * 63 31 30 1 0 361 * 362 */ 363 #define ICACHE_FLUSHSZ 0x20 /* one line in i$ */ 364 #define CHEETAH_DC_VBIT_SHIFT 1 365 #define CHEETAH_DC_VBIT_MASK 0x1 366 367 /* 368 * Define for max size of "reason" string in panic flows. Since this is on 369 * the stack, we want to keep it as small as is reasonable. 370 */ 371 #define MAX_REASON_STRING 40 372 373 /* 374 * These error types are specific to Cheetah and are used internally for the 375 * Cheetah fault structure flt_type field. 376 */ 377 #define CPU_TO 1 /* Timeout */ 378 #define CPU_BERR 2 /* Bus Error */ 379 #define CPU_CE 3 /* Correctable Memory Error */ 380 #define CPU_UE 4 /* Uncorrectable Memory Error */ 381 #define CPU_CE_ECACHE 5 /* Correctable Ecache Error */ 382 #define CPU_UE_ECACHE 6 /* Uncorrectable Ecache Error */ 383 #define CPU_EMC 7 /* Correctable Mtag Error */ 384 #define CPU_FATAL 8 /* Fatal Error */ 385 #define CPU_ORPH 9 /* Orphaned UCC/UCU error */ 386 #define CPU_IV 10 /* IVU or IVC */ 387 #define CPU_INV_AFSR 11 /* Invalid AFSR */ 388 #define CPU_UE_ECACHE_RETIRE 12 /* Uncorrectable Ecache, retire page */ 389 #define CPU_IC_PARITY 13 /* Icache parity error trap */ 390 #define CPU_DC_PARITY 14 /* Dcache parity error trap */ 391 #define CPU_DUE 15 /* Disrupting UE */ 392 #define CPU_FPUERR 16 /* FPU Error */ 393 /* 394 * These next six error types (17-22) are only used in Jalapeno code 395 */ 396 #define CPU_RCE 17 /* Correctable remote memory error */ 397 #define CPU_RUE 18 /* Uncorrectable remote memory error */ 398 #define CPU_FRC 19 /* Correctable foreign memory error */ 399 #define CPU_FRU 20 /* Uncorrectable foreign memory error */ 400 #define CPU_BPAR 21 /* Bus parity (BP or WBP) errorrs */ 401 #define CPU_UMS 22 /* Unsupported memory store */ 402 /* 403 * These next four error types (23-26) are only used in Panther code 404 */ 405 #define CPU_PC_PARITY 23 /* Pcache parity error */ 406 #define CPU_ITLB_PARITY 24 /* Panther ITLB parity error */ 407 #define CPU_DTLB_PARITY 25 /* Panther DTLB parity error */ 408 #define CPU_L3_ADDR_PE 26 /* Panther L3$ address parity error */ 409 410 /* 411 * Sets trap table entry ttentry by overwriting eight instructions from ttlabel 412 */ 413 #define CH_SET_TRAP(ttentry, ttlabel) \ 414 bcopy((const void *)&ttlabel, &ttentry, 32); \ 415 flush_instr_mem((caddr_t)&ttentry, 32); 416 417 /* 418 * Return values for implementation specific error logging in the routine 419 * cpu_impl_async_log_err() 420 */ 421 #define CH_ASYNC_LOG_DONE 0 /* finished logging the error */ 422 #define CH_ASYNC_LOG_CONTINUE 1 /* continue onto handle panicker */ 423 #define CH_ASYNC_LOG_UNKNOWN 2 /* unknown error type */ 424 #define CH_ASYNC_LOG_RECIRC 3 /* suppress logging of error */ 425 426 #ifndef _ASM 427 428 /* 429 * Define Cheetah family (UltraSPARC-III) specific asynchronous error structure 430 */ 431 typedef struct cheetah_async_flt { 432 struct async_flt cmn_asyncflt; /* common - see sun4u/sys/async.h */ 433 ushort_t flt_type; /* types of faults - cpu specific */ 434 uint64_t flt_bit; /* fault bit for this log msg */ 435 uint64_t afsr_ext; /* Panther has an AFSR_EXT register */ 436 uint64_t afsr_errs; /* Store all AFSR error bits together */ 437 uint64_t afar2; /* Serrano has an AFAR2 for FRC/FRU */ 438 ch_diag_data_t flt_diag_data; /* Diagnostic data */ 439 int flt_data_incomplete; /* Diagnostic data is incomplete */ 440 int flt_trapped_ce; /* CEEN fault caught by trap handler */ 441 #if defined(CPU_IMP_L1_CACHE_PARITY) 442 ch_l1_parity_log_t parity_data; /* L1$ Parity error logging info */ 443 #endif /* CPU_IMP_L1_CACHE_PARITY */ 444 pn_tlb_logout_t tlb_diag_data; /* TLB parity error Diagnostic data */ 445 uint32_t flt_fpdata[16]; /* Data from fpras failure */ 446 uint64_t flt_sdw_afar; /* Shadow AFAR */ 447 uint64_t flt_sdw_afsr; /* Shadow AFSR */ 448 uint64_t flt_sdw_afsr_ext; /* Shadow Extended AFSR */ 449 } ch_async_flt_t; 450 451 #define ECC_ALL_TRAPS (ECC_D_TRAP | ECC_I_TRAP | ECC_C_TRAP | ECC_F_TRAP) 452 #define ECC_ORPH_TRAPS (ECC_D_TRAP | ECC_I_TRAP | ECC_C_TRAP) 453 #define ECC_ASYNC_TRAPS (ECC_D_TRAP | ECC_I_TRAP) 454 #define ECC_MECC_TRAPS (ECC_D_TRAP | ECC_C_TRAP | ECC_F_TRAP) 455 456 /* 457 * Error type table struct. 458 */ 459 typedef struct ecc_type_to_info { 460 uint64_t ec_afsr_bit; /* AFSR bit of error */ 461 char *ec_reason; /* Short error description */ 462 uint_t ec_flags; /* Trap type error should be seen at */ 463 int ec_flt_type; /* Used by cpu_async_log_err */ 464 char *ec_desc; /* Long error description */ 465 uint64_t ec_err_payload; /* FM ereport payload information */ 466 char *ec_err_class; /* FM ereport class */ 467 } ecc_type_to_info_t; 468 469 typedef struct bus_config_eclk { 470 uint_t divisor; 471 uint64_t mask; 472 } bus_config_eclk_t; 473 474 #endif /* _ASM */ 475 476 #endif /* _KERNEL */ 477 478 #ifndef _ASM 479 480 #include <sys/cpuvar.h> 481 482 /* 483 * Since all the US3_* files share a bunch of routines between each other 484 * we will put all the "extern" definitions in this header file so that we 485 * don't have to repeat it all in every file. 486 */ 487 488 /* 489 * functions that are defined in the US3 cpu module: 490 * ------------------------------------------------- 491 */ 492 extern uint64_t get_safari_config(void); 493 extern void set_safari_config(uint64_t safari_config); 494 extern void shipit(int, int); 495 extern void cpu_aflt_log(int ce_code, int tagnum, ch_async_flt_t *aflt, 496 uint_t logflags, const char *endstr, const char *fmt, ...); 497 extern uint8_t flt_to_trap_type(struct async_flt *aflt); 498 extern void cpu_log_err(struct async_flt *aflt); 499 extern void cpu_page_retire(ch_async_flt_t *ch_flt); 500 extern int clear_errors(ch_async_flt_t *ch_flt); 501 extern void cpu_init_ecache_scrub_dr(struct cpu *cp); 502 extern void get_cpu_error_state(ch_cpu_errors_t *); 503 extern void set_cpu_error_state(ch_cpu_errors_t *); 504 extern int cpu_flt_in_memory(ch_async_flt_t *ch_flt, uint64_t t_afsr_bit); 505 extern int cpu_queue_events(ch_async_flt_t *ch_flt, char *reason, 506 uint64_t t_afsr, ch_cpu_logout_t *clop); 507 extern void cpu_error_ecache_flush(ch_async_flt_t *); 508 extern void cpu_clearphys(struct async_flt *aflt); 509 extern void cpu_async_log_ic_parity_err(ch_async_flt_t *); 510 extern void cpu_async_log_dc_parity_err(ch_async_flt_t *); 511 extern uint64_t get_ecache_ctrl(void); 512 extern uint64_t get_jbus_config(void); 513 extern void set_jbus_config(uint64_t jbus_config); 514 extern uint64_t get_mcu_ctl_reg1(void); 515 extern void set_mcu_ctl_reg1(uint64_t mcu_ctl); 516 extern void cpu_init_trap(void); 517 extern int cpu_ecache_nway(void); 518 extern void cpu_delayed_logout(size_t, ch_cpu_logout_t *); 519 extern void cpu_payload_add_pcache(struct async_flt *, nvlist_t *); 520 extern void cpu_payload_add_tlb(struct async_flt *, nvlist_t *); 521 extern int cpu_scrub_cpu_setup(cpu_setup_t, int, void *); 522 #if defined(JALAPENO) || defined(SERRANO) 523 extern int afsr_to_jaid_status(uint64_t afsr, uint64_t afsr_bit); 524 #endif /* JALAPENO || SERRANO */ 525 /* 526 * Address of the level 15 interrupt handler preamble, used to log Fast ECC 527 * at TL>0 errors, which will be moved to the trap table address above. 528 */ 529 extern void ch_pil15_interrupt_instr(); 530 #ifdef CHEETAHPLUS_ERRATUM_25 531 extern int mondo_recover(uint16_t, int); 532 #endif /* CHEETAHPLUS_ERRATUM_25 */ 533 /* 534 * Adddresses of the Fast ECC Error trap handler preambles which will be 535 * moved to the appropriate trap table addresses. 536 */ 537 extern void fecc_err_instr(void); 538 extern void fecc_err_tl1_instr(void); 539 extern void fecc_err_tl1_cont_instr(void); 540 541 extern int afsr_to_overw_status(uint64_t afsr, uint64_t afsr_bit, 542 uint64_t *ow_bits); 543 #if defined(CHEETAH_PLUS) 544 extern int afsr_to_pn_esynd_status(uint64_t afsr, uint64_t afsr_bit); 545 #endif /* CHEETAH_PLUS */ 546 extern void flush_ecache(uint64_t physaddr, size_t ecachesize, size_t linesize); 547 extern void flush_dcache(void); 548 extern void flush_icache(void); 549 extern void flush_pcache(void); 550 extern void flush_ipb(void); 551 extern uint64_t get_dcu(void); 552 extern void set_dcu(uint64_t ncc); 553 extern void scrubphys(uint64_t paddr, int ecache_set_size); 554 extern void clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize); 555 extern void stick_adj(int64_t skew); 556 extern void stick_timestamp(int64_t *ts); 557 extern void icache_inval_all(void); 558 extern void dcache_inval_line(int index); 559 extern void ecache_flush_line(uint64_t flushaddr, int ec_size); 560 extern int ecache_get_lineinfo(uint32_t ecache_index, uint64_t *tag, 561 uint64_t *data); 562 #if defined(CPU_IMP_L1_CACHE_PARITY) 563 extern void get_dcache_dtag(uint32_t dcache_idx, uint64_t *data); 564 extern void get_icache_dtag(uint32_t icache_idx, uint64_t *data); 565 extern void get_pcache_dtag(uint32_t pcache_idx, uint64_t *data); 566 extern void correct_dcache_parity(size_t dcache_size, size_t dcache_linesize); 567 #endif /* CPU_IMP_L1_CACHE_PARITY */ 568 extern void cpu_check_block(caddr_t, uint_t); 569 extern uint32_t us3_gen_ecc(uint64_t data_low, uint64_t data_high); 570 extern int cpu_impl_async_log_err(void *, errorq_elem_t *); 571 extern void cpu_fast_ecc_error(struct regs *rp, ulong_t p_clo_flags); 572 extern void cpu_tl1_error(struct regs *rp, int panic); 573 extern void cpu_tl1_err_panic(struct regs *rp, ulong_t flags); 574 extern void cpu_disrupting_error(struct regs *rp, ulong_t p_clo_flags); 575 extern void cpu_deferred_error(struct regs *rp, ulong_t p_clo_flags); 576 #if defined(CPU_IMP_L1_CACHE_PARITY) 577 extern void cpu_parity_error(struct regs *rp, uint_t flags, caddr_t tpc); 578 #endif /* CPU_IMP_L1_CACHE_PARITY */ 579 extern void claimlines(uint64_t startpa, size_t len, int stride); 580 extern void copy_tsb_entry(uintptr_t src, uintptr_t dest); 581 extern void hwblkpagecopy(const void *src, void *dst); 582 #if defined(CHEETAH_PLUS) 583 extern void pn_cpu_log_diag_l2_info(ch_async_flt_t *ch_flt); 584 extern void set_afsr_ext(uint64_t afsr_ext); 585 #endif 586 extern void cpu_tlb_parity_error(struct regs *rp, ulong_t trap_va, 587 ulong_t tlb_info); 588 extern void log_flt_func(struct async_flt *aflt, char *unum); 589 extern uint64_t pn_get_tlb_index(uint64_t va, uint64_t pg_sz); 590 extern int popc64(uint64_t val); 591 592 /* 593 * variables and structures that are defined in the US3 cpu module: 594 * ---------------------------------------------------------------- 595 */ 596 extern bus_config_eclk_t bus_config_eclk[]; 597 extern ecc_type_to_info_t ecc_type_to_info[]; 598 extern uint64_t ch_err_tl1_paddrs[]; 599 extern uchar_t ch_err_tl1_pending[]; 600 #ifdef CHEETAHPLUS_ERRATUM_25 601 /* 602 * Tunable defined in us3_common.c 603 */ 604 extern int cheetah_sendmondo_recover; 605 #endif /* CHEETAHPLUS_ERRATUM_25 */ 606 /* 607 * The following allows for a one time calculation of the number of dcache 608 * lines vs. calculating the number every time through the scrub routine. 609 */ 610 int dcache_nlines; /* max number of D$ lines */ 611 612 extern uint64_t afar_overwrite[]; 613 extern uint64_t esynd_overwrite[]; 614 extern uint64_t msynd_overwrite[]; 615 616 #if defined(JALAPENO) || defined(SERRANO) 617 extern uint64_t jreq_overwrite[]; 618 #if defined(SERRANO) 619 extern uint64_t afar2_overwrite[]; 620 #endif /* SERRANO */ 621 #endif /* JALAPENO || SERRANO */ 622 623 /* 624 * variables and structures that are defined outside the US3 cpu module: 625 * --------------------------------------------------------------------- 626 */ 627 extern uint64_t xc_tick_limit; 628 extern uint64_t xc_tick_jump_limit; 629 extern struct kmem_cache *ch_private_cache; 630 631 #if defined(CPU_IMP_L1_CACHE_PARITY) 632 /* 633 * Addresses of the Dcache and Icache parity error trap table entries. 634 * If L1 cache parity protection is implemented, need to replace Dcache and 635 * Icache parity error handlers. 636 */ 637 extern void *tt0_dperr; 638 extern void *tt1_dperr; 639 extern void *tt1_swtrap1; 640 extern void *tt0_iperr; 641 extern void *tt1_iperr; 642 extern void *tt1_swtrap2; 643 /* 644 * Addresses of the Dcache and Icache parity error trap preambles, which will 645 * be moved to the appropriate trap table addresses. 646 */ 647 extern void dcache_parity_instr(); 648 extern void dcache_parity_tl1_instr(); 649 extern void dcache_parity_tl1_cont_instr(); 650 extern void icache_parity_instr(); 651 extern void icache_parity_tl1_instr(); 652 extern void icache_parity_tl1_cont_instr(); 653 #endif /* CPU_IMP_L1_CACHE_PARITY */ 654 655 /* 656 * Addresses of the Fast ECC error trap table entries. 657 */ 658 extern void *tt0_fecc; 659 extern void *tt1_fecc; 660 extern void *tt1_swtrap0; 661 /* 662 * Address of trap table level 15 interrupt handler in the trap table. 663 */ 664 extern void *tt_pil15; 665 /* 666 * D$ and I$ global parameters. 667 */ 668 extern int dcache_size; 669 extern int dcache_linesize; 670 extern int icache_size; 671 extern int icache_linesize; 672 673 /* 674 * Set of all offline cpus 675 */ 676 extern cpuset_t cpu_offline_set; 677 678 #endif /* _ASM */ 679 680 #ifdef __cplusplus 681 } 682 #endif 683 684 #endif /* _SYS_US3_MODULE_H */ 685