1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_US3_MODULE_H 27 #define _SYS_US3_MODULE_H 28 29 #include <sys/async.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #ifdef _KERNEL 36 37 /* 38 * Macros to access the "cheetah cpu private" data structure. 39 */ 40 #define CPU_PRIVATE_PTR(cp, x) (&(((cheetah_private_t *)CPU_PRIVATE(cp))->x)) 41 #define CPU_PRIVATE_VAL(cp, x) (((cheetah_private_t *)CPU_PRIVATE(cp))->x) 42 43 #define CHP_WORD_TO_OFF(word, off) (((word) * 8) == off) 44 45 #if defined(JALAPENO) || defined(SERRANO) 46 /* JP J_REQ errors */ 47 #define C_AFSR_JREQ_ERRS (C_AFSR_RUE | C_AFSR_BP | C_AFSR_WBP | \ 48 C_AFSR_RCE | C_AFSR_TO | C_AFSR_BERR | C_AFSR_UMS) 49 /* JP AID errors */ 50 #define C_AFSR_AID_ERRS (C_AFSR_CPU | C_AFSR_FRU | C_AFSR_CPC | \ 51 C_AFSR_FRC) 52 53 #if defined(SERRANO) 54 /* SERRANO AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 55 #define C_AFSR_CECC_ERRS (C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_CPC | \ 56 C_AFSR_CPU | C_AFSR_WDC | C_AFSR_WDU | C_AFSR_EDC | \ 57 C_AFSR_CE | C_AFSR_RCE | C_AFSR_WBP | C_AFSR_FRC | \ 58 C_AFSR_FRU | C_AFSR_EDU | C_AFSR_ETI | C_AFSR_ETC) 59 60 #else /* SERRANO */ 61 /* JP AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 62 #define C_AFSR_CECC_ERRS (C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_CPC | \ 63 C_AFSR_CPU | C_AFSR_WDC | C_AFSR_WDU | C_AFSR_EDC | \ 64 C_AFSR_CE | C_AFSR_RCE | C_AFSR_WBP | C_AFSR_FRC | \ 65 C_AFSR_FRU | C_AFSR_EDU) 66 #endif /* SERRANO */ 67 68 #if defined(SERRANO) 69 /* 70 * SERRANO AFSR bits from {Instruction,Data}_access_error traps 71 * (Traps 0xa, 0x32) 72 */ 73 #define C_AFSR_ASYNC_ERRS (C_AFSR_OM | C_AFSR_TO | C_AFSR_BERR | \ 74 C_AFSR_UE | C_AFSR_RUE | C_AFSR_EDU | C_AFSR_BP | \ 75 C_AFSR_ETU | C_AFSR_ETS) 76 #else /* SERRANO */ 77 /* JP AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */ 78 #define C_AFSR_ASYNC_ERRS (C_AFSR_OM | C_AFSR_TO | C_AFSR_BERR | \ 79 C_AFSR_UE | C_AFSR_RUE | C_AFSR_EDU | C_AFSR_BP) 80 #endif /* SERRANO */ 81 82 #if defined(SERRANO) 83 /* SERRANO AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 84 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_ETI | \ 85 C_AFSR_ETC) 86 87 #else /* SERRANO */ 88 /* JP AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 89 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC) 90 #endif /* SERRANO */ 91 92 #if defined(SERRANO) 93 /* SERRANO AFSR bits from Fatal errors (processor asserts ERROR pin) */ 94 #define C_AFSR_FATAL_ERRS (C_AFSR_JETO | C_AFSR_SCE | C_AFSR_JEIC | \ 95 C_AFSR_JEIT | C_AFSR_JEIS | C_AFSR_IERR | \ 96 C_AFSR_ISAP | C_AFSR_EFES | C_AFSR_ETS | C_AFSR_ETU) 97 98 #else /* SERRANO */ 99 /* JP AFSR bits from Fatal errors (processor asserts ERROR pin) */ 100 #define C_AFSR_FATAL_ERRS (C_AFSR_JETO | C_AFSR_SCE | C_AFSR_JEIC | \ 101 C_AFSR_JEIT | C_AFSR_JEIS | C_AFSR_IERR | \ 102 C_AFSR_ISAP | C_AFSR_ETP) 103 #endif /* SERRANO */ 104 105 /* JP AFSR all valid error status bits */ 106 #define C_AFSR_ALL_ERRS (C_AFSR_FATAL_ERRS | C_AFSR_FECC_ERRS | \ 107 C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME) 108 109 #if defined(SERRANO) 110 /* SERRANO AFSR all ME status bits */ 111 #define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_UCU | \ 112 C_AFSR_EDU | C_AFSR_WDU | C_AFSR_CPU | C_AFSR_UCC | \ 113 C_AFSR_BERR | C_AFSR_TO | C_AFSR_ETU | C_AFSR_OM | \ 114 C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_RUE | C_AFSR_BP | \ 115 C_AFSR_WBP | C_AFSR_FRU | C_AFSR_JETO | C_AFSR_SCE | \ 116 C_AFSR_JEIC | C_AFSR_JEIT | C_AFSR_JEIS | \ 117 C_AFSR_ETC | C_AFSR_ETI) 118 119 #else /* SERRANO */ 120 /* JP AFSR all ME status bits */ 121 #define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_UCU | \ 122 C_AFSR_EDU | C_AFSR_WDU | C_AFSR_CPU | C_AFSR_UCC | \ 123 C_AFSR_BERR | C_AFSR_TO | C_AFSR_ETP | C_AFSR_OM | \ 124 C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_RUE | C_AFSR_BP | \ 125 C_AFSR_WBP | C_AFSR_FRU | C_AFSR_JETO | C_AFSR_SCE | \ 126 C_AFSR_JEIC | C_AFSR_JEIT | C_AFSR_JEIS) 127 #endif /* SERRANO */ 128 129 /* JP AFSR bits due to a Memory error */ 130 #define C_AFSR_MEMORY (C_AFSR_UE | C_AFSR_CE | C_AFSR_FRC | C_AFSR_FRU |\ 131 C_AFSR_RCE | C_AFSR_RUE) 132 133 /* JP AFSR bits due to parity errors and have a valid BSYND */ 134 #define C_AFSR_MSYND_ERRS (C_AFSR_IVPE | C_AFSR_BP | C_AFSR_WBP) 135 136 /* JP AFSR bits with a valid ESYND field */ 137 #define C_AFSR_ESYND_ERRS (C_AFSR_UE | C_AFSR_CE | \ 138 C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 139 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \ 140 C_AFSR_FRC | C_AFSR_FRU) 141 142 /* JP AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */ 143 #define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_RUE | C_AFSR_UCU | C_AFSR_EDU | \ 144 C_AFSR_WDU | C_AFSR_CPU | C_AFSR_IVPE | C_AFSR_TO | \ 145 C_AFSR_BERR | C_AFSR_UMS | C_AFSR_OM | C_AFSR_WBP | \ 146 C_AFSR_FRU | C_AFSR_BP) 147 148 #elif defined(CHEETAH_PLUS) 149 150 /* Ch+ AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 151 #define C_AFSR_CECC_ERRS (C_AFSR_CE | C_AFSR_EMC | C_AFSR_EDU | \ 152 C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \ 153 C_AFSR_CPC | C_AFSR_IVU | C_AFSR_IVC | C_AFSR_DUE | \ 154 C_AFSR_THCE | C_AFSR_DBERR | C_AFSR_DTO | C_AFSR_IMU | \ 155 C_AFSR_IMC) 156 157 /* Ch+ AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */ 158 #define C_AFSR_ASYNC_ERRS (C_AFSR_UE | C_AFSR_EMU | C_AFSR_EDU | \ 159 C_AFSR_TO | C_AFSR_BERR) 160 161 /* Ch+ AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 162 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_TSCE) 163 164 /* Ch+ AFSR bits from Fatal errors (processor asserts ERROR pin) */ 165 #define C_AFSR_FATAL_ERRS (C_AFSR_PERR | C_AFSR_IERR | C_AFSR_ISAP | \ 166 C_AFSR_TUE | C_AFSR_TUE_SH | C_AFSR_IMU | C_AFSR_EMU) 167 168 /* Ch+ AFSR all valid error status bits */ 169 #define C_AFSR_ALL_ERRS (C_AFSR_FATAL_ERRS | C_AFSR_FECC_ERRS | \ 170 C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME) 171 172 /* Ch+ AFSR all errors that set ME bit, in both AFSR and AFSR_EXT */ 173 #define C_AFSR_ALL_ME_ERRS (C_AFSR_TUE_SH | C_AFSR_IMU | C_AFSR_DTO | \ 174 C_AFSR_DBERR | C_AFSR_TSCE | C_AFSR_TUE | C_AFSR_DUE | \ 175 C_AFSR_ISAP | C_AFSR_EMU | C_AFSR_IVU | C_AFSR_TO | \ 176 C_AFSR_BERR | C_AFSR_UCC | C_AFSR_UCU | C_AFSR_CPU | \ 177 C_AFSR_WDU | C_AFSR_EDU | C_AFSR_UE | \ 178 C_AFSR_L3_TUE_SH | C_AFSR_L3_TUE | C_AFSR_L3_EDU | \ 179 C_AFSR_L3_UCC | C_AFSR_L3_UCU | C_AFSR_L3_CPU | \ 180 C_AFSR_L3_WDU) 181 182 /* Ch+ AFSR bits due to an Ecache data error */ 183 #define C_AFSR_EC_DATA_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | \ 184 C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \ 185 C_AFSR_CPC) 186 187 /* Ch+ AFSR bits due to a Memory error */ 188 #define C_AFSR_MEMORY (C_AFSR_UE | C_AFSR_CE | C_AFSR_EMU | C_AFSR_EMC | \ 189 C_AFSR_DUE) 190 191 /* Ch+ AFSR bits due to an Mtag error and have a valid MSYND */ 192 #define C_AFSR_MSYND_ERRS (C_AFSR_EMU | C_AFSR_EMC | C_AFSR_IMU | \ 193 C_AFSR_IMC) 194 195 /* Ch+ AFSR bits with a valid ESYND field */ 196 #define C_AFSR_ESYND_ERRS (C_AFSR_UE | C_AFSR_CE | \ 197 C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 198 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \ 199 C_AFSR_IVU | C_AFSR_IVC | C_AFSR_DUE) 200 201 /* Ch+ AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */ 202 #define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_UCU | C_AFSR_EMU | C_AFSR_EDU | \ 203 C_AFSR_WDU | C_AFSR_CPU | C_AFSR_IVU | C_AFSR_TO | \ 204 C_AFSR_BERR | C_AFSR_DUE | C_AFSR_TUE | C_AFSR_DTO | \ 205 C_AFSR_DBERR | C_AFSR_TUE_SH | C_AFSR_IMU) 206 207 #else /* CHEETAH_PLUS */ 208 209 /* AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 210 #define C_AFSR_CECC_ERRS (C_AFSR_CE | C_AFSR_EMC | C_AFSR_EDU | \ 211 C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \ 212 C_AFSR_CPC | C_AFSR_IVU | C_AFSR_IVC) 213 214 /* AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */ 215 #define C_AFSR_ASYNC_ERRS (C_AFSR_UE | C_AFSR_EMU | C_AFSR_EDU | \ 216 C_AFSR_TO | C_AFSR_BERR) 217 218 /* AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 219 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC) 220 221 /* AFSR bits from Fatal errors (processor asserts ERROR pin) */ 222 #define C_AFSR_FATAL_ERRS (C_AFSR_PERR | C_AFSR_IERR | C_AFSR_ISAP | \ 223 C_AFSR_EMU) 224 225 /* AFSR all valid error status bits */ 226 #define C_AFSR_ALL_ERRS (C_AFSR_FATAL_ERRS | C_AFSR_FECC_ERRS | \ 227 C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME) 228 229 /* AFSR all ME status bits */ 230 #define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_IVU | \ 231 C_AFSR_EMU | C_AFSR_UCU | C_AFSR_EDU | C_AFSR_WDU | \ 232 C_AFSR_CPU | C_AFSR_UCC | C_AFSR_BERR | C_AFSR_TO) 233 234 /* AFSR bits due to an Ecache error */ 235 #define C_AFSR_EC_DATA_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | \ 236 C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \ 237 C_AFSR_CPC) 238 239 /* AFSR bits due to a Memory error */ 240 #define C_AFSR_MEMORY (C_AFSR_UE | C_AFSR_CE | C_AFSR_EMU | C_AFSR_EMC) 241 242 /* AFSR bits due to an Mtag error and have a valid MSYND */ 243 #define C_AFSR_MSYND_ERRS (C_AFSR_EMU | C_AFSR_EMC) 244 245 /* AFSR bits with a valid ESYND field */ 246 #define C_AFSR_ESYND_ERRS (C_AFSR_UE | C_AFSR_CE | \ 247 C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 248 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \ 249 C_AFSR_IVU | C_AFSR_IVC) 250 251 /* AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */ 252 #define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_UCU | C_AFSR_EMU | C_AFSR_EDU | \ 253 C_AFSR_WDU | C_AFSR_CPU | C_AFSR_IVU | C_AFSR_TO | \ 254 C_AFSR_BERR) 255 256 #endif /* CHEETAH_PLUS */ 257 258 #if defined(JALAPENO) || defined(SERRANO) 259 /* AFSR all valid bits (except for ETW) */ 260 #define C_AFSR_MASK (C_AFSR_ALL_ERRS | C_AFSR_PRIV | C_AFSR_B_SYND | \ 261 C_AFSR_E_SYND | C_AFSR_AID | C_AFSR_JREQ) 262 #else /* JALAPENO || SERRANO */ 263 /* AFSR all valid bits */ 264 #define C_AFSR_MASK (C_AFSR_ALL_ERRS | C_AFSR_PRIV | C_AFSR_M_SYND | \ 265 C_AFSR_E_SYND) 266 #endif /* JALAPENO || SERRANO */ 267 268 /* 269 * Panther AFSR_EXT bits from Disrupting (Corrected) ECC error Trap 270 * (Trap 0x63) 271 */ 272 #define C_AFSR_EXT_CECC_ERRS (C_AFSR_L3_EDU | C_AFSR_L3_EDC | \ 273 C_AFSR_L3_WDU | C_AFSR_L3_WDC | C_AFSR_L3_CPU | \ 274 C_AFSR_L3_CPC | C_AFSR_L3_THCE) 275 276 /* 277 * Panther AFSR_EXT bits from {Instruction,Data}_access_error traps 278 * (Traps 0xa, 0x32) 279 */ 280 #define C_AFSR_EXT_ASYNC_ERRS (C_AFSR_L3_EDU) 281 282 /* Panther AFSR_EXT bits from Fast_ECC_error trap (Trap 0x70) */ 283 #define C_AFSR_EXT_FECC_ERRS (C_AFSR_L3_UCU | C_AFSR_L3_UCC) 284 285 /* Panther AFSR_EXT bits from Fatal errors (processor asserts ERROR pin) */ 286 #define C_AFSR_EXT_FATAL_ERRS (C_AFSR_L3_TUE | C_AFSR_L3_TUE_SH | \ 287 C_AFSR_RED_ERR | C_AFSR_EFA_PAR_ERR) 288 289 /* Panther AFSR_EXT all valid error status bits */ 290 #define C_AFSR_EXT_ALL_ERRS (C_AFSR_EXT_FATAL_ERRS | \ 291 C_AFSR_EXT_FECC_ERRS | C_AFSR_EXT_CECC_ERRS | \ 292 C_AFSR_EXT_ASYNC_ERRS | C_AFSR_L3_MECC) 293 294 /* Panther AFSR_EXT bits for errors to report a L3 cache data resource */ 295 #define C_AFSR_EXT_L3_DATA_ERRS (C_AFSR_L3_WDU | C_AFSR_L3_WDC | \ 296 C_AFSR_L3_CPU | C_AFSR_L3_CPC | C_AFSR_L3_UCU | \ 297 C_AFSR_L3_UCC | C_AFSR_L3_EDU | C_AFSR_L3_EDC | \ 298 C_AFSR_L3_MECC) 299 300 /* Panther AFSR_EXT bits with a valid ESYND field */ 301 #define C_AFSR_EXT_ESYND_ERRS (C_AFSR_L3_UCU | C_AFSR_L3_UCC | \ 302 C_AFSR_L3_EDU | C_AFSR_L3_EDC | C_AFSR_L3_WDU | \ 303 C_AFSR_L3_WDC | C_AFSR_L3_CPU | C_AFSR_L3_CPC) 304 305 /* PANTHER AFSR_EXT error bits for AFT Level 1 messages (uncorrected) */ 306 #define C_AFSR_EXT_LEVEL1 (C_AFSR_L3_UCU | C_AFSR_L3_EDU | \ 307 C_AFSR_L3_WDU | C_AFSR_L3_CPU | C_AFSR_L3_TUE | \ 308 C_AFSR_L3_TUE_SH) 309 310 /* 311 * AFSR / AFSR_EXT bits for which we need to panic the system. 312 */ 313 #define C_AFSR_PANIC(errs) (((errs) & (C_AFSR_FATAL_ERRS | \ 314 C_AFSR_EXT_FATAL_ERRS)) != 0) 315 316 /* 317 * For the Fast ECC TL1 handler, we are limited in how many registers 318 * we can use, so we need to store the AFSR_EXT bits within the AFSR 319 * register using some of the AFSR reserved bits. 320 */ 321 #define AFSR_EXT_IN_AFSR_MASK C_AFSR_EXT_ALL_ERRS 322 #define AFSR_EXT_IN_AFSR_SHIFT 20 323 324 /* 325 * Defines for the flag field in the CPU logout structure. See the 326 * definition of ch_cpu_logout_t for further description. 327 */ 328 #define CLO_FLAGS_TT_MASK 0xff000 329 #define CLO_FLAGS_TT_SHIFT 12 330 #define CLO_FLAGS_TL_MASK 0xf00 331 #define CLO_FLAGS_TL_SHIFT 8 332 #define CLO_NESTING_MAX 20 /* Arbitrary maximum value */ 333 334 #define C_M_SYND_SHIFT 16 335 #define GET_M_SYND(afsr) (((afsr) & C_AFSR_M_SYND) >> C_M_SYND_SHIFT) 336 #define GET_E_SYND(afsr) ((afsr) & C_AFSR_E_SYND) 337 338 /* 339 * Bits of Cheetah Asynchronous Fault Address Register 340 */ 341 #define C_AFAR_PA INT64_C(0x000007fffffffff0) /* PA<42:4> physical address */ 342 343 /* 344 * Defines for the different types of dcache_flush 345 * it is stored in dflush_type 346 */ 347 #define FLUSHALL_TYPE 0x0 /* blasts all cache lines */ 348 #define FLUSHMATCH_TYPE 0x1 /* flush entire cache but check each */ 349 /* each line for a match */ 350 #define FLUSHPAGE_TYPE 0x2 /* flush only one page and check */ 351 /* each line for a match */ 352 353 /* 354 * D-Cache Tag Data Register 355 * 356 * +----------+--------+----------+ 357 * | Reserved | DC_Tag | DC_Valid | 358 * +----------+--------+----------+ 359 * 63 31 30 1 0 360 * 361 */ 362 #define ICACHE_FLUSHSZ 0x20 /* one line in i$ */ 363 #define CHEETAH_DC_VBIT_SHIFT 1 364 #define CHEETAH_DC_VBIT_MASK 0x1 365 366 /* 367 * Define for max size of "reason" string in panic flows. Since this is on 368 * the stack, we want to keep it as small as is reasonable. 369 */ 370 #define MAX_REASON_STRING 40 371 372 /* 373 * These error types are specific to Cheetah and are used internally for the 374 * Cheetah fault structure flt_type field. 375 */ 376 #define CPU_TO 1 /* Timeout */ 377 #define CPU_BERR 2 /* Bus Error */ 378 #define CPU_CE 3 /* Correctable Memory Error */ 379 #define CPU_UE 4 /* Uncorrectable Memory Error */ 380 #define CPU_CE_ECACHE 5 /* Correctable Ecache Error */ 381 #define CPU_UE_ECACHE 6 /* Uncorrectable Ecache Error */ 382 #define CPU_EMC 7 /* Correctable Mtag Error */ 383 #define CPU_FATAL 8 /* Fatal Error */ 384 #define CPU_ORPH 9 /* Orphaned UCC/UCU error */ 385 #define CPU_IV 10 /* IVU or IVC */ 386 #define CPU_INV_AFSR 11 /* Invalid AFSR */ 387 #define CPU_UE_ECACHE_RETIRE 12 /* Uncorrectable Ecache, retire page */ 388 #define CPU_IC_PARITY 13 /* Icache parity error trap */ 389 #define CPU_DC_PARITY 14 /* Dcache parity error trap */ 390 #define CPU_DUE 15 /* Disrupting UE */ 391 #define CPU_FPUERR 16 /* FPU Error */ 392 /* 393 * These next six error types (17-22) are only used in Jalapeno code 394 */ 395 #define CPU_RCE 17 /* Correctable remote memory error */ 396 #define CPU_RUE 18 /* Uncorrectable remote memory error */ 397 #define CPU_FRC 19 /* Correctable foreign memory error */ 398 #define CPU_FRU 20 /* Uncorrectable foreign memory error */ 399 #define CPU_BPAR 21 /* Bus parity (BP or WBP) errorrs */ 400 #define CPU_UMS 22 /* Unsupported memory store */ 401 /* 402 * These next four error types (23-26) are only used in Panther code 403 */ 404 #define CPU_PC_PARITY 23 /* Pcache parity error */ 405 #define CPU_ITLB_PARITY 24 /* Panther ITLB parity error */ 406 #define CPU_DTLB_PARITY 25 /* Panther DTLB parity error */ 407 #define CPU_L3_ADDR_PE 26 /* Panther L3$ address parity error */ 408 409 /* 410 * Sets trap table entry ttentry by overwriting eight instructions from ttlabel 411 */ 412 #define CH_SET_TRAP(ttentry, ttlabel) \ 413 bcopy((const void *)&ttlabel, &ttentry, 32); \ 414 flush_instr_mem((caddr_t)&ttentry, 32); 415 416 /* 417 * Return values for implementation specific error logging in the routine 418 * cpu_impl_async_log_err() 419 */ 420 #define CH_ASYNC_LOG_DONE 0 /* finished logging the error */ 421 #define CH_ASYNC_LOG_CONTINUE 1 /* continue onto handle panicker */ 422 #define CH_ASYNC_LOG_UNKNOWN 2 /* unknown error type */ 423 #define CH_ASYNC_LOG_RECIRC 3 /* suppress logging of error */ 424 425 #ifndef _ASM 426 427 /* 428 * Define Cheetah family (UltraSPARC-III) specific asynchronous error structure 429 */ 430 typedef struct cheetah_async_flt { 431 struct async_flt cmn_asyncflt; /* common - see sun4u/sys/async.h */ 432 ushort_t flt_type; /* types of faults - cpu specific */ 433 uint64_t flt_bit; /* fault bit for this log msg */ 434 uint64_t afsr_ext; /* Panther has an AFSR_EXT register */ 435 uint64_t afsr_errs; /* Store all AFSR error bits together */ 436 uint64_t afar2; /* Serrano has an AFAR2 for FRC/FRU */ 437 ch_diag_data_t flt_diag_data; /* Diagnostic data */ 438 int flt_data_incomplete; /* Diagnostic data is incomplete */ 439 int flt_trapped_ce; /* CEEN fault caught by trap handler */ 440 #if defined(CPU_IMP_L1_CACHE_PARITY) 441 ch_l1_parity_log_t parity_data; /* L1$ Parity error logging info */ 442 #endif /* CPU_IMP_L1_CACHE_PARITY */ 443 pn_tlb_logout_t tlb_diag_data; /* TLB parity error Diagnostic data */ 444 uint32_t flt_fpdata[16]; /* Data from fpras failure */ 445 uint64_t flt_sdw_afar; /* Shadow AFAR */ 446 uint64_t flt_sdw_afsr; /* Shadow AFSR */ 447 uint64_t flt_sdw_afsr_ext; /* Shadow Extended AFSR */ 448 } ch_async_flt_t; 449 450 #define ECC_ALL_TRAPS (ECC_D_TRAP | ECC_I_TRAP | ECC_C_TRAP | ECC_F_TRAP) 451 #define ECC_ORPH_TRAPS (ECC_D_TRAP | ECC_I_TRAP | ECC_C_TRAP) 452 #define ECC_ASYNC_TRAPS (ECC_D_TRAP | ECC_I_TRAP) 453 #define ECC_MECC_TRAPS (ECC_D_TRAP | ECC_C_TRAP | ECC_F_TRAP) 454 455 /* 456 * Error type table struct. 457 */ 458 typedef struct ecc_type_to_info { 459 uint64_t ec_afsr_bit; /* AFSR bit of error */ 460 char *ec_reason; /* Short error description */ 461 uint_t ec_flags; /* Trap type error should be seen at */ 462 int ec_flt_type; /* Used by cpu_async_log_err */ 463 char *ec_desc; /* Long error description */ 464 uint64_t ec_err_payload; /* FM ereport payload information */ 465 char *ec_err_class; /* FM ereport class */ 466 } ecc_type_to_info_t; 467 468 typedef struct bus_config_eclk { 469 uint_t divisor; 470 uint64_t mask; 471 } bus_config_eclk_t; 472 473 #endif /* _ASM */ 474 475 #endif /* _KERNEL */ 476 477 #ifndef _ASM 478 479 #include <sys/cpuvar.h> 480 481 /* 482 * Since all the US3_* files share a bunch of routines between each other 483 * we will put all the "extern" definitions in this header file so that we 484 * don't have to repeat it all in every file. 485 */ 486 487 /* 488 * functions that are defined in the US3 cpu module: 489 * ------------------------------------------------- 490 */ 491 extern uint64_t get_safari_config(void); 492 extern void set_safari_config(uint64_t safari_config); 493 extern void shipit(int, int); 494 extern void cpu_aflt_log(int ce_code, int tagnum, ch_async_flt_t *aflt, 495 uint_t logflags, const char *endstr, const char *fmt, ...); 496 extern uint8_t flt_to_trap_type(struct async_flt *aflt); 497 extern void cpu_log_err(struct async_flt *aflt); 498 extern void cpu_page_retire(ch_async_flt_t *ch_flt); 499 extern int clear_errors(ch_async_flt_t *ch_flt); 500 extern void cpu_init_ecache_scrub_dr(struct cpu *cp); 501 extern void get_cpu_error_state(ch_cpu_errors_t *); 502 extern void set_cpu_error_state(ch_cpu_errors_t *); 503 extern int cpu_flt_in_memory(ch_async_flt_t *ch_flt, uint64_t t_afsr_bit); 504 extern int cpu_queue_events(ch_async_flt_t *ch_flt, char *reason, 505 uint64_t t_afsr, ch_cpu_logout_t *clop); 506 extern void cpu_error_ecache_flush(ch_async_flt_t *); 507 extern void cpu_clearphys(struct async_flt *aflt); 508 extern void cpu_async_log_ic_parity_err(ch_async_flt_t *); 509 extern void cpu_async_log_dc_parity_err(ch_async_flt_t *); 510 extern uint64_t get_ecache_ctrl(void); 511 extern uint64_t get_jbus_config(void); 512 extern void set_jbus_config(uint64_t jbus_config); 513 extern uint64_t get_mcu_ctl_reg1(void); 514 extern void set_mcu_ctl_reg1(uint64_t mcu_ctl); 515 extern void cpu_init_trap(void); 516 extern int cpu_ecache_nway(void); 517 extern void cpu_delayed_logout(size_t, ch_cpu_logout_t *); 518 extern void cpu_payload_add_pcache(struct async_flt *, nvlist_t *); 519 extern void cpu_payload_add_tlb(struct async_flt *, nvlist_t *); 520 extern int cpu_scrub_cpu_setup(cpu_setup_t, int, void *); 521 #if defined(JALAPENO) || defined(SERRANO) 522 extern int afsr_to_jaid_status(uint64_t afsr, uint64_t afsr_bit); 523 #endif /* JALAPENO || SERRANO */ 524 /* 525 * Address of the level 15 interrupt handler preamble, used to log Fast ECC 526 * at TL>0 errors, which will be moved to the trap table address above. 527 */ 528 extern void ch_pil15_interrupt_instr(); 529 #ifdef CHEETAHPLUS_ERRATUM_25 530 extern int mondo_recover(uint16_t, int); 531 #endif /* CHEETAHPLUS_ERRATUM_25 */ 532 /* 533 * Adddresses of the Fast ECC Error trap handler preambles which will be 534 * moved to the appropriate trap table addresses. 535 */ 536 extern void fecc_err_instr(void); 537 extern void fecc_err_tl1_instr(void); 538 extern void fecc_err_tl1_cont_instr(void); 539 540 extern int afsr_to_overw_status(uint64_t afsr, uint64_t afsr_bit, 541 uint64_t *ow_bits); 542 #if defined(CHEETAH_PLUS) 543 extern int afsr_to_pn_esynd_status(uint64_t afsr, uint64_t afsr_bit); 544 #endif /* CHEETAH_PLUS */ 545 extern void flush_ecache(uint64_t physaddr, size_t ecachesize, size_t linesize); 546 extern void flush_dcache(void); 547 extern void flush_icache(void); 548 extern void flush_pcache(void); 549 extern void flush_ipb(void); 550 extern uint64_t get_dcu(void); 551 extern void set_dcu(uint64_t ncc); 552 extern void scrubphys(uint64_t paddr, int ecache_set_size); 553 extern void clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize); 554 extern void stick_adj(int64_t skew); 555 extern void stick_timestamp(int64_t *ts); 556 extern void icache_inval_all(void); 557 extern void dcache_inval_line(int index); 558 extern void ecache_flush_line(uint64_t flushaddr, int ec_size); 559 extern int ecache_get_lineinfo(uint32_t ecache_index, uint64_t *tag, 560 uint64_t *data); 561 #if defined(CPU_IMP_L1_CACHE_PARITY) 562 extern void get_dcache_dtag(uint32_t dcache_idx, uint64_t *data); 563 extern void get_icache_dtag(uint32_t icache_idx, uint64_t *data); 564 extern void get_pcache_dtag(uint32_t pcache_idx, uint64_t *data); 565 extern void correct_dcache_parity(size_t dcache_size, size_t dcache_linesize); 566 #endif /* CPU_IMP_L1_CACHE_PARITY */ 567 extern void cpu_check_block(caddr_t, uint_t); 568 extern uint32_t us3_gen_ecc(uint64_t data_low, uint64_t data_high); 569 extern int cpu_impl_async_log_err(void *, errorq_elem_t *); 570 extern void cpu_fast_ecc_error(struct regs *rp, ulong_t p_clo_flags); 571 extern void cpu_tl1_error(struct regs *rp, int panic); 572 extern void cpu_tl1_err_panic(struct regs *rp, ulong_t flags); 573 extern void cpu_disrupting_error(struct regs *rp, ulong_t p_clo_flags); 574 extern void cpu_deferred_error(struct regs *rp, ulong_t p_clo_flags); 575 #if defined(CPU_IMP_L1_CACHE_PARITY) 576 extern void cpu_parity_error(struct regs *rp, uint_t flags, caddr_t tpc); 577 #endif /* CPU_IMP_L1_CACHE_PARITY */ 578 extern void claimlines(uint64_t startpa, size_t len, int stride); 579 extern void copy_tsb_entry(uintptr_t src, uintptr_t dest); 580 extern void hwblkpagecopy(const void *src, void *dst); 581 #if defined(CHEETAH_PLUS) 582 extern void pn_cpu_log_diag_l2_info(ch_async_flt_t *ch_flt); 583 extern void set_afsr_ext(uint64_t afsr_ext); 584 #endif 585 extern void cpu_tlb_parity_error(struct regs *rp, ulong_t trap_va, 586 ulong_t tlb_info); 587 extern void log_flt_func(struct async_flt *aflt, char *unum); 588 extern uint64_t pn_get_tlb_index(uint64_t va, uint64_t pg_sz); 589 extern int popc64(uint64_t val); 590 591 /* 592 * variables and structures that are defined in the US3 cpu module: 593 * ---------------------------------------------------------------- 594 */ 595 extern bus_config_eclk_t bus_config_eclk[]; 596 extern ecc_type_to_info_t ecc_type_to_info[]; 597 extern uint64_t ch_err_tl1_paddrs[]; 598 extern uchar_t ch_err_tl1_pending[]; 599 #ifdef CHEETAHPLUS_ERRATUM_25 600 /* 601 * Tunable defined in us3_common.c 602 */ 603 extern int cheetah_sendmondo_recover; 604 #endif /* CHEETAHPLUS_ERRATUM_25 */ 605 /* 606 * The following allows for a one time calculation of the number of dcache 607 * lines vs. calculating the number every time through the scrub routine. 608 */ 609 int dcache_nlines; /* max number of D$ lines */ 610 611 extern uint64_t afar_overwrite[]; 612 extern uint64_t esynd_overwrite[]; 613 extern uint64_t msynd_overwrite[]; 614 615 #if defined(JALAPENO) || defined(SERRANO) 616 extern uint64_t jreq_overwrite[]; 617 #if defined(SERRANO) 618 extern uint64_t afar2_overwrite[]; 619 #endif /* SERRANO */ 620 #endif /* JALAPENO || SERRANO */ 621 622 /* 623 * variables and structures that are defined outside the US3 cpu module: 624 * --------------------------------------------------------------------- 625 */ 626 extern uint64_t xc_tick_limit; 627 extern uint64_t xc_tick_jump_limit; 628 extern struct kmem_cache *ch_private_cache; 629 630 #if defined(CPU_IMP_L1_CACHE_PARITY) 631 /* 632 * Addresses of the Dcache and Icache parity error trap table entries. 633 * If L1 cache parity protection is implemented, need to replace Dcache and 634 * Icache parity error handlers. 635 */ 636 extern void *tt0_dperr; 637 extern void *tt1_dperr; 638 extern void *tt1_swtrap1; 639 extern void *tt0_iperr; 640 extern void *tt1_iperr; 641 extern void *tt1_swtrap2; 642 /* 643 * Addresses of the Dcache and Icache parity error trap preambles, which will 644 * be moved to the appropriate trap table addresses. 645 */ 646 extern void dcache_parity_instr(); 647 extern void dcache_parity_tl1_instr(); 648 extern void dcache_parity_tl1_cont_instr(); 649 extern void icache_parity_instr(); 650 extern void icache_parity_tl1_instr(); 651 extern void icache_parity_tl1_cont_instr(); 652 #endif /* CPU_IMP_L1_CACHE_PARITY */ 653 654 /* 655 * Addresses of the Fast ECC error trap table entries. 656 */ 657 extern void *tt0_fecc; 658 extern void *tt1_fecc; 659 extern void *tt1_swtrap0; 660 /* 661 * Address of trap table level 15 interrupt handler in the trap table. 662 */ 663 extern void *pil15_epilogue; 664 /* 665 * D$ and I$ global parameters. 666 */ 667 extern int dcache_size; 668 extern int dcache_linesize; 669 extern int icache_size; 670 extern int icache_linesize; 671 672 /* 673 * Set of all offline cpus 674 */ 675 extern cpuset_t cpu_offline_set; 676 677 #endif /* _ASM */ 678 679 #ifdef __cplusplus 680 } 681 #endif 682 683 #endif /* _SYS_US3_MODULE_H */ 684