1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PLAT_ECC_NUM_H 28 #define _SYS_PLAT_ECC_NUM_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/int_types.h> 37 #include <sys/cheetahregs.h> 38 #include <sys/cpuvar.h> 39 #include <sys/dditypes.h> 40 #include <sys/ddipropdefs.h> 41 #include <sys/ddi_impldefs.h> 42 #include <sys/sunddi.h> 43 #include <sys/platform_module.h> 44 #include <sys/errno.h> 45 #include <sys/conf.h> 46 #include <sys/cmn_err.h> 47 #include <sys/sysmacros.h> 48 49 /* 50 * This file contains the common definitions used by the platform 51 * unum ecc logging. 52 */ 53 54 typedef enum { 55 PLAT_ECC_ERROR_MESSAGE, 56 PLAT_ECC_INDICTMENT_MESSAGE, 57 PLAT_ECC_ERROR2_MESSAGE, 58 PLAT_ECC_INDICTMENT2_MESSAGE, 59 PLAT_ECC_CAPABILITY_MESSAGE, 60 PLAT_ECC_DIMM_SID_MESSAGE 61 } plat_ecc_message_type_t; 62 63 /* Platform-specific function for sending mailbox message */ 64 extern int plat_send_ecc_mailbox_msg(plat_ecc_message_type_t, void *); 65 66 /* For figuring out unique CPU id */ 67 extern int plat_make_fru_cpuid(int, int, int); 68 69 /* For figuring out board number for given CPU id */ 70 extern int plat_make_fru_boardnum(int); 71 72 /* For initializing the taskqs */ 73 extern void plat_ecc_init(void); 74 75 /* For setting the capability value */ 76 extern void plat_ecc_capability_sc_set(uint32_t cap); 77 78 /* For sending a capability message to the SC */ 79 extern int plat_ecc_capability_send(void); 80 81 /* For determining the maximum cpumem boards possible */ 82 extern int plat_max_cpumem_boards(void); 83 84 /* For parsing the values from a memory unum */ 85 extern int parse_unum_memory(char *, int *, int *, int *, int *, int *); 86 87 /* 88 * The following variables enable and disable the fruid message logging on SC. 89 * ecc_log_fruid_enable can be set in /etc/system or via mdb. A value 90 * of 1 is default, and indicates the messages are sent. A value of 0 91 * indicates that the messages are not sent. 92 */ 93 extern int ecc_log_fruid_enable; 94 95 #define ECC_FRUID_ENABLE_DEFAULT 1 96 97 #define PLAT_ECC_JNUMBER_LENGTH 60 98 typedef struct plat_ecc_error_data { 99 uint8_t version; /* Starting with 1 */ 100 uint8_t error_code; /* Error Code */ 101 uint16_t proc_num; /* Processor Number of */ 102 /* CPU in error */ 103 uint8_t bank_no; /* 0 or 1 */ 104 uint8_t ecache_dimm_no; /* 0 to 3 */ 105 uint8_t error_type; /* single, two, three, quad */ 106 /* or multiple bit error status */ 107 uint8_t databit_type; /* Identify the databit type: */ 108 /* MTAG, ECC, MTAGECC or Data */ 109 uint8_t databit_no; /* Failed Databit number */ 110 uint8_t node_no; /* Wildcat node number */ 111 uint16_t detecting_proc; /* Processor detecting the ECC error */ 112 char Jnumber[60]; /* Jnumber of the Dimm or Ecache */ 113 } plat_ecc_error_data_t; 114 115 #define PLAT_ECC_VERSION 3 116 #define PLAT_ERROR_CODE_UNK 0x0 /* Unknown */ 117 #define PLAT_ERROR_CODE_CE 0x1 /* Correctable ECC error */ 118 #define PLAT_ERROR_CODE_UE 0x2 /* Uncorrectable ECC error */ 119 #define PLAT_ERROR_CODE_EDC 0x3 /* Correctable ECC error from E$ */ 120 #define PLAT_ERROR_CODE_EDU 0x4 /* Uncorrectable ECC error from E$ */ 121 #define PLAT_ERROR_CODE_WDC 0x5 /* Correctable E$ write-back ECC */ 122 #define PLAT_ERROR_CODE_WDU 0x6 /* Uncorrectable E$ write-back ECC */ 123 #define PLAT_ERROR_CODE_CPC 0x7 /* Copy-out correctable ECC error */ 124 #define PLAT_ERROR_CODE_CPU 0x8 /* Copy-out uncorrectable ECC error */ 125 #define PLAT_ERROR_CODE_UCC 0x9 /* SW handled correctable ECC */ 126 #define PLAT_ERROR_CODE_UCU 0xa /* SW handled uncorrectable ECC */ 127 #define PLAT_ERROR_CODE_EMC 0xb /* Correctable MTAG ECC error */ 128 #define PLAT_ERROR_CODE_EMU 0xc /* Uncorrectable MTAG ECC error */ 129 130 #define PLAT_ERROR_TYPE_UNK 0x0 /* Unknown */ 131 #define PLAT_ERROR_TYPE_SINGLE 0x1 /* Single bit error */ 132 #define PLAT_ERROR_TYPE_M2 0x2 /* Double bit error */ 133 #define PLAT_ERROR_TYPE_M3 0x3 /* Triple bit error */ 134 #define PLAT_ERROR_TYPE_M4 0x4 /* Quad bit error */ 135 #define PLAT_ERROR_TYPE_M 0x5 /* Multiple bit error */ 136 137 #define PLAT_BIT_TYPE_MULTI 0x0 /* Error is 2 or more bits */ 138 #define PLAT_BIT_TYPE_MTAG_D 0x1 /* MTAG data error */ 139 #define PLAT_BIT_TYPE_MTAG_E 0x2 /* MTAG ECC error */ 140 #define PLAT_BIT_TYPE_ECC 0x3 /* ECC error */ 141 #define PLAT_BIT_TYPE_DATA 0x4 /* Data error */ 142 143 /* 144 * Based on "UltraSPARC-III Programmer's Reference Manual", these values are 145 * obtained when you use the syndrome bits from the AFSR to index into the 146 * ECC syndrome table. See us3_common.c for more details on the definitions 147 * of C0, C1, C2, ... C8, MT0, MT1, ... M3, M4 ... etc. 148 */ 149 150 #define ECC_SYND_DATA_BEGIN 0 151 #define ECC_SYND_DATA_LENGTH 128 /* data bits 0-127 */ 152 #define ECC_SYND_ECC_BEGIN (ECC_SYND_DATA_BEGIN + ECC_SYND_DATA_LENGTH) 153 #define ECC_SYND_ECC_LENGTH 9 /* ECC bits C0 - C* */ 154 #define ECC_SYND_MTAG_BEGIN (ECC_SYND_ECC_BEGIN + ECC_SYND_ECC_LENGTH) 155 #define ECC_SYND_MTAG_LENGTH 3 /* MTAG DATA bits MT0, MT1, MT3 */ 156 #define ECC_SYND_MECC_BEGIN (ECC_SYND_MTAG_BEGIN + ECC_SYND_MTAG_LENGTH) 157 #define ECC_SYND_MECC_LENGTH 4 /* MTAG ECC bits MTC0 - MTC3 */ 158 #define ECC_SYND_M2 144 159 #define ECC_SYND_M3 145 160 #define ECC_SYND_M4 146 161 #define ECC_SYND_M 147 162 163 enum plat_ecc_type {PLAT_ECC_UNKNOWN, PLAT_ECC_MEMORY, PLAT_ECC_ECACHE }; 164 165 typedef struct plat_ecc_msg_hdr { 166 uint8_t emh_major_ver; 167 uint8_t emh_minor_ver; 168 uint16_t emh_msg_type; 169 uint16_t emh_msg_length; 170 uint16_t emh_future0; /* pad */ 171 } plat_ecc_msg_hdr_t; 172 173 extern uint16_t ecc_error2_mailbox_flags; 174 175 #define PLAT_ECC_ERROR2_SEND_L2_XXC 0x0001 176 #define PLAT_ECC_ERROR2_SEND_L2_XXU 0x0002 177 #define PLAT_ECC_ERROR2_SEND_L3_XXC 0x0004 178 #define PLAT_ECC_ERROR2_SEND_L3_XXU 0x0008 179 #define PLAT_ECC_ERROR2_SEND_MEM_ERRS 0x0010 180 #define PLAT_ECC_ERROR2_SEND_BUS_ERRS 0x0020 181 #define PLAT_ECC_ERROR2_SEND_L2_TAG_ERRS 0x0040 182 #define PLAT_ECC_ERROR2_SEND_L3_TAG_ERRS 0x0080 183 #define PLAT_ECC_ERROR2_SEND_L1_PARITY 0x0100 184 #define PLAT_ECC_ERROR2_SEND_TLB_PARITY 0x0200 185 #define PLAT_ECC_ERROR2_SEND_IV_ERRS 0x0400 186 #define PLAT_ECC_ERROR2_SEND_MTAG_XXC 0x0800 187 #define PLAT_ECC_ERROR2_SEND_IV_MTAG_XXC 0x1000 188 #define PLAT_ECC_ERROR2_SEND_PCACHE 0x2000 189 190 /* default value for ecc_error2_mailbox_flags */ 191 #define PLAT_ECC_ERROR2_SEND_DEFAULT 0x3fff 192 193 typedef struct plat_ecc_error2_data { 194 plat_ecc_msg_hdr_t ee2d_header; /* Header info */ 195 uint8_t ee2d_type; /* PLAT_ECC_ERROR2_* */ 196 uint8_t ee2d_afar_status; /* AFLT_STAT_* (see async.h) */ 197 uint8_t ee2d_synd_status; /* AFLT_STAT_* (see async.h) */ 198 uint8_t ee2d_bank_number; /* 0 or 1 */ 199 uint16_t ee2d_detecting_proc; /* Proc that detected error */ 200 uint16_t ee2d_jnumber; /* J# of the part in error */ 201 uint16_t ee2d_owning_proc; /* Proc that controls memory */ 202 uint16_t ee2d_future1; /* pad */ 203 uint32_t ee2d_cpu_impl; /* Proc type */ 204 uint64_t ee2d_afsr; /* AFSR */ 205 uint64_t ee2d_sdw_afsr; /* Shadow AFSR */ 206 uint64_t ee2d_afsr_ext; /* Extended AFSR */ 207 uint64_t ee2d_sdw_afsr_ext; /* Shadow extended AFSR */ 208 uint64_t ee2d_afar; /* AFAR */ 209 uint64_t ee2d_sdw_afar; /* Shadow AFAR */ 210 uint64_t ee2d_timestamp; /* Time stamp */ 211 } plat_ecc_error2_data_t; 212 213 #define ee2d_major_version ee2d_header.emh_major_ver 214 #define ee2d_minor_version ee2d_header.emh_minor_ver 215 #define ee2d_msg_type ee2d_header.emh_msg_type 216 #define ee2d_msg_length ee2d_header.emh_msg_length 217 218 #define PLAT_ECC_ERROR2_VERSION_MAJOR 1 219 #define PLAT_ECC_ERROR2_VERSION_MINOR 1 220 221 /* Values for ee2d_type */ 222 #define PLAT_ECC_ERROR2_NONE 0x00 223 #define PLAT_ECC_ERROR2_L2_CE 0x01 224 #define PLAT_ECC_ERROR2_L2_UE 0x02 225 #define PLAT_ECC_ERROR2_L3_CE 0x03 226 #define PLAT_ECC_ERROR2_L3_UE 0x04 227 #define PLAT_ECC_ERROR2_CE 0x05 228 #define PLAT_ECC_ERROR2_UE 0x06 229 #define PLAT_ECC_ERROR2_DUE 0x07 230 #define PLAT_ECC_ERROR2_TO 0x08 231 #define PLAT_ECC_ERROR2_BERR 0x09 232 #define PLAT_ECC_ERROR2_DTO 0x0a 233 #define PLAT_ECC_ERROR2_DBERR 0x0b 234 #define PLAT_ECC_ERROR2_L2_TSCE 0x0c 235 #define PLAT_ECC_ERROR2_L2_THCE 0x0d 236 #define PLAT_ECC_ERROR2_L3_TSCE 0x0e /* Unused */ 237 #define PLAT_ECC_ERROR2_L3_THCE 0x0f 238 #define PLAT_ECC_ERROR2_DPE 0x10 239 #define PLAT_ECC_ERROR2_IPE 0x11 240 #define PLAT_ECC_ERROR2_ITLB 0x12 241 #define PLAT_ECC_ERROR2_DTLB 0x13 242 #define PLAT_ECC_ERROR2_IVU 0x14 243 #define PLAT_ECC_ERROR2_IVC 0x15 244 #define PLAT_ECC_ERROR2_EMC 0x16 245 #define PLAT_ECC_ERROR2_IMC 0x17 246 #define PLAT_ECC_ERROR2_L3_MECC 0x18 247 #define PLAT_ECC_ERROR2_PCACHE 0x19 248 249 #define PLAT_ECC_ERROR2_NUMVALS 0x1a 250 251 typedef struct plat_ecc_ch_async_flt { 252 int ecaf_synd_status; /* AFLT_STAT_* (see async.h) */ 253 int ecaf_afar_status; /* AFLT_STAT_* (see async.h) */ 254 uint64_t ecaf_sdw_afar; 255 uint64_t ecaf_sdw_afsr; 256 uint64_t ecaf_afsr_ext; 257 uint64_t ecaf_sdw_afsr_ext; 258 } plat_ecc_ch_async_flt_t; 259 260 /* 261 * The following structures/#defines are used to notify the SC 262 * of DIMMs that fail the leaky bucket algorithm, E$ that experience 263 * multiple correctable errors and fail the serd algorithm, and 264 * E$ that experience any non-fatal uncorrectable error. 265 */ 266 267 extern uint8_t ecc_indictment_mailbox_disable; 268 269 /* The message is OK */ 270 #define PLAT_ECC_INDICTMENT_OK 0x00 271 272 /* Send the message, but don't trust it */ 273 #define PLAT_ECC_INDICTMENT_SUSPECT 0x01 274 275 /* Don't send message */ 276 #define PLAT_ECC_INDICTMENT_NO_SEND 0x02 277 278 extern uint8_t ecc_indictment_mailbox_flags; 279 280 /* DIMM indictments for CEs */ 281 #define PLAT_ECC_SEND_DIMM_INDICT 0x01 282 283 /* E$ indictments for UCC, WDC, CPC, EDC */ 284 #define PLAT_ECC_SEND_ECACHE_XXC_INDICT 0x02 285 286 /* E$ indictments for UCU, WDU, CPU, EDU */ 287 #define PLAT_ECC_SEND_ECACHE_XXU_INDICT 0x04 288 289 /* Default value for ecc_indictment_mailbox_flags */ 290 #define PLAT_ECC_SEND_DEFAULT_INDICT (PLAT_ECC_SEND_ECACHE_XXC_INDICT |\ 291 PLAT_ECC_SEND_ECACHE_XXU_INDICT) 292 293 /* 294 * WARNING: The plat_ecc_indictment_data_t struct size can be no bigger than 295 * 128 bytes. The union will fill out the structure to the correct size - 296 * the string space used in solaris_version will fill out the rest of the 297 * structure. 298 * 299 * Any changes made to this structure in the future should ensure that the 300 * structure does not go over 128 bytes. 301 */ 302 303 #define PLAT_ECC_INDICT_SIZE 128 304 305 typedef struct { 306 uint8_t version; /* Starting with 1 */ 307 uint8_t indictment_type; /* see below for values */ 308 uint8_t indictment_uncertain; 309 /* Value of ecc_indictment_mailbox_disable */ 310 uint8_t board_num; /* board number of dimm/E$ */ 311 uint16_t detecting_proc; /* Processor Number of CPU */ 312 /* reporting error */ 313 uint16_t syndrome; /* syndrome of last error */ 314 uint16_t jnumber; /* Jnumber of dimm/E$ */ 315 uint16_t future[7]; /* For future use */ 316 uint64_t afsr; /* AFSR of last error */ 317 uint64_t afar; /* AFAR of last error */ 318 char solaris_version[1]; 319 /* Solaris version string */ 320 } plat_ecc_indict_msg_contents_t; 321 322 typedef union { 323 plat_ecc_indict_msg_contents_t msg_contents; 324 uint8_t filler[PLAT_ECC_INDICT_SIZE]; 325 } plat_ecc_indictment_data_t; 326 327 #define PLAT_ECC_VERSION_LENGTH (PLAT_ECC_INDICT_SIZE - \ 328 offsetof(plat_ecc_indict_msg_contents_t, solaris_version)) 329 330 #define PLAT_ECC_INDICTMENT_VERSION 1 331 332 /* 333 * Values for indictment_type. For Panther, E$ refers to 334 * the L3$. For previous procs, E$ refers to the L2$. 335 */ 336 #define PLAT_ECC_INDICT_NONE 0x00 337 #define PLAT_ECC_INDICT_DIMM 0x01 338 #define PLAT_ECC_INDICT_ECACHE_CORRECTABLES 0x02 339 #define PLAT_ECC_INDICT_ECACHE_UNCORRECTABLE 0x03 340 341 342 /* 343 * These values are used to set the state of msg_status 344 * 345 * 0 - No message in transit 346 * 1 - taskq thread dispatched, dispatching thread waiting for signal 347 * 2 - dispatched thread completed sending message 348 * 3 - dispatching thread received interrupt, not waiting for signal 349 */ 350 #define PLAT_ECC_NO_MSG_ACTIVE 0 351 #define PLAT_ECC_TASK_DISPATCHED 1 352 #define PLAT_ECC_MSG_SENT 2 353 #define PLAT_ECC_INTERRUPT_RECEIVED 3 354 355 /* 356 * Min and max sizes of plat_ecc_taskq 357 */ 358 #define PLAT_ECC_TASKQ_MIN 2 359 #define PLAT_ECC_TASKQ_MAX 8 360 361 extern uint16_t ecc_indictment2_mailbox_flags; 362 363 364 #define PLAT_ECC_SEND_INDICT2_L2_XXU 0x0001 365 #define PLAT_ECC_SEND_INDICT2_L2_XXC_SERD 0x0002 366 #define PLAT_ECC_SEND_INDICT2_L2_TAG_SERD 0x0004 367 #define PLAT_ECC_SEND_INDICT2_L3_XXU 0x0008 368 #define PLAT_ECC_SEND_INDICT2_L3_XXC_SERD 0x0010 369 #define PLAT_ECC_SEND_INDICT2_L3_TAG_SERD 0x0020 370 #define PLAT_ECC_SEND_INDICT2_L1_SERD 0x0040 371 #define PLAT_ECC_SEND_INDICT2_TLB_SERD 0x0080 372 #define PLAT_ECC_SEND_INDICT2_FPU 0x0100 373 #define PLAT_ECC_SEND_INDICT2_PCACHE_SERD 0x0200 374 375 #define PLAT_ECC_SEND_INDICT2_DEFAULT 0x03ff 376 377 typedef struct plat_ecc_indictment2_data { 378 plat_ecc_msg_hdr_t ei2d_header; /* Header info */ 379 uint8_t ei2d_type; /* PLAT_ECC_INDICT2_* */ 380 uint8_t ei2d_uncertain; /* See indictment_uncertain */ 381 uint8_t ei2d_board_num; /* Board number of dimm */ 382 uint8_t ei2d_future1; /* pad */ 383 uint16_t ei2d_arraigned_proc; /* Proc number */ 384 uint16_t ei2d_jnumber; /* Jnumber */ 385 uint32_t ei2d_cpu_impl; /* Proc type */ 386 uint32_t ei2d_future2; /* pad */ 387 uint64_t ei2d_timestamp; /* Time stamp */ 388 } plat_ecc_indictment2_data_t; 389 390 #define ei2d_major_version ei2d_header.emh_major_ver 391 #define ei2d_minor_version ei2d_header.emh_minor_ver 392 #define ei2d_msg_type ei2d_header.emh_msg_type 393 #define ei2d_msg_length ei2d_header.emh_msg_length 394 395 #define PLAT_ECC_INDICT2_MAJOR_VERSION 1 396 #define PLAT_ECC_INDICT2_MINOR_VERSION 1 397 398 /* 399 * Values for ei2d_type 400 */ 401 402 #define PLAT_ECC_INDICT2_NONE 0x00 403 #define PLAT_ECC_INDICT2_L2_UE 0x01 404 #define PLAT_ECC_INDICT2_L2_SERD 0x02 405 #define PLAT_ECC_INDICT2_L2_TAG_SERD 0x03 406 #define PLAT_ECC_INDICT2_L3_UE 0x04 407 #define PLAT_ECC_INDICT2_L3_SERD 0x05 408 #define PLAT_ECC_INDICT2_L3_TAG_SERD 0x06 409 #define PLAT_ECC_INDICT2_DCACHE_SERD 0x07 410 #define PLAT_ECC_INDICT2_ICACHE_SERD 0x08 411 #define PLAT_ECC_INDICT2_ITLB_SERD 0x09 412 #define PLAT_ECC_INDICT2_DTLB_SERD 0x0a 413 #define PLAT_ECC_INDICT2_FPU 0x0b 414 #define PLAT_ECC_INDICT2_PCACHE_SERD 0x0c 415 416 #define PLAT_ECC_INDICT2_NUMVALS 0x0d 417 418 /* 419 * The following structure maps the indictment reason to its 420 * corresponding type. 421 */ 422 typedef struct plat_ecc_bl_map { 423 char *ebm_reason; /* Indictment reason */ 424 int ebm_type; /* Indictment type */ 425 } plat_ecc_bl_map_t; 426 427 /* 428 * This message is used to exchange the capability of the SC and Domain 429 * so that both entities can adjust their behavior as appropriate. 430 * Also the Solaris version is sent from the Domain along with the 431 * capability bitmap. 432 */ 433 typedef struct plat_capability_data { 434 plat_ecc_msg_hdr_t capd_header; /* Header info */ 435 uint32_t capd_capability; /* Capability bitmap */ 436 uint32_t capd_future1; /* pad */ 437 uint64_t capd_future2; /* pad */ 438 char capd_solaris_version[1]; 439 /* Solaris version string ptr */ 440 } plat_capability_data_t; 441 442 #define capd_major_version capd_header.emh_major_ver 443 #define capd_minor_version capd_header.emh_minor_ver 444 #define capd_msg_type capd_header.emh_msg_type 445 #define capd_msg_length capd_header.emh_msg_length 446 447 #define PLAT_ECC_CAP_VERSION_MAJOR 1 448 #define PLAT_ECC_CAP_VERSION_MINOR 1 449 450 #define PLAT_ECC_CAPABILITY_ERROR 0x001 451 #define PLAT_ECC_CAPABILITY_INDICT 0x002 452 #define PLAT_ECC_CAPABILITY_ERROR2 0x004 453 #define PLAT_ECC_CAPABILITY_INDICT2 0x008 454 #define PLAT_ECC_CAPABILITY_FMA 0x010 455 #define PLAT_ECC_CAPABILITY_EREPORTS 0x020 /* unused */ 456 #define PLAT_ECC_CAPABILITY_DIMM_SID 0x040 457 #define PLAT_ECC_CAPABILITY_DP_ERROR 0x080 458 #define PLAT_ECC_CAPABILITY_DP_FAULT 0x100 459 460 #define PLAT_ECC_CAPABILITY_DOMAIN_DEFAULT 0x1df 461 #define PLAT_ECC_CAPABILITY_SC_DEFAULT 0x003 462 463 extern uint32_t plat_ecc_capability_map_domain; 464 extern uint32_t plat_ecc_capability_map_sc; 465 466 /* 467 * The following structure is a wrapper around the all messages. The 468 * extra members are used for communicating between two threads. 469 */ 470 typedef struct plat_ecc_message { 471 plat_ecc_message_type_t ecc_msg_type; 472 uint32_t ecc_msg_status; 473 uint32_t ecc_msg_ret; 474 uint32_t ecc_msg_len; 475 void * ecc_msg_data; 476 } plat_ecc_message_t; 477 478 #ifdef __cplusplus 479 } 480 #endif 481 482 #endif /* _SYS_PLAT_ECC_NUM_H */ 483