1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_MACHINTREG_H 28 #define _SYS_MACHINTREG_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Interrupt Receive Data Registers 38 * ASI_SDB_INTR_R or ASI_INTR_RECEIVE; ASI 0x7F; VA 0x40, 0x50, 0x60 39 */ 40 #define IRDR_0 0x40 41 #define IRDR_1 0x50 42 #define IRDR_2 0x60 43 44 #define UIII_IRDR_0 0x40 45 #define UIII_IRDR_1 0x48 46 #define UIII_IRDR_2 0x50 47 #define UIII_IRDR_3 0x58 48 #define UIII_IRDR_4 0x60 49 #define UIII_IRDR_5 0x68 50 #define UIII_IRDR_6 0x80 51 #define UIII_IRDR_7 0x88 52 53 /* 54 * Interrupt Receive Status Register 55 * ASI_INTR_RECEIVE_STATUS; ASI 0x49; VA 0x0 56 * 57 * |---------------------------------------------------| 58 * | RESERVED (Read as 0) | BUSY | PORTID | 59 * |--------------------------------|------|-----------| 60 * 63 6 5 4 0 61 * 62 */ 63 #define IRSR_BUSY 0x20 /* set when there's a vector received */ 64 #define IRSR_PID_MASK 0x1F /* PORTID bit mask <4:0> */ 65 66 /* 67 * Interrupt Dispatch Data Register 68 * ASI_SDB_INTR_W or ASI_INTR_DISPATCH; ASI 0x77; VA 0x40, 0x50, 0x60 69 */ 70 #define IDDR_0 0x40 71 #define IDDR_1 0x50 72 #define IDDR_2 0x60 73 74 #define UIII_IDDR_0 0x40 75 #define UIII_IDDR_1 0x48 76 #define UIII_IDDR_2 0x50 77 #define UIII_IDDR_3 0x58 78 #define UIII_IDDR_4 0x60 79 #define UIII_IDDR_5 0x68 80 #define UIII_IDDR_6 0x80 81 #define UIII_IDDR_7 0x88 82 83 #if defined(JALAPENO) || defined(SERRANO) 84 /* 85 * Interrupt Dispatch Command Register 86 * ASI_INTR_DISPATCH or ASI_SDB_INTR_W; ASI 0x77; VA = PORTID<<14|0x70 87 * 88 * |------------------------------------------------| 89 * | 0 | PORTID & BUSY/NACK | 0x70 | 90 * |---------|-----------------------|--------------| 91 * 63 19 18 14 13 0 92 */ 93 #define IDCR_OFFSET 0x70 /* IDCR VA<13:0> */ 94 #define IDCR_PID_SHIFT 14 95 #define IDCR_BN_SHIFT 14 /* JBUS only */ 96 #define IDCR_BN_MASK 0x3 /* JBUS only */ 97 #else /* (JALAPENO || SERRANO) */ 98 /* 99 * Interrupt Dispatch Command Register 100 * ASI_INTR_DISPATCH or ASI_SDB_INTR_W; ASI 0x77; VA = PORTID<<14|0x70 101 * 102 * |------------------------------------------------| 103 * | 0 | BUSY/NACK | PORTID | 0x70 | 104 * |---------|-----------|-----------|--------------| 105 * 63 29 28 24 23 14 13 0 106 */ 107 #define IDCR_OFFSET 0x70 /* IDCR VA<13:0> */ 108 #define IDCR_PID_SHIFT 14 109 #define IDCR_BN_SHIFT 24 /* safari only */ 110 #endif /* (JALAPENO || SERRANO) */ 111 112 /* 113 * Interrupt Dispatch Status Register 114 * ASI_INTR_DISPATCH_STATUS; ASI 0x48; VA 0x0 115 * 116 * |---------------------------------------------------| 117 * | RESERVED (Read as 0) | NACK | BUSY | 118 * |-----------------------------------|-------|-------| 119 * 63 2 1 0 | 120 */ 121 #define IDSR_NACK 0x2 /* set if interrupt dispatch failed */ 122 #define IDSR_BUSY 0x1 /* set when there's a dispatch */ 123 124 /* 125 * Safari systems define IDSR as 32 busy/nack pairs 126 */ 127 #if defined(JALAPENO) || defined(SERRANO) 128 #define IDSR_BN_SETS 4 129 #define CPUID_TO_BN_PAIR(x) ((x) & (IDSR_BN_SETS-1)) 130 #else /* (JALAPENO || SERRANO) */ 131 #define IDSR_BN_SETS 32 132 #endif /* (JALAPENO || SERRANO) */ 133 #define IDSR_NACK_BIT(i) ((uint64_t)IDSR_NACK << (2 * (i))) 134 #define IDSR_BUSY_BIT(i) ((uint64_t)IDSR_BUSY << (2 * (i))) 135 #define IDSR_NACK_TO_BUSY(n) ((n) >> 1) 136 #define IDSR_BUSY_TO_NACK(n) ((n) << 1) 137 #define IDSR_NACK_IDX(bit) (((bit) - 1) / 2) 138 #define IDSR_BUSY_IDX(bit) ((bit) / 2) 139 140 /* 141 * Interrupt Number Register 142 * Every interrupt source has a register associated with it 143 * 144 * |---------------------------------------------------| 145 * |INT_EN | PORTID |RESERVED (Read as 0)| INT_NUMBER| 146 * | | | | IGN | INO | 147 * |-------|----------|--------------------|-----|-----| 148 * | 31 30 26 25 11 10 6 5 0 149 */ 150 #define INR_EN_SHIFT 31 151 #define INR_PID_SHIFT 26 152 #define INR_PID_MASK (IRSR_PID_MASK << (INR_PID_SHIFT)) 153 #ifdef _STARFIRE 154 /* 155 * Starfire interrupt group number is 7 bits 156 * Starfire's IGN (inter group #) is not the same as upaid 157 */ 158 #define IGN_SIZE 7 /* Interrupt Group Number bit size */ 159 #define UPAID_TO_IGN(upaid) ((((upaid & 0x3C) >> 1) | (upaid & 0x1)) | \ 160 (((upaid & 0x2) << 4) | \ 161 ((upaid & 0x40) ^ 0x40))) 162 #else 163 /* 164 * IGN_SIZE can be defined in a platform's makefile. If it is not defined, 165 * use a default of 5. 166 */ 167 #ifndef IGN_SIZE 168 #define IGN_SIZE 5 /* Interrupt Group Number bit size */ 169 #endif 170 #define UPAID_TO_IGN(upaid) (upaid) 171 #endif /* _STARFIRE */ 172 173 #define IR_CPU_CLEAR 0x4 /* clear pending register for cpu */ 174 #define IR_MASK_OFFSET 0x4 175 #define IR_SET_ITR 0x10 176 #define IR_SOFT_INT(n) (0x000010000 << (n)) 177 #define IR_SOFT_INT4 IR_SOFT_INT(4) /* r/w - software level 4 interrupt */ 178 #define IR_CPU_SOFTINT 0x8 /* set soft interrupt for cpu */ 179 #define IR_CLEAR_OFFSET 0x8 180 181 182 #ifdef __cplusplus 183 } 184 #endif 185 186 #endif /* _SYS_MACHINTREG_H */ 187