xref: /titanic_52/usr/src/uts/sun4u/sys/jbusppm.h (revision f6e214c7418f43af38bd8c3a557e3d0a1d311cfa)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_SYS_JBUSPPM_H
28 #define	_SYS_JBUSPPM_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 /*
37  * Driver state structure
38  */
39 typedef struct {
40 	dev_info_t		*dip;
41 	ddi_acc_handle_t	devid_hndl;
42 	ddi_acc_handle_t	estar_hndl;
43 	uint64_t		*devid_csr;
44 	uint64_t		*estar_csr;
45 	uint64_t		*j_chng_csr;
46 	int			is_master;
47 	int			lyropen;		/* ref count */
48 } jbppm_unit;
49 
50 /* offset to JBus Change Initiation Control Register */
51 #define	J_CHNG_INITIATION_OFFSET	0x08
52 
53 /* J_ID[1] set indicates master IO bridge */
54 #define	MASTER_IOBRIDGE_BIT		0x040000	/* j_id[1] */
55 
56 /*
57  * JBus Estar Control Register
58  */
59 #define	JBUS_ESTAR_CNTL_32	0x20ULL
60 #define	JBUS_ESTAR_CNTL_2	0x2ULL
61 #define	JBUS_ESTAR_CNTL_1	0x1ULL
62 #define	JBUS_ESTAR_CNTL_MASK (JBUS_ESTAR_CNTL_32 |	\
63     JBUS_ESTAR_CNTL_2 | JBUS_ESTAR_CNTL_1)
64 
65 /*
66  * JBus Change Initiation Control Register
67  */
68 #define	J_CHNG_INITIATION_MASK	0x18ULL		/* Chng_Init[1:0] */
69 #define	J_CHNG_START		0x10ULL
70 #define	J_CHNG_OCCURED		0x18ULL
71 #define	J_CHNG_DELAY_MASK	0x07ULL		/* Chng_Delay[2:0] */
72 
73 #ifdef __cplusplus
74 }
75 #endif
76 
77 #endif /* _SYS_JBUSPPM_H */
78