1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_CHEETAHREGS_H 27 #define _SYS_CHEETAHREGS_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/machasi.h> 32 #include <sys/cpu_impl.h> 33 #ifdef _KERNEL 34 #include <sys/fpras.h> 35 #endif /* _KERNEL */ 36 37 /* 38 * This file is cpu dependent. 39 */ 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /* 46 * Cheetah includes the process info in its mask to make things 47 * more difficult. The process is the low bit of the major mask, 48 * so to convert to the netlist major: 49 * netlist_major = ((mask_major >> 1) + 1) 50 */ 51 #define REMAP_CHEETAH_MASK(x) (((((x) >> 1) + 0x10) & 0xf0) | ((x) & 0xf)) 52 53 #ifdef _ASM 54 /* 55 * assembler doesn't understand the 'ull' suffix for C constants so 56 * use the inttypes.h macros and undefine them here for assembly code 57 */ 58 #undef INT64_C 59 #undef UINT64_C 60 #define INT64_C(x) (x) 61 #define UINT64_C(x) (x) 62 #endif /* _ASM */ 63 64 /* 65 * DCU Control Register 66 * 67 * +------+----+----+----+----+----+-----+-----+----+----+----+ 68 * | Resv | CP | CV | ME | RE | PE | HPE | SPE | SL | WE | PM | 69 * +------+----+----+----+----+----+-----+-----+----+----+----+ 70 * 63:50 49 48 47 46 45 44 43 42 41 40:33 71 * 72 * +----+----+----+----+----+----------+-----+----+----+----+---+ 73 * | VM | PR | PW | VR | VW | Reserved | WIH | DM | IM | DC | IC| 74 * +----+----+----+----+----+----------+-----+----+----+----+---+ 75 * 32:25 24 23 22 21 20:5 4 3 2 1 0 76 */ 77 78 #define ASI_DCU ASI_LSU /* same as spitfire ASI_LSU 0x45 */ 79 #define DCU_IC INT64_C(0x0000000000000001) /* icache enable */ 80 #define DCU_DC INT64_C(0x0000000000000002) /* dcache enable */ 81 #define DCU_IM INT64_C(0x0000000000000004) /* immu enable */ 82 #define DCU_DM INT64_C(0x0000000000000008) /* dmmu enable */ 83 #define DCU_WIH INT64_C(0x0000000000000010) /* Jaguar only - W$ hash index */ 84 #define DCU_VW INT64_C(0x0000000000200000) /* virt watchpoint write enable */ 85 #define DCU_VR INT64_C(0x0000000000400000) /* virt watchpoint read enable */ 86 #define DCU_PW INT64_C(0x0000000000800000) /* phys watchpoint write enable */ 87 #define DCU_PR INT64_C(0x0000000001000000) /* phys watchpoint read enable */ 88 #define DCU_VM INT64_C(0x00000001FE000000) /* virtual watchpoint write mask */ 89 #define DCU_PM INT64_C(0x000001FE00000000) /* phys watchpoint write mask */ 90 #define DCU_WE INT64_C(0x0000020000000000) /* write cache enable */ 91 #define DCU_SL INT64_C(0x0000040000000000) /* second load control */ 92 #define DCU_SPE INT64_C(0x0000080000000000) /* software prefetch enable */ 93 #define DCU_HPE INT64_C(0x0000100000000000) /* hardware prefetch enable */ 94 #define DCU_PE INT64_C(0x0000200000000000) /* prefetch enable */ 95 #define DCU_RE INT64_C(0x0000400000000000) /* RAW bypass enable */ 96 #define DCU_ME INT64_C(0x0000800000000000) /* noncache store merging enable */ 97 #define DCU_CV INT64_C(0x0001000000000000) /* virt cacheability when DM=0 */ 98 #define DCU_CP INT64_C(0x0002000000000000) /* phys cacheable when DM,IM=0 */ 99 #define DCU_CACHE (DCU_IC|DCU_DC|DCU_WE|DCU_SPE|DCU_HPE|DCU_PE) 100 101 /* 102 * bit shifts for the prefetch enable bit 103 */ 104 #define DCU_PE_SHIFT 45 105 106 /* 107 * Safari Configuration Register 108 */ 109 #define ASI_SAFARI_CONFIG ASI_UPA_CONFIG /* Safari Config Reg, 0x4A */ 110 #define SAFARI_CONFIG_ECLK_1 INT64_C(0x0000000000000000) /* 1/1 clock */ 111 #define SAFARI_CONFIG_ECLK_1_DIV 1 /* clock divisor: 1 */ 112 #define SAFARI_CONFIG_ECLK_2 INT64_C(0x0000000040000000) /* 1/2 clock */ 113 #define SAFARI_CONFIG_ECLK_2_DIV 2 /* clock divisor: 2 */ 114 #define SAFARI_CONFIG_ECLK_32 INT64_C(0x0000000080000000) /* 1/32 clock */ 115 #define SAFARI_CONFIG_ECLK_32_DIV 32 /* clock divisor: 32 */ 116 #define SAFARI_CONFIG_ECLK_MASK (SAFARI_CONFIG_ECLK_32 | SAFARI_CONFIG_ECLK_2) 117 118 #if defined(JALAPENO) || defined(SERRANO) 119 /* 120 * JBUS Configuration Register 121 */ 122 #define ASI_JBUS_CONFIG ASI_UPA_CONFIG /* JBUS Config Reg, 0x4A */ 123 #define JBUS_CONFIG_ECLK_1 INT64_C(0x0000000000000000) /* 1/1 clock */ 124 #define JBUS_CONFIG_ECLK_1_DIV 1 /* clock divisor: 1 */ 125 #define JBUS_CONFIG_ECLK_2 INT64_C(0x0000000000002000) /* 1/2 clock */ 126 #define JBUS_CONFIG_ECLK_2_DIV 2 /* clock divisor: 2 */ 127 #define JBUS_CONFIG_ECLK_32 INT64_C(0x0000000000004000) /* 1/32 clock */ 128 #define JBUS_CONFIG_ECLK_32_DIV 32 /* clock divisor: 32 */ 129 #define JBUS_CONFIG_ECLK_MASK (JBUS_CONFIG_ECLK_32 | JBUS_CONFIG_ECLK_2) 130 #define JBUS_CONFIG_ECLK_SHIFT 13 131 132 /* 133 * Jalapeno/Serrano MCU control registers and ASI 134 */ 135 #define ASI_MCU_CTRL 0x72 /* MCU Control Reg ASI */ 136 #define JP_MCU_FSM_MASK INT64_C(0x0000000006000000) /* 26..25 */ 137 #define JP_MCU_FSM_SHIFT 25 138 #endif /* JALAPENO || SERRANO */ 139 140 #if defined(SERRANO) 141 #define ASI_MCU_AFAR2_VA 0x18 /* captures FRC/FRU addr */ 142 #endif /* SERRANO */ 143 144 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 145 /* 146 * Tomatillo Estar control registers (for JP Errataum 85) 147 */ 148 #define JBUS_SLAVE_T_PORT_BIT 48 149 #define TOM_HIGH_PA 0x400 /* Hi 32 bit of Tom reg PA */ 150 #define M_T_ESTAR_CTRL_PA 0x0f410050 /* M T estar PA */ 151 #define S_T_ESTAR_CTRL_PA 0x0e410050 /* S T estar PA */ 152 #define M_T_J_CHNG_INIT_PA 0x0f410058 /* Master T estar PA */ 153 #define TOM_ESTAR_ELCK_MASK 0x23 /* bit 5,1,0 */ 154 #define TOM_FULL_SPEED 0x1 155 #define TOM_HALF_SPEED 0x2 156 #define TOM_SLOW_SPEED 0x20 157 #define TOM_TRIGGER_MASK 0x18 158 #define TOM_TRIGGER 0x10 159 160 #endif /* JALAPENO && JALAPENO_ERRATA_85 */ 161 162 163 /* 164 * Miscellaneous ASI definitions not in machasi.h 165 */ 166 #define ASI_DC_UTAG 0x43 /* Dcache Microtag Fields */ 167 #define ASI_DC_SNP_TAG 0x44 /* Dcache Snoop Tag Fields */ 168 #define ASI_IC_SNP_TAG 0x68 /* Icache Snoop Tag Fields */ 169 #define ASI_IPB_DATA 0x69 /* Instruction Prefetch Buffer Data */ 170 #define ASI_IPB_TAG 0x6A /* Instruction Prefetch Buffer Tag */ 171 #define ASI_MC_DECODE 0x72 /* Memory Address Decoding Registers */ 172 #define ASI_EC_CFG_TIMING 0x73 /* Jaguar shared Ecache Control Reg */ 173 #define ASI_EC_DATA 0x74 /* Ecache Data Staging Registers */ 174 #define ASI_EC_CTRL 0x75 /* Ecache Control Register */ 175 #define ASI_PC_STATUS_DATA 0x30 /* Pcache Status Data Access */ 176 #define ASI_PC_DATA 0x31 /* Pcache Diagnostic Data Register */ 177 #define ASI_PC_TAG 0x32 /* Pcache Virtual Tag/Valid Field */ 178 #define ASI_PC_SNP_TAG 0x33 /* Pcache Snoop Tag Register */ 179 #define ASI_L2_DATA 0x6B /* L2 cache Data Diagnostic Access */ 180 #define ASI_L2_TAG 0x6C /* L2 cache Tag Diagnostic Access */ 181 182 /* 183 * Bits of Cheetah Asynchronous Fault Status Register 184 * 185 * +---+--+----+----+----+----+---+---+---+---+--+---- 186 * |rsv|ME|PRIV|PERR|IERR|ISAP|EMC|EMU|IVC|IVU|TO|BERR 187 * +---+--+----+----+----+----+---+---+---+---+--+---- 188 * 63:54 53 52 51 50 49 48 47 46 45 44 43 189 * +---+---+---+---+---+---+---+---+--+--+---+------+---+-------+ 190 * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|rsv|M_SYND|rsv||E_SYND| 191 * +---+---+---+---+---+---+---+---+--+--+---+------+---+-------+ 192 * 42 41 40 39 38 37 36 35 34 33 32:20 19:16 15:9 8:0 193 * 194 */ 195 #if defined(CHEETAH_PLUS) 196 /* 197 * Bits of Cheetah+ Asynchronous Fault Status Register 198 * 199 * +------------------+---------------------------- 200 * |rsv|TUE_SH|IMC|IMU|DTO|DBERR|THCE|TSCE|TUE|DUE| 201 * +------------------+---------------------------- . . . 202 * 63 62 61 60 59 58 57 56 55 54 203 * 204 * Note that bits 60-62 are only implemented in Panther (reserved 205 * in Cheetah+ and Jaguar. Also, bit 56 is reserved in Panther instead 206 * of TSCE since those errors are HW corrected in Panther. 207 */ 208 #define C_AFSR_TUE_SH INT64_C(0x4000000000000000) /* uncorrectable tag UE */ 209 #define C_AFSR_IMC INT64_C(0x2000000000000000) /* intr vector MTAG ECC */ 210 #define C_AFSR_IMU INT64_C(0x1000000000000000) /* intr vector MTAG ECC */ 211 #define C_AFSR_DTO INT64_C(0x0800000000000000) /* disrupting TO error */ 212 #define C_AFSR_DBERR INT64_C(0x0400000000000000) /* disrupting BERR error */ 213 #define C_AFSR_THCE INT64_C(0x0200000000000000) /* h/w correctable E$ tag err */ 214 #define C_AFSR_TSCE INT64_C(0x0100000000000000) /* s/w correctable E$ tag err */ 215 #define C_AFSR_TUE INT64_C(0x0080000000000000) /* uncorrectable E$ tag error */ 216 #define C_AFSR_DUE INT64_C(0x0040000000000000) /* disrupting UE error */ 217 #endif /* CHEETAH_PLUS */ 218 #define C_AFSR_ME INT64_C(0x0020000000000000) /* errors > 1, same type!=CE */ 219 #define C_AFSR_PRIV INT64_C(0x0010000000000000) /* priv code access error */ 220 #define C_AFSR_PERR INT64_C(0x0008000000000000) /* system interface protocol */ 221 #define C_AFSR_IERR INT64_C(0x0004000000000000) /* internal system interface */ 222 #define C_AFSR_ISAP INT64_C(0x0002000000000000) /* system request parity err */ 223 #define C_AFSR_EMC INT64_C(0x0001000000000000) /* mtag with CE error */ 224 #define C_AFSR_EMU INT64_C(0x0000800000000000) /* mtag with UE error */ 225 #define C_AFSR_IVC INT64_C(0x0000400000000000) /* intr vector with CE error */ 226 #define C_AFSR_IVU INT64_C(0x0000200000000000) /* intr vector with UE error */ 227 #define C_AFSR_TO INT64_C(0x0000100000000000) /* bus timeout from sys bus */ 228 #define C_AFSR_BERR INT64_C(0x0000080000000000) /* bus error from system bus */ 229 #define C_AFSR_UCC INT64_C(0x0000040000000000) /* E$ with software CE error */ 230 #define C_AFSR_UCU INT64_C(0x0000020000000000) /* E$ with software UE error */ 231 #define C_AFSR_CPC INT64_C(0x0000010000000000) /* copyout with CE error */ 232 #define C_AFSR_CPU INT64_C(0x0000008000000000) /* copyout with UE error */ 233 #define C_AFSR_WDC INT64_C(0x0000004000000000) /* writeback ecache CE error */ 234 #define C_AFSR_WDU INT64_C(0x0000002000000000) /* writeback ecache UE error */ 235 #define C_AFSR_EDC INT64_C(0x0000001000000000) /* ecache CE ECC error */ 236 #define C_AFSR_EDU INT64_C(0x0000000800000000) /* ecache UE ECC error */ 237 #define C_AFSR_UE INT64_C(0x0000000400000000) /* uncorrectable ECC error */ 238 #define C_AFSR_CE INT64_C(0x0000000200000000) /* correctable ECC error */ 239 #define C_AFSR_M_SYND INT64_C(0x00000000000f0000) /* mtag ECC syndrome */ 240 #define C_AFSR_E_SYND INT64_C(0x00000000000001ff) /* data ECC syndrome */ 241 242 /* AFSR bits that could result in CPU removal due to E$ error */ 243 #define C_AFSR_L2_SERD_FAIL_UE (C_AFSR_UCU | C_AFSR_CPU | C_AFSR_WDU | \ 244 C_AFSR_EDU) 245 #define C_AFSR_L2_SERD_FAIL_CE (C_AFSR_UCC | C_AFSR_CPC | C_AFSR_WDC | \ 246 C_AFSR_EDC) 247 /* 248 * Bits of the Panther Extended Asynchronous Fault Status Register (AFSR_EXT) 249 * 250 * +-----+-------+-----------+-------+-------+---------+------+------+------+ 251 * | rsv |RED_ERR|EFA_PAR_ERR|L3_MECC|L3_THCE|L3_TUE_SH|L3_TUE|L3_EDC|L3_EDU| 252 * +-----+-------+-----------+-------+-------+---------+------+------+------+ 253 * 63:14 13 12 11 10 9 8 7 6 254 * 255 * +------+------+------+------+------+------+ 256 * |L3_UCC|L3_UCU|L3_CPC|L3_CPU|L3_WDC|L3_WDU| 257 * +------+------+------+------+------+------+ 258 * 5 4 3 2 1 0 259 * 260 * If the L3_MECC bit is set along with any of the L3 cache errors (bits 0-7) 261 * above, it indicates that an address parity error has occured. 262 */ 263 #define C_AFSR_RED_ERR INT64_C(0x0000000000002000) /* redunancy Efuse error */ 264 #define C_AFSR_EFA_PAR_ERR INT64_C(0x0000000000001000) /* Efuse parity error */ 265 #define C_AFSR_L3_MECC INT64_C(0x0000000000000800) /* L3 address parity */ 266 #define C_AFSR_L3_THCE INT64_C(0x0000000000000400) /* tag CE */ 267 #define C_AFSR_L3_TUE_SH INT64_C(0x0000000000000200) /* tag UE from snp/cpy */ 268 #define C_AFSR_L3_TUE INT64_C(0x0000000000000100) /* tag UE */ 269 #define C_AFSR_L3_EDC INT64_C(0x0000000000000080) /* L3 cache CE */ 270 #define C_AFSR_L3_EDU INT64_C(0x0000000000000040) /* L3 cache UE */ 271 #define C_AFSR_L3_UCC INT64_C(0x0000000000000020) /* software recover CE */ 272 #define C_AFSR_L3_UCU INT64_C(0x0000000000000010) /* software recover UE */ 273 #define C_AFSR_L3_CPC INT64_C(0x0000000000000008) /* copyout with CE */ 274 #define C_AFSR_L3_CPU INT64_C(0x0000000000000004) /* copyout with UE */ 275 #define C_AFSR_L3_WDC INT64_C(0x0000000000000002) /* writeback CE */ 276 #define C_AFSR_L3_WDU INT64_C(0x0000000000000001) /* writeback UE */ 277 278 #if defined(JALAPENO) || defined(SERRANO) 279 /* 280 * Bits of Jalapeno Asynchronous Fault Status Register 281 * 282 * +-----+------------------------------------------------------------------ 283 * | rsv |JETO|SCE|JEIC|JEIT|ME|PRIV|JEIS|IERR|ISAP|ETP|OM|UMS|IVPE|TO|BERR| 284 * +-----+------------------------------------------------------------------ 285 * 63:58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 286 * 287 * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+ 288 * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|RUE|RCE|BP|WBP|FRC|FRU| 289 * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+ 290 * 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 291 * 292 * +-----+-----+-----+------+-----------+-------+ 293 * | JREQ| ETW | rsv |B_SYND| rsv | AID | E_SYND| 294 * +-----+-----+-----+------+-----+-----+-------+ 295 * 26:24 23:22 21:20 19:16 15:14 13:9 8:0 296 * 297 */ 298 299 /* 300 * Bits of Serrano Asynchronous Fault Status Register 301 * 302 * +-----+------------------------------------------------------------------ 303 * | rsv |JETO|SCE|JEIC|JEIT|ME|PRIV|JEIS|IERR|ISAP|ETU|OM|UMS|IVPE|TO|BERR| 304 * +-----+------------------------------------------------------------------ 305 * 63:58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 306 * 307 * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+ 308 * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|RUE|RCE|BP|WBP|FRC|FRU| 309 * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+ 310 * 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 311 * 312 * +-----+-----+------+---+------+---+---+-----+-------+ 313 * | JREQ| ETW | EFES |ETS|B_SYND|ETI|ETC| AID | E_SYND| 314 * +-----+-----+------+---+------+---+---+-----+-------+ 315 * 26:24 23:22 21 20 19:16 15 14 13:9 8:0 316 * 317 */ 318 319 #define C_AFSR_JETO INT64_C(0x0200000000000000) /* JBus Timeout */ 320 #define C_AFSR_SCE INT64_C(0x0100000000000000) /* Snoop parity error */ 321 #define C_AFSR_JEIC INT64_C(0x0080000000000000) /* JBus Illegal Cmd */ 322 #define C_AFSR_JEIT INT64_C(0x0040000000000000) /* Illegal ADTYPE */ 323 #define C_AFSR_JEIS INT64_C(0x0008000000000000) /* Illegal Install State */ 324 #if defined(SERRANO) 325 #define C_AFSR_ETU INT64_C(0x0001000000000000) /* L2$ tag CE error */ 326 #elif defined(JALAPENO) 327 #define C_AFSR_ETP INT64_C(0x0001000000000000) /* L2$ tag parity error */ 328 #endif /* JALAPENO */ 329 #define C_AFSR_OM INT64_C(0x0000800000000000) /* out of range mem error */ 330 #define C_AFSR_UMS INT64_C(0x0000400000000000) /* Unsupported store */ 331 #define C_AFSR_IVPE INT64_C(0x0000200000000000) /* intr vector parity err */ 332 #define C_AFSR_RUE INT64_C(0x0000000100000000) /* remote mem UE error */ 333 #define C_AFSR_RCE INT64_C(0x0000000080000000) /* remote mem CE error */ 334 #define C_AFSR_BP INT64_C(0x0000000040000000) /* read data parity err */ 335 #define C_AFSR_WBP INT64_C(0x0000000020000000) /* wb/bs data parity err */ 336 #define C_AFSR_FRC INT64_C(0x0000000010000000) /* foregin mem CE error */ 337 #define C_AFSR_FRU INT64_C(0x0000000008000000) /* foregin mem UE error */ 338 #define C_AFSR_JREQ INT64_C(0x0000000007000000) /* Active JBus req at err */ 339 #define C_AFSR_ETW INT64_C(0x0000000000c00000) /* AID causing UE/CE */ 340 341 #if defined(SERRANO) 342 #define C_AFSR_EFES INT64_C(0x0000000000200000) /* E-fuse error summary */ 343 #define C_AFSR_ETS INT64_C(0x0000000000100000) /* L2$ tag SRAM stuck-at */ 344 #endif /* SERRANO */ 345 346 #define C_AFSR_B_SYND INT64_C(0x00000000000f0000) /* jbus parity syndrome */ 347 348 #if defined(SERRANO) 349 #define C_AFSR_ETI INT64_C(0x0000000000008000) /* L2$ tag intermittent */ 350 #define C_AFSR_ETC INT64_C(0x0000000000004000) /* L2$ tag CE */ 351 #endif /* SERRANO */ 352 353 #define C_AFSR_AID INT64_C(0x0000000000003e00) /* AID causing UE/CE */ 354 355 /* bit shifts for selected errors */ 356 #define C_AFSR_WDU_SHIFT 37 357 #define C_AFSR_UCU_SHIFT 41 358 #define C_AFSR_UCC_SHIFT 42 359 #define C_AFSR_JREQ_SHIFT 24 360 #define C_AFSR_AID_SHIFT 9 361 362 /* 363 * Overloaded AFSR fields. During error processing, some of the reserved 364 * fields within the saved AFSR are overwritten with extra information. 365 */ 366 #define C_AFSR_PANIC_SHIFT 62 367 #define C_AFSR_IPE_SHIFT 59 368 #define C_AFSR_DPE_SHIFT 58 369 370 #else /* JALAPENO || SERRANO */ 371 372 /* bit shifts for selected errors */ 373 #define C_AFSR_WDU_SHIFT 37 374 #define C_AFSR_UCU_SHIFT 41 375 #define C_AFSR_UCC_SHIFT 42 376 #define C_AFSR_L3_UCU_SHIFT 4 377 378 /* 379 * Overloaded AFSR fields. During error processing, some of the reserved fields 380 * within the saved AFSR are overwritten with extra information. 381 */ 382 #define C_AFSR_FIRSTFLT_SHIFT 63 383 #define C_AFSR_PANIC_SHIFT 30 384 #define C_AFSR_DPE_SHIFT 20 385 #define C_AFSR_IPE_SHIFT 21 386 387 #endif /* JALAPENO || SERRANO */ 388 389 #if defined(JALAPENO) || defined(SERRANO) 390 /* 391 * Jalapeno L2 Cache Control Register Bits. 392 * 393 * Bit# Name Description 394 * 63-24 - reserved 395 * 23:20 EC_ACT_WAY (read only) indicates which sets are present 396 * 19:16 EC_BLK_WAY Bit mask indicating which sets are blocked 397 * from replacement 398 * 15:14 EC_SIZE L2 cache size 399 * 13:12 - reserved 400 * 11 EC_PAR_EN Enables parity checking on L2 cache tags 401 * 10 EC_ECC_EN Enables ECC checking on L2 cache data 402 * 9 EC_ECC_FORCE Enables EC_CHECK[8:0] onto L2 cache ECC bits 403 * 8:0 EC_CHECK ECC check vector to force onto ECC bits 404 */ 405 406 #define JP_ECCTRL_ECSIZE_MASK 0xc000 407 #define JP_ECCTRL_ECSIZE_SHIFT 14 408 #define JP_ECCTRL_ECSIZE_MIN 0x80000 409 410 /* 411 * Jalapeno L2 Cache Error Enable Register Bits 412 * 413 * Bit# Name Description 414 * 63-33 - reserved 415 * 32 SCDE Enable detection of JBUS control parity error 416 * 31:24 - reserved 417 * 23 IAEN Enable trap on illegal physical address 418 * 22 IERREN Enable FERR system reset on CPU internal errors 419 * 21 PERREN Enable FERR system reset on JBUS protocol errors 420 * 20 SCEN Enable FERR system reset on JBUS control parity error 421 * 19:11 FMED Forced error on the memory ECC 422 * 10 FME Force error on memory ECC 423 * 9:6 FPD Bits to use when FSP forces JBUS addr/data parity error 424 * 5 FSP Force error on outgoing JBUS addr/data parity 425 * 4 ETPEN Enable FERR system reset on L2 tags parity error 426 * 3 UCEEN Enable trap on SW handled external cache error 427 * 2 ISAPEN Enable FERR system reset on request parity error 428 * 1 NCEEN Enable trap on uncorrectable ECC error and system err 429 * 0 CEEN Enable trap on correctable ECC errors 430 */ 431 432 #define EN_REG_UCEEN INT64_C(0x0000000000000008) /* enable UCC,UCU */ 433 #define EN_REG_ISAPEN INT64_C(0x0000000000000004) /* enable ISAP */ 434 #define EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */ 435 #define EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */ 436 437 #define EN_REG_DISABLE INT64_C(0x0000000000000000) /* no errors enabled */ 438 #define EN_REG_ECC_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN) 439 #define EN_REG_CE_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN) 440 #define EN_REG_ENABLE \ 441 (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN | EN_REG_CEEN) 442 443 #else /* JALAPENO || SERRANO */ 444 #if defined(CHEETAH_PLUS) 445 /* 446 * Cheetah+ External Cache Control Register Bits. 447 */ 448 #define ECCR_ASSOC INT64_C(0x0000000001000000) /* Ecache Assoc. */ 449 #define ECCR_ASSOC_SHIFT 24 450 #endif /* CHEETAH_PLUS */ 451 452 /* 453 * Bits of Cheetah External Cache Error Enable Register 454 * 455 * +-----+-----+-------+-----+-------+-------+--------+-------+------+ 456 * | rsv | FMT | FMECC | FMD | FDECC | UCEEN | ISAPEN | NCEEN | CEEN | 457 * +-----+-----+-------+-----+-------+-------+--------+-------+------+ 458 * 63:19 18 17 14 13 12:4 3 2 1 0 459 * 460 */ 461 #define EN_REG_FMT INT64_C(0x0000000000040000) /* force system mtag ECC */ 462 #define EN_REG_FMECC INT64_C(0x000000000003C000) /* forced mtag ECC vector */ 463 #define EN_REG_FMD INT64_C(0x0000000000002000) /* force system data ECC */ 464 #define EN_REG_FDECC INT64_C(0x0000000000001ff0) /* forced data ECC vector */ 465 #define EN_REG_UCEEN INT64_C(0x0000000000000008) /* enable UCC,UCU */ 466 #define EN_REG_ISAPEN INT64_C(0x0000000000000004) /* enable ISAP */ 467 #define EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */ 468 #define EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */ 469 #define EN_REG_DISABLE INT64_C(0x0000000000000000) /* no errors enabled */ 470 #define EN_REG_ECC_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN) 471 #define EN_REG_CE_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN) 472 #define EN_REG_ENABLE \ 473 (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN | EN_REG_CEEN) 474 #endif /* JALAPENO || SERRANO */ 475 476 /* 477 * bit shifts for selected bits 478 */ 479 #define EN_REG_CEEN_SHIFT 0 480 481 /* Cheetah/Cheetah+ Dcache size */ 482 #define CH_DCACHE_SIZE 0x10000 483 484 /* Cheetah/Cheetah+ Dcache linesize */ 485 #define CH_DCACHE_LSIZE 0x20 486 487 /* Cheetah/Cheetah+/Jaguar Icache size */ 488 #define CH_ICACHE_SIZE 0x8000 489 490 /* Cheetah/Cheetah+/Jaguar Icache linesize */ 491 #define CH_ICACHE_LSIZE 0x20 492 493 /* Panther Icache size */ 494 #define PN_ICACHE_SIZE 0x10000 495 496 /* Panther Icache linesize */ 497 #define PN_ICACHE_LSIZE 0x40 498 499 /* Pcache size for the cheetah family of CPUs */ 500 #define CH_PCACHE_SIZE 0x800 501 502 /* Pcache linesize for the cheetah family of CPUs */ 503 #define CH_PCACHE_LSIZE 0x40 504 505 /* 506 * The cheetah+ CPU module handles Cheetah+, Jaguar, and Panther so 507 * we have to pick max size and min linesize values for the Icache 508 * accordingly. 509 */ 510 #define CHP_ICACHE_MAX_SIZE PN_ICACHE_SIZE 511 #define CHP_ICACHE_MIN_LSIZE CH_ICACHE_LSIZE 512 513 /* 514 * The minimum size needed to ensure consistency on a virtually address 515 * cache. Computed by taking the largest virtually indexed cache and dividing 516 * by its associativity. 517 */ 518 #define CH_VAC_SIZE 0x4000 519 520 /* 521 * The following definitions give the syndromes that will be seen when attempts 522 * are made to read data that has been intentionally poisoned. Intentional 523 * poisoning is performed when an error has been detected, and is designed to 524 * allow software to effectively distinguish between root problems and secondary 525 * effects. The following syndromes and their descriptions are taken from the 526 * UltraSPARC-III Cu Error Manual, Section 5.4.3.1. 527 */ 528 529 /* 530 * For a DSTAT = 2 or 3 event (see Sec 5.3.4.4) from the system bus for a 531 * cacheable load, data bits [1:0] are inverted in the data stored in the 532 * L2-cache. The syndrome seen when one of these signalling words is read will 533 * be 0x11c. 534 */ 535 #define CH_POISON_SYND_FROM_DSTAT23 0x11c 536 537 /* 538 * For an uncorrectable data ECC error from the L2-cache, data bits [127:126] 539 * are inverted in data sent to the system bus as part of a writeback or 540 * copyout. The syndrome seen when one of these signalling words is read will 541 * be 0x071. 542 */ 543 #define CH_POISON_SYND_FROM_XXU_WRITE 0x71 544 545 /* 546 * For uncorrectable data ECC error on the L2-cache read done to complete a 547 * store merge event, where bytes written by the processor are merged with 548 * bytes from an L2-cache line, ECC check bits [1:0] are inverted in the data 549 * scrubbed back to the L2-cache. The syndrome seen when one of these 550 * signalling words is read will be 0x003. 551 */ 552 #define CH_POISON_SYND_FROM_XXU_WRMERGE 0x3 553 554 /* 555 * To help understand the following definitions, this block of comments 556 * provides information on Cheetah's E$. 557 * 558 * Cheetah supports three different E$ sizes (1MB, 4MB, and 8MB). The 559 * number of E$ lines remains constant regardless of the size of the E$ 560 * as does the subblock size, however the number of 64-byte subblocks per 561 * line varies depending on the E$ size. 562 * 563 * An E$ tag (for an E$ line) contains an EC_tag field, corresponding to the 564 * high order physical address bits of that E$ line's contents, and 1 to 8 565 * EC_state fields, indicating the state of each subblock. Due to the E$ line 566 * size variance depending on the total size of the E$, the number of bits in 567 * the EC_tag field varies as does the number of subblocks (and EC_state 568 * fields) per E$ line. 569 * 570 * A 1MB E$ has a line size of 64 bytes, containing 1 subblock per line. 571 * A 4MB E$ has a line size of 256 bytes, containing 4 subblocks per line. 572 * An 8MB E$ has a line size of 512 bytes, containing 8 subblocks per line. 573 * 574 * An E$ tag for a particular E$ line can be read via a diagnostic ASI 575 * as a 64-bit value. 576 * Within the E$ tag 64-bit value, the EC_tag field is interpreted as follows: 577 * - for a 1MB E$, the EC_tag is in bits <43:21> and corresponds 578 * to physical address bits <42:20> (bits <41:19> for Cheetah+) 579 * - for a 4MB E$, the EC_tag is in bits <43:23> and corresponds 580 * to physical address bits <42:22> (bits <41:21> for Cheetah+) 581 * - for an 8MB E$, the EC_tag is in bits <43:24> and corresponds 582 * to physical address bits <42:23> (bits <41:22> for Cheetah+) 583 * Within the E$ tag 64-bit value, the EC_state field(s) is(are) interpreted 584 * as follows: 585 * - for a 1MB E$, EC_state0 is in bits <2:0> 586 * - for a 4MB E$, EC_state0 is in bits <2:0>, EC_state1 is in 587 * bits <5:3>, EC_state2 is in bits <8:6>, EC_state3 is 588 * in bits <11:9> 589 * - for an 8MB E$, EC_state0 is in bits <2:0>, EC_state1 is in 590 * bits <5:3>, EC_state2 is in bits <8:6>, EC_state3 is 591 * in bits <11:9>, EC_state4 is in bits <14:12>, EC_state5 592 * is in bits <17:15>, EC_state6 is in bits <20:18>, 593 * EC_state7 is in bits <23:21> 594 * Note that each EC_state field contains a value representing the state 595 * of its corresponding subblock. 596 * 597 */ 598 /* 599 * Jaguar changes from Cheetah/Cheetah+ Ecache: 600 * 601 * The Jaguar Ecache is similiar to that used for Cheetah/Cheetah+ with a 602 * couple of differences : 603 * - Jaguar Ecache only comes in 4MB and 8MB versions. 604 * - 8MB E$ has 2 64 byte subblocks per line. 605 * - 4MB E$ has 1 64 byte subblock per line. 606 * 607 * An E$ tag for a particular E$ line can be read via a diagnostic ASI 608 * as a 64-bit value. 609 * Within the E$ tag 64-bit value, the EC_tag field is interpreted as follows: 610 * - for a 4MB E$, the EC_tag is in bits <41:21> and corresponds 611 * to physical address bits <41:21> 612 * - for a 8MB E$, the EC_tag is in bits <41:22> and corresponds 613 * to physical address bits <41:22> 614 * 615 * The Jaguar E$ tag also contains LRU field in bit <42> which must be 616 * masked off when the tag value is being compared to a PA. 617 * 618 * Within the E$ tag 64-bit value, the EC_state field(s) is(are) interpreted 619 * as follows: 620 * - for 4MB E$, EC_state0 is in bits <2:0> 621 * - for 8MB E$, EC_state0 is in bits <2:0>, EC_state1 is in bits <5:3>. 622 * Each EC_state field contains a value representing the state of its 623 * corresponding subblock. 624 * 625 * Note that the subblock size and state values are the same for both 626 * Cheetah/Cheetah+ and Jaguar. 627 */ 628 629 /* Ecache sizes */ 630 #define CH_ECACHE_8M_SIZE 0x800000 631 #define CH_ECACHE_4M_SIZE 0x400000 632 #define CH_ECACHE_1M_SIZE 0x100000 633 634 #define PN_L2_SIZE 0x200000 635 #define PN_L2_LINESIZE 64 636 #define PN_L2_ECC_WORDS 2 637 #define PN_L2_NWAYS 4 638 #define PN_L2_SET_SIZE (PN_L2_SIZE / PN_L2_NWAYS) 639 #define PN_L2_MAX_SET (PN_L2_SIZE - PN_L2_SET_SIZE) 640 #define PN_L2_DATA_ECC_SEL 0x200000 /* bit 21 selects ECC */ 641 #define PN_L2_ECC_LO_REG 0x20 /* bit 5 set for L2 tag access */ 642 #define PN_L2_INDEX_MASK 0x7ffc0 /* bits 18:6 */ 643 #define PN_L2_WAY_INCR 0x80000 /* l2-ec-way = <20:19> */ 644 #define PN_L2_WAY_LIM INT64_C(0x200000) 645 #define PN_L2_WAY_SHIFT 19 646 647 #define PN_L3_SIZE 0x2000000 648 #define PN_L3_LINESIZE 64 649 #define PN_L3_NWAYS 4 650 #define PN_L3_SET_SIZE (PN_L3_SIZE / PN_L3_NWAYS) 651 #define PN_L3_MAX_SET (PN_L3_SIZE - PN_L3_SET_SIZE) 652 #define PN_L3_WAY_SHIFT 23 653 #define PN_L3_TAG_RD_MASK 0x7fffc0 /* ec_tag = PA<22:6> */ 654 #define PN_L3_WAY_INCR 0x800000 /* ec_way = <24:23> */ 655 #define PN_L3_WAY_LIM INT64_C(0x2000000) 656 657 /* Pcache Defines */ 658 #define PN_PCACHE_ADDR_MASK 0x1c0 /* PC_addr = <8:6> */ 659 #define PN_PCACHE_WAY_INCR 0x200 /* PC_way = <10:9> */ 660 #define PN_PCACHE_WORD_SHIFT 3 /* PC_dbl_word = <5:3> */ 661 #define PN_PCACHE_NWAYS 4 662 663 /* Cheetah Ecache is direct-mapped, Cheetah+ can be 2-way or direct-mapped */ 664 #define CH_ECACHE_NWAY 1 665 #if defined(CHEETAH_PLUS) 666 #define CHP_ECACHE_NWAY 2 667 #define PN_ECACHE_NWAY 4 668 #endif /* CHEETAH_PLUS */ 669 #if defined(JALAPENO) || defined(SERRANO) 670 #define JP_ECACHE_NWAY 4 671 #define JP_ECACHE_NWAY_SHIFT 2 672 #endif /* JALAPENO || SERRANO */ 673 674 /* Maximum Ecache size */ 675 #define CH_ECACHE_MAX_SIZE CH_ECACHE_8M_SIZE 676 677 /* Minimum Ecache line size */ 678 #define CH_ECACHE_MIN_LSIZE 64 679 680 /* Maximum Ecache line size - 8Mb Ecache has 512 byte linesize */ 681 #define CH_ECACHE_MAX_LSIZE 512 682 683 /* Size of Ecache data staging register size (see Cheetah PRM 10.7.2) */ 684 #define CH_ECACHE_STGREG_SIZE 32 685 #define CH_ECACHE_STGREG_TOTALSIZE 40 /* data regs + ecc */ 686 687 /* The number of staging registers containing data, for ASI_EC_DATA */ 688 #define CH_ECACHE_STGREG_NUM (CH_ECACHE_STGREG_SIZE / sizeof (uint64_t)) 689 690 /* Size of Ecache data subblock which has state field in Ecache tag */ 691 #define CH_ECACHE_SUBBLK_SIZE 64 692 #define CH_ECACHE_SUBBLK_SHIFT 6 693 694 #if defined(JALAPENO) || defined(SERRANO) 695 #define JP_ECACHE_MAX_LSIZE CH_ECACHE_SUBBLK_SIZE 696 #define JP_ECACHE_MAX_SIZE 0x400000 697 #endif /* JALAPENO || SERRANO */ 698 699 /* 700 * Maximum ecache setsize to support page coloring of heterogenous 701 * cheetah+ cpus. Max ecache setsize is calculated to be the max ecache size 702 * divided by the minimum associativity of the max ecache. 703 * 704 * NOTE: CHP_ECACHE_MAX_SIZE and CHP_ECACHE_MIN_NWAY need to be updated with 705 * new cheetah+ cpus. The maximum setsize may not necessarily be associated with 706 * the max ecache size if the cache associativity is large. If so, MAX_SETSIZE 707 * needs to be updated accordingly. 708 */ 709 #if defined(CHEETAH_PLUS) 710 #define CHP_ECACHE_MIN_NWAY 1 /* direct-mapped */ 711 #define CHP_ECACHE_MAX_SIZE CH_ECACHE_MAX_SIZE 712 #define CHP_ECACHE_MAX_SETSIZE (CHP_ECACHE_MAX_SIZE / CHP_ECACHE_MIN_NWAY) 713 #endif /* CHEETAH_PLUS */ 714 715 /* 716 * Bits to shift EC_tag field of E$ tag to form PA 717 * (See Cheetah PRM 10.7.4, Cheetah+ Delta PRM 10.7) 718 */ 719 #if defined(JALAPENO) || defined(SERRANO) 720 #define CH_ECTAG_PA_SHIFT 18 721 #elif defined(CHEETAH_PLUS) 722 #define CH_ECTAG_PA_SHIFT 2 723 #else /* CHEETAH_PLUS */ 724 #define CH_ECTAG_PA_SHIFT 1 725 #endif /* CHEETAH_PLUS */ 726 #define PN_L3TAG_PA_SHIFT 1 727 #define PN_L3TAG_PA_MASK 0xfffff000000 /* tag bits[43:24] */ 728 #define PN_L2TAG_PA_MASK 0x7fffff80000 /* tag bits[42:19] */ 729 730 #if defined(JALAPENO) || defined(SERRANO) 731 /* 732 * Macros for Jalapeno L2 Cache Tag/State/Parity 733 * 734 * +-----------+--------+--------+----------------------+ 735 * | - | EC_par |EC_state| EC_tag = PA[42:18] | 736 * +-----------+--------+--------+----------------------+ 737 * 63:29 28 27:25 24:0 738 */ 739 /* 740 * Constants representing the complete Jalapeno Ecache tag state: 741 */ 742 #define JP_ECSTATE_SIZE 3 /* three bits */ 743 #define JP_ECSTATE_MASK 0x7 /* three bit field */ 744 #define JP_ECSTATE_INV 0x0 /* invalid */ 745 #define JP_ECSTATE_SHR 0x1 /* shared */ 746 #define JP_ECSTATE_RES1 0x2 /* reserved */ 747 #define JP_ECSTATE_EXL 0x3 /* exclusive */ 748 #define JP_ECSTATE_RES2 0x4 /* reserved */ 749 #define JP_ECSTATE_OWN 0x5 /* owner */ 750 #define JP_ECSTATE_MOD 0x7 /* modified */ 751 #define JP_ECSTATE_RES3 0x6 /* reserved */ 752 #define JP_ECTAG_STATE_SHIFT 25 753 754 #define CH_ECSTATE_SIZE JP_ECSTATE_SIZE 755 #define CH_ECSTATE_MASK JP_ECSTATE_MASK 756 #define CH_ECSTATE_INV JP_ECSTATE_INV 757 #define CH_ECSTATE_SHR JP_ECSTATE_SHR 758 #define CH_ECSTATE_EXL JP_ECSTATE_EXL 759 #define CH_ECSTATE_OWN JP_ECSTATE_OWN 760 #define CH_ECSTATE_MOD JP_ECSTATE_MOD 761 #define CH_ECSTATE_RES1 JP_ECSTATE_RES1 762 #define CH_ECSTATE_OWS JP_ECSTATE_RES3 763 #define CH_ECSTATE_RES2 JP_ECSTATE_RES2 764 765 /* Number of subblock states per Ecache line. */ 766 #define CH_ECTAG_NSUBBLKS(totalsize) 1 767 768 /* Mask for Tag state(s) field, 3 bits per subblock state. */ 769 #define CH_ECTAG_STATE_SHIFT(subblk) JP_ECTAG_STATE_SHIFT 770 #define CH_ECTAG_STATE_MASK(totalsize) \ 771 ((uint64_t)(JP_ECSTATE_MASK<<JP_ECTAG_STATE_SHIFT)) 772 773 /* For a line to be invalid, all of its subblock states must be invalid. */ 774 #define CH_ECTAG_LINE_INVALID(totalsize, tag) \ 775 (((tag) & CH_ECTAG_STATE_MASK(totalsize)) == 0) 776 777 /* Build address mask for tag physical address bits. */ 778 #define CH_ECTAG_PA_MASK(setsize) P2ALIGN(C_AFAR_PA, (int)(setsize)) 779 780 /* Get physical address bits from the EC_tag field of an E$ tag */ 781 #define CH_ECTAG_TO_PA(setsize, tag) (((tag) << CH_ECTAG_PA_SHIFT) & \ 782 CH_ECTAG_PA_MASK(setsize)) 783 784 /* Given a physical address, compute index for subblock tag state. */ 785 #define CH_ECTAG_PA_TO_SUBBLK(totalsize, pa) 1 786 787 /* Given a physical address and assoc. tag, get the subblock state. */ 788 #define CH_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag) \ 789 (((tag) >> JP_ECTAG_STATE_SHIFT) & JP_ECSTATE_MASK) 790 791 #else /* JALAPENO || SERRANO */ 792 793 /* 794 * Constants representing the complete Cheetah Ecache tag state: 795 */ 796 #define CH_ECSTATE_SIZE 3 /* three bits per subblock */ 797 #define CH_ECSTATE_MASK 0x7 /* three bit field */ 798 #define CH_ECSTATE_INV 0x0 /* invalid */ 799 #define CH_ECSTATE_SHR 0x1 /* shared */ 800 #define CH_ECSTATE_EXL 0x2 /* exclusive */ 801 #define CH_ECSTATE_OWN 0x3 /* owner */ 802 #define CH_ECSTATE_MOD 0x4 /* modified */ 803 #define CH_ECSTATE_RES1 0x5 /* reserved */ 804 #define CH_ECSTATE_OWS 0x6 /* owner/shared */ 805 #define CH_ECSTATE_RES2 0x7 /* reserved */ 806 807 /* 808 * Macros for Cheetah Ecache tags 809 */ 810 811 /* Number of subblock states per Ecache line. */ 812 #define CH_ECTAG_NSUBBLKS(totalsize) ((totalsize) / CH_ECACHE_1M_SIZE) 813 814 /* Mask for Tag state(s) field, 3 bits per subblock state. */ 815 #define CH_ECTAG_STATE_SHIFT(subblk) (subblk * CH_ECSTATE_SIZE) 816 #define CH_ECTAG_STATE_MASK(totalsize) \ 817 ((uint64_t) \ 818 ((1 << (CH_ECTAG_NSUBBLKS(totalsize) * CH_ECSTATE_SIZE)) - 1)) 819 820 /* For a line to be invalid, all of its subblock states must be invalid. */ 821 #define CH_ECTAG_LINE_INVALID(totalsize, tag) \ 822 (((tag) & CH_ECTAG_STATE_MASK(totalsize)) == 0) 823 824 /* Build address mask for tag physical address bits. */ 825 #define CH_ECTAG_PA_MASK(setsize) P2ALIGN(C_AFAR_PA, (int)(setsize)) 826 827 /* Get physical address bits from the EC_tag field of an E$ tag */ 828 #define CH_ECTAG_TO_PA(setsize, tag) (((tag) >> CH_ECTAG_PA_SHIFT) & \ 829 CH_ECTAG_PA_MASK(setsize)) 830 831 /* Given a physical address, compute index for subblock tag state. */ 832 #define CH_ECTAG_PA_TO_SUBBLK(totalsize, pa) \ 833 (((pa) >> CH_ECACHE_SUBBLK_SHIFT) & (CH_ECTAG_NSUBBLKS(totalsize) - 1)) 834 835 /* Given a physical address and assoc. tag, get the subblock state. */ 836 #define CH_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag) \ 837 (((tag) >> \ 838 (CH_ECTAG_PA_TO_SUBBLK(totalsize, pa) * CH_ECSTATE_SIZE)) & \ 839 CH_ECSTATE_MASK) 840 #endif /* JALAPENO || SERRANO */ 841 842 /* Panther only has one EC_State field in the L3 tag */ 843 #define PN_L3_LINE_INVALID(tag) (((tag) & CH_ECSTATE_MASK) == 0) 844 845 /* Panther only has one State field in the L2 tag */ 846 #define PN_L2_LINE_INVALID(tag) (((tag) & CH_ECSTATE_MASK) == 0) 847 848 /* Get physical address bits from the EC_tag field of an L3$ tag */ 849 #define PN_L3TAG_TO_PA(tag) (((tag) & PN_L3TAG_PA_MASK) >> \ 850 PN_L3TAG_PA_SHIFT) 851 852 /* Get physical address bits from the tag field of an L2$ tag */ 853 #define PN_L2TAG_TO_PA(tag) ((tag) & PN_L2TAG_PA_MASK) 854 855 #if defined(JALAPENO) || defined(SERRANO) 856 /* 857 * Jalapeno L2 Cache ASI_ECACHE_FLUSH: 858 * +-------+-----------------+--------+---+-----+-------------+------+ 859 * | - | Port_ID | - | EC_Way | 1 | - | EC_Tag_Addr | - | 860 * +-------+-----------------+--------+---+-----+-------------+------+ 861 * 63:41 40:36 35:34 33:32 31 30:18 17:6 5:0 862 */ 863 864 #define JP_EC_TO_SET_SIZE_SHIFT 2 865 #define JP_ECACHE_IDX_DISP_FLUSH INT64_C(0x0000000080000000) 866 #define JP_ECFLUSH_PORTID_SHIFT 36 867 #define JP_ECFLUSH_EC_WAY_SHIFT 32 868 #define JP_EC_TAG_DATA_WAY_SHIFT JP_ECFLUSH_EC_WAY_SHIFT 869 #endif /* JALAPENO || SERRANO */ 870 871 /* 872 * Macros for Jaguar Ecache tags 873 */ 874 875 /* Ecache sizes */ 876 #define JG_ECACHE_8M_SIZE 0x800000 877 #define JG_ECACHE_4M_SIZE 0x400000 878 879 /* Jaguar E$ tag LRU mask */ 880 #define JG_LRU_MASK UINT64_C(0x0000040000000000) /* PA<42> LRU bit */ 881 882 /* 883 * Note that Jaguar and Cheetah/Cheetah+ have the same subblock state size 884 * so rather than duplicating existing defn's we can use the Cheetah+ versions 885 * in the Jaguar defn's below. 886 */ 887 /* Number of subblock states per Ecache line. */ 888 #define JG_ECTAG_NSUBBLKS(cachesize) ((cachesize) / JG_ECACHE_4M_SIZE) 889 890 /* Mask for Tag state(s) field, 3 bits per subblock state. */ 891 #define JG_ECTAG_STATE_MASK(totalsize) \ 892 ((uint64_t) \ 893 ((1 << (JG_ECTAG_NSUBBLKS(totalsize) * CH_ECSTATE_SIZE)) - 1)) 894 895 /* For a line to be invalid, all of its subblock states must be invalid. */ 896 #define JG_ECTAG_LINE_INVALID(totalsize, tag) \ 897 (((tag) & JG_ECTAG_STATE_MASK(totalsize)) == 0) 898 899 /* Build address mask for tag physical address bits. */ 900 #define JG_ECTAG_PA_MASK(setsize) P2ALIGN(((~JG_LRU_MASK) & C_AFAR_PA), \ 901 (int)(setsize)) 902 903 /* Get physical address bits from the EC_tag field of an E$ tag */ 904 #define JG_ECTAG_TO_PA(setsize, tag) ((tag & JG_ECTAG_PA_MASK(setsize))) 905 906 /* Given a physical address, compute index for subblock tag state. */ 907 #define JG_ECTAG_PA_TO_SUBBLK(totalsize, pa) \ 908 (((pa) >> CH_ECACHE_SUBBLK_SHIFT) & (JG_ECTAG_NSUBBLKS(totalsize) - 1)) 909 910 /* Given a physical address and assoc. tag, get the subblock state. */ 911 #define JG_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag) \ 912 (((tag) >> \ 913 (JG_ECTAG_PA_TO_SUBBLK(totalsize, pa) * CH_ECSTATE_SIZE)) & \ 914 CH_ECSTATE_MASK) 915 916 917 #if defined(CHEETAH_PLUS) 918 /* 919 * Cheetah+ Tag ECC Bit and Displacement Flush Bit in Ecache Tag Access. 920 * See Cheetah+ Delta PRM 10.7 921 */ 922 #define CHP_ECACHE_IDX_TAG_ECC INT64_C(0x0000000000800000) 923 #define CHP_ECACHE_IDX_DISP_FLUSH INT64_C(0x0000000001000000) 924 #define PN_L2_IDX_DISP_FLUSH INT64_C(0x0000000000800000) 925 #define PN_L3_IDX_DISP_FLUSH INT64_C(0x0000000004000000) 926 #endif /* CHEETAH_PLUS */ 927 928 /* 929 * Macros for Cheetah Dcache diagnostic accesses. 930 */ 931 932 /* 933 * Dcache Index Mask for bits from *AFAR*. Note that Dcache is virtually 934 * indexed, so only bits [12:5] are valid from the AFAR. This 935 * means we have to search through the 4 ways + bit 13 (i.e. we have 936 * to try 8 indexes). 937 */ 938 #define CH_DCACHE_IDX_MASK 0x01fe0 939 #define CH_DCACHE_IDX_INCR 0x02000 940 #define CH_DCACHE_IDX_LIMIT 0x10000 941 #define CH_DCACHE_NWAY 4 942 #define CH_DCACHE_WAY_MASK 0x0c000 943 #define CH_DCACHE_WAY_SHIFT 14 944 #define CH_DCIDX_TO_WAY(idx) (((idx) & CH_DCACHE_WAY_MASK) >> \ 945 CH_DCACHE_WAY_SHIFT) 946 #define CH_DCTAG_PA_MASK INT64_C(0x000007ffffffe000) 947 #define CH_DCTAG_PA_SHIFT 12 948 #define CH_DCTAG_VALID_BIT INT64_C(0x0000000000000001) 949 #define CH_DCTAG_LINE_INVALID(tag) (((tag) & CH_DCTAG_VALID_BIT) == 0) 950 #define CH_DCIDX_TO_ADDR(idx) ((idx) & CH_DCACHE_IDX_MASK) 951 #define CH_DCTAG_TO_PA(tag) (((tag) << CH_DCTAG_PA_SHIFT) & \ 952 CH_DCTAG_PA_MASK) 953 #define CH_DCTAG_MATCH(tag, pa) (!CH_DCTAG_LINE_INVALID(tag) && \ 954 ((pa) & CH_DCTAG_PA_MASK) == CH_DCTAG_TO_PA(tag)) 955 #define CH_DCSNTAG_MASK INT64_C(0x000007ffffffe000) 956 #define CH_DCSNTAG_TO_PA(tag) ((tag << CH_DCTAG_PA_SHIFT) \ 957 & CH_DCSNTAG_MASK) 958 #define CH_DCUTAG_TO_UTAG(tag) ((tag) & 0xff) 959 #define CH_DCUTAG_TO_VA(tag) ((tag & 0xff) << 14) 960 #define CH_DCUTAG_IDX_MASK 0x03fe0 961 #define CH_DC_DATA_REG_SIZE 32 962 #define CH_DC_UTAG_MASK 0xff 963 #if defined(CHEETAH_PLUS) || defined(JALAPENO) || defined(SERRANO) 964 #define CHP_DCTAG_PARMASK INT64_C(0x000000007ffffffe) 965 #define CHP_DCSNTAG_PARMASK INT64_C(0x000000007ffffffe) 966 #define CHP_DCTAG_MASK INT64_C(0x000003ffffffe000) 967 #define CHP_DCSNTAG_MASK INT64_C(0x000003ffffffe000) 968 #define CHP_DCWAY_MASK INT64_C(0x0000000000003fe0) 969 #define CHP_DCUTAG_TO_UTAG(tag) ((tag) & 0xffff) 970 #define CHP_DCPATAG_TO_PA(tag) ((tag << CH_DCTAG_PA_SHIFT) \ 971 & CHP_DCTAG_MASK) 972 #define CHP_DCSNTAG_TO_PA(tag) ((tag << CH_DCTAG_PA_SHIFT) \ 973 & CHP_DCSNTAG_MASK) 974 #define CHP_DC_IDX(dcp) ((dcp->dc_idx & 0x1fc0) >> 5) 975 #define CHP_DCTAG_PARITY(tag) (tag & CHP_DC_TAG) 976 #define CHP_DCSNTAG_PARITY(tag) (tag & CHP_DC_SNTAG) 977 #define CHP_DC_TAG 0x1 978 #define CHP_DC_SNTAG 0x2 979 #define PN_DC_DATA_PARITY_SHIFT 8 980 #define PN_DC_DATA_PARITY_MASK 0xff 981 #define PN_DC_DATA_ALL_PARITY_MASK 0xffffffff 982 #endif /* CHEETAH_PLUS || JALAPENO || SERRANO */ 983 #define PN_DC_DATA_PARITY_BIT_SHIFT 16 984 985 /* 986 * Macros for Cheetah Icache diagnostic accesses. 987 */ 988 989 /* 990 * Icache Index Mask for bits from *AFAR*. Note that the Icache is virtually 991 * indexed for Panther and physically indexed for other CPUs. For Panther, 992 * we obtain an index by looking at bits[12:6] of the AFAR PA and we check 993 * both lines associated with bit 13 = 0 or 1 (total of 8 entries to check). 994 * For non-Panther CPUs we get our index by just looking at bits[12:5] of 995 * the AFAR PA (total of 4 entries to check). The Icache index is also 996 * confusing because we need to shift the virtual address bits left by one 997 * for the index. 998 */ 999 #define CH_ICACHE_IDX_MASK 0x01fe0 1000 #define PN_ICACHE_IDX_MASK 0x03fc0 1001 #define PN_ICACHE_VA_IDX_MASK 0x01fc0 1002 #define CH_ICACHE_IDX_SHIFT 1 1003 #define CH_ICACHE_IDX_INCR 0x04000 1004 #define PN_ICACHE_IDX_INCR 0x08000 1005 #define CH_ICACHE_IDX_LIMIT 0x10000 1006 #define PN_ICACHE_IDX_LIMIT 0x20000 1007 #define CH_ICACHE_NWAY 4 1008 #define CH_ICACHE_WAY_MASK 0x0c000 1009 #define CH_ICACHE_WAY_SHIFT 14 1010 #define PN_ICACHE_WAY_MASK 0x18000 1011 #define PN_ICACHE_WAY_SHIFT 15 1012 #define CH_ICTAG_PA 0x00 1013 #define CH_ICTAG_UTAG 0x08 1014 #define CH_ICTAG_UPPER 0x10 1015 #define CH_ICTAG_LOWER 0x30 1016 #define CH_ICTAG_TMASK 0x3f 1017 #define CH_ICPATAG_MASK INT64_C(0x000007ffffffe000) 1018 #define CH_ICPATAG_LBITS 0xff /* lower 8 bits undefined */ 1019 #define CH_ICPATAG_SHIFT 5 1020 #define CH_ICIDX_TO_WAY(idx) (((idx) & CH_ICACHE_WAY_MASK) >> \ 1021 CH_ICACHE_WAY_SHIFT) 1022 #define PN_ICIDX_TO_WAY(idx) (((idx) & PN_ICACHE_WAY_MASK) >> \ 1023 PN_ICACHE_WAY_SHIFT) 1024 #define CH_ICIDX_TO_ADDR(idx) (((idx) >> CH_ICACHE_IDX_SHIFT) & \ 1025 CH_ICACHE_IDX_MASK) 1026 #define PN_ICIDX_TO_ADDR(idx) (((idx) >> CH_ICACHE_IDX_SHIFT) & \ 1027 PN_ICACHE_IDX_MASK) 1028 #define CH_ICPATAG_TO_PA(tag) (((tag) << CH_ICPATAG_SHIFT) & \ 1029 CH_ICPATAG_MASK) 1030 #define CH_ICPATAG_MATCH(tag, pa) (CH_ICPATAG_TO_PA(tag) == \ 1031 ((pa) & CH_ICPATAG_MASK)) 1032 #define CH_ICUTAG_MASK INT64_C(0x00000000001fe000) 1033 #define CH_ICUTAG_TO_UTAG(tag) (((tag) >> 38) & 0xff) 1034 #define CH_ICUTAG_TO_VA(tag) (((tag) >> 25) & CH_ICUTAG_MASK) 1035 #define CH_ICSNTAG_MASK INT64_C(0x000007ffffffe000) 1036 #define CH_ICSNTAG_TO_PA(tag) (((tag) << 5) & CH_ICSNTAG_MASK) 1037 #define CH_ICLOWER_VALID INT64_C(0x0004000000000000) 1038 #define CH_ICUPPER_VALID INT64_C(0x0004000000000000) 1039 #define CH_ICLOWER_TO_VPRED(lower) (((lower) >> 46) & 0xf) 1040 #define CH_ICUPPER_TO_VPRED(upper) (((upper) >> 46) & 0xf) 1041 #if defined(CHEETAH_PLUS) 1042 #define CH_ICTAG_MATCH(icp, pa) (((icp->ic_lower | icp->ic_upper) & \ 1043 CH_ICLOWER_VALID) && \ 1044 CH_ICPATAG_MATCH(icp->ic_patag, pa)) 1045 #define PN_ICUTAG_TO_VA(tag) ((tag >> 24) & PN_ICUTAG_MASK) 1046 #else /* CHEETAH_PLUS */ 1047 #define CH_ICTAG_MATCH(icp, pa) ((icp->ic_lower & CH_ICLOWER_VALID) &&\ 1048 CH_ICPATAG_MATCH(icp->ic_patag, pa)) 1049 #define PN_ICUTAG_TO_VA(tag) 0 1050 #endif /* CHEETAH_PLUS */ 1051 1052 #define CH_IC_DATA_REG_SIZE 64 1053 #define PN_IC_DATA_REG_SIZE 128 1054 #if defined(CHEETAH_PLUS) || defined(JALAPENO) || defined(SERRANO) 1055 #define CHP_IC_IDX(icp) ((icp->ic_idx & 0x3fc0) >> 6) 1056 #define PN_IC_IDX(icp) ((icp->ic_idx & 0x7f80) >> 7) 1057 #define CHP_ICPATAG_MASK INT64_C(0x000003ffffffe000) 1058 #define CHP_ICSNTAG_MASK INT64_C(0x000003ffffffe000) 1059 #define CHP_ICUTAG_MASK INT64_C(0x00000000001fe000) 1060 #define PN_ICUTAG_MASK INT64_C(0x00000000003fc000) 1061 #define CHP_ICWAY_MASK INT64_C(0x0000000000003fe0) 1062 #define CHP_ICPATAG_TO_PA(tag) ((tag << 5) & CHP_ICPATAG_MASK) 1063 #define CHP_ICSNTAG_TO_PA(tag) ((tag << 5) & CHP_ICSNTAG_MASK) 1064 #define CHP_ICUTAG_TO_VA(tag) ((tag >> 25) & CHP_ICUTAG_MASK) 1065 #define CHP_ICPATAG_PARMASK INT64_C(0x0000003fffffff00) 1066 #define CHP_ICSNTAG_PARMASK INT64_C(0x0000003fffffff00) 1067 1068 /* 1069 * Cheetah+ Icache data parity masks, see Cheetah+ Delta PRM 7.3 1070 * PC-relative instructions have different bits protected by parity. 1071 * Predecode bit 7 is not parity protected and indicates if the instruction 1072 * is PC-relative or not. 1073 */ 1074 #define CH_ICDATA_PRED_ISPCREL INT64_C(0x0000008000000000) 1075 #define CHP_ICDATA_PCREL_PARMASK INT64_C(0x0000039ffffff800) 1076 #define CHP_ICDATA_NPCREL_PARMASK INT64_C(0x000003bfffffffff) 1077 #define PN_ICDATA_PARITY_BIT_MASK INT64_C(0x40000000000) 1078 #define CHP_ICTAG_PARITY(tag) (tag & CHP_IC_TAG) 1079 #define CHP_ICSNTAG_PARITY(tag) (tag & CHP_IC_SNTAG) 1080 #define CHP_IC_TAG 0x1 1081 #define CHP_IC_SNTAG 0x2 1082 #endif /* CHEETAH_PLUS || JALAPENO || SERRANO */ 1083 #if defined(CHEETAH_PLUS) 1084 #define PN_IPB_TAG_ADDR_LINESIZE 0x40 1085 #define PN_IPB_TAG_ADDR_MAX 0x3c0 1086 #endif /* CHEETAH_PLUS */ 1087 1088 /* 1089 * Macros for Pcache diagnostic accesses. 1090 */ 1091 #define CH_PC_WAY_MASK 0x600 1092 #define CH_PC_WAY_SHIFT 9 1093 #define CH_PCIDX_TO_WAY(idx) (((idx) & CH_PC_WAY_MASK) >> \ 1094 CH_PC_WAY_SHIFT) 1095 #define CH_PC_DATA_REG_SIZE 64 1096 #define CH_PCACHE_NWAY 4 1097 #define PN_PC_PARITY_SHIFT 50 1098 #define PN_PC_PARITY_MASK 0xff 1099 #define PN_PC_PARITY_BITS(status) \ 1100 (((status) >> PN_PC_PARITY_SHIFT) & PN_PC_PARITY_MASK) 1101 #define CH_PC_IDX_ADR(pcp) ((pcp->pc_idx & 0x1c0) >> 6) 1102 #define CH_PCTAG_ADDR_SHIFT 6 1103 #define CH_PC_PA_MASK 0x7ffffffffc0 1104 #define CH_PCTAG_TO_VA(tag) ((tag) << CH_PCTAG_ADDR_SHIFT) 1105 #define CH_PCSTAG_TO_PA(tag) (((tag) << CH_PCTAG_ADDR_SHIFT) & \ 1106 CH_PC_PA_MASK) 1107 #define CH_PCTAG_BNK0_VALID_MASK 0x2000000000000000 1108 #define CH_PCTAG_BNK1_VALID_MASK 0x1000000000000000 1109 #define CH_PCTAG_BNK0_INVALID(tag) (((tag) & CH_PCTAG_BNK0_VALID_MASK) == \ 1110 0) 1111 #define CH_PCTAG_BNK1_INVALID(tag) (((tag) & CH_PCTAG_BNK1_VALID_MASK) == \ 1112 0) 1113 1114 /* 1115 * CPU Log Out Structure parameters. 1116 * This structure is filled in by the Error Trap handlers and captures the 1117 * Ecache/Dcache/Icache line(s) associated with the AFAR. 1118 * For Cheetah Phase II, this structure is filled in at the TL=0 code. For 1119 * Cheetah Phase III, this will be filled in at the trap handlers. 1120 */ 1121 1122 /* 1123 * We use this to mark the LOGOUT structure as invalid. Note that 1124 * this cannot be a valid AFAR, as AFAR bits outside of [41:5] should always 1125 * be zero. 1126 */ 1127 #define LOGOUT_INVALID_U32 0xecc1ecc1 1128 #define LOGOUT_INVALID_L32 0xecc1ecc1 1129 #define LOGOUT_INVALID UINT64_C(0xecc1ecc1ecc1ecc1) 1130 1131 /* 1132 * Max number of TLs to support for Fast ECC or Cache Parity Errors 1133 * at TL>0. Traps are OK from TL=1-2, at TL>=3, we will Red Mode. 1134 */ 1135 #define CH_ERR_TL1_TLMAX 2 1136 1137 /* 1138 * Software traps used by TL>0 handlers. 1139 */ 1140 #define SWTRAP_0 0 /* Used by Fast ECC */ 1141 #define SWTRAP_1 1 /* Used by Dcache Parity */ 1142 #define SWTRAP_2 2 /* Used by Icache Parity */ 1143 1144 /* 1145 * Bit mask defines for various Cheetah Error conditions. 1146 */ 1147 #define CH_ERR_FECC 0x01 /* Data/Event is Fast ECC */ 1148 #define CH_ERR_IPE 0x02 /* Data/Event is Icache Parity Error */ 1149 #define CH_ERR_DPE 0x04 /* Data/Event is Dcache Parity Error */ 1150 #define CH_ERR_PANIC 0x08 /* Fatal error in TL>0 handler */ 1151 #define CH_ERR_TL 0x10 /* Error occured at TL>0 */ 1152 #define CH_ERR_ME_SHIFT 8 /* If multiple errors, shift left newest */ 1153 #define CH_ERR_ME_FLAGS(x) ((x) >> CH_ERR_ME_SHIFT) 1154 1155 /* 1156 * Defines for Bit8 (CH_ERR_TSTATE_IC_ON) and Bit9 (CH_ERR_TSTATE_DC_ON) 1157 * in %tstate, which is used to remember D$/I$ state on Fast ECC handler 1158 * at TL>0. Note that DCU_IC=0x1, DCU_DC=0x2. 1159 */ 1160 #define CH_ERR_G2_TO_TSTATE_SHFT 10 1161 #define CH_ERR_DCU_TO_TSTATE_SHFT 8 1162 #define CH_ERR_TSTATE_IC_ON (DCU_IC << CH_ERR_DCU_TO_TSTATE_SHFT) 1163 #define CH_ERR_TSTATE_DC_ON (DCU_DC << CH_ERR_DCU_TO_TSTATE_SHFT) 1164 1165 /* 1166 * Multiple offset TL>0 handler structure elements 1167 */ 1168 #define CH_ERR_TL1_DATA (CH_ERR_TL1_LOGOUT + CH_CLO_DATA) 1169 #define CH_ERR_TL1_SDW_DATA (CH_ERR_TL1_LOGOUT + CH_CLO_SDW_DATA) 1170 #define CH_ERR_TL1_NEST_CNT (CH_ERR_TL1_LOGOUT + CH_CLO_NEST_CNT) 1171 #define CH_ERR_TL1_AFAR (CH_ERR_TL1_DATA + CH_CHD_AFAR) 1172 #define CH_ERR_TL1_AFSR (CH_ERR_TL1_DATA + CH_CHD_AFSR) 1173 #define CH_ERR_TL1_SDW_AFAR (CH_ERR_TL1_SDW_DATA + CH_CHD_AFAR) 1174 #define CH_ERR_TL1_SDW_AFSR (CH_ERR_TL1_SDW_DATA + CH_CHD_AFSR) 1175 #define CH_ERR_TL1_SDW_AFSR_EXT (CH_ERR_TL1_SDW_DATA + CH_CHD_AFSR_EXT) 1176 1177 /* 1178 * Interval for deferred CEEN reenable 1179 */ 1180 #define CPU_CEEN_DELAY_SECS 6 1181 1182 /* 1183 * flags for flt_trapped_ce variable 1184 */ 1185 #define CE_CEEN_DEFER 0x1 /* no CEEN reenable in trap handler */ 1186 #define CE_CEEN_NODEFER 0x2 /* reenable CEEN in handler */ 1187 #define CE_CEEN_TIMEOUT 0x4 /* CE caught by timeout */ 1188 #define CE_CEEN_TRAPPED 0x8 /* CE caught by trap */ 1189 1190 /* 1191 * default value for cpu_ce_not_deferred 1192 */ 1193 #if defined(JALAPENO) || defined(SERRANO) 1194 #define CPU_CE_NOT_DEFERRED (C_AFSR_CECC_ERRS & \ 1195 ~(C_AFSR_CE | C_AFSR_FRC | C_AFSR_RCE | C_AFSR_EMC)) 1196 #else /* JALAPENO || SERRANO */ 1197 #if defined(CHEETAH_PLUS) 1198 #define CPU_CE_NOT_DEFERRED (C_AFSR_CECC_ERRS & \ 1199 ~(C_AFSR_CE | C_AFSR_EMC | C_AFSR_THCE)) 1200 #else /* CHEETAH_PLUS */ 1201 #define CPU_CE_NOT_DEFERRED (C_AFSR_CECC_ERRS & \ 1202 ~(C_AFSR_CE | C_AFSR_EMC)) 1203 #endif /* CHEETAH_PLUS */ 1204 #endif /* JALAPENO || SERRANO */ 1205 1206 #define CPU_CE_NOT_DEFERRED_EXT (C_AFSR_EXT_CECC_ERRS & \ 1207 ~(C_AFSR_L3_THCE)) 1208 1209 #if defined(CHEETAH_PLUS) 1210 1211 /* 1212 * VA for primary and shadow AFSR/AFAR/AFSR_EXT registers 1213 */ 1214 #define ASI_SHADOW_REG_VA 0x8 1215 #define ASI_AFSR_EXT_VA 0x10 1216 #define ASI_SHADOW_AFSR_EXT_VA 0x18 1217 1218 /* 1219 * Bitmask for keeping track of core parking in ECC error handlers. 1220 * We share a register that also saves the DCUCR value so we use 1221 * one of the reserved bit positions of the DCUCR register to keep 1222 * track of whether or not we have parked our sibling core. 1223 */ 1224 #define PN_PARKED_OTHER_CORE 0x20 1225 #define PN_BOTH_CORES_RUNNING 0x3 1226 1227 /* 1228 * Panther EMU Activity Status Register Bits. 1229 */ 1230 #define ASI_EMU_ACT_STATUS_VA 0x18 1231 #define MCU_ACT_STATUS INT64_C(0x0000000000000001) 1232 #define SIU_ACT_STATUS INT64_C(0x0000000000000002) 1233 #endif /* CHEETAH_PLUS */ 1234 1235 #define ASI_CESR_ID_VA 0x40 /* ASI_CESRD_ID per-core registers */ 1236 1237 #define ASR_DISPATCH_CONTROL %asr18 1238 #define ASR_DISPATCH_CONTROL_BPE 0x20 1239 1240 /* 1241 * Max number of E$ sets logged in ch_diag_data structure 1242 */ 1243 #define CHD_EC_DATA_SETS 4 /* max 4 sets of E$ data */ 1244 1245 /* 1246 * Definitions for Panther TLB parity handling. 1247 */ 1248 #define PN_ITLB_NWAYS 2 1249 #define PN_NUM_512_ITLBS 1 1250 #define PN_DTLB_NWAYS 2 1251 #define PN_NUM_512_DTLBS 2 1252 #define PN_SFSR_PARITY_SHIFT 12 1253 #define PN_ITLB_PGSZ_SHIFT 22 1254 #define PN_ITLB_PGSZ_MASK (7 << PN_ITLB_PGSZ_SHIFT) 1255 #define PN_DTLB_PGSZ0_SHIFT 16 1256 #define PN_DTLB_PGSZ0_MASK (7 << PN_DTLB_PGSZ0_SHIFT) 1257 #define PN_DTLB_PGSZ1_SHIFT 19 1258 #define PN_DTLB_PGSZ1_MASK (7 << PN_DTLB_PGSZ1_SHIFT) 1259 #define PN_DTLB_PGSZ_MASK (PN_DTLB_PGSZ1_MASK | PN_DTLB_PGSZ0_MASK) 1260 #define PN_DTLB_T512_0 (2 << 16) 1261 #define PN_DTLB_T512_1 (3 << 16) 1262 #define PN_TLO_INFO_IMMU_SHIFT 14 1263 #define PN_TLO_INFO_IMMU (1 << PN_TLO_INFO_IMMU_SHIFT) 1264 #define PN_TLO_INFO_TL1_SHIFT 13 1265 #define PN_TLO_INFO_TL1 (1 << PN_TLO_INFO_TL1_SHIFT) 1266 #define PN_ITLB_T512 (2 << 16) 1267 #define PN_TLB_ACC_IDX_SHIFT 3 1268 #define PN_TLB_ACC_WAY_BIT (1 << 11) 1269 #define PN_TLB_DIAGACC_OFFSET 0x40000 /* Diag Acc ASI VA offset */ 1270 /* 1271 * tag parity = XOR(Size[2:0],Global,VA[63:21],Context[12:0]) 1272 * which requires looking at both the tag and the data. 1273 */ 1274 #define PN_TLB_TAG_PARITY_TAG_MASK 0xffffffffffe01fff 1275 #define PN_TLB_TAG_PARITY_DATA_MASK 0x6001400000000001 1276 /* data parity = XOR(NFO,IE,PA[42:13],CP,CV,E,P,W) */ 1277 #define PN_TLB_DATA_PARITY_DATA_MASK 0x180087ffffffe03e 1278 1279 #ifdef _KERNEL 1280 1281 #ifndef _ASM 1282 1283 #include <sys/kstat.h> 1284 1285 /* 1286 * One Ecache data element, 32 bytes of data, 8 bytes of ECC. 1287 * See Cheetah PRM 10.7.2. 1288 */ 1289 typedef struct ec_data_elm { 1290 uint64_t ec_d8[CH_ECACHE_STGREG_NUM]; 1291 uint64_t ec_eccd; /* EC_data_ECC field */ 1292 } ec_data_elm_t; 1293 1294 /* 1295 * L2 and L3 cache data captured by cpu log out code. 1296 * See Cheetah PRM 10.7.4. 1297 */ 1298 typedef struct ch_ec_data { 1299 uint64_t ec_logflag; /* Flag indicates if data was logged */ 1300 uint64_t ec_idx; /* Ecache index */ 1301 uint64_t ec_way; /* Ecache way */ 1302 uint64_t ec_tag; /* Ecache Tag */ 1303 uint64_t ec_tag_ecc; /* Ecache Tag ECC (Cheetah+ only) */ 1304 ec_data_elm_t ec_data[CH_ECACHE_SUBBLK_SIZE/CH_ECACHE_STGREG_SIZE]; 1305 } ch_ec_data_t; 1306 1307 /* 1308 * Dcache data captured by cpu log out code and get_dcache_dtag. 1309 * See Cheetah PRM 10.6.[1-4]. 1310 */ 1311 typedef struct ch_dc_data { 1312 uint64_t dc_logflag; /* Flag indicates if data was logged */ 1313 uint64_t dc_idx; /* Dcache index */ 1314 uint64_t dc_way; /* Dcache way */ 1315 uint64_t dc_tag; /* Tag/Valid Fields */ 1316 uint64_t dc_utag; /* Microtag */ 1317 uint64_t dc_sntag; /* Snoop Tag */ 1318 uint64_t dc_data[CH_DC_DATA_REG_SIZE/sizeof (uint64_t)]; /* Data */ 1319 uint64_t dc_pn_data_parity; /* Data parity bits for Panther */ 1320 } ch_dc_data_t; 1321 1322 /* 1323 * Icache data captured by cpu log out code and get_icache_dtag. 1324 * See Cheetah PRM 10.4.[1-3]. 1325 */ 1326 typedef struct ch_ic_data { 1327 uint64_t ic_logflag; /* Flag indicates if data was logged */ 1328 uint64_t ic_idx; /* Icache index */ 1329 uint64_t ic_way; /* Icache way */ 1330 uint64_t ic_patag; /* Physical address tag */ 1331 uint64_t ic_utag; /* Microtag */ 1332 uint64_t ic_upper; /* Upper valid/predict tag */ 1333 uint64_t ic_lower; /* Lower valid/predict tag */ 1334 uint64_t ic_sntag; /* Snoop Tag */ 1335 uint64_t ic_data[PN_IC_DATA_REG_SIZE/sizeof (uint64_t)]; /* Data */ 1336 } ch_ic_data_t; 1337 1338 /* 1339 * Pcache data captured by get_pcache_dtag 1340 */ 1341 typedef struct ch_pc_data { 1342 uint64_t pc_logflag; /* Flag indicates if data was logged */ 1343 uint64_t pc_idx; /* Pcache index */ 1344 uint64_t pc_way; /* Pcache way */ 1345 uint64_t pc_status; /* Pcache status data */ 1346 uint64_t pc_tag; /* Tag/Valid Fields */ 1347 uint64_t pc_sntag; /* Snoop Tag */ 1348 uint64_t pc_data[CH_PC_DATA_REG_SIZE/sizeof (uint64_t)]; /* Data */ 1349 } ch_pc_data_t; 1350 1351 /* 1352 * CPU Error State 1353 */ 1354 typedef struct ch_cpu_errors { 1355 uint64_t afsr; /* AFSR */ 1356 uint64_t afar; /* AFAR */ 1357 /* 1358 * The following registers don't exist on cheetah 1359 */ 1360 uint64_t shadow_afsr; /* Shadow AFSR */ 1361 uint64_t shadow_afar; /* Shadow AFAR */ 1362 uint64_t afsr_ext; /* AFSR1_EXT */ 1363 uint64_t shadow_afsr_ext; /* AFSR2_EXT */ 1364 uint64_t afar2; /* AFAR2 - Serrano only */ 1365 } ch_cpu_errors_t; 1366 1367 /* 1368 * CPU logout structures. 1369 * NOTE: These structures should be the same for Cheetah, Cheetah+, 1370 * Jaguar, Panther, and Jalapeno since the assembler code relies 1371 * on one set of offsets. Panther is the only processor that 1372 * uses the chd_l2_data field since it has both L3 and L2 caches. 1373 */ 1374 typedef struct ch_diag_data { 1375 uint64_t chd_afar; /* AFAR */ 1376 uint64_t chd_afsr; /* AFSR */ 1377 uint64_t chd_afsr_ext; /* AFSR_EXT */ 1378 uint64_t chd_afar2; /* AFAR2 - Serrano only */ 1379 ch_ec_data_t chd_ec_data[CHD_EC_DATA_SETS]; /* Ecache data */ 1380 ch_ec_data_t chd_l2_data[PN_L2_NWAYS]; /* L2 cache data */ 1381 ch_dc_data_t chd_dc_data; /* Dcache data */ 1382 ch_ic_data_t chd_ic_data; /* Icache data */ 1383 } ch_diag_data_t; 1384 1385 1386 /* 1387 * Top level CPU logout structure. 1388 * clo_flags is used to hold information such as trap type, trap level, 1389 * CEEN value, etc that is needed by the individual trap handlers. Not 1390 * all fields in this flag are used by all trap handlers but when they 1391 * are used, here's how they are laid out: 1392 * 1393 * |-------------------------------------------------------| 1394 * | | trap type | trap level | |UCEEN| |NCEEN|CEEN| 1395 * |-------------------------------------------------------| 1396 * 63 19 12 11 8 3 2 1 0 1397 * 1398 * Note that the *CEEN bits correspond exactly to the same bit positions 1399 * that are used in the error enable register. 1400 */ 1401 typedef struct ch_cpu_logout { 1402 uint64_t clo_flags; /* Information about this trap */ 1403 uint64_t clo_nest_cnt; /* To force an upper bound */ 1404 ch_diag_data_t clo_data; /* Diag data for primary AFAR */ 1405 ch_diag_data_t clo_sdw_data; /* Diag data for shadow AFAR */ 1406 } ch_cpu_logout_t; 1407 1408 typedef struct ch_tte_entry { 1409 uint64_t ch_tte_tag; 1410 uint64_t ch_tte_data; 1411 } ch_tte_entry_t; 1412 1413 /* 1414 * Top level CPU logout structure for TLB parity errors. 1415 * 1416 * tlo_logflag - Flag indicates if data was logged 1417 * tlo_info - Used to keep track of a number of values: 1418 * itlb pgsz - Page size of the VA whose lookup in the ITLB caused 1419 * the exception (from ASI_IMMU_TAG_ACCESS_EXT.) 1420 * dtlb pgsz1 - Page size of the VA whose lookup in the DTLB T512_1 1421 * caused the exception (from ASI_DMMU_TAG_ACCESS_EXT.). 1422 * dtlb pgsz0 - Page size of the VA whose lookup in the DTLB T512_0 1423 * caused the exception (from ASI_DMMU_TAG_ACCESS_EXT.). 1424 * immu - Trap is the result of an ITLB exception if immu == 1. 1425 * Otherwise, for DTLB exceptions immu == 0. 1426 * tl1 - Set to 1 if the exception occured at TL>0. 1427 * context - Context of the VA whose lookup in the TLB caused the 1428 * exception (from ASI_[I|D]MMU_TAG_ACCESS.) 1429 * |---------------------------------------------------------------------| 1430 * |...| itlb pgsz | dtlb pgsz1 | dtlb pgsz0 |...| immu | tl1 | context | 1431 * |---------------------------------------------------------------------| 1432 * 24 22 21 19 18 16 14 13 12 0 1433 * 1434 * tlo_addr - VA that cause the MMU exception trap. 1435 * tlo_pc - PC where the exception occured. 1436 * tlo_itlb_tte - TTEs that were in the ITLB after the trap at the index 1437 * specific to the VA and page size in question. 1438 * tlo_dtlb_tte - TTEs that were in the DTLB after the trap at the index 1439 * specific to the VA and page size in question. 1440 */ 1441 typedef struct pn_tlb_logout { 1442 uint64_t tlo_logflag; 1443 uint64_t tlo_info; 1444 uint64_t tlo_addr; 1445 uint64_t tlo_pc; 1446 ch_tte_entry_t tlo_itlb_tte[PN_ITLB_NWAYS * PN_NUM_512_ITLBS]; 1447 ch_tte_entry_t tlo_dtlb_tte[PN_DTLB_NWAYS * PN_NUM_512_DTLBS]; 1448 } pn_tlb_logout_t; 1449 1450 #if defined(CPU_IMP_L1_CACHE_PARITY) 1451 /* 1452 * Parity error logging structure. 1453 */ 1454 typedef union ch_l1_parity_log { 1455 struct { 1456 int cpl_way; /* Faulty line way */ 1457 int cpl_off; /* Faulty line offset */ 1458 int cpl_tag; /* Faulty tags list */ 1459 int cpl_lcnt; /* Faulty cache lines */ 1460 ch_dc_data_t cpl_dc[CH_DCACHE_NWAY]; /* D$ data nWays */ 1461 ch_pc_data_t cpl_pc[CH_PCACHE_NWAY]; /* P$ data nWays */ 1462 int cpl_cache; /* error in D$ or P$? */ 1463 } dpe; /* D$ parity error */ 1464 struct { 1465 int cpl_way; /* Faulty line way */ 1466 int cpl_off; /* Faulty line offset */ 1467 int cpl_tag; /* Faulty tags list */ 1468 int cpl_lcnt; /* Faulty cache lines */ 1469 ch_ic_data_t cpl_ic[CH_ICACHE_NWAY]; /* I$ data nWays */ 1470 } ipe; /* I$ parity error */ 1471 } ch_l1_parity_log_t; 1472 1473 #endif /* CPU_IMP_L1_CACHE_PARITY */ 1474 1475 /* 1476 * Error at TL>0 CPU logout data. 1477 * Needs some extra space to save %g registers and miscellaneous info. 1478 */ 1479 typedef struct ch_err_tl1_data { 1480 uint64_t ch_err_tl1_g1; /* Saved %g1 */ 1481 uint64_t ch_err_tl1_g2; /* Saved %g2 */ 1482 uint64_t ch_err_tl1_g3; /* Saved %g3 */ 1483 uint64_t ch_err_tl1_g4; /* Saved %g4 */ 1484 uint64_t ch_err_tl1_g5; /* Saved %g5 */ 1485 uint64_t ch_err_tl1_g6; /* Saved %g6 */ 1486 uint64_t ch_err_tl1_g7; /* Saved %g7 */ 1487 uint64_t ch_err_tl1_tpc; /* Trap PC */ 1488 uint64_t ch_err_tl1_flags; /* miscellaneous flags */ 1489 uint64_t ch_err_tl1_tmp; /* some handlers may use as tmp */ 1490 ch_cpu_logout_t ch_err_tl1_logout; /* logout */ 1491 } ch_err_tl1_data_t; 1492 1493 /* Indices into chsm_outstanding and friends */ 1494 #define CACHE_SCRUBBER_INFO_E 0 1495 #define CACHE_SCRUBBER_INFO_D 1 1496 #define CACHE_SCRUBBER_INFO_I 2 1497 1498 /* We define 3 scrubbers: E$, D$, and I$ */ 1499 #define CACHE_SCRUBBER_COUNT 3 1500 1501 /* 1502 * The ch_scrub_misc structure contains miscellaneous bookkeeping 1503 * items for scrubbing the I$, D$, and E$. 1504 * 1505 * For a description of the use of chsm_core_state and why it's not needed 1506 * on Jaguar, see the comment above cpu_scrub_cpu_setup() in us3_cheetahplus.c. 1507 */ 1508 typedef struct ch_scrub_misc { 1509 uint32_t chsm_outstanding[CACHE_SCRUBBER_COUNT]; 1510 /* outstanding requests */ 1511 int chsm_flush_index[CACHE_SCRUBBER_COUNT]; 1512 /* next line to flush */ 1513 int chsm_enable[CACHE_SCRUBBER_COUNT]; 1514 /* is this scrubber enabled on this core? */ 1515 int chsm_ecache_nlines; /* no. of E$ lines */ 1516 int chsm_ecache_busy; /* keeps track if cpu busy */ 1517 int chsm_icache_nlines; /* no. of I$ lines */ 1518 int chsm_core_state; /* which core the scrubber is */ 1519 /* running on (Panther only) */ 1520 } ch_scrub_misc_t; 1521 1522 /* 1523 * Cheetah module private data structure. One of these is allocated for 1524 * each valid cpu at setup time and is pointed to by the machcpu 1525 * "cpu_private" pointer. For Cheetah, we have the miscellaneous scrubber 1526 * variables and cpu log out structures for Fast ECC traps at TL=0, 1527 * Disrupting (correctable) traps and Deferred (asynchronous) traps. For 1528 * Disrupting traps only one log out structure is needed because we cannot 1529 * get a TL>0 disrupting trap since it obeys IE. For Deferred traps we 1530 * cannot get a TL>0 because we turn off NCEEN during log out capture. E$ 1531 * set size (E$ size / nways) is saved here to avoid repeated calculations. 1532 * NB: The ch_err_tl1_data_t structures cannot cross a page boundary 1533 * because we use physical addresses to access them. We ensure this 1534 * by allocating them near the front of cheetah_private_t, which is 1535 * aligned on PAGESIZE (8192) via kmem_cache_create, and by ASSERTing 1536 * sizeof (chpr_tl1_err_data) <= CH_ECACHE_MAX_LSIZE in the 1537 * cpu_init_private routines. 1538 * NB: chpr_icache_size and chpr_icache_linesize need to be at the front 1539 * of cheetah_private_t because putting them after chpr_tl1_err_data 1540 * would make their offsets > 4195. 1541 */ 1542 typedef struct cheetah_private { 1543 int chpr_icache_size; 1544 int chpr_icache_linesize; 1545 ch_err_tl1_data_t chpr_tl1_err_data[CH_ERR_TL1_TLMAX]; 1546 ch_scrub_misc_t chpr_scrub_misc; 1547 int chpr_ec_set_size; 1548 ch_cpu_logout_t chpr_fecctl0_logout; 1549 ch_cpu_logout_t chpr_cecc_logout; 1550 ch_cpu_logout_t chpr_async_logout; 1551 pn_tlb_logout_t chpr_tlb_logout; 1552 uint64_t chpr_fpras_timestamp[FPRAS_NCOPYOPS]; 1553 hrtime_t chpr_ceptnr_seltime; 1554 int chpr_ceptnr_id; 1555 } cheetah_private_t; 1556 1557 #endif /* _ASM */ 1558 1559 #endif /* _KERNEL */ 1560 1561 #ifdef __cplusplus 1562 } 1563 #endif 1564 1565 #endif /* _SYS_CHEETAHREGS_H */ 1566