1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_CHEETAHREGS_H 27 #define _SYS_CHEETAHREGS_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/machasi.h> 32 #include <sys/cpu_impl.h> 33 #ifdef _KERNEL 34 #include <sys/fpras.h> 35 #endif /* _KERNEL */ 36 37 /* 38 * This file is cpu dependent. 39 */ 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /* 46 * Cheetah includes the process info in its mask to make things 47 * more difficult. The process is the low bit of the major mask, 48 * so to convert to the netlist major: 49 * netlist_major = ((mask_major >> 1) + 1) 50 */ 51 #define REMAP_CHEETAH_MASK(x) (((((x) >> 1) + 0x10) & 0xf0) | ((x) & 0xf)) 52 53 #ifdef _ASM 54 /* 55 * assembler doesn't understand the 'ull' suffix for C constants so 56 * use the inttypes.h macros and undefine them here for assembly code 57 */ 58 #undef INT64_C 59 #undef UINT64_C 60 #define INT64_C(x) (x) 61 #define UINT64_C(x) (x) 62 #endif /* _ASM */ 63 64 /* 65 * DCU Control Register 66 * 67 * +------+----+----+----+----+----+-----+-----+----+----+----+ 68 * | Resv | CP | CV | ME | RE | PE | HPE | SPE | SL | WE | PM | 69 * +------+----+----+----+----+----+-----+-----+----+----+----+ 70 * 63:50 49 48 47 46 45 44 43 42 41 40:33 71 * 72 * +----+----+----+----+----+----------+-----+----+----+----+---+ 73 * | VM | PR | PW | VR | VW | Reserved | WIH | DM | IM | DC | IC| 74 * +----+----+----+----+----+----------+-----+----+----+----+---+ 75 * 32:25 24 23 22 21 20:5 4 3 2 1 0 76 */ 77 78 #define ASI_DCU ASI_LSU /* same as spitfire ASI_LSU 0x45 */ 79 #define DCU_IC INT64_C(0x0000000000000001) /* icache enable */ 80 #define DCU_DC INT64_C(0x0000000000000002) /* dcache enable */ 81 #define DCU_IM INT64_C(0x0000000000000004) /* immu enable */ 82 #define DCU_DM INT64_C(0x0000000000000008) /* dmmu enable */ 83 #define DCU_WIH INT64_C(0x0000000000000010) /* Jaguar only - W$ hash index */ 84 #define DCU_VW INT64_C(0x0000000000200000) /* virt watchpoint write enable */ 85 #define DCU_VR INT64_C(0x0000000000400000) /* virt watchpoint read enable */ 86 #define DCU_PW INT64_C(0x0000000000800000) /* phys watchpoint write enable */ 87 #define DCU_PR INT64_C(0x0000000001000000) /* phys watchpoint read enable */ 88 #define DCU_VM INT64_C(0x00000001FE000000) /* virtual watchpoint write mask */ 89 #define DCU_PM INT64_C(0x000001FE00000000) /* phys watchpoint write mask */ 90 #define DCU_WE INT64_C(0x0000020000000000) /* write cache enable */ 91 #define DCU_SL INT64_C(0x0000040000000000) /* second load control */ 92 #define DCU_SPE INT64_C(0x0000080000000000) /* software prefetch enable */ 93 #define DCU_HPE INT64_C(0x0000100000000000) /* hardware prefetch enable */ 94 #define DCU_PE INT64_C(0x0000200000000000) /* prefetch enable */ 95 #define DCU_RE INT64_C(0x0000400000000000) /* RAW bypass enable */ 96 #define DCU_ME INT64_C(0x0000800000000000) /* noncache store merging enable */ 97 #define DCU_CV INT64_C(0x0001000000000000) /* virt cacheability when DM=0 */ 98 #define DCU_CP INT64_C(0x0002000000000000) /* phys cacheable when DM,IM=0 */ 99 #define DCU_CACHE (DCU_IC|DCU_DC|DCU_WE|DCU_SPE|DCU_HPE|DCU_PE) 100 101 /* 102 * bit shifts for the prefetch enable bit 103 */ 104 #define DCU_PE_SHIFT 45 105 106 /* 107 * Safari Configuration Register 108 */ 109 #define ASI_SAFARI_CONFIG ASI_UPA_CONFIG /* Safari Config Reg, 0x4A */ 110 #define SAFARI_CONFIG_ECLK_1 INT64_C(0x0000000000000000) /* 1/1 clock */ 111 #define SAFARI_CONFIG_ECLK_1_DIV 1 /* clock divisor: 1 */ 112 #define SAFARI_CONFIG_ECLK_2 INT64_C(0x0000000040000000) /* 1/2 clock */ 113 #define SAFARI_CONFIG_ECLK_2_DIV 2 /* clock divisor: 2 */ 114 #define SAFARI_CONFIG_ECLK_32 INT64_C(0x0000000080000000) /* 1/32 clock */ 115 #define SAFARI_CONFIG_ECLK_32_DIV 32 /* clock divisor: 32 */ 116 #define SAFARI_CONFIG_ECLK_MASK (SAFARI_CONFIG_ECLK_32 | SAFARI_CONFIG_ECLK_2) 117 118 #if defined(JALAPENO) || defined(SERRANO) 119 /* 120 * JBUS Configuration Register 121 */ 122 #define ASI_JBUS_CONFIG ASI_UPA_CONFIG /* JBUS Config Reg, 0x4A */ 123 #define JBUS_CONFIG_ECLK_1 INT64_C(0x0000000000000000) /* 1/1 clock */ 124 #define JBUS_CONFIG_ECLK_1_DIV 1 /* clock divisor: 1 */ 125 #define JBUS_CONFIG_ECLK_2 INT64_C(0x0000000000002000) /* 1/2 clock */ 126 #define JBUS_CONFIG_ECLK_2_DIV 2 /* clock divisor: 2 */ 127 #define JBUS_CONFIG_ECLK_32 INT64_C(0x0000000000004000) /* 1/32 clock */ 128 #define JBUS_CONFIG_ECLK_32_DIV 32 /* clock divisor: 32 */ 129 #define JBUS_CONFIG_ECLK_MASK (JBUS_CONFIG_ECLK_32 | JBUS_CONFIG_ECLK_2) 130 #define JBUS_CONFIG_ECLK_SHIFT 13 131 132 /* 133 * Jalapeno/Serrano MCU control registers and ASI 134 */ 135 #define ASI_MCU_CTRL 0x72 /* MCU Control Reg ASI */ 136 #define JP_MCU_FSM_MASK INT64_C(0x0000000006000000) /* 26..25 */ 137 #define JP_MCU_FSM_SHIFT 25 138 #endif /* JALAPENO || SERRANO */ 139 140 #if defined(SERRANO) 141 #define ASI_MCU_AFAR2_VA 0x18 /* captures FRC/FRU addr */ 142 #endif /* SERRANO */ 143 144 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85) 145 /* 146 * Tomatillo Estar control registers (for JP Errataum 85) 147 */ 148 #define JBUS_SLAVE_T_PORT_BIT 48 149 #define TOM_HIGH_PA 0x400 /* Hi 32 bit of Tom reg PA */ 150 #define M_T_ESTAR_CTRL_PA 0x0f410050 /* M T estar PA */ 151 #define S_T_ESTAR_CTRL_PA 0x0e410050 /* S T estar PA */ 152 #define M_T_J_CHNG_INIT_PA 0x0f410058 /* Master T estar PA */ 153 #define TOM_ESTAR_ELCK_MASK 0x23 /* bit 5,1,0 */ 154 #define TOM_FULL_SPEED 0x1 155 #define TOM_HALF_SPEED 0x2 156 #define TOM_SLOW_SPEED 0x20 157 #define TOM_TRIGGER_MASK 0x18 158 #define TOM_TRIGGER 0x10 159 160 #endif /* JALAPENO && JALAPENO_ERRATA_85 */ 161 162 163 /* 164 * Miscellaneous ASI definitions not in machasi.h 165 */ 166 #define ASI_DC_UTAG 0x43 /* Dcache Microtag Fields */ 167 #define ASI_DC_SNP_TAG 0x44 /* Dcache Snoop Tag Fields */ 168 #define ASI_IC_SNP_TAG 0x68 /* Icache Snoop Tag Fields */ 169 #define ASI_IPB_DATA 0x69 /* Instruction Prefetch Buffer Data */ 170 #define ASI_IPB_TAG 0x6A /* Instruction Prefetch Buffer Tag */ 171 #define ASI_MC_DECODE 0x72 /* Memory Address Decoding Registers */ 172 #define ASI_EC_CFG_TIMING 0x73 /* Jaguar shared Ecache Control Reg */ 173 #define ASI_EC_DATA 0x74 /* Ecache Data Staging Registers */ 174 #define ASI_EC_CTRL 0x75 /* Ecache Control Register */ 175 #define ASI_PC_STATUS_DATA 0x30 /* Pcache Status Data Access */ 176 #define ASI_PC_DATA 0x31 /* Pcache Diagnostic Data Register */ 177 #define ASI_PC_TAG 0x32 /* Pcache Virtual Tag/Valid Field */ 178 #define ASI_PC_SNP_TAG 0x33 /* Pcache Snoop Tag Register */ 179 #define ASI_L2_DATA 0x6B /* L2 cache Data Diagnostic Access */ 180 #define ASI_L2_TAG 0x6C /* L2 cache Tag Diagnostic Access */ 181 #define ASI_L2CACHE_CTRL 0x6D /* L2 cache Control Register */ 182 183 /* 184 * Bits of Cheetah Asynchronous Fault Status Register 185 * 186 * +---+--+----+----+----+----+---+---+---+---+--+---- 187 * |rsv|ME|PRIV|PERR|IERR|ISAP|EMC|EMU|IVC|IVU|TO|BERR 188 * +---+--+----+----+----+----+---+---+---+---+--+---- 189 * 63:54 53 52 51 50 49 48 47 46 45 44 43 190 * +---+---+---+---+---+---+---+---+--+--+---+------+---+-------+ 191 * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|rsv|M_SYND|rsv||E_SYND| 192 * +---+---+---+---+---+---+---+---+--+--+---+------+---+-------+ 193 * 42 41 40 39 38 37 36 35 34 33 32:20 19:16 15:9 8:0 194 * 195 */ 196 #if defined(CHEETAH_PLUS) 197 /* 198 * Bits of Cheetah+ Asynchronous Fault Status Register 199 * 200 * +------------------+---------------------------- 201 * |rsv|TUE_SH|IMC|IMU|DTO|DBERR|THCE|TSCE|TUE|DUE| 202 * +------------------+---------------------------- . . . 203 * 63 62 61 60 59 58 57 56 55 54 204 * 205 * Note that bits 60-62 are only implemented in Panther (reserved 206 * in Cheetah+ and Jaguar. Also, bit 56 is reserved in Panther instead 207 * of TSCE since those errors are HW corrected in Panther. 208 */ 209 #define C_AFSR_TUE_SH INT64_C(0x4000000000000000) /* uncorrectable tag UE */ 210 #define C_AFSR_IMC INT64_C(0x2000000000000000) /* intr vector MTAG ECC */ 211 #define C_AFSR_IMU INT64_C(0x1000000000000000) /* intr vector MTAG ECC */ 212 #define C_AFSR_DTO INT64_C(0x0800000000000000) /* disrupting TO error */ 213 #define C_AFSR_DBERR INT64_C(0x0400000000000000) /* disrupting BERR error */ 214 #define C_AFSR_THCE INT64_C(0x0200000000000000) /* h/w correctable E$ tag err */ 215 #define C_AFSR_TSCE INT64_C(0x0100000000000000) /* s/w correctable E$ tag err */ 216 #define C_AFSR_TUE INT64_C(0x0080000000000000) /* uncorrectable E$ tag error */ 217 #define C_AFSR_DUE INT64_C(0x0040000000000000) /* disrupting UE error */ 218 #endif /* CHEETAH_PLUS */ 219 #define C_AFSR_ME INT64_C(0x0020000000000000) /* errors > 1, same type!=CE */ 220 #define C_AFSR_PRIV INT64_C(0x0010000000000000) /* priv code access error */ 221 #define C_AFSR_PERR INT64_C(0x0008000000000000) /* system interface protocol */ 222 #define C_AFSR_IERR INT64_C(0x0004000000000000) /* internal system interface */ 223 #define C_AFSR_ISAP INT64_C(0x0002000000000000) /* system request parity err */ 224 #define C_AFSR_EMC INT64_C(0x0001000000000000) /* mtag with CE error */ 225 #define C_AFSR_EMU INT64_C(0x0000800000000000) /* mtag with UE error */ 226 #define C_AFSR_IVC INT64_C(0x0000400000000000) /* intr vector with CE error */ 227 #define C_AFSR_IVU INT64_C(0x0000200000000000) /* intr vector with UE error */ 228 #define C_AFSR_TO INT64_C(0x0000100000000000) /* bus timeout from sys bus */ 229 #define C_AFSR_BERR INT64_C(0x0000080000000000) /* bus error from system bus */ 230 #define C_AFSR_UCC INT64_C(0x0000040000000000) /* E$ with software CE error */ 231 #define C_AFSR_UCU INT64_C(0x0000020000000000) /* E$ with software UE error */ 232 #define C_AFSR_CPC INT64_C(0x0000010000000000) /* copyout with CE error */ 233 #define C_AFSR_CPU INT64_C(0x0000008000000000) /* copyout with UE error */ 234 #define C_AFSR_WDC INT64_C(0x0000004000000000) /* writeback ecache CE error */ 235 #define C_AFSR_WDU INT64_C(0x0000002000000000) /* writeback ecache UE error */ 236 #define C_AFSR_EDC INT64_C(0x0000001000000000) /* ecache CE ECC error */ 237 #define C_AFSR_EDU INT64_C(0x0000000800000000) /* ecache UE ECC error */ 238 #define C_AFSR_UE INT64_C(0x0000000400000000) /* uncorrectable ECC error */ 239 #define C_AFSR_CE INT64_C(0x0000000200000000) /* correctable ECC error */ 240 #define C_AFSR_M_SYND INT64_C(0x00000000000f0000) /* mtag ECC syndrome */ 241 #define C_AFSR_E_SYND INT64_C(0x00000000000001ff) /* data ECC syndrome */ 242 243 /* AFSR bits that could result in CPU removal due to E$ error */ 244 #define C_AFSR_L2_SERD_FAIL_UE (C_AFSR_UCU | C_AFSR_CPU | C_AFSR_WDU | \ 245 C_AFSR_EDU) 246 #define C_AFSR_L2_SERD_FAIL_CE (C_AFSR_UCC | C_AFSR_CPC | C_AFSR_WDC | \ 247 C_AFSR_EDC) 248 /* 249 * Bits of the Panther Extended Asynchronous Fault Status Register (AFSR_EXT) 250 * 251 * +-----+-------+-----------+-------+-------+---------+------+------+------+ 252 * | rsv |RED_ERR|EFA_PAR_ERR|L3_MECC|L3_THCE|L3_TUE_SH|L3_TUE|L3_EDC|L3_EDU| 253 * +-----+-------+-----------+-------+-------+---------+------+------+------+ 254 * 63:14 13 12 11 10 9 8 7 6 255 * 256 * +------+------+------+------+------+------+ 257 * |L3_UCC|L3_UCU|L3_CPC|L3_CPU|L3_WDC|L3_WDU| 258 * +------+------+------+------+------+------+ 259 * 5 4 3 2 1 0 260 * 261 * If the L3_MECC bit is set along with any of the L3 cache errors (bits 0-7) 262 * above, it indicates that an address parity error has occured. 263 */ 264 #define C_AFSR_RED_ERR INT64_C(0x0000000000002000) /* redunancy Efuse error */ 265 #define C_AFSR_EFA_PAR_ERR INT64_C(0x0000000000001000) /* Efuse parity error */ 266 #define C_AFSR_L3_MECC INT64_C(0x0000000000000800) /* L3 address parity */ 267 #define C_AFSR_L3_THCE INT64_C(0x0000000000000400) /* tag CE */ 268 #define C_AFSR_L3_TUE_SH INT64_C(0x0000000000000200) /* tag UE from snp/cpy */ 269 #define C_AFSR_L3_TUE INT64_C(0x0000000000000100) /* tag UE */ 270 #define C_AFSR_L3_EDC INT64_C(0x0000000000000080) /* L3 cache CE */ 271 #define C_AFSR_L3_EDU INT64_C(0x0000000000000040) /* L3 cache UE */ 272 #define C_AFSR_L3_UCC INT64_C(0x0000000000000020) /* software recover CE */ 273 #define C_AFSR_L3_UCU INT64_C(0x0000000000000010) /* software recover UE */ 274 #define C_AFSR_L3_CPC INT64_C(0x0000000000000008) /* copyout with CE */ 275 #define C_AFSR_L3_CPU INT64_C(0x0000000000000004) /* copyout with UE */ 276 #define C_AFSR_L3_WDC INT64_C(0x0000000000000002) /* writeback CE */ 277 #define C_AFSR_L3_WDU INT64_C(0x0000000000000001) /* writeback UE */ 278 279 #if defined(JALAPENO) || defined(SERRANO) 280 /* 281 * Bits of Jalapeno Asynchronous Fault Status Register 282 * 283 * +-----+------------------------------------------------------------------ 284 * | rsv |JETO|SCE|JEIC|JEIT|ME|PRIV|JEIS|IERR|ISAP|ETP|OM|UMS|IVPE|TO|BERR| 285 * +-----+------------------------------------------------------------------ 286 * 63:58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 287 * 288 * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+ 289 * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|RUE|RCE|BP|WBP|FRC|FRU| 290 * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+ 291 * 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 292 * 293 * +-----+-----+-----+------+-----------+-------+ 294 * | JREQ| ETW | rsv |B_SYND| rsv | AID | E_SYND| 295 * +-----+-----+-----+------+-----+-----+-------+ 296 * 26:24 23:22 21:20 19:16 15:14 13:9 8:0 297 * 298 */ 299 300 /* 301 * Bits of Serrano Asynchronous Fault Status Register 302 * 303 * +-----+------------------------------------------------------------------ 304 * | rsv |JETO|SCE|JEIC|JEIT|ME|PRIV|JEIS|IERR|ISAP|ETU|OM|UMS|IVPE|TO|BERR| 305 * +-----+------------------------------------------------------------------ 306 * 63:58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 307 * 308 * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+ 309 * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|RUE|RCE|BP|WBP|FRC|FRU| 310 * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+ 311 * 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 312 * 313 * +-----+-----+------+---+------+---+---+-----+-------+ 314 * | JREQ| ETW | EFES |ETS|B_SYND|ETI|ETC| AID | E_SYND| 315 * +-----+-----+------+---+------+---+---+-----+-------+ 316 * 26:24 23:22 21 20 19:16 15 14 13:9 8:0 317 * 318 */ 319 320 #define C_AFSR_JETO INT64_C(0x0200000000000000) /* JBus Timeout */ 321 #define C_AFSR_SCE INT64_C(0x0100000000000000) /* Snoop parity error */ 322 #define C_AFSR_JEIC INT64_C(0x0080000000000000) /* JBus Illegal Cmd */ 323 #define C_AFSR_JEIT INT64_C(0x0040000000000000) /* Illegal ADTYPE */ 324 #define C_AFSR_JEIS INT64_C(0x0008000000000000) /* Illegal Install State */ 325 #if defined(SERRANO) 326 #define C_AFSR_ETU INT64_C(0x0001000000000000) /* L2$ tag CE error */ 327 #elif defined(JALAPENO) 328 #define C_AFSR_ETP INT64_C(0x0001000000000000) /* L2$ tag parity error */ 329 #endif /* JALAPENO */ 330 #define C_AFSR_OM INT64_C(0x0000800000000000) /* out of range mem error */ 331 #define C_AFSR_UMS INT64_C(0x0000400000000000) /* Unsupported store */ 332 #define C_AFSR_IVPE INT64_C(0x0000200000000000) /* intr vector parity err */ 333 #define C_AFSR_RUE INT64_C(0x0000000100000000) /* remote mem UE error */ 334 #define C_AFSR_RCE INT64_C(0x0000000080000000) /* remote mem CE error */ 335 #define C_AFSR_BP INT64_C(0x0000000040000000) /* read data parity err */ 336 #define C_AFSR_WBP INT64_C(0x0000000020000000) /* wb/bs data parity err */ 337 #define C_AFSR_FRC INT64_C(0x0000000010000000) /* foregin mem CE error */ 338 #define C_AFSR_FRU INT64_C(0x0000000008000000) /* foregin mem UE error */ 339 #define C_AFSR_JREQ INT64_C(0x0000000007000000) /* Active JBus req at err */ 340 #define C_AFSR_ETW INT64_C(0x0000000000c00000) /* AID causing UE/CE */ 341 342 #if defined(SERRANO) 343 #define C_AFSR_EFES INT64_C(0x0000000000200000) /* E-fuse error summary */ 344 #define C_AFSR_ETS INT64_C(0x0000000000100000) /* L2$ tag SRAM stuck-at */ 345 #endif /* SERRANO */ 346 347 #define C_AFSR_B_SYND INT64_C(0x00000000000f0000) /* jbus parity syndrome */ 348 349 #if defined(SERRANO) 350 #define C_AFSR_ETI INT64_C(0x0000000000008000) /* L2$ tag intermittent */ 351 #define C_AFSR_ETC INT64_C(0x0000000000004000) /* L2$ tag CE */ 352 #endif /* SERRANO */ 353 354 #define C_AFSR_AID INT64_C(0x0000000000003e00) /* AID causing UE/CE */ 355 356 /* bit shifts for selected errors */ 357 #define C_AFSR_WDU_SHIFT 37 358 #define C_AFSR_UCU_SHIFT 41 359 #define C_AFSR_UCC_SHIFT 42 360 #define C_AFSR_JREQ_SHIFT 24 361 #define C_AFSR_AID_SHIFT 9 362 363 /* 364 * Overloaded AFSR fields. During error processing, some of the reserved 365 * fields within the saved AFSR are overwritten with extra information. 366 */ 367 #define C_AFSR_PANIC_SHIFT 62 368 #define C_AFSR_IPE_SHIFT 59 369 #define C_AFSR_DPE_SHIFT 58 370 371 #else /* JALAPENO || SERRANO */ 372 373 /* bit shifts for selected errors */ 374 #define C_AFSR_WDU_SHIFT 37 375 #define C_AFSR_UCU_SHIFT 41 376 #define C_AFSR_UCC_SHIFT 42 377 #define C_AFSR_L3_UCU_SHIFT 4 378 379 /* 380 * Overloaded AFSR fields. During error processing, some of the reserved fields 381 * within the saved AFSR are overwritten with extra information. 382 */ 383 #define C_AFSR_FIRSTFLT_SHIFT 63 384 #define C_AFSR_PANIC_SHIFT 30 385 #define C_AFSR_DPE_SHIFT 20 386 #define C_AFSR_IPE_SHIFT 21 387 388 #endif /* JALAPENO || SERRANO */ 389 390 #if defined(JALAPENO) || defined(SERRANO) 391 /* 392 * Jalapeno L2 Cache Control Register Bits. 393 * 394 * Bit# Name Description 395 * 63-24 - reserved 396 * 23:20 EC_ACT_WAY (read only) indicates which sets are present 397 * 19:16 EC_BLK_WAY Bit mask indicating which sets are blocked 398 * from replacement 399 * 15:14 EC_SIZE L2 cache size 400 * 13:12 - reserved 401 * 11 EC_PAR_EN Enables parity checking on L2 cache tags 402 * 10 EC_ECC_EN Enables ECC checking on L2 cache data 403 * 9 EC_ECC_FORCE Enables EC_CHECK[8:0] onto L2 cache ECC bits 404 * 8:0 EC_CHECK ECC check vector to force onto ECC bits 405 */ 406 407 #define JP_ECCTRL_ECSIZE_MASK 0xc000 408 #define JP_ECCTRL_ECSIZE_SHIFT 14 409 #define JP_ECCTRL_ECSIZE_MIN 0x80000 410 411 /* 412 * Jalapeno L2 Cache Error Enable Register Bits 413 * 414 * Bit# Name Description 415 * 63-33 - reserved 416 * 32 SCDE Enable detection of JBUS control parity error 417 * 31:24 - reserved 418 * 23 IAEN Enable trap on illegal physical address 419 * 22 IERREN Enable FERR system reset on CPU internal errors 420 * 21 PERREN Enable FERR system reset on JBUS protocol errors 421 * 20 SCEN Enable FERR system reset on JBUS control parity error 422 * 19:11 FMED Forced error on the memory ECC 423 * 10 FME Force error on memory ECC 424 * 9:6 FPD Bits to use when FSP forces JBUS addr/data parity error 425 * 5 FSP Force error on outgoing JBUS addr/data parity 426 * 4 ETPEN Enable FERR system reset on L2 tags parity error 427 * 3 UCEEN Enable trap on SW handled external cache error 428 * 2 ISAPEN Enable FERR system reset on request parity error 429 * 1 NCEEN Enable trap on uncorrectable ECC error and system err 430 * 0 CEEN Enable trap on correctable ECC errors 431 */ 432 433 #define EN_REG_UCEEN INT64_C(0x0000000000000008) /* enable UCC,UCU */ 434 #define EN_REG_ISAPEN INT64_C(0x0000000000000004) /* enable ISAP */ 435 #define EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */ 436 #define EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */ 437 438 #define EN_REG_DISABLE INT64_C(0x0000000000000000) /* no errors enabled */ 439 #define EN_REG_ECC_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN) 440 #define EN_REG_CE_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN) 441 #define EN_REG_ENABLE \ 442 (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN | EN_REG_CEEN) 443 444 #else /* JALAPENO || SERRANO */ 445 #if defined(CHEETAH_PLUS) 446 /* 447 * Cheetah+ External Cache Control Register Bits. 448 */ 449 #define ECCR_ASSOC INT64_C(0x0000000001000000) /* Ecache Assoc. */ 450 #define ECCR_ASSOC_SHIFT 24 451 #endif /* CHEETAH_PLUS */ 452 453 /* 454 * Bits of Cheetah External Cache Error Enable Register 455 * 456 * +-----+-----+-------+-----+-------+-------+--------+-------+------+ 457 * | rsv | FMT | FMECC | FMD | FDECC | UCEEN | ISAPEN | NCEEN | CEEN | 458 * +-----+-----+-------+-----+-------+-------+--------+-------+------+ 459 * 63:19 18 17 14 13 12:4 3 2 1 0 460 * 461 */ 462 #define EN_REG_FMT INT64_C(0x0000000000040000) /* force system mtag ECC */ 463 #define EN_REG_FMECC INT64_C(0x000000000003C000) /* forced mtag ECC vector */ 464 #define EN_REG_FMD INT64_C(0x0000000000002000) /* force system data ECC */ 465 #define EN_REG_FDECC INT64_C(0x0000000000001ff0) /* forced data ECC vector */ 466 #define EN_REG_UCEEN INT64_C(0x0000000000000008) /* enable UCC,UCU */ 467 #define EN_REG_ISAPEN INT64_C(0x0000000000000004) /* enable ISAP */ 468 #define EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */ 469 #define EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */ 470 #define EN_REG_DISABLE INT64_C(0x0000000000000000) /* no errors enabled */ 471 #define EN_REG_ECC_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN) 472 #define EN_REG_CE_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN) 473 #define EN_REG_ENABLE \ 474 (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN | EN_REG_CEEN) 475 #endif /* JALAPENO || SERRANO */ 476 477 /* 478 * bit shifts for selected bits 479 */ 480 #define EN_REG_CEEN_SHIFT 0 481 482 /* Cheetah/Cheetah+ Dcache size */ 483 #define CH_DCACHE_SIZE 0x10000 484 485 /* Cheetah/Cheetah+ Dcache linesize */ 486 #define CH_DCACHE_LSIZE 0x20 487 488 /* Cheetah/Cheetah+/Jaguar Icache size */ 489 #define CH_ICACHE_SIZE 0x8000 490 491 /* Cheetah/Cheetah+/Jaguar Icache linesize */ 492 #define CH_ICACHE_LSIZE 0x20 493 494 /* Panther Icache size */ 495 #define PN_ICACHE_SIZE 0x10000 496 497 /* Panther Icache linesize */ 498 #define PN_ICACHE_LSIZE 0x40 499 500 /* Pcache size for the cheetah family of CPUs */ 501 #define CH_PCACHE_SIZE 0x800 502 503 /* Pcache linesize for the cheetah family of CPUs */ 504 #define CH_PCACHE_LSIZE 0x40 505 506 /* 507 * The cheetah+ CPU module handles Cheetah+, Jaguar, and Panther so 508 * we have to pick max size and min linesize values for the Icache 509 * accordingly. 510 */ 511 #define CHP_ICACHE_MAX_SIZE PN_ICACHE_SIZE 512 #define CHP_ICACHE_MIN_LSIZE CH_ICACHE_LSIZE 513 514 /* 515 * The minimum size needed to ensure consistency on a virtually address 516 * cache. Computed by taking the largest virtually indexed cache and dividing 517 * by its associativity. 518 */ 519 #define CH_VAC_SIZE 0x4000 520 521 /* 522 * The following definitions give the syndromes that will be seen when attempts 523 * are made to read data that has been intentionally poisoned. Intentional 524 * poisoning is performed when an error has been detected, and is designed to 525 * allow software to effectively distinguish between root problems and secondary 526 * effects. The following syndromes and their descriptions are taken from the 527 * UltraSPARC-III Cu Error Manual, Section 5.4.3.1. 528 */ 529 530 /* 531 * For a DSTAT = 2 or 3 event (see Sec 5.3.4.4) from the system bus for a 532 * cacheable load, data bits [1:0] are inverted in the data stored in the 533 * L2-cache. The syndrome seen when one of these signalling words is read will 534 * be 0x11c. 535 */ 536 #define CH_POISON_SYND_FROM_DSTAT23 0x11c 537 538 /* 539 * For an uncorrectable data ECC error from the L2-cache, data bits [127:126] 540 * are inverted in data sent to the system bus as part of a writeback or 541 * copyout. The syndrome seen when one of these signalling words is read will 542 * be 0x071. 543 */ 544 #define CH_POISON_SYND_FROM_XXU_WRITE 0x71 545 546 /* 547 * For uncorrectable data ECC error on the L2-cache read done to complete a 548 * store merge event, where bytes written by the processor are merged with 549 * bytes from an L2-cache line, ECC check bits [1:0] are inverted in the data 550 * scrubbed back to the L2-cache. The syndrome seen when one of these 551 * signalling words is read will be 0x003. 552 */ 553 #define CH_POISON_SYND_FROM_XXU_WRMERGE 0x3 554 555 /* 556 * To help understand the following definitions, this block of comments 557 * provides information on Cheetah's E$. 558 * 559 * Cheetah supports three different E$ sizes (1MB, 4MB, and 8MB). The 560 * number of E$ lines remains constant regardless of the size of the E$ 561 * as does the subblock size, however the number of 64-byte subblocks per 562 * line varies depending on the E$ size. 563 * 564 * An E$ tag (for an E$ line) contains an EC_tag field, corresponding to the 565 * high order physical address bits of that E$ line's contents, and 1 to 8 566 * EC_state fields, indicating the state of each subblock. Due to the E$ line 567 * size variance depending on the total size of the E$, the number of bits in 568 * the EC_tag field varies as does the number of subblocks (and EC_state 569 * fields) per E$ line. 570 * 571 * A 1MB E$ has a line size of 64 bytes, containing 1 subblock per line. 572 * A 4MB E$ has a line size of 256 bytes, containing 4 subblocks per line. 573 * An 8MB E$ has a line size of 512 bytes, containing 8 subblocks per line. 574 * 575 * An E$ tag for a particular E$ line can be read via a diagnostic ASI 576 * as a 64-bit value. 577 * Within the E$ tag 64-bit value, the EC_tag field is interpreted as follows: 578 * - for a 1MB E$, the EC_tag is in bits <43:21> and corresponds 579 * to physical address bits <42:20> (bits <41:19> for Cheetah+) 580 * - for a 4MB E$, the EC_tag is in bits <43:23> and corresponds 581 * to physical address bits <42:22> (bits <41:21> for Cheetah+) 582 * - for an 8MB E$, the EC_tag is in bits <43:24> and corresponds 583 * to physical address bits <42:23> (bits <41:22> for Cheetah+) 584 * Within the E$ tag 64-bit value, the EC_state field(s) is(are) interpreted 585 * as follows: 586 * - for a 1MB E$, EC_state0 is in bits <2:0> 587 * - for a 4MB E$, EC_state0 is in bits <2:0>, EC_state1 is in 588 * bits <5:3>, EC_state2 is in bits <8:6>, EC_state3 is 589 * in bits <11:9> 590 * - for an 8MB E$, EC_state0 is in bits <2:0>, EC_state1 is in 591 * bits <5:3>, EC_state2 is in bits <8:6>, EC_state3 is 592 * in bits <11:9>, EC_state4 is in bits <14:12>, EC_state5 593 * is in bits <17:15>, EC_state6 is in bits <20:18>, 594 * EC_state7 is in bits <23:21> 595 * Note that each EC_state field contains a value representing the state 596 * of its corresponding subblock. 597 * 598 */ 599 /* 600 * Jaguar changes from Cheetah/Cheetah+ Ecache: 601 * 602 * The Jaguar Ecache is similiar to that used for Cheetah/Cheetah+ with a 603 * couple of differences : 604 * - Jaguar Ecache only comes in 4MB and 8MB versions. 605 * - 8MB E$ has 2 64 byte subblocks per line. 606 * - 4MB E$ has 1 64 byte subblock per line. 607 * 608 * An E$ tag for a particular E$ line can be read via a diagnostic ASI 609 * as a 64-bit value. 610 * Within the E$ tag 64-bit value, the EC_tag field is interpreted as follows: 611 * - for a 4MB E$, the EC_tag is in bits <41:21> and corresponds 612 * to physical address bits <41:21> 613 * - for a 8MB E$, the EC_tag is in bits <41:22> and corresponds 614 * to physical address bits <41:22> 615 * 616 * The Jaguar E$ tag also contains LRU field in bit <42> which must be 617 * masked off when the tag value is being compared to a PA. 618 * 619 * Within the E$ tag 64-bit value, the EC_state field(s) is(are) interpreted 620 * as follows: 621 * - for 4MB E$, EC_state0 is in bits <2:0> 622 * - for 8MB E$, EC_state0 is in bits <2:0>, EC_state1 is in bits <5:3>. 623 * Each EC_state field contains a value representing the state of its 624 * corresponding subblock. 625 * 626 * Note that the subblock size and state values are the same for both 627 * Cheetah/Cheetah+ and Jaguar. 628 */ 629 630 /* Ecache sizes */ 631 #define CH_ECACHE_8M_SIZE 0x800000 632 #define CH_ECACHE_4M_SIZE 0x400000 633 #define CH_ECACHE_1M_SIZE 0x100000 634 635 #define PN_L2_SIZE 0x200000 636 #define PN_L2_LINESIZE 64 637 #define PN_L2_ECC_WORDS 2 638 #define PN_L2_NWAYS 4 639 #define PN_L2_SET_SIZE (PN_L2_SIZE / PN_L2_NWAYS) 640 #define PN_L2_MAX_SET (PN_L2_SIZE - PN_L2_SET_SIZE) 641 #define PN_L2_DATA_ECC_SEL 0x200000 /* bit 21 selects ECC */ 642 #define PN_L2_ECC_LO_REG 0x20 /* bit 5 set for L2 tag access */ 643 #define PN_L2_INDEX_MASK 0x7ffc0 /* bits 18:6 */ 644 #define PN_L2_WAY_INCR 0x80000 /* l2-ec-way = <20:19> */ 645 #define PN_L2_WAY_LIM INT64_C(0x200000) 646 #define PN_L2_WAY_SHIFT 19 647 #define PN_L2_WAY_MASK (3ULL << PN_L2_WAY_SHIFT) /* <20:19> */ 648 #define PN_L2_HW_ECC_SHIFT 22 /* Set to force HW ECC generation */ 649 #define PN_L2_SPLIT_EN_SHIFT 2 /* L2_Cache_Ctrl<2> = L2_split_en */ 650 651 #define PN_L3_SIZE 0x2000000 652 #define PN_L3_LINESIZE 64 653 #define PN_L3_NWAYS 4 654 #define PN_L3_SET_SIZE (PN_L3_SIZE / PN_L3_NWAYS) 655 #define PN_L3_MAX_SET (PN_L3_SIZE - PN_L3_SET_SIZE) 656 #define PN_L3_WAY_SHIFT 23 657 #define PN_L3_HW_ECC_SHIFT 25 /* Set to force HW ECC generation */ 658 #define PN_L3_TAG_RD_MASK 0x7fffc0 /* ec_tag = PA<22:6> */ 659 #define PN_L3_WAY_INCR 0x800000 /* ec_way = <24:23> */ 660 #define PN_L3_WAY_MASK (3ULL << PN_L3_WAY_SHIFT) /* <24:23> */ 661 #define PN_L3_WAY_LIM INT64_C(0x2000000) 662 #define PN_L3_SPLIT_EN_SHIFT 30 /* L3_Cache_Ctrl<30> = L3_split_en */ 663 664 /* Pcache Defines */ 665 #define PN_PCACHE_ADDR_MASK 0x1c0 /* PC_addr = <8:6> */ 666 #define PN_PCACHE_WAY_INCR 0x200 /* PC_way = <10:9> */ 667 #define PN_PCACHE_WORD_SHIFT 3 /* PC_dbl_word = <5:3> */ 668 #define PN_PCACHE_NWAYS 4 669 670 /* Cheetah Ecache is direct-mapped, Cheetah+ can be 2-way or direct-mapped */ 671 #define CH_ECACHE_NWAY 1 672 #if defined(CHEETAH_PLUS) 673 #define CHP_ECACHE_NWAY 2 674 #define PN_ECACHE_NWAY 4 675 #endif /* CHEETAH_PLUS */ 676 #if defined(JALAPENO) || defined(SERRANO) 677 #define JP_ECACHE_NWAY 4 678 #define JP_ECACHE_NWAY_SHIFT 2 679 #endif /* JALAPENO || SERRANO */ 680 681 /* Maximum Ecache size */ 682 #define CH_ECACHE_MAX_SIZE CH_ECACHE_8M_SIZE 683 684 /* Minimum Ecache line size */ 685 #define CH_ECACHE_MIN_LSIZE 64 686 687 /* Maximum Ecache line size - 8Mb Ecache has 512 byte linesize */ 688 #define CH_ECACHE_MAX_LSIZE 512 689 690 /* Size of Ecache data staging register size (see Cheetah PRM 10.7.2) */ 691 #define CH_ECACHE_STGREG_SIZE 32 692 #define CH_ECACHE_STGREG_TOTALSIZE 40 /* data regs + ecc */ 693 694 /* The number of staging registers containing data, for ASI_EC_DATA */ 695 #define CH_ECACHE_STGREG_NUM (CH_ECACHE_STGREG_SIZE / sizeof (uint64_t)) 696 697 /* Size of Ecache data subblock which has state field in Ecache tag */ 698 #define CH_ECACHE_SUBBLK_SIZE 64 699 #define CH_ECACHE_SUBBLK_SHIFT 6 700 701 #if defined(JALAPENO) || defined(SERRANO) 702 #define JP_ECACHE_MAX_LSIZE CH_ECACHE_SUBBLK_SIZE 703 #define JP_ECACHE_MAX_SIZE 0x400000 704 #endif /* JALAPENO || SERRANO */ 705 706 /* 707 * Maximum ecache setsize to support page coloring of heterogenous 708 * cheetah+ cpus. Max ecache setsize is calculated to be the max ecache size 709 * divided by the minimum associativity of the max ecache. 710 * 711 * NOTE: CHP_ECACHE_MAX_SIZE and CHP_ECACHE_MIN_NWAY need to be updated with 712 * new cheetah+ cpus. The maximum setsize may not necessarily be associated with 713 * the max ecache size if the cache associativity is large. If so, MAX_SETSIZE 714 * needs to be updated accordingly. 715 */ 716 #if defined(CHEETAH_PLUS) 717 #define CHP_ECACHE_MIN_NWAY 1 /* direct-mapped */ 718 #define CHP_ECACHE_MAX_SIZE CH_ECACHE_MAX_SIZE 719 #define CHP_ECACHE_MAX_SETSIZE (CHP_ECACHE_MAX_SIZE / CHP_ECACHE_MIN_NWAY) 720 #endif /* CHEETAH_PLUS */ 721 722 /* 723 * Bits to shift EC_tag field of E$ tag to form PA 724 * (See Cheetah PRM 10.7.4, Cheetah+ Delta PRM 10.7) 725 */ 726 #if defined(JALAPENO) || defined(SERRANO) 727 #define CH_ECTAG_PA_SHIFT 18 728 #elif defined(CHEETAH_PLUS) 729 #define CH_ECTAG_PA_SHIFT 2 730 #else /* CHEETAH_PLUS */ 731 #define CH_ECTAG_PA_SHIFT 1 732 #endif /* CHEETAH_PLUS */ 733 #define PN_L3TAG_PA_SHIFT 1 734 #define PN_L3TAG_PA_MASK 0xfffff000000 /* tag bits[43:24] */ 735 #define PN_L2TAG_PA_MASK 0x7fffff80000 /* tag bits[42:19] */ 736 737 #if defined(JALAPENO) || defined(SERRANO) 738 /* 739 * Macros for Jalapeno L2 Cache Tag/State/Parity 740 * 741 * +-----------+--------+--------+----------------------+ 742 * | - | EC_par |EC_state| EC_tag = PA[42:18] | 743 * +-----------+--------+--------+----------------------+ 744 * 63:29 28 27:25 24:0 745 */ 746 /* 747 * Constants representing the complete Jalapeno Ecache tag state: 748 */ 749 #define JP_ECSTATE_SIZE 3 /* three bits */ 750 #define JP_ECSTATE_MASK 0x7 /* three bit field */ 751 #define JP_ECSTATE_INV 0x0 /* invalid */ 752 #define JP_ECSTATE_SHR 0x1 /* shared */ 753 #define JP_ECSTATE_RES1 0x2 /* reserved */ 754 #define JP_ECSTATE_EXL 0x3 /* exclusive */ 755 #define JP_ECSTATE_RES2 0x4 /* reserved */ 756 #define JP_ECSTATE_OWN 0x5 /* owner */ 757 #define JP_ECSTATE_MOD 0x7 /* modified */ 758 #define JP_ECSTATE_RES3 0x6 /* reserved */ 759 #define JP_ECTAG_STATE_SHIFT 25 760 761 #define CH_ECSTATE_SIZE JP_ECSTATE_SIZE 762 #define CH_ECSTATE_MASK JP_ECSTATE_MASK 763 #define CH_ECSTATE_INV JP_ECSTATE_INV 764 #define CH_ECSTATE_SHR JP_ECSTATE_SHR 765 #define CH_ECSTATE_EXL JP_ECSTATE_EXL 766 #define CH_ECSTATE_OWN JP_ECSTATE_OWN 767 #define CH_ECSTATE_MOD JP_ECSTATE_MOD 768 #define CH_ECSTATE_RES1 JP_ECSTATE_RES1 769 #define CH_ECSTATE_OWS JP_ECSTATE_RES3 770 #define CH_ECSTATE_RES2 JP_ECSTATE_RES2 771 772 /* Number of subblock states per Ecache line. */ 773 #define CH_ECTAG_NSUBBLKS(totalsize) 1 774 775 /* Mask for Tag state(s) field, 3 bits per subblock state. */ 776 #define CH_ECTAG_STATE_SHIFT(subblk) JP_ECTAG_STATE_SHIFT 777 #define CH_ECTAG_STATE_MASK(totalsize) \ 778 ((uint64_t)(JP_ECSTATE_MASK<<JP_ECTAG_STATE_SHIFT)) 779 780 /* For a line to be invalid, all of its subblock states must be invalid. */ 781 #define CH_ECTAG_LINE_INVALID(totalsize, tag) \ 782 (((tag) & CH_ECTAG_STATE_MASK(totalsize)) == 0) 783 784 /* Build address mask for tag physical address bits. */ 785 #define CH_ECTAG_PA_MASK(setsize) P2ALIGN(C_AFAR_PA, (int)(setsize)) 786 787 /* Get physical address bits from the EC_tag field of an E$ tag */ 788 #define CH_ECTAG_TO_PA(setsize, tag) (((tag) << CH_ECTAG_PA_SHIFT) & \ 789 CH_ECTAG_PA_MASK(setsize)) 790 791 /* Given a physical address, compute index for subblock tag state. */ 792 #define CH_ECTAG_PA_TO_SUBBLK(totalsize, pa) 1 793 794 /* Given a physical address and assoc. tag, get the subblock state. */ 795 #define CH_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag) \ 796 (((tag) >> JP_ECTAG_STATE_SHIFT) & JP_ECSTATE_MASK) 797 798 #else /* JALAPENO || SERRANO */ 799 800 /* 801 * Constants representing the complete Cheetah Ecache tag state: 802 */ 803 #define CH_ECSTATE_SIZE 3 /* three bits per subblock */ 804 #define CH_ECSTATE_MASK 0x7 /* three bit field */ 805 #define CH_ECSTATE_INV 0x0 /* invalid */ 806 #define CH_ECSTATE_SHR 0x1 /* shared */ 807 #define CH_ECSTATE_EXL 0x2 /* exclusive */ 808 #define CH_ECSTATE_OWN 0x3 /* owner */ 809 #define CH_ECSTATE_MOD 0x4 /* modified */ 810 #define CH_ECSTATE_RES1 0x5 /* reserved */ 811 #define CH_ECSTATE_OWS 0x6 /* owner/shared */ 812 #define CH_ECSTATE_RES2 0x7 /* reserved */ 813 814 /* 815 * Macros for Cheetah Ecache tags 816 */ 817 818 /* Number of subblock states per Ecache line. */ 819 #define CH_ECTAG_NSUBBLKS(totalsize) ((totalsize) / CH_ECACHE_1M_SIZE) 820 821 /* Mask for Tag state(s) field, 3 bits per subblock state. */ 822 #define CH_ECTAG_STATE_SHIFT(subblk) (subblk * CH_ECSTATE_SIZE) 823 #define CH_ECTAG_STATE_MASK(totalsize) \ 824 ((uint64_t) \ 825 ((1 << (CH_ECTAG_NSUBBLKS(totalsize) * CH_ECSTATE_SIZE)) - 1)) 826 827 /* For a line to be invalid, all of its subblock states must be invalid. */ 828 #define CH_ECTAG_LINE_INVALID(totalsize, tag) \ 829 (((tag) & CH_ECTAG_STATE_MASK(totalsize)) == 0) 830 831 /* Build address mask for tag physical address bits. */ 832 #define CH_ECTAG_PA_MASK(setsize) P2ALIGN(C_AFAR_PA, (int)(setsize)) 833 834 /* Get physical address bits from the EC_tag field of an E$ tag */ 835 #define CH_ECTAG_TO_PA(setsize, tag) (((tag) >> CH_ECTAG_PA_SHIFT) & \ 836 CH_ECTAG_PA_MASK(setsize)) 837 838 /* Given a physical address, compute index for subblock tag state. */ 839 #define CH_ECTAG_PA_TO_SUBBLK(totalsize, pa) \ 840 (((pa) >> CH_ECACHE_SUBBLK_SHIFT) & (CH_ECTAG_NSUBBLKS(totalsize) - 1)) 841 842 /* Given a physical address and assoc. tag, get the subblock state. */ 843 #define CH_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag) \ 844 (((tag) >> \ 845 (CH_ECTAG_PA_TO_SUBBLK(totalsize, pa) * CH_ECSTATE_SIZE)) & \ 846 CH_ECSTATE_MASK) 847 #endif /* JALAPENO || SERRANO */ 848 849 /* Panther only has one EC_State field in the L3 tag */ 850 #define PN_L3_LINE_INVALID(tag) (((tag) & CH_ECSTATE_MASK) == 0) 851 852 /* Panther only has one State field in the L2 tag */ 853 #define PN_L2_LINE_INVALID(tag) (((tag) & CH_ECSTATE_MASK) == 0) 854 855 /* Get physical address bits from the EC_tag field of an L3$ tag */ 856 #define PN_L3TAG_TO_PA(tag) (((tag) & PN_L3TAG_PA_MASK) >> \ 857 PN_L3TAG_PA_SHIFT) 858 859 /* Get physical address bits from the tag field of an L2$ tag */ 860 #define PN_L2TAG_TO_PA(tag) ((tag) & PN_L2TAG_PA_MASK) 861 862 #if defined(JALAPENO) || defined(SERRANO) 863 /* 864 * Jalapeno L2 Cache ASI_ECACHE_FLUSH: 865 * +-------+-----------------+--------+---+-----+-------------+------+ 866 * | - | Port_ID | - | EC_Way | 1 | - | EC_Tag_Addr | - | 867 * +-------+-----------------+--------+---+-----+-------------+------+ 868 * 63:41 40:36 35:34 33:32 31 30:18 17:6 5:0 869 */ 870 871 #define JP_EC_TO_SET_SIZE_SHIFT 2 872 #define JP_ECACHE_IDX_DISP_FLUSH INT64_C(0x0000000080000000) 873 #define JP_ECFLUSH_PORTID_SHIFT 36 874 #define JP_ECFLUSH_EC_WAY_SHIFT 32 875 #define JP_EC_TAG_DATA_WAY_SHIFT JP_ECFLUSH_EC_WAY_SHIFT 876 #endif /* JALAPENO || SERRANO */ 877 878 /* 879 * Macros for Jaguar Ecache tags 880 */ 881 882 /* Ecache sizes */ 883 #define JG_ECACHE_8M_SIZE 0x800000 884 #define JG_ECACHE_4M_SIZE 0x400000 885 886 /* Jaguar E$ tag LRU mask */ 887 #define JG_LRU_MASK UINT64_C(0x0000040000000000) /* PA<42> LRU bit */ 888 889 /* 890 * Note that Jaguar and Cheetah/Cheetah+ have the same subblock state size 891 * so rather than duplicating existing defn's we can use the Cheetah+ versions 892 * in the Jaguar defn's below. 893 */ 894 /* Number of subblock states per Ecache line. */ 895 #define JG_ECTAG_NSUBBLKS(cachesize) ((cachesize) / JG_ECACHE_4M_SIZE) 896 897 /* Mask for Tag state(s) field, 3 bits per subblock state. */ 898 #define JG_ECTAG_STATE_MASK(totalsize) \ 899 ((uint64_t) \ 900 ((1 << (JG_ECTAG_NSUBBLKS(totalsize) * CH_ECSTATE_SIZE)) - 1)) 901 902 /* For a line to be invalid, all of its subblock states must be invalid. */ 903 #define JG_ECTAG_LINE_INVALID(totalsize, tag) \ 904 (((tag) & JG_ECTAG_STATE_MASK(totalsize)) == 0) 905 906 /* Build address mask for tag physical address bits. */ 907 #define JG_ECTAG_PA_MASK(setsize) P2ALIGN(((~JG_LRU_MASK) & C_AFAR_PA), \ 908 (int)(setsize)) 909 910 /* Get physical address bits from the EC_tag field of an E$ tag */ 911 #define JG_ECTAG_TO_PA(setsize, tag) ((tag & JG_ECTAG_PA_MASK(setsize))) 912 913 /* Given a physical address, compute index for subblock tag state. */ 914 #define JG_ECTAG_PA_TO_SUBBLK(totalsize, pa) \ 915 (((pa) >> CH_ECACHE_SUBBLK_SHIFT) & (JG_ECTAG_NSUBBLKS(totalsize) - 1)) 916 917 /* Given a physical address and assoc. tag, get the subblock state. */ 918 #define JG_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag) \ 919 (((tag) >> \ 920 (JG_ECTAG_PA_TO_SUBBLK(totalsize, pa) * CH_ECSTATE_SIZE)) & \ 921 CH_ECSTATE_MASK) 922 923 924 #if defined(CHEETAH_PLUS) 925 /* 926 * Cheetah+ Tag ECC Bit and Displacement Flush Bit in Ecache Tag Access. 927 * See Cheetah+ Delta PRM 10.7 928 */ 929 #define CHP_ECACHE_IDX_TAG_ECC INT64_C(0x0000000000800000) 930 #define CHP_ECACHE_IDX_DISP_FLUSH INT64_C(0x0000000001000000) 931 #define PN_L2_IDX_DISP_FLUSH INT64_C(0x0000000000800000) 932 #define PN_L3_IDX_DISP_FLUSH INT64_C(0x0000000004000000) 933 #endif /* CHEETAH_PLUS */ 934 935 /* 936 * Macros for Cheetah Dcache diagnostic accesses. 937 */ 938 939 /* 940 * Dcache Index Mask for bits from *AFAR*. Note that Dcache is virtually 941 * indexed, so only bits [12:5] are valid from the AFAR. This 942 * means we have to search through the 4 ways + bit 13 (i.e. we have 943 * to try 8 indexes). 944 */ 945 #define CH_DCACHE_IDX_MASK 0x01fe0 946 #define CH_DCACHE_IDX_INCR 0x02000 947 #define CH_DCACHE_IDX_LIMIT 0x10000 948 #define CH_DCACHE_NWAY 4 949 #define CH_DCACHE_WAY_MASK 0x0c000 950 #define CH_DCACHE_WAY_SHIFT 14 951 #define CH_DCIDX_TO_WAY(idx) (((idx) & CH_DCACHE_WAY_MASK) >> \ 952 CH_DCACHE_WAY_SHIFT) 953 #define CH_DCTAG_PA_MASK INT64_C(0x000007ffffffe000) 954 #define CH_DCTAG_PA_SHIFT 12 955 #define CH_DCTAG_VALID_BIT INT64_C(0x0000000000000001) 956 #define CH_DCTAG_LINE_INVALID(tag) (((tag) & CH_DCTAG_VALID_BIT) == 0) 957 #define CH_DCIDX_TO_ADDR(idx) ((idx) & CH_DCACHE_IDX_MASK) 958 #define CH_DCTAG_TO_PA(tag) (((tag) << CH_DCTAG_PA_SHIFT) & \ 959 CH_DCTAG_PA_MASK) 960 #define CH_DCTAG_MATCH(tag, pa) (!CH_DCTAG_LINE_INVALID(tag) && \ 961 ((pa) & CH_DCTAG_PA_MASK) == CH_DCTAG_TO_PA(tag)) 962 #define CH_DCSNTAG_MASK INT64_C(0x000007ffffffe000) 963 #define CH_DCSNTAG_TO_PA(tag) ((tag << CH_DCTAG_PA_SHIFT) \ 964 & CH_DCSNTAG_MASK) 965 #define CH_DCUTAG_TO_UTAG(tag) ((tag) & 0xff) 966 #define CH_DCUTAG_TO_VA(tag) ((tag & 0xff) << 14) 967 #define CH_DCUTAG_IDX_MASK 0x03fe0 968 #define CH_DC_DATA_REG_SIZE 32 969 #define CH_DC_UTAG_MASK 0xff 970 #if defined(CHEETAH_PLUS) || defined(JALAPENO) || defined(SERRANO) 971 #define CHP_DCTAG_PARMASK INT64_C(0x000000007ffffffe) 972 #define CHP_DCSNTAG_PARMASK INT64_C(0x000000007ffffffe) 973 #define CHP_DCTAG_MASK INT64_C(0x000003ffffffe000) 974 #define CHP_DCSNTAG_MASK INT64_C(0x000003ffffffe000) 975 #define CHP_DCWAY_MASK INT64_C(0x0000000000003fe0) 976 #define CHP_DCUTAG_TO_UTAG(tag) ((tag) & 0xffff) 977 #define CHP_DCPATAG_TO_PA(tag) ((tag << CH_DCTAG_PA_SHIFT) \ 978 & CHP_DCTAG_MASK) 979 #define CHP_DCSNTAG_TO_PA(tag) ((tag << CH_DCTAG_PA_SHIFT) \ 980 & CHP_DCSNTAG_MASK) 981 #define CHP_DC_IDX(dcp) ((dcp->dc_idx & 0x1fc0) >> 5) 982 #define CHP_DCTAG_PARITY(tag) (tag & CHP_DC_TAG) 983 #define CHP_DCSNTAG_PARITY(tag) (tag & CHP_DC_SNTAG) 984 #define CHP_DC_TAG 0x1 985 #define CHP_DC_SNTAG 0x2 986 #define PN_DC_DATA_PARITY_SHIFT 8 987 #define PN_DC_DATA_PARITY_MASK 0xff 988 #define PN_DC_DATA_ALL_PARITY_MASK 0xffffffff 989 #endif /* CHEETAH_PLUS || JALAPENO || SERRANO */ 990 #define PN_DC_DATA_PARITY_BIT_SHIFT 16 991 992 /* 993 * Macros for Cheetah Icache diagnostic accesses. 994 */ 995 996 /* 997 * Icache Index Mask for bits from *AFAR*. Note that the Icache is virtually 998 * indexed for Panther and physically indexed for other CPUs. For Panther, 999 * we obtain an index by looking at bits[12:6] of the AFAR PA and we check 1000 * both lines associated with bit 13 = 0 or 1 (total of 8 entries to check). 1001 * For non-Panther CPUs we get our index by just looking at bits[12:5] of 1002 * the AFAR PA (total of 4 entries to check). The Icache index is also 1003 * confusing because we need to shift the virtual address bits left by one 1004 * for the index. 1005 */ 1006 #define CH_ICACHE_IDX_MASK 0x01fe0 1007 #define PN_ICACHE_IDX_MASK 0x03fc0 1008 #define PN_ICACHE_VA_IDX_MASK 0x01fc0 1009 #define CH_ICACHE_IDX_SHIFT 1 1010 #define CH_ICACHE_IDX_INCR 0x04000 1011 #define PN_ICACHE_IDX_INCR 0x08000 1012 #define CH_ICACHE_IDX_LIMIT 0x10000 1013 #define PN_ICACHE_IDX_LIMIT 0x20000 1014 #define CH_ICACHE_NWAY 4 1015 #define CH_ICACHE_WAY_MASK 0x0c000 1016 #define CH_ICACHE_WAY_SHIFT 14 1017 #define PN_ICACHE_WAY_MASK 0x18000 1018 #define PN_ICACHE_WAY_SHIFT 15 1019 #define CH_ICTAG_PA 0x00 1020 #define CH_ICTAG_UTAG 0x08 1021 #define CH_ICTAG_UPPER 0x10 1022 #define CH_ICTAG_LOWER 0x30 1023 #define CH_ICTAG_TMASK 0x3f 1024 #define CH_ICPATAG_MASK INT64_C(0x000007ffffffe000) 1025 #define CH_ICPATAG_LBITS 0xff /* lower 8 bits undefined */ 1026 #define CH_ICPATAG_SHIFT 5 1027 #define CH_ICIDX_TO_WAY(idx) (((idx) & CH_ICACHE_WAY_MASK) >> \ 1028 CH_ICACHE_WAY_SHIFT) 1029 #define PN_ICIDX_TO_WAY(idx) (((idx) & PN_ICACHE_WAY_MASK) >> \ 1030 PN_ICACHE_WAY_SHIFT) 1031 #define CH_ICIDX_TO_ADDR(idx) (((idx) >> CH_ICACHE_IDX_SHIFT) & \ 1032 CH_ICACHE_IDX_MASK) 1033 #define PN_ICIDX_TO_ADDR(idx) (((idx) >> CH_ICACHE_IDX_SHIFT) & \ 1034 PN_ICACHE_IDX_MASK) 1035 #define CH_ICPATAG_TO_PA(tag) (((tag) << CH_ICPATAG_SHIFT) & \ 1036 CH_ICPATAG_MASK) 1037 #define CH_ICPATAG_MATCH(tag, pa) (CH_ICPATAG_TO_PA(tag) == \ 1038 ((pa) & CH_ICPATAG_MASK)) 1039 #define CH_ICUTAG_MASK INT64_C(0x00000000001fe000) 1040 #define CH_ICUTAG_TO_UTAG(tag) (((tag) >> 38) & 0xff) 1041 #define CH_ICUTAG_TO_VA(tag) (((tag) >> 25) & CH_ICUTAG_MASK) 1042 #define CH_ICSNTAG_MASK INT64_C(0x000007ffffffe000) 1043 #define CH_ICSNTAG_TO_PA(tag) (((tag) << 5) & CH_ICSNTAG_MASK) 1044 #define CH_ICLOWER_VALID INT64_C(0x0004000000000000) 1045 #define CH_ICUPPER_VALID INT64_C(0x0004000000000000) 1046 #define CH_ICLOWER_TO_VPRED(lower) (((lower) >> 46) & 0xf) 1047 #define CH_ICUPPER_TO_VPRED(upper) (((upper) >> 46) & 0xf) 1048 #if defined(CHEETAH_PLUS) 1049 #define CH_ICTAG_MATCH(icp, pa) (((icp->ic_lower | icp->ic_upper) & \ 1050 CH_ICLOWER_VALID) && \ 1051 CH_ICPATAG_MATCH(icp->ic_patag, pa)) 1052 #define PN_ICUTAG_TO_VA(tag) ((tag >> 24) & PN_ICUTAG_MASK) 1053 #else /* CHEETAH_PLUS */ 1054 #define CH_ICTAG_MATCH(icp, pa) ((icp->ic_lower & CH_ICLOWER_VALID) &&\ 1055 CH_ICPATAG_MATCH(icp->ic_patag, pa)) 1056 #define PN_ICUTAG_TO_VA(tag) 0 1057 #endif /* CHEETAH_PLUS */ 1058 1059 #define CH_IC_DATA_REG_SIZE 64 1060 #define PN_IC_DATA_REG_SIZE 128 1061 #if defined(CHEETAH_PLUS) || defined(JALAPENO) || defined(SERRANO) 1062 #define CHP_IC_IDX(icp) ((icp->ic_idx & 0x3fc0) >> 6) 1063 #define PN_IC_IDX(icp) ((icp->ic_idx & 0x7f80) >> 7) 1064 #define CHP_ICPATAG_MASK INT64_C(0x000003ffffffe000) 1065 #define CHP_ICSNTAG_MASK INT64_C(0x000003ffffffe000) 1066 #define CHP_ICUTAG_MASK INT64_C(0x00000000001fe000) 1067 #define PN_ICUTAG_MASK INT64_C(0x00000000003fc000) 1068 #define CHP_ICWAY_MASK INT64_C(0x0000000000003fe0) 1069 #define CHP_ICPATAG_TO_PA(tag) ((tag << 5) & CHP_ICPATAG_MASK) 1070 #define CHP_ICSNTAG_TO_PA(tag) ((tag << 5) & CHP_ICSNTAG_MASK) 1071 #define CHP_ICUTAG_TO_VA(tag) ((tag >> 25) & CHP_ICUTAG_MASK) 1072 #define CHP_ICPATAG_PARMASK INT64_C(0x0000003fffffff00) 1073 #define CHP_ICSNTAG_PARMASK INT64_C(0x0000003fffffff00) 1074 1075 /* 1076 * Cheetah+ Icache data parity masks, see Cheetah+ Delta PRM 7.3 1077 * PC-relative instructions have different bits protected by parity. 1078 * Predecode bit 7 is not parity protected and indicates if the instruction 1079 * is PC-relative or not. 1080 */ 1081 #define CH_ICDATA_PRED_ISPCREL INT64_C(0x0000008000000000) 1082 #define CHP_ICDATA_PCREL_PARMASK INT64_C(0x0000039ffffff800) 1083 #define CHP_ICDATA_NPCREL_PARMASK INT64_C(0x000003bfffffffff) 1084 #define PN_ICDATA_PARITY_BIT_MASK INT64_C(0x40000000000) 1085 #define CHP_ICTAG_PARITY(tag) (tag & CHP_IC_TAG) 1086 #define CHP_ICSNTAG_PARITY(tag) (tag & CHP_IC_SNTAG) 1087 #define CHP_IC_TAG 0x1 1088 #define CHP_IC_SNTAG 0x2 1089 #endif /* CHEETAH_PLUS || JALAPENO || SERRANO */ 1090 #if defined(CHEETAH_PLUS) 1091 #define PN_IPB_TAG_ADDR_LINESIZE 0x40 1092 #define PN_IPB_TAG_ADDR_MAX 0x3c0 1093 #endif /* CHEETAH_PLUS */ 1094 1095 /* 1096 * Macros for Pcache diagnostic accesses. 1097 */ 1098 #define CH_PC_WAY_MASK 0x600 1099 #define CH_PC_WAY_SHIFT 9 1100 #define CH_PCIDX_TO_WAY(idx) (((idx) & CH_PC_WAY_MASK) >> \ 1101 CH_PC_WAY_SHIFT) 1102 #define CH_PC_DATA_REG_SIZE 64 1103 #define CH_PCACHE_NWAY 4 1104 #define PN_PC_PARITY_SHIFT 50 1105 #define PN_PC_PARITY_MASK 0xff 1106 #define PN_PC_PARITY_BITS(status) \ 1107 (((status) >> PN_PC_PARITY_SHIFT) & PN_PC_PARITY_MASK) 1108 #define CH_PC_IDX_ADR(pcp) ((pcp->pc_idx & 0x1c0) >> 6) 1109 #define CH_PCTAG_ADDR_SHIFT 6 1110 #define CH_PC_PA_MASK 0x7ffffffffc0 1111 #define CH_PCTAG_TO_VA(tag) ((tag) << CH_PCTAG_ADDR_SHIFT) 1112 #define CH_PCSTAG_TO_PA(tag) (((tag) << CH_PCTAG_ADDR_SHIFT) & \ 1113 CH_PC_PA_MASK) 1114 #define CH_PCTAG_BNK0_VALID_MASK 0x2000000000000000 1115 #define CH_PCTAG_BNK1_VALID_MASK 0x1000000000000000 1116 #define CH_PCTAG_BNK0_INVALID(tag) (((tag) & CH_PCTAG_BNK0_VALID_MASK) == \ 1117 0) 1118 #define CH_PCTAG_BNK1_INVALID(tag) (((tag) & CH_PCTAG_BNK1_VALID_MASK) == \ 1119 0) 1120 1121 /* 1122 * CPU Log Out Structure parameters. 1123 * This structure is filled in by the Error Trap handlers and captures the 1124 * Ecache/Dcache/Icache line(s) associated with the AFAR. 1125 * For Cheetah Phase II, this structure is filled in at the TL=0 code. For 1126 * Cheetah Phase III, this will be filled in at the trap handlers. 1127 */ 1128 1129 /* 1130 * We use this to mark the LOGOUT structure as invalid. Note that 1131 * this cannot be a valid AFAR, as AFAR bits outside of [41:5] should always 1132 * be zero. 1133 */ 1134 #define LOGOUT_INVALID_U32 0xecc1ecc1 1135 #define LOGOUT_INVALID_L32 0xecc1ecc1 1136 #define LOGOUT_INVALID UINT64_C(0xecc1ecc1ecc1ecc1) 1137 1138 /* 1139 * Max number of TLs to support for Fast ECC or Cache Parity Errors 1140 * at TL>0. Traps are OK from TL=1-2, at TL>=3, we will Red Mode. 1141 */ 1142 #define CH_ERR_TL1_TLMAX 2 1143 1144 /* 1145 * Software traps used by TL>0 handlers. 1146 */ 1147 #define SWTRAP_0 0 /* Used by Fast ECC */ 1148 #define SWTRAP_1 1 /* Used by Dcache Parity */ 1149 #define SWTRAP_2 2 /* Used by Icache Parity */ 1150 1151 /* 1152 * Bit mask defines for various Cheetah Error conditions. 1153 */ 1154 #define CH_ERR_FECC 0x01 /* Data/Event is Fast ECC */ 1155 #define CH_ERR_IPE 0x02 /* Data/Event is Icache Parity Error */ 1156 #define CH_ERR_DPE 0x04 /* Data/Event is Dcache Parity Error */ 1157 #define CH_ERR_PANIC 0x08 /* Fatal error in TL>0 handler */ 1158 #define CH_ERR_TL 0x10 /* Error occured at TL>0 */ 1159 #define CH_ERR_ME_SHIFT 8 /* If multiple errors, shift left newest */ 1160 #define CH_ERR_ME_FLAGS(x) ((x) >> CH_ERR_ME_SHIFT) 1161 1162 /* 1163 * Defines for Bit8 (CH_ERR_TSTATE_IC_ON) and Bit9 (CH_ERR_TSTATE_DC_ON) 1164 * in %tstate, which is used to remember D$/I$ state on Fast ECC handler 1165 * at TL>0. Note that DCU_IC=0x1, DCU_DC=0x2. 1166 */ 1167 #define CH_ERR_G2_TO_TSTATE_SHFT 10 1168 #define CH_ERR_DCU_TO_TSTATE_SHFT 8 1169 #define CH_ERR_TSTATE_IC_ON (DCU_IC << CH_ERR_DCU_TO_TSTATE_SHFT) 1170 #define CH_ERR_TSTATE_DC_ON (DCU_DC << CH_ERR_DCU_TO_TSTATE_SHFT) 1171 1172 /* 1173 * Multiple offset TL>0 handler structure elements 1174 */ 1175 #define CH_ERR_TL1_DATA (CH_ERR_TL1_LOGOUT + CH_CLO_DATA) 1176 #define CH_ERR_TL1_SDW_DATA (CH_ERR_TL1_LOGOUT + CH_CLO_SDW_DATA) 1177 #define CH_ERR_TL1_NEST_CNT (CH_ERR_TL1_LOGOUT + CH_CLO_NEST_CNT) 1178 #define CH_ERR_TL1_AFAR (CH_ERR_TL1_DATA + CH_CHD_AFAR) 1179 #define CH_ERR_TL1_AFSR (CH_ERR_TL1_DATA + CH_CHD_AFSR) 1180 #define CH_ERR_TL1_SDW_AFAR (CH_ERR_TL1_SDW_DATA + CH_CHD_AFAR) 1181 #define CH_ERR_TL1_SDW_AFSR (CH_ERR_TL1_SDW_DATA + CH_CHD_AFSR) 1182 #define CH_ERR_TL1_SDW_AFSR_EXT (CH_ERR_TL1_SDW_DATA + CH_CHD_AFSR_EXT) 1183 1184 /* 1185 * Interval for deferred CEEN reenable 1186 */ 1187 #define CPU_CEEN_DELAY_SECS 6 1188 1189 /* 1190 * flags for flt_trapped_ce variable 1191 */ 1192 #define CE_CEEN_DEFER 0x1 /* no CEEN reenable in trap handler */ 1193 #define CE_CEEN_NODEFER 0x2 /* reenable CEEN in handler */ 1194 #define CE_CEEN_TIMEOUT 0x4 /* CE caught by timeout */ 1195 #define CE_CEEN_TRAPPED 0x8 /* CE caught by trap */ 1196 1197 /* 1198 * default value for cpu_ce_not_deferred 1199 */ 1200 #if defined(JALAPENO) || defined(SERRANO) 1201 #define CPU_CE_NOT_DEFERRED (C_AFSR_CECC_ERRS & \ 1202 ~(C_AFSR_CE | C_AFSR_FRC | C_AFSR_RCE | C_AFSR_EMC)) 1203 #else /* JALAPENO || SERRANO */ 1204 #if defined(CHEETAH_PLUS) 1205 #define CPU_CE_NOT_DEFERRED (C_AFSR_CECC_ERRS & \ 1206 ~(C_AFSR_CE | C_AFSR_EMC | C_AFSR_THCE)) 1207 #else /* CHEETAH_PLUS */ 1208 #define CPU_CE_NOT_DEFERRED (C_AFSR_CECC_ERRS & \ 1209 ~(C_AFSR_CE | C_AFSR_EMC)) 1210 #endif /* CHEETAH_PLUS */ 1211 #endif /* JALAPENO || SERRANO */ 1212 1213 #define CPU_CE_NOT_DEFERRED_EXT (C_AFSR_EXT_CECC_ERRS & \ 1214 ~(C_AFSR_L3_THCE)) 1215 1216 #if defined(CHEETAH_PLUS) 1217 1218 /* 1219 * VA for primary and shadow AFSR/AFAR/AFSR_EXT registers 1220 */ 1221 #define ASI_SHADOW_REG_VA 0x8 1222 #define ASI_AFSR_EXT_VA 0x10 1223 #define ASI_SHADOW_AFSR_EXT_VA 0x18 1224 1225 /* 1226 * Bitmask for keeping track of core parking in ECC error handlers. 1227 * We share a register that also saves the DCUCR value so we use 1228 * one of the reserved bit positions of the DCUCR register to keep 1229 * track of whether or not we have parked our sibling core. 1230 */ 1231 #define PN_PARKED_OTHER_CORE 0x20 1232 #define PN_BOTH_CORES_RUNNING 0x3 1233 1234 /* 1235 * Panther EMU Activity Status Register Bits. 1236 */ 1237 #define ASI_EMU_ACT_STATUS_VA 0x18 1238 #define MCU_ACT_STATUS INT64_C(0x0000000000000001) 1239 #define SIU_ACT_STATUS INT64_C(0x0000000000000002) 1240 #endif /* CHEETAH_PLUS */ 1241 1242 #define ASI_CESR_ID_VA 0x40 /* ASI_CESRD_ID per-core registers */ 1243 1244 #define ASR_DISPATCH_CONTROL %asr18 1245 #define ASR_DISPATCH_CONTROL_BPE 0x20 1246 1247 /* 1248 * Max number of E$ sets logged in ch_diag_data structure 1249 */ 1250 #define CHD_EC_DATA_SETS 4 /* max 4 sets of E$ data */ 1251 1252 /* 1253 * Definitions for Panther TLB parity handling. 1254 */ 1255 #define PN_ITLB_NWAYS 2 1256 #define PN_NUM_512_ITLBS 1 1257 #define PN_DTLB_NWAYS 2 1258 #define PN_NUM_512_DTLBS 2 1259 #define PN_SFSR_PARITY_SHIFT 12 1260 #define PN_ITLB_PGSZ_SHIFT 22 1261 #define PN_ITLB_PGSZ_MASK (7 << PN_ITLB_PGSZ_SHIFT) 1262 #define PN_DTLB_PGSZ0_SHIFT 16 1263 #define PN_DTLB_PGSZ0_MASK (7 << PN_DTLB_PGSZ0_SHIFT) 1264 #define PN_DTLB_PGSZ1_SHIFT 19 1265 #define PN_DTLB_PGSZ1_MASK (7 << PN_DTLB_PGSZ1_SHIFT) 1266 #define PN_DTLB_PGSZ_MASK (PN_DTLB_PGSZ1_MASK | PN_DTLB_PGSZ0_MASK) 1267 #define PN_DTLB_T512_0 (2 << 16) 1268 #define PN_DTLB_T512_1 (3 << 16) 1269 #define PN_TLO_INFO_IMMU_SHIFT 14 1270 #define PN_TLO_INFO_IMMU (1 << PN_TLO_INFO_IMMU_SHIFT) 1271 #define PN_TLO_INFO_TL1_SHIFT 13 1272 #define PN_TLO_INFO_TL1 (1 << PN_TLO_INFO_TL1_SHIFT) 1273 #define PN_ITLB_T512 (2 << 16) 1274 #define PN_TLB_ACC_IDX_SHIFT 3 1275 #define PN_TLB_ACC_WAY_BIT (1 << 11) 1276 #define PN_TLB_DIAGACC_OFFSET 0x40000 /* Diag Acc ASI VA offset */ 1277 /* 1278 * tag parity = XOR(Size[2:0],Global,VA[63:21],Context[12:0]) 1279 * which requires looking at both the tag and the data. 1280 */ 1281 #define PN_TLB_TAG_PARITY_TAG_MASK 0xffffffffffe01fff 1282 #define PN_TLB_TAG_PARITY_DATA_MASK 0x6001400000000001 1283 /* data parity = XOR(NFO,IE,PA[42:13],CP,CV,E,P,W) */ 1284 #define PN_TLB_DATA_PARITY_DATA_MASK 0x180087ffffffe03e 1285 1286 #ifdef _KERNEL 1287 1288 #ifndef _ASM 1289 1290 #include <sys/kstat.h> 1291 1292 /* 1293 * One Ecache data element, 32 bytes of data, 8 bytes of ECC. 1294 * See Cheetah PRM 10.7.2. 1295 */ 1296 typedef struct ec_data_elm { 1297 uint64_t ec_d8[CH_ECACHE_STGREG_NUM]; 1298 uint64_t ec_eccd; /* EC_data_ECC field */ 1299 } ec_data_elm_t; 1300 1301 /* 1302 * L2 and L3 cache data captured by cpu log out code. 1303 * See Cheetah PRM 10.7.4. 1304 */ 1305 typedef struct ch_ec_data { 1306 uint64_t ec_logflag; /* Flag indicates if data was logged */ 1307 uint64_t ec_idx; /* Ecache index */ 1308 uint64_t ec_way; /* Ecache way */ 1309 uint64_t ec_tag; /* Ecache Tag */ 1310 uint64_t ec_tag_ecc; /* Ecache Tag ECC (Cheetah+ only) */ 1311 ec_data_elm_t ec_data[CH_ECACHE_SUBBLK_SIZE/CH_ECACHE_STGREG_SIZE]; 1312 } ch_ec_data_t; 1313 1314 /* 1315 * Dcache data captured by cpu log out code and get_dcache_dtag. 1316 * See Cheetah PRM 10.6.[1-4]. 1317 */ 1318 typedef struct ch_dc_data { 1319 uint64_t dc_logflag; /* Flag indicates if data was logged */ 1320 uint64_t dc_idx; /* Dcache index */ 1321 uint64_t dc_way; /* Dcache way */ 1322 uint64_t dc_tag; /* Tag/Valid Fields */ 1323 uint64_t dc_utag; /* Microtag */ 1324 uint64_t dc_sntag; /* Snoop Tag */ 1325 uint64_t dc_data[CH_DC_DATA_REG_SIZE/sizeof (uint64_t)]; /* Data */ 1326 uint64_t dc_pn_data_parity; /* Data parity bits for Panther */ 1327 } ch_dc_data_t; 1328 1329 /* 1330 * Icache data captured by cpu log out code and get_icache_dtag. 1331 * See Cheetah PRM 10.4.[1-3]. 1332 */ 1333 typedef struct ch_ic_data { 1334 uint64_t ic_logflag; /* Flag indicates if data was logged */ 1335 uint64_t ic_idx; /* Icache index */ 1336 uint64_t ic_way; /* Icache way */ 1337 uint64_t ic_patag; /* Physical address tag */ 1338 uint64_t ic_utag; /* Microtag */ 1339 uint64_t ic_upper; /* Upper valid/predict tag */ 1340 uint64_t ic_lower; /* Lower valid/predict tag */ 1341 uint64_t ic_sntag; /* Snoop Tag */ 1342 uint64_t ic_data[PN_IC_DATA_REG_SIZE/sizeof (uint64_t)]; /* Data */ 1343 } ch_ic_data_t; 1344 1345 /* 1346 * Pcache data captured by get_pcache_dtag 1347 */ 1348 typedef struct ch_pc_data { 1349 uint64_t pc_logflag; /* Flag indicates if data was logged */ 1350 uint64_t pc_idx; /* Pcache index */ 1351 uint64_t pc_way; /* Pcache way */ 1352 uint64_t pc_status; /* Pcache status data */ 1353 uint64_t pc_tag; /* Tag/Valid Fields */ 1354 uint64_t pc_sntag; /* Snoop Tag */ 1355 uint64_t pc_data[CH_PC_DATA_REG_SIZE/sizeof (uint64_t)]; /* Data */ 1356 } ch_pc_data_t; 1357 1358 /* 1359 * CPU Error State 1360 */ 1361 typedef struct ch_cpu_errors { 1362 uint64_t afsr; /* AFSR */ 1363 uint64_t afar; /* AFAR */ 1364 /* 1365 * The following registers don't exist on cheetah 1366 */ 1367 uint64_t shadow_afsr; /* Shadow AFSR */ 1368 uint64_t shadow_afar; /* Shadow AFAR */ 1369 uint64_t afsr_ext; /* AFSR1_EXT */ 1370 uint64_t shadow_afsr_ext; /* AFSR2_EXT */ 1371 uint64_t afar2; /* AFAR2 - Serrano only */ 1372 } ch_cpu_errors_t; 1373 1374 /* 1375 * CPU logout structures. 1376 * NOTE: These structures should be the same for Cheetah, Cheetah+, 1377 * Jaguar, Panther, and Jalapeno since the assembler code relies 1378 * on one set of offsets. Panther is the only processor that 1379 * uses the chd_l2_data field since it has both L3 and L2 caches. 1380 */ 1381 typedef struct ch_diag_data { 1382 uint64_t chd_afar; /* AFAR */ 1383 uint64_t chd_afsr; /* AFSR */ 1384 uint64_t chd_afsr_ext; /* AFSR_EXT */ 1385 uint64_t chd_afar2; /* AFAR2 - Serrano only */ 1386 ch_ec_data_t chd_ec_data[CHD_EC_DATA_SETS]; /* Ecache data */ 1387 ch_ec_data_t chd_l2_data[PN_L2_NWAYS]; /* L2 cache data */ 1388 ch_dc_data_t chd_dc_data; /* Dcache data */ 1389 ch_ic_data_t chd_ic_data; /* Icache data */ 1390 } ch_diag_data_t; 1391 1392 1393 /* 1394 * Top level CPU logout structure. 1395 * clo_flags is used to hold information such as trap type, trap level, 1396 * CEEN value, etc that is needed by the individual trap handlers. Not 1397 * all fields in this flag are used by all trap handlers but when they 1398 * are used, here's how they are laid out: 1399 * 1400 * |-------------------------------------------------------| 1401 * | | trap type | trap level | |UCEEN| |NCEEN|CEEN| 1402 * |-------------------------------------------------------| 1403 * 63 19 12 11 8 3 2 1 0 1404 * 1405 * Note that the *CEEN bits correspond exactly to the same bit positions 1406 * that are used in the error enable register. 1407 */ 1408 typedef struct ch_cpu_logout { 1409 uint64_t clo_flags; /* Information about this trap */ 1410 uint64_t clo_nest_cnt; /* To force an upper bound */ 1411 ch_diag_data_t clo_data; /* Diag data for primary AFAR */ 1412 ch_diag_data_t clo_sdw_data; /* Diag data for shadow AFAR */ 1413 } ch_cpu_logout_t; 1414 1415 typedef struct ch_tte_entry { 1416 uint64_t ch_tte_tag; 1417 uint64_t ch_tte_data; 1418 } ch_tte_entry_t; 1419 1420 /* 1421 * Top level CPU logout structure for TLB parity errors. 1422 * 1423 * tlo_logflag - Flag indicates if data was logged 1424 * tlo_info - Used to keep track of a number of values: 1425 * itlb pgsz - Page size of the VA whose lookup in the ITLB caused 1426 * the exception (from ASI_IMMU_TAG_ACCESS_EXT.) 1427 * dtlb pgsz1 - Page size of the VA whose lookup in the DTLB T512_1 1428 * caused the exception (from ASI_DMMU_TAG_ACCESS_EXT.). 1429 * dtlb pgsz0 - Page size of the VA whose lookup in the DTLB T512_0 1430 * caused the exception (from ASI_DMMU_TAG_ACCESS_EXT.). 1431 * immu - Trap is the result of an ITLB exception if immu == 1. 1432 * Otherwise, for DTLB exceptions immu == 0. 1433 * tl1 - Set to 1 if the exception occured at TL>0. 1434 * context - Context of the VA whose lookup in the TLB caused the 1435 * exception (from ASI_[I|D]MMU_TAG_ACCESS.) 1436 * |---------------------------------------------------------------------| 1437 * |...| itlb pgsz | dtlb pgsz1 | dtlb pgsz0 |...| immu | tl1 | context | 1438 * |---------------------------------------------------------------------| 1439 * 24 22 21 19 18 16 14 13 12 0 1440 * 1441 * tlo_addr - VA that cause the MMU exception trap. 1442 * tlo_pc - PC where the exception occured. 1443 * tlo_itlb_tte - TTEs that were in the ITLB after the trap at the index 1444 * specific to the VA and page size in question. 1445 * tlo_dtlb_tte - TTEs that were in the DTLB after the trap at the index 1446 * specific to the VA and page size in question. 1447 */ 1448 typedef struct pn_tlb_logout { 1449 uint64_t tlo_logflag; 1450 uint64_t tlo_info; 1451 uint64_t tlo_addr; 1452 uint64_t tlo_pc; 1453 ch_tte_entry_t tlo_itlb_tte[PN_ITLB_NWAYS * PN_NUM_512_ITLBS]; 1454 ch_tte_entry_t tlo_dtlb_tte[PN_DTLB_NWAYS * PN_NUM_512_DTLBS]; 1455 } pn_tlb_logout_t; 1456 1457 #if defined(CPU_IMP_L1_CACHE_PARITY) 1458 /* 1459 * Parity error logging structure. 1460 */ 1461 typedef union ch_l1_parity_log { 1462 struct { 1463 int cpl_way; /* Faulty line way */ 1464 int cpl_off; /* Faulty line offset */ 1465 int cpl_tag; /* Faulty tags list */ 1466 int cpl_lcnt; /* Faulty cache lines */ 1467 ch_dc_data_t cpl_dc[CH_DCACHE_NWAY]; /* D$ data nWays */ 1468 ch_pc_data_t cpl_pc[CH_PCACHE_NWAY]; /* P$ data nWays */ 1469 int cpl_cache; /* error in D$ or P$? */ 1470 } dpe; /* D$ parity error */ 1471 struct { 1472 int cpl_way; /* Faulty line way */ 1473 int cpl_off; /* Faulty line offset */ 1474 int cpl_tag; /* Faulty tags list */ 1475 int cpl_lcnt; /* Faulty cache lines */ 1476 ch_ic_data_t cpl_ic[CH_ICACHE_NWAY]; /* I$ data nWays */ 1477 } ipe; /* I$ parity error */ 1478 } ch_l1_parity_log_t; 1479 1480 #endif /* CPU_IMP_L1_CACHE_PARITY */ 1481 1482 /* 1483 * Error at TL>0 CPU logout data. 1484 * Needs some extra space to save %g registers and miscellaneous info. 1485 */ 1486 typedef struct ch_err_tl1_data { 1487 uint64_t ch_err_tl1_g1; /* Saved %g1 */ 1488 uint64_t ch_err_tl1_g2; /* Saved %g2 */ 1489 uint64_t ch_err_tl1_g3; /* Saved %g3 */ 1490 uint64_t ch_err_tl1_g4; /* Saved %g4 */ 1491 uint64_t ch_err_tl1_g5; /* Saved %g5 */ 1492 uint64_t ch_err_tl1_g6; /* Saved %g6 */ 1493 uint64_t ch_err_tl1_g7; /* Saved %g7 */ 1494 uint64_t ch_err_tl1_tpc; /* Trap PC */ 1495 uint64_t ch_err_tl1_flags; /* miscellaneous flags */ 1496 uint64_t ch_err_tl1_tmp; /* some handlers may use as tmp */ 1497 ch_cpu_logout_t ch_err_tl1_logout; /* logout */ 1498 } ch_err_tl1_data_t; 1499 1500 /* Indices into chsm_outstanding and friends */ 1501 #define CACHE_SCRUBBER_INFO_E 0 1502 #define CACHE_SCRUBBER_INFO_D 1 1503 #define CACHE_SCRUBBER_INFO_I 2 1504 1505 /* We define 3 scrubbers: E$, D$, and I$ */ 1506 #define CACHE_SCRUBBER_COUNT 3 1507 1508 /* 1509 * The ch_scrub_misc structure contains miscellaneous bookkeeping 1510 * items for scrubbing the I$, D$, and E$. 1511 * 1512 * For a description of the use of chsm_core_state and why it's not needed 1513 * on Jaguar, see the comment above cpu_scrub_cpu_setup() in us3_cheetahplus.c. 1514 */ 1515 typedef struct ch_scrub_misc { 1516 uint32_t chsm_outstanding[CACHE_SCRUBBER_COUNT]; 1517 /* outstanding requests */ 1518 int chsm_flush_index[CACHE_SCRUBBER_COUNT]; 1519 /* next line to flush */ 1520 int chsm_enable[CACHE_SCRUBBER_COUNT]; 1521 /* is this scrubber enabled on this core? */ 1522 int chsm_ecache_nlines; /* no. of E$ lines */ 1523 int chsm_ecache_busy; /* keeps track if cpu busy */ 1524 int chsm_icache_nlines; /* no. of I$ lines */ 1525 int chsm_core_state; /* which core the scrubber is */ 1526 /* running on (Panther only) */ 1527 } ch_scrub_misc_t; 1528 1529 /* 1530 * Cheetah module private data structure. One of these is allocated for 1531 * each valid cpu at setup time and is pointed to by the machcpu 1532 * "cpu_private" pointer. For Cheetah, we have the miscellaneous scrubber 1533 * variables and cpu log out structures for Fast ECC traps at TL=0, 1534 * Disrupting (correctable) traps and Deferred (asynchronous) traps. For 1535 * Disrupting traps only one log out structure is needed because we cannot 1536 * get a TL>0 disrupting trap since it obeys IE. For Deferred traps we 1537 * cannot get a TL>0 because we turn off NCEEN during log out capture. E$ 1538 * set size (E$ size / nways) is saved here to avoid repeated calculations. 1539 * NB: The ch_err_tl1_data_t structures cannot cross a page boundary 1540 * because we use physical addresses to access them. We ensure this 1541 * by allocating them near the front of cheetah_private_t, which is 1542 * aligned on PAGESIZE (8192) via kmem_cache_create, and by ASSERTing 1543 * sizeof (chpr_tl1_err_data) <= CH_ECACHE_MAX_LSIZE in the 1544 * cpu_init_private routines. 1545 * NB: chpr_icache_size and chpr_icache_linesize need to be at the front 1546 * of cheetah_private_t because putting them after chpr_tl1_err_data 1547 * would make their offsets > 4195. 1548 */ 1549 typedef struct cheetah_private { 1550 int chpr_icache_size; 1551 int chpr_icache_linesize; 1552 ch_err_tl1_data_t chpr_tl1_err_data[CH_ERR_TL1_TLMAX]; 1553 ch_scrub_misc_t chpr_scrub_misc; 1554 int chpr_ec_set_size; 1555 ch_cpu_logout_t chpr_fecctl0_logout; 1556 ch_cpu_logout_t chpr_cecc_logout; 1557 ch_cpu_logout_t chpr_async_logout; 1558 pn_tlb_logout_t chpr_tlb_logout; 1559 uint64_t chpr_fpras_timestamp[FPRAS_NCOPYOPS]; 1560 hrtime_t chpr_ceptnr_seltime; 1561 int chpr_ceptnr_id; 1562 } cheetah_private_t; 1563 1564 #endif /* _ASM */ 1565 1566 #endif /* _KERNEL */ 1567 1568 #ifdef __cplusplus 1569 } 1570 #endif 1571 1572 #endif /* _SYS_CHEETAHREGS_H */ 1573