1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/time.h> 30 #include <sys/cpuvar.h> 31 #include <sys/dditypes.h> 32 #include <sys/ddipropdefs.h> 33 #include <sys/ddi_impldefs.h> 34 #include <sys/sunddi.h> 35 #include <sys/esunddi.h> 36 #include <sys/sunndi.h> 37 #include <sys/platform_module.h> 38 #include <sys/errno.h> 39 #include <sys/conf.h> 40 #include <sys/modctl.h> 41 #include <sys/promif.h> 42 #include <sys/promimpl.h> 43 #include <sys/prom_plat.h> 44 #include <sys/cmn_err.h> 45 #include <sys/sysmacros.h> 46 #include <sys/mem_cage.h> 47 #include <sys/kobj.h> 48 #include <sys/utsname.h> 49 #include <sys/cpu_sgnblk_defs.h> 50 #include <sys/atomic.h> 51 #include <sys/kdi_impl.h> 52 53 #include <sys/sgsbbc.h> 54 #include <sys/sgsbbc_iosram.h> 55 #include <sys/sgsbbc_iosram_priv.h> 56 #include <sys/sgsbbc_mailbox.h> 57 #include <sys/sgsgn.h> 58 #include <sys/serengeti.h> 59 #include <sys/sgfrutypes.h> 60 #include <sys/machsystm.h> 61 #include <sys/sbd_ioctl.h> 62 #include <sys/sbd.h> 63 #include <sys/sbdp_mem.h> 64 #include <sys/sgcn.h> 65 66 #include <sys/memnode.h> 67 #include <vm/vm_dep.h> 68 #include <vm/page.h> 69 70 #include <sys/cheetahregs.h> 71 #include <sys/plat_ecc_unum.h> 72 #include <sys/plat_ecc_dimm.h> 73 74 #include <sys/lgrp.h> 75 76 static int sg_debug = 0; 77 78 #ifdef DEBUG 79 #define DCMNERR if (sg_debug) cmn_err 80 #else 81 #define DCMNERR 82 #endif 83 84 int (*p2get_mem_unum)(int, uint64_t, char *, int, int *); 85 86 /* local functions */ 87 static void cpu_sgn_update(ushort_t sgn, uchar_t state, 88 uchar_t sub_state, int cpuid); 89 90 91 /* 92 * Local data. 93 * 94 * iosram_write_ptr is a pointer to iosram_write(). Because of 95 * kernel dynamic linking, we can't get to the function by name, 96 * but we can look up its address, and store it in this variable 97 * instead. 98 * 99 * We include the extern for iosram_write() here not because we call 100 * it, but to force compilation errors if its prototype doesn't 101 * match the prototype of iosram_write_ptr. 102 * 103 * The same issues apply to iosram_read() and iosram_read_ptr. 104 */ 105 /*CSTYLED*/ 106 extern int iosram_write (int, uint32_t, caddr_t, uint32_t); 107 static int (*iosram_write_ptr)(int, uint32_t, caddr_t, uint32_t) = NULL; 108 /*CSTYLED*/ 109 extern int iosram_read (int, uint32_t, caddr_t, uint32_t); 110 static int (*iosram_read_ptr)(int, uint32_t, caddr_t, uint32_t) = NULL; 111 112 113 /* 114 * Variable to indicate if the date should be obtained from the SC or not. 115 */ 116 int todsg_use_sc = FALSE; /* set the false at the beginning */ 117 118 /* 119 * Preallocation of spare tsb's for DR 120 * 121 * We don't allocate spares for Wildcat since TSBs should come 122 * out of memory local to the node. 123 */ 124 #define IOMMU_PER_SCHIZO 2 125 int serengeti_tsb_spares = (SG_MAX_IO_BDS * SG_SCHIZO_PER_IO_BD * 126 IOMMU_PER_SCHIZO); 127 128 /* 129 * sg_max_ncpus is the maximum number of CPUs supported on lw8. 130 * sg_max_ncpus is set to be smaller than NCPU to reduce the amount of 131 * memory the logs take up until we have a dynamic log memory allocation 132 * solution. 133 */ 134 int sg_max_ncpus = (12 * 2); /* (max # of processors * # of cores/proc) */ 135 136 /* 137 * variables to control mailbox message timeouts. 138 * These can be patched via /etc/system or mdb. 139 */ 140 int sbbc_mbox_default_timeout = MBOX_DEFAULT_TIMEOUT; 141 int sbbc_mbox_min_timeout = MBOX_MIN_TIMEOUT; 142 143 /* cached 'chosen' node_id */ 144 pnode_t chosen_nodeid = (pnode_t)0; 145 146 /* 147 * Table that maps memory slices to a specific memnode. 148 */ 149 int slice_to_memnode[SG_MAX_SLICE]; 150 151 /* 152 * We define and use LW8_MAX_CPU_BDS here instead of SG_MAX_CPU_BDS 153 * since a LW8 machine will never have a CPU/Mem board #5 (SB5). 154 * A LW8 machine can only have a maximum of three CPU/Mem boards, but 155 * the board numbers assigned are 0, 2, and 4. LW8_MAX_CPU_BDS is 156 * defined to be 5 since the entries in the domain_dimm_sids array 157 * are keyed by board number. Not perfect but some wasted space 158 * is avoided. 159 */ 160 #define LW8_MAX_CPU_BDS 5 161 162 plat_dimm_sid_board_t domain_dimm_sids[LW8_MAX_CPU_BDS]; 163 164 int 165 set_platform_tsb_spares() 166 { 167 return (MIN(serengeti_tsb_spares, MAX_UPA)); 168 } 169 170 #pragma weak mmu_init_large_pages 171 172 void 173 set_platform_defaults(void) 174 { 175 extern int watchdog_enable; 176 extern uint64_t xc_tick_limit_scale; 177 extern void mmu_init_large_pages(size_t); 178 179 #ifdef DEBUG 180 char *todsg_name = "todsg"; 181 ce_verbose_memory = 2; 182 ce_verbose_other = 2; 183 #endif /* DEBUG */ 184 185 watchdog_enable = TRUE; 186 watchdog_available = TRUE; 187 188 cpu_sgn_func = cpu_sgn_update; 189 190 #ifdef DEBUG 191 /* tod_module_name should be set to "todsg" from OBP property */ 192 if (tod_module_name && (strcmp(tod_module_name, todsg_name) == 0)) 193 prom_printf("Using todsg driver\n"); 194 else { 195 prom_printf("Force using todsg driver\n"); 196 tod_module_name = todsg_name; 197 } 198 #endif /* DEBUG */ 199 200 /* lw8 does not support forthdebug */ 201 forthdebug_supported = 0; 202 203 204 /* 205 * Some DR operations require the system to be sync paused. 206 * Sync pause on Serengeti could potentially take up to 4 207 * seconds to complete depending on the load on the SC. To 208 * avoid send_mond panics during such operations, we need to 209 * increase xc_tick_limit to a larger value on Serengeti by 210 * setting xc_tick_limit_scale to 5. 211 */ 212 xc_tick_limit_scale = 5; 213 214 if ((mmu_page_sizes == max_mmu_page_sizes) && 215 (mmu_ism_pagesize != DEFAULT_ISM_PAGESIZE)) { 216 if (&mmu_init_large_pages) 217 mmu_init_large_pages(mmu_ism_pagesize); 218 } 219 } 220 221 void 222 load_platform_modules(void) 223 { 224 if (modload("misc", "pcihp") < 0) { 225 cmn_err(CE_NOTE, "pcihp driver failed to load"); 226 } 227 } 228 229 /*ARGSUSED*/ 230 int 231 plat_cpu_poweron(struct cpu *cp) 232 { 233 int (*serengeti_cpu_poweron)(struct cpu *) = NULL; 234 235 serengeti_cpu_poweron = 236 (int (*)(struct cpu *))modgetsymvalue("sbdp_cpu_poweron", 0); 237 238 if (serengeti_cpu_poweron == NULL) 239 return (ENOTSUP); 240 else 241 return ((serengeti_cpu_poweron)(cp)); 242 } 243 244 /*ARGSUSED*/ 245 int 246 plat_cpu_poweroff(struct cpu *cp) 247 { 248 int (*serengeti_cpu_poweroff)(struct cpu *) = NULL; 249 250 serengeti_cpu_poweroff = 251 (int (*)(struct cpu *))modgetsymvalue("sbdp_cpu_poweroff", 0); 252 253 if (serengeti_cpu_poweroff == NULL) 254 return (ENOTSUP); 255 else 256 return ((serengeti_cpu_poweroff)(cp)); 257 } 258 259 #ifdef DEBUG 260 pgcnt_t serengeti_cage_size_limit; 261 #endif 262 263 /* Preferred minimum cage size (expressed in pages)... for DR */ 264 pgcnt_t serengeti_minimum_cage_size = 0; 265 266 void 267 set_platform_cage_params(void) 268 { 269 extern pgcnt_t total_pages; 270 extern struct memlist *phys_avail; 271 272 if (kernel_cage_enable) { 273 pgcnt_t preferred_cage_size; 274 275 preferred_cage_size = 276 MAX(serengeti_minimum_cage_size, total_pages / 256); 277 #ifdef DEBUG 278 if (serengeti_cage_size_limit) 279 preferred_cage_size = serengeti_cage_size_limit; 280 #endif 281 /* 282 * Post copies obp into the lowest slice. This requires the 283 * cage to grow upwards 284 */ 285 kcage_range_init(phys_avail, KCAGE_UP, preferred_cage_size); 286 } 287 288 kcage_startup_dir = KCAGE_UP; 289 290 /* Only note when the cage is off since it should always be on. */ 291 if (!kcage_on) 292 cmn_err(CE_NOTE, "!DR Kernel Cage is DISABLED"); 293 } 294 295 #define ALIGN(x, a) ((a) == 0 ? (uint64_t)(x) : \ 296 (((uint64_t)(x) + (uint64_t)(a) - 1l) & ~((uint64_t)(a) - 1l))) 297 298 void 299 update_mem_bounds(int brd, uint64_t base, uint64_t sz) 300 { 301 uint64_t end; 302 int mnode; 303 304 end = base + sz - 1; 305 306 /* 307 * First see if this board already has a memnode associated 308 * with it. If not, see if this slice has a memnode. This 309 * covers the cases where a single slice covers multiple 310 * boards (cross-board interleaving) and where a single 311 * board has multiple slices (1+GB DIMMs). 312 */ 313 if ((mnode = plat_lgrphand_to_mem_node(brd)) == -1) { 314 if ((mnode = slice_to_memnode[PA_2_SLICE(base)]) == -1) 315 mnode = mem_node_alloc(); 316 plat_assign_lgrphand_to_mem_node(brd, mnode); 317 } 318 319 /* 320 * Align base at 16GB boundary 321 */ 322 base = ALIGN(base, (1ul << PA_SLICE_SHIFT)); 323 324 while (base < end) { 325 slice_to_memnode[PA_2_SLICE(base)] = mnode; 326 base += (1ul << PA_SLICE_SHIFT); 327 } 328 } 329 330 /* 331 * Dynamically detect memory slices in the system by decoding 332 * the cpu memory decoder registers at boot time. 333 */ 334 void 335 plat_fill_mc(pnode_t nodeid) 336 { 337 uint64_t mc_addr, mask; 338 uint64_t mc_decode[SG_MAX_BANKS_PER_MC]; 339 uint64_t base, size; 340 uint32_t regs[4]; 341 int len; 342 int local_mc; 343 int portid; 344 int boardid; 345 int i; 346 347 if ((prom_getprop(nodeid, "portid", (caddr_t)&portid) < 0) || 348 (portid == -1)) 349 return; 350 351 /* 352 * Decode the board number from the MC portid 353 */ 354 boardid = SG_PORTID_TO_BOARD_NUM(portid); 355 356 /* 357 * The "reg" property returns 4 32-bit values. The first two are 358 * combined to form a 64-bit address. The second two are for a 359 * 64-bit size, but we don't actually need to look at that value. 360 */ 361 len = prom_getproplen(nodeid, "reg"); 362 if (len != (sizeof (uint32_t) * 4)) { 363 prom_printf("Warning: malformed 'reg' property\n"); 364 return; 365 } 366 if (prom_getprop(nodeid, "reg", (caddr_t)regs) < 0) 367 return; 368 mc_addr = ((uint64_t)regs[0]) << 32; 369 mc_addr |= (uint64_t)regs[1]; 370 371 /* 372 * Figure out whether the memory controller we are examining 373 * belongs to this CPU or a different one. 374 */ 375 if (portid == cpunodes[CPU->cpu_id].portid) 376 local_mc = 1; 377 else 378 local_mc = 0; 379 380 for (i = 0; i < SG_MAX_BANKS_PER_MC; i++) { 381 mask = SG_REG_2_OFFSET(i); 382 383 /* 384 * If the memory controller is local to this CPU, we use 385 * the special ASI to read the decode registers. 386 * Otherwise, we load the values from a magic address in 387 * I/O space. 388 */ 389 if (local_mc) 390 mc_decode[i] = lddmcdecode(mask & MC_OFFSET_MASK); 391 else 392 mc_decode[i] = lddphysio((mc_addr | mask)); 393 394 if (mc_decode[i] >> MC_VALID_SHIFT) { 395 /* 396 * The memory decode register is a bitmask field, 397 * so we can decode that into both a base and 398 * a span. 399 */ 400 base = MC_BASE(mc_decode[i]) << PHYS2UM_SHIFT; 401 size = MC_UK2SPAN(mc_decode[i]); 402 update_mem_bounds(boardid, base, size); 403 } 404 } 405 } 406 407 /* 408 * This routine is run midway through the boot process. By the time we get 409 * here, we know about all the active CPU boards in the system, and we have 410 * extracted information about each board's memory from the memory 411 * controllers. We have also figured out which ranges of memory will be 412 * assigned to which memnodes, so we walk the slice table to build the table 413 * of memnodes. 414 */ 415 /* ARGSUSED */ 416 void 417 plat_build_mem_nodes(prom_memlist_t *list, size_t nelems) 418 { 419 int slice; 420 pfn_t basepfn; 421 pgcnt_t npgs; 422 423 mem_node_pfn_shift = PFN_SLICE_SHIFT; 424 mem_node_physalign = (1ull << PA_SLICE_SHIFT); 425 426 for (slice = 0; slice < SG_MAX_SLICE; slice++) { 427 if (slice_to_memnode[slice] == -1) 428 continue; 429 basepfn = (uint64_t)slice << PFN_SLICE_SHIFT; 430 npgs = 1ull << PFN_SLICE_SHIFT; 431 mem_node_add_slice(basepfn, basepfn + npgs - 1); 432 } 433 } 434 435 int 436 plat_pfn_to_mem_node(pfn_t pfn) 437 { 438 int node; 439 440 node = slice_to_memnode[PFN_2_SLICE(pfn)]; 441 442 return (node); 443 } 444 445 /* 446 * Serengeti support for lgroups. 447 * 448 * On Serengeti, an lgroup platform handle == board number. 449 * 450 * Mappings between lgroup handles and memnodes are managed 451 * in addition to mappings between memory slices and memnodes 452 * to support cross-board interleaving as well as multiple 453 * slices per board (e.g. >1GB DIMMs). The initial mapping 454 * of memnodes to lgroup handles is determined at boot time. 455 * A DR addition of memory adds a new mapping. A DR copy-rename 456 * swaps mappings. 457 */ 458 459 /* 460 * Macro for extracting the board number from the CPU id 461 */ 462 #define CPUID_TO_BOARD(id) (((id) >> 2) & 0x7) 463 464 /* 465 * Return the platform handle for the lgroup containing the given CPU 466 * 467 * For Serengeti, lgroup platform handle == board number 468 */ 469 lgrp_handle_t 470 plat_lgrp_cpu_to_hand(processorid_t id) 471 { 472 return (CPUID_TO_BOARD(id)); 473 } 474 475 /* 476 * Platform specific lgroup initialization 477 */ 478 void 479 plat_lgrp_init(void) 480 { 481 int i; 482 extern uint32_t lgrp_expand_proc_thresh; 483 extern uint32_t lgrp_expand_proc_diff; 484 485 /* 486 * Initialize lookup tables to invalid values so we catch 487 * any illegal use of them. 488 */ 489 for (i = 0; i < SG_MAX_SLICE; i++) { 490 slice_to_memnode[i] = -1; 491 } 492 493 /* 494 * Set tuneables for Serengeti architecture 495 * 496 * lgrp_expand_proc_thresh is the minimum load on the lgroups 497 * this process is currently running on before considering 498 * expanding threads to another lgroup. 499 * 500 * lgrp_expand_proc_diff determines how much less the remote lgroup 501 * must be loaded before expanding to it. 502 * 503 * Bandwidth is maximized on Serengeti by spreading load across 504 * the machine. The impact to inter-thread communication isn't 505 * too costly since remote latencies are relatively low. These 506 * values equate to one CPU's load and so attempt to spread the 507 * load out across as many lgroups as possible one CPU at a time. 508 */ 509 lgrp_expand_proc_thresh = LGRP_LOADAVG_THREAD_MAX; 510 lgrp_expand_proc_diff = LGRP_LOADAVG_THREAD_MAX; 511 } 512 513 /* 514 * Platform notification of lgroup (re)configuration changes 515 */ 516 /*ARGSUSED*/ 517 void 518 plat_lgrp_config(lgrp_config_flag_t evt, uintptr_t arg) 519 { 520 update_membounds_t *umb; 521 lgrp_config_mem_rename_t lmr; 522 lgrp_handle_t shand, thand; 523 int snode, tnode; 524 525 switch (evt) { 526 527 case LGRP_CONFIG_MEM_ADD: 528 umb = (update_membounds_t *)arg; 529 update_mem_bounds(umb->u_board, umb->u_base, umb->u_len); 530 531 break; 532 533 case LGRP_CONFIG_MEM_DEL: 534 /* We don't have to do anything */ 535 536 break; 537 538 case LGRP_CONFIG_MEM_RENAME: 539 /* 540 * During a DR copy-rename operation, all of the memory 541 * on one board is moved to another board -- but the 542 * addresses/pfns and memnodes don't change. This means 543 * the memory has changed locations without changing identity. 544 * 545 * Source is where we are copying from and target is where we 546 * are copying to. After source memnode is copied to target 547 * memnode, the physical addresses of the target memnode are 548 * renamed to match what the source memnode had. Then target 549 * memnode can be removed and source memnode can take its 550 * place. 551 * 552 * To do this, swap the lgroup handle to memnode mappings for 553 * the boards, so target lgroup will have source memnode and 554 * source lgroup will have empty target memnode which is where 555 * its memory will go (if any is added to it later). 556 * 557 * Then source memnode needs to be removed from its lgroup 558 * and added to the target lgroup where the memory was living 559 * but under a different name/memnode. The memory was in the 560 * target memnode and now lives in the source memnode with 561 * different physical addresses even though it is the same 562 * memory. 563 */ 564 shand = arg & 0xffff; 565 thand = (arg & 0xffff0000) >> 16; 566 snode = plat_lgrphand_to_mem_node(shand); 567 tnode = plat_lgrphand_to_mem_node(thand); 568 569 plat_assign_lgrphand_to_mem_node(thand, snode); 570 plat_assign_lgrphand_to_mem_node(shand, tnode); 571 572 /* 573 * Remove source memnode of copy rename from its lgroup 574 * and add it to its new target lgroup 575 */ 576 lmr.lmem_rename_from = shand; 577 lmr.lmem_rename_to = thand; 578 579 lgrp_config(LGRP_CONFIG_MEM_RENAME, (uintptr_t)snode, 580 (uintptr_t)&lmr); 581 582 break; 583 584 default: 585 break; 586 } 587 } 588 589 /* 590 * Return latency between "from" and "to" lgroups 591 * 592 * This latency number can only be used for relative comparison 593 * between lgroups on the running system, cannot be used across platforms, 594 * and may not reflect the actual latency. It is platform and implementation 595 * specific, so platform gets to decide its value. It would be nice if the 596 * number was at least proportional to make comparisons more meaningful though. 597 * NOTE: The numbers below are supposed to be load latencies for uncached 598 * memory divided by 10. 599 */ 600 int 601 plat_lgrp_latency(lgrp_handle_t from, lgrp_handle_t to) 602 { 603 /* 604 * Return min remote latency when there are more than two lgroups 605 * (root and child) and getting latency between two different lgroups 606 * or root is involved 607 */ 608 if (lgrp_optimizations() && (from != to || 609 from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE)) 610 return (28); 611 else 612 return (23); 613 } 614 615 /* ARGSUSED */ 616 void 617 plat_freelist_process(int mnode) 618 { 619 } 620 621 /* 622 * Find dip for chosen IOSRAM 623 */ 624 dev_info_t * 625 find_chosen_dip(void) 626 { 627 dev_info_t *dip; 628 char master_sbbc[MAXNAMELEN]; 629 int nodeid; 630 uint_t tunnel; 631 632 /* 633 * find the /chosen SBBC node, prom interface will handle errors 634 */ 635 nodeid = prom_chosennode(); 636 /* 637 * get the 'iosram' property from the /chosen node 638 */ 639 if (prom_getprop(nodeid, IOSRAM_CHOSEN_PROP, (caddr_t)&tunnel) <= 0) { 640 SBBC_ERR(CE_PANIC, "No iosram property found! \n"); 641 } 642 643 if (prom_phandle_to_path((phandle_t)tunnel, master_sbbc, 644 sizeof (master_sbbc)) < 0) { 645 SBBC_ERR1(CE_PANIC, "prom_phandle_to_path(%d) failed\n", 646 tunnel); 647 } 648 649 chosen_nodeid = nodeid; 650 651 /* 652 * load and attach the sgsbbc driver. 653 * This will also attach all the sgsbbc driver instances 654 */ 655 if (i_ddi_attach_hw_nodes("sgsbbc") != DDI_SUCCESS) { 656 cmn_err(CE_WARN, "sgsbbc failed to load\n"); 657 } 658 /* translate a path name to a dev_info_t */ 659 dip = e_ddi_hold_devi_by_path(master_sbbc, 0); 660 if ((dip == NULL) || (ddi_get_nodeid(dip) != tunnel)) { 661 cmn_err(CE_PANIC, 662 "e_ddi_hold_devi_by_path(%x) failed for SBBC\n", tunnel); 663 } 664 665 /* make sure devi_ref is ZERO */ 666 ndi_rele_devi(dip); 667 DCMNERR(CE_CONT, "Chosen IOSRAM is at %s \n", master_sbbc); 668 669 return (dip); 670 } 671 672 void 673 load_platform_drivers(void) 674 { 675 int ret; 676 677 /* 678 * Load the mc-us3 memory driver. 679 */ 680 if (i_ddi_attach_hw_nodes("mc-us3") != DDI_SUCCESS) 681 cmn_err(CE_WARN, "mc-us3 failed to load"); 682 else 683 (void) ddi_hold_driver(ddi_name_to_major("mc-us3")); 684 685 /* 686 * Initialize the chosen IOSRAM before its clients 687 * are loaded. 688 */ 689 (void) find_chosen_dip(); 690 691 /* 692 * Load the environmentals driver (sgenv) 693 * 694 * We need this driver to handle events from the SC when state 695 * changes occur in the environmental data. 696 */ 697 if (i_ddi_attach_hw_nodes("sgenv") != DDI_SUCCESS) 698 cmn_err(CE_WARN, "sgenv failed to load"); 699 700 /* 701 * Ideally, we'd do this in set_platform_defaults(), but 702 * at that point it's too early to look up symbols. 703 */ 704 iosram_write_ptr = (int (*)(int, uint32_t, caddr_t, uint32_t)) 705 modgetsymvalue("iosram_write", 0); 706 707 if (iosram_write_ptr == NULL) { 708 DCMNERR(CE_WARN, "load_platform_defaults: iosram_write()" 709 " not found; signatures will not be updated\n"); 710 } else { 711 /* 712 * The iosram read ptr is only needed if we can actually 713 * write CPU signatures, so only bother setting it if we 714 * set a valid write pointer, above. 715 */ 716 iosram_read_ptr = (int (*)(int, uint32_t, caddr_t, uint32_t)) 717 modgetsymvalue("iosram_read", 0); 718 719 if (iosram_read_ptr == NULL) 720 DCMNERR(CE_WARN, "load_platform_defaults: iosram_read()" 721 " not found\n"); 722 } 723 724 /* 725 * Set todsg_use_sc to TRUE so that we will be getting date 726 * from the SC. 727 */ 728 todsg_use_sc = TRUE; 729 730 /* 731 * Now is a good time to activate hardware watchdog (if one exists). 732 */ 733 mutex_enter(&tod_lock); 734 if (watchdog_enable) 735 ret = tod_ops.tod_set_watchdog_timer(watchdog_timeout_seconds); 736 mutex_exit(&tod_lock); 737 if (ret != 0) 738 printf("Hardware watchdog enabled\n"); 739 740 plat_ecc_init(); 741 } 742 743 /* 744 * No platform drivers on this platform 745 */ 746 char *platform_module_list[] = { 747 (char *)0 748 }; 749 750 /*ARGSUSED*/ 751 void 752 plat_tod_fault(enum tod_fault_type tod_bad) 753 { 754 } 755 int 756 plat_max_boards() 757 { 758 return (SG_MAX_BDS); 759 } 760 int 761 plat_max_io_units_per_board() 762 { 763 return (SG_MAX_IO_PER_BD); 764 } 765 int 766 plat_max_cmp_units_per_board() 767 { 768 return (SG_MAX_CMPS_PER_BD); 769 } 770 int 771 plat_max_cpu_units_per_board() 772 { 773 return (SG_MAX_CPUS_PER_BD); 774 } 775 776 int 777 plat_max_mc_units_per_board() 778 { 779 return (SG_MAX_CMPS_PER_BD); /* each CPU die has a memory controller */ 780 } 781 782 int 783 plat_max_mem_units_per_board() 784 { 785 return (SG_MAX_MEM_PER_BD); 786 } 787 788 int 789 plat_max_cpumem_boards(void) 790 { 791 return (LW8_MAX_CPU_BDS); 792 } 793 794 int 795 set_platform_max_ncpus(void) 796 { 797 return (sg_max_ncpus); 798 } 799 800 void 801 plat_dmv_params(uint_t *hwint, uint_t *swint) 802 { 803 *hwint = MAX_UPA; 804 *swint = 0; 805 } 806 807 static int (*sg_mbox)(sbbc_msg_t *, sbbc_msg_t *, time_t) = NULL; 808 809 /* 810 * Our nodename has been set, pass it along to the SC. 811 */ 812 void 813 plat_nodename_set(void) 814 { 815 sbbc_msg_t req; /* request */ 816 sbbc_msg_t resp; /* response */ 817 int rv; /* return value from call to mbox */ 818 struct nodename_info { 819 int32_t namelen; 820 char nodename[_SYS_NMLN]; 821 } nni; 822 823 /* 824 * find the symbol for the mailbox routine 825 */ 826 if (sg_mbox == NULL) 827 sg_mbox = (int (*)(sbbc_msg_t *, sbbc_msg_t *, time_t)) 828 modgetsymvalue("sbbc_mbox_request_response", 0); 829 830 if (sg_mbox == NULL) { 831 cmn_err(CE_NOTE, "!plat_nodename_set: sg_mbox not found\n"); 832 return; 833 } 834 835 /* 836 * construct the message telling the SC our nodename 837 */ 838 (void) strcpy(nni.nodename, utsname.nodename); 839 nni.namelen = (int32_t)strlen(nni.nodename); 840 841 req.msg_type.type = INFO_MBOX; 842 req.msg_type.sub_type = INFO_MBOX_NODENAME; 843 req.msg_status = 0; 844 req.msg_len = (int)(nni.namelen + sizeof (nni.namelen)); 845 req.msg_bytes = 0; 846 req.msg_buf = (caddr_t)&nni; 847 req.msg_data[0] = 0; 848 req.msg_data[1] = 0; 849 850 /* 851 * initialize the response back from the SC 852 */ 853 resp.msg_type.type = INFO_MBOX; 854 resp.msg_type.sub_type = INFO_MBOX_NODENAME; 855 resp.msg_status = 0; 856 resp.msg_len = 0; 857 resp.msg_bytes = 0; 858 resp.msg_buf = (caddr_t)0; 859 resp.msg_data[0] = 0; 860 resp.msg_data[1] = 0; 861 862 /* 863 * ship it and check for success 864 */ 865 rv = (sg_mbox)(&req, &resp, sbbc_mbox_default_timeout); 866 867 if (rv != 0) { 868 cmn_err(CE_NOTE, "!plat_nodename_set: sg_mbox retval %d\n", rv); 869 } else if (resp.msg_status != 0) { 870 cmn_err(CE_NOTE, "!plat_nodename_set: msg_status %d\n", 871 resp.msg_status); 872 } else { 873 DCMNERR(CE_NOTE, "!plat_nodename_set was successful\n"); 874 875 /* 876 * It is necessary to exchange capability the bitmap 877 * with SC before sending any ecc error information and 878 * indictment. We are calling the plat_ecc_capability_send() 879 * here just after sending the nodename successfully. 880 */ 881 rv = plat_ecc_capability_send(); 882 if (rv == 0) { 883 DCMNERR(CE_NOTE, "!plat_ecc_capability_send was" 884 "successful\n"); 885 } 886 } 887 } 888 889 /* 890 * flag to allow users switch between using OBP's 891 * prom_get_unum() and mc-us3 driver's p2get_mem_unum() 892 * (for main memory errors only). 893 */ 894 int sg_use_prom_get_unum = 0; 895 896 /* 897 * Debugging flag: set to 1 to call into obp for get_unum, or set it to 0 898 * to call into the unum cache system. This is the E$ equivalent of 899 * sg_use_prom_get_unum. 900 */ 901 int sg_use_prom_ecache_unum = 0; 902 903 /* used for logging ECC errors to the SC */ 904 #define SG_MEMORY_ECC 1 905 #define SG_ECACHE_ECC 2 906 #define SG_UNKNOWN_ECC (-1) 907 908 /* 909 * plat_get_mem_unum() generates a string identifying either the 910 * memory or E$ DIMM(s) during error logging. Depending on whether 911 * the error is E$ or memory related, the appropriate support 912 * routine is called to assist in the string generation. 913 * 914 * - For main memory errors we can use the mc-us3 drivers p2getunum() 915 * (or prom_get_unum() for debugging purposes). 916 * 917 * - For E$ errors we call sg_get_ecacheunum() to generate the unum (or 918 * prom_serengeti_get_ecacheunum() for debugging purposes). 919 */ 920 921 static int 922 sg_prom_get_unum(int synd_code, uint64_t paddr, char *buf, int buflen, 923 int *lenp) 924 { 925 if ((prom_get_unum(synd_code, (unsigned long long)paddr, 926 buf, buflen, lenp)) != 0) 927 return (EIO); 928 else if (*lenp <= 1) 929 return (EINVAL); 930 else 931 return (0); 932 } 933 934 /*ARGSUSED*/ 935 int 936 plat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id, 937 int flt_in_memory, ushort_t flt_status, char *buf, int buflen, int *lenp) 938 { 939 /* 940 * unum_func will either point to the memory drivers p2get_mem_unum() 941 * or to prom_get_unum() for memory errors. 942 */ 943 int (*unum_func)(int synd_code, uint64_t paddr, char *buf, 944 int buflen, int *lenp) = p2get_mem_unum; 945 946 /* 947 * check if it's a Memory or an Ecache error. 948 */ 949 if (flt_in_memory) { 950 /* 951 * It's a main memory error. 952 * 953 * For debugging we allow the user to switch between 954 * using OBP's get_unum and the memory driver's get_unum 955 * so we create a pointer to the functions and switch 956 * depending on the sg_use_prom_get_unum flag. 957 */ 958 if (sg_use_prom_get_unum) { 959 DCMNERR(CE_NOTE, "Using prom_get_unum from OBP"); 960 return (sg_prom_get_unum(synd_code, 961 P2ALIGN(flt_addr, 8), buf, buflen, lenp)); 962 } else if (unum_func != NULL) { 963 return (unum_func(synd_code, P2ALIGN(flt_addr, 8), 964 buf, buflen, lenp)); 965 } else { 966 return (ENOTSUP); 967 } 968 } else if (flt_status & ECC_ECACHE) { 969 /* 970 * It's an E$ error. 971 */ 972 if (sg_use_prom_ecache_unum) { 973 /* 974 * We call to OBP to handle this. 975 */ 976 DCMNERR(CE_NOTE, 977 "Using prom_serengeti_get_ecacheunum from OBP"); 978 if (prom_serengeti_get_ecacheunum(flt_bus_id, 979 P2ALIGN(flt_addr, 8), buf, buflen, lenp) != 0) { 980 return (EIO); 981 } 982 } else { 983 return (sg_get_ecacheunum(flt_bus_id, flt_addr, 984 buf, buflen, lenp)); 985 } 986 } else { 987 return (ENOTSUP); 988 } 989 990 return (0); 991 } 992 993 /* 994 * This platform hook gets called from mc_add_mem_unum_label() in the mc-us3 995 * driver giving each platform the opportunity to add platform 996 * specific label information to the unum for ECC error logging purposes. 997 */ 998 void 999 plat_add_mem_unum_label(char *unum, int mcid, int bank, int dimm) 1000 { 1001 char new_unum[UNUM_NAMLEN] = ""; 1002 int node = SG_PORTID_TO_NODEID(mcid); 1003 int board = SG_CPU_BD_PORTID_TO_BD_NUM(mcid); 1004 int position = SG_PORTID_TO_CPU_POSN(mcid); 1005 1006 /* 1007 * The mc-us3 driver deals with logical banks but for unum 1008 * purposes we need to use physical banks so that the correct 1009 * dimm can be physically located. Logical banks 0 and 2 1010 * make up physical bank 0. Logical banks 1 and 3 make up 1011 * physical bank 1. Here we do the necessary conversion. 1012 */ 1013 bank = (bank % 2); 1014 1015 if (dimm == -1) { 1016 SG_SET_FRU_NAME_NODE(new_unum, node); 1017 SG_SET_FRU_NAME_CPU_BOARD(new_unum, board); 1018 SG_SET_FRU_NAME_MODULE(new_unum, position); 1019 SG_SET_FRU_NAME_BANK(new_unum, bank); 1020 1021 } else { 1022 SG_SET_FRU_NAME_NODE(new_unum, node); 1023 SG_SET_FRU_NAME_CPU_BOARD(new_unum, board); 1024 SG_SET_FRU_NAME_MODULE(new_unum, position); 1025 SG_SET_FRU_NAME_BANK(new_unum, bank); 1026 SG_SET_FRU_NAME_DIMM(new_unum, dimm); 1027 1028 strcat(new_unum, " "); 1029 strcat(new_unum, unum); 1030 } 1031 1032 strcpy(unum, new_unum); 1033 } 1034 1035 int 1036 plat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp) 1037 { 1038 int node = SG_PORTID_TO_NODEID(cpuid); 1039 int board = SG_CPU_BD_PORTID_TO_BD_NUM(cpuid); 1040 1041 if (snprintf(buf, buflen, "/N%d/%s%d", node, 1042 SG_HPU_TYPE_CPU_BOARD_ID, board) >= buflen) { 1043 return (ENOSPC); 1044 } else { 1045 *lenp = strlen(buf); 1046 return (0); 1047 } 1048 } 1049 1050 static void (*sg_ecc_taskq_func)(sbbc_ecc_mbox_t *) = NULL; 1051 static int (*sg_ecc_mbox_func)(sbbc_ecc_mbox_t *) = NULL; 1052 1053 /* 1054 * We log all ECC errors to the SC so we send a mailbox 1055 * message to the SC passing it the relevant data. 1056 * ECC mailbox messages are sent via a taskq mechanism to 1057 * prevent impaired system performance during ECC floods. 1058 * Indictments have already passed through a taskq, so they 1059 * are not queued here. 1060 */ 1061 int 1062 plat_send_ecc_mailbox_msg(plat_ecc_message_type_t msg_type, void *datap) 1063 { 1064 sbbc_ecc_mbox_t *msgp; 1065 uint16_t msg_subtype; 1066 int sleep_flag, log_error; 1067 size_t msg_size; 1068 1069 if (sg_ecc_taskq_func == NULL) { 1070 sg_ecc_taskq_func = (void (*)(sbbc_ecc_mbox_t *)) 1071 modgetsymvalue("sbbc_mbox_queue_ecc_event", 0); 1072 if (sg_ecc_taskq_func == NULL) { 1073 cmn_err(CE_NOTE, "!plat_send_ecc_mailbox_msg: " 1074 "sbbc_mbox_queue_ecc_event not found"); 1075 return (ENODEV); 1076 } 1077 } 1078 if (sg_ecc_mbox_func == NULL) { 1079 sg_ecc_mbox_func = (int (*)(sbbc_ecc_mbox_t *)) 1080 modgetsymvalue("sbbc_mbox_ecc_output", 0); 1081 if (sg_ecc_mbox_func == NULL) { 1082 cmn_err(CE_NOTE, "!plat_send_ecc_mailbox_msg: " 1083 "sbbc_mbox_ecc_output not found"); 1084 return (ENODEV); 1085 } 1086 } 1087 1088 /* 1089 * Initialize the request and response structures 1090 */ 1091 switch (msg_type) { 1092 case PLAT_ECC_ERROR_MESSAGE: 1093 msg_subtype = INFO_MBOX_ERROR_ECC; 1094 msg_size = sizeof (plat_ecc_error_data_t); 1095 sleep_flag = KM_NOSLEEP; 1096 log_error = 1; 1097 break; 1098 case PLAT_ECC_ERROR2_MESSAGE: 1099 msg_subtype = INFO_MBOX_ECC; 1100 msg_size = sizeof (plat_ecc_error2_data_t); 1101 sleep_flag = KM_NOSLEEP; 1102 log_error = 1; 1103 break; 1104 case PLAT_ECC_INDICTMENT_MESSAGE: 1105 msg_subtype = INFO_MBOX_ERROR_INDICT; 1106 msg_size = sizeof (plat_ecc_indictment_data_t); 1107 sleep_flag = KM_SLEEP; 1108 log_error = 0; 1109 break; 1110 case PLAT_ECC_INDICTMENT2_MESSAGE: 1111 msg_subtype = INFO_MBOX_ECC; 1112 msg_size = sizeof (plat_ecc_indictment2_data_t); 1113 sleep_flag = KM_SLEEP; 1114 log_error = 0; 1115 break; 1116 case PLAT_ECC_CAPABILITY_MESSAGE: 1117 msg_subtype = INFO_MBOX_ECC_CAP; 1118 msg_size = sizeof (plat_capability_data_t) + 1119 strlen(utsname.release) + strlen(utsname.version) + 2; 1120 sleep_flag = KM_SLEEP; 1121 log_error = 0; 1122 break; 1123 case PLAT_ECC_DIMM_SID_MESSAGE: 1124 msg_subtype = INFO_MBOX_ECC; 1125 msg_size = sizeof (plat_dimm_sid_request_data_t); 1126 sleep_flag = KM_SLEEP; 1127 log_error = 0; 1128 break; 1129 default: 1130 return (EINVAL); 1131 } 1132 1133 msgp = (sbbc_ecc_mbox_t *)kmem_zalloc(sizeof (sbbc_ecc_mbox_t), 1134 sleep_flag); 1135 if (msgp == NULL) { 1136 cmn_err(CE_NOTE, "!plat_send_ecc_mailbox_msg: " 1137 "unable to allocate sbbc_ecc_mbox"); 1138 return (ENOMEM); 1139 } 1140 1141 msgp->ecc_log_error = log_error; 1142 1143 msgp->ecc_req.msg_type.type = INFO_MBOX; 1144 msgp->ecc_req.msg_type.sub_type = msg_subtype; 1145 msgp->ecc_req.msg_status = 0; 1146 msgp->ecc_req.msg_len = (int)msg_size; 1147 msgp->ecc_req.msg_bytes = 0; 1148 msgp->ecc_req.msg_buf = (caddr_t)kmem_zalloc(msg_size, sleep_flag); 1149 msgp->ecc_req.msg_data[0] = 0; 1150 msgp->ecc_req.msg_data[1] = 0; 1151 1152 if (msgp->ecc_req.msg_buf == NULL) { 1153 cmn_err(CE_NOTE, "!plat_send_ecc_mailbox_msg: " 1154 "unable to allocate request msg_buf"); 1155 kmem_free((void *)msgp, sizeof (sbbc_ecc_mbox_t)); 1156 return (ENOMEM); 1157 } 1158 1159 bcopy(datap, (void *)msgp->ecc_req.msg_buf, msg_size); 1160 1161 /* 1162 * initialize the response back from the SC 1163 */ 1164 msgp->ecc_resp.msg_type.type = INFO_MBOX; 1165 msgp->ecc_resp.msg_type.sub_type = msg_subtype; 1166 msgp->ecc_resp.msg_status = 0; 1167 msgp->ecc_resp.msg_len = 0; 1168 msgp->ecc_resp.msg_bytes = 0; 1169 msgp->ecc_resp.msg_buf = NULL; 1170 msgp->ecc_resp.msg_data[0] = 0; 1171 msgp->ecc_resp.msg_data[1] = 0; 1172 1173 switch (msg_type) { 1174 case PLAT_ECC_ERROR_MESSAGE: 1175 case PLAT_ECC_ERROR2_MESSAGE: 1176 /* 1177 * For Error Messages, we go through a taskq. 1178 * Queue up message for processing 1179 */ 1180 (*sg_ecc_taskq_func)(msgp); 1181 return (0); 1182 1183 case PLAT_ECC_CAPABILITY_MESSAGE: 1184 /* 1185 * For indictment and capability messages, we've already gone 1186 * through the taskq, so we can call the mailbox routine 1187 * directly. Find the symbol for the routine that sends 1188 * the mailbox msg 1189 */ 1190 msgp->ecc_resp.msg_len = (int)msg_size; 1191 msgp->ecc_resp.msg_buf = (caddr_t)kmem_zalloc(msg_size, 1192 sleep_flag); 1193 /* FALLTHRU */ 1194 1195 case PLAT_ECC_INDICTMENT_MESSAGE: 1196 case PLAT_ECC_INDICTMENT2_MESSAGE: 1197 return ((*sg_ecc_mbox_func)(msgp)); 1198 1199 case PLAT_ECC_DIMM_SID_MESSAGE: 1200 msgp->ecc_resp.msg_len = sizeof (plat_dimm_sid_board_data_t); 1201 msgp->ecc_resp.msg_buf = (caddr_t)kmem_zalloc( 1202 sizeof (plat_dimm_sid_board_data_t), sleep_flag); 1203 1204 return ((*sg_ecc_mbox_func)(msgp)); 1205 1206 default: 1207 ASSERT(0); 1208 return (EINVAL); 1209 } 1210 } 1211 1212 /* 1213 * m is redundant on serengeti as the multiplyer is always 4 1214 */ 1215 /*ARGSUSED*/ 1216 int 1217 plat_make_fru_cpuid(int sb, int m, int proc) 1218 { 1219 return (MAKE_CPUID(sb, proc)); 1220 } 1221 1222 /* 1223 * board number for a given proc 1224 */ 1225 int 1226 plat_make_fru_boardnum(int proc) 1227 { 1228 return (SG_PORTID_TO_BOARD_NUM(proc)); 1229 } 1230 1231 static 1232 void 1233 cpu_sgn_update(ushort_t sig, uchar_t state, uchar_t sub_state, int cpuid) 1234 { 1235 uint32_t signature = CPU_SIG_BLD(sig, state, sub_state); 1236 sig_state_t current_sgn; 1237 int i; 1238 1239 if (iosram_write_ptr == NULL) { 1240 /* 1241 * If the IOSRAM write pointer isn't set, we won't be able 1242 * to write signatures to ANYTHING, so we may as well just 1243 * write out an error message (if desired) and exit this 1244 * routine now... 1245 */ 1246 DCMNERR(CE_WARN, 1247 "cpu_sgn_update: iosram_write() not found;" 1248 " cannot write signature 0x%x for CPU(s) or domain\n", 1249 signature); 1250 return; 1251 } 1252 1253 1254 /* 1255 * Differentiate a panic reboot from a non-panic reboot in the 1256 * setting of the substate of the signature. 1257 * 1258 * If the new substate is REBOOT and we're rebooting due to a panic, 1259 * then set the new substate to a special value indicating a panic 1260 * reboot, SIGSUBST_PANIC_REBOOT. 1261 * 1262 * A panic reboot is detected by a current (previous) domain signature 1263 * state of SIGST_EXIT, and a new signature substate of SIGSUBST_REBOOT. 1264 * The domain signature state SIGST_EXIT is used as the panic flow 1265 * progresses. 1266 * 1267 * At the end of the panic flow, the reboot occurs but we should now 1268 * one that was involuntary, something that may be quite useful to know 1269 * at OBP level. 1270 */ 1271 if (sub_state == SIGSUBST_REBOOT) { 1272 if (iosram_read_ptr == NULL) { 1273 DCMNERR(CE_WARN, 1274 "cpu_sgn_update: iosram_read() not found;" 1275 " could not check current domain signature\n"); 1276 } else { 1277 (void) (*iosram_read_ptr)(SBBC_SIGBLCK_KEY, 1278 SG_SGNBLK_DOMAINSIG_OFFSET, 1279 (char *)¤t_sgn, sizeof (current_sgn)); 1280 if (current_sgn.state_t.state == SIGST_EXIT) 1281 signature = CPU_SIG_BLD(sig, state, 1282 SIGSUBST_PANIC_REBOOT); 1283 } 1284 } 1285 1286 /* 1287 * cpuid == -1 indicates that the operation applies to all cpus. 1288 */ 1289 if (cpuid >= 0) { 1290 (void) (*iosram_write_ptr)(SBBC_SIGBLCK_KEY, 1291 SG_SGNBLK_CPUSIG_OFFSET(cpuid), (char *)&signature, 1292 sizeof (signature)); 1293 } else { 1294 for (i = 0; i < NCPU; i++) { 1295 if (cpu[i] == NULL || !(cpu[i]->cpu_flags & 1296 (CPU_EXISTS|CPU_QUIESCED))) { 1297 continue; 1298 } 1299 (void) (*iosram_write_ptr)(SBBC_SIGBLCK_KEY, 1300 SG_SGNBLK_CPUSIG_OFFSET(i), (char *)&signature, 1301 sizeof (signature)); 1302 } 1303 } 1304 1305 if (state == SIGST_OFFLINE || state == SIGST_DETACHED) { 1306 return; 1307 } 1308 1309 (void) (*iosram_write_ptr)(SBBC_SIGBLCK_KEY, 1310 SG_SGNBLK_DOMAINSIG_OFFSET, (char *)&signature, 1311 sizeof (signature)); 1312 } 1313 1314 void 1315 startup_platform(void) 1316 { 1317 } 1318 1319 /* 1320 * A routine to convert a number (represented as a string) to 1321 * the integer value it represents. 1322 */ 1323 1324 static int 1325 isdigit(int ch) 1326 { 1327 return (ch >= '0' && ch <= '9'); 1328 } 1329 1330 #define isspace(c) ((c) == ' ' || (c) == '\t' || (c) == '\n') 1331 1332 static int 1333 strtoi(char *p, char **pos) 1334 { 1335 int n; 1336 int c, neg = 0; 1337 1338 if (!isdigit(c = *p)) { 1339 while (isspace(c)) 1340 c = *++p; 1341 switch (c) { 1342 case '-': 1343 neg++; 1344 /* FALLTHROUGH */ 1345 case '+': 1346 c = *++p; 1347 } 1348 if (!isdigit(c)) { 1349 if (pos != NULL) 1350 *pos = p; 1351 return (0); 1352 } 1353 } 1354 for (n = '0' - c; isdigit(c = *++p); ) { 1355 n *= 10; /* two steps to avoid unnecessary overflow */ 1356 n += '0' - c; /* accum neg to avoid surprises at MAX */ 1357 } 1358 if (pos != NULL) 1359 *pos = p; 1360 return (neg ? n : -n); 1361 } 1362 1363 /* 1364 * Get the three parts of the Serengeti PROM version. 1365 * Used for feature readiness tests. 1366 * 1367 * Return 0 if version extracted successfully, -1 otherwise. 1368 */ 1369 1370 int 1371 sg_get_prom_version(int *sysp, int *intfp, int *bldp) 1372 { 1373 int plen; 1374 char vers[512]; 1375 static pnode_t node; 1376 static char version[] = "version"; 1377 char *verp, *ep; 1378 1379 node = prom_finddevice("/openprom"); 1380 if (node == OBP_BADNODE) 1381 return (-1); 1382 1383 plen = prom_getproplen(node, version); 1384 if (plen <= 0 || plen >= sizeof (vers)) 1385 return (-1); 1386 (void) prom_getprop(node, version, vers); 1387 vers[plen] = '\0'; 1388 1389 /* Make sure it's an OBP flashprom */ 1390 if (vers[0] != 'O' && vers[1] != 'B' && vers[2] != 'P') { 1391 cmn_err(CE_WARN, "sg_get_prom_version: " 1392 "unknown <version> string in </openprom>\n"); 1393 return (-1); 1394 } 1395 verp = &vers[4]; 1396 1397 *sysp = strtoi(verp, &ep); 1398 if (ep == verp || *ep != '.') 1399 return (-1); 1400 verp = ep + 1; 1401 1402 *intfp = strtoi(verp, &ep); 1403 if (ep == verp || *ep != '.') 1404 return (-1); 1405 verp = ep + 1; 1406 1407 *bldp = strtoi(verp, &ep); 1408 if (ep == verp || (*ep != '\0' && !isspace(*ep))) 1409 return (-1); 1410 return (0); 1411 } 1412 1413 /* 1414 * Return 0 if system board Dynamic Reconfiguration 1415 * is supported by the firmware, -1 otherwise. 1416 */ 1417 int 1418 sg_prom_sb_dr_check(void) 1419 { 1420 static int prom_res = 1; 1421 1422 if (prom_res == 1) { 1423 int sys, intf, bld; 1424 int rv; 1425 1426 rv = sg_get_prom_version(&sys, &intf, &bld); 1427 if (rv == 0 && sys == 5 && 1428 (intf >= 12 || (intf == 11 && bld >= 200))) { 1429 prom_res = 0; 1430 } else { 1431 prom_res = -1; 1432 } 1433 } 1434 return (prom_res); 1435 } 1436 1437 /* 1438 * Return 0 if cPCI Dynamic Reconfiguration 1439 * is supported by the firmware, -1 otherwise. 1440 */ 1441 int 1442 sg_prom_cpci_dr_check(void) 1443 { 1444 /* 1445 * The version check is currently the same as for 1446 * system boards. Since the two DR sub-systems are 1447 * independent, this could change. 1448 */ 1449 return (sg_prom_sb_dr_check()); 1450 } 1451 1452 /* 1453 * Our implementation of this KDI op updates the CPU signature in the system 1454 * controller. Note that we set the signature to OBP_SIG, rather than DBG_SIG. 1455 * The Forth words we execute will, among other things, transform our OBP_SIG 1456 * into DBG_SIG. They won't function properly if we try to use DBG_SIG. 1457 */ 1458 static void 1459 sg_system_claim(void) 1460 { 1461 prom_interpret("sigb-sig! my-sigb-sig!", OBP_SIG, OBP_SIG, 0, 0, 0); 1462 } 1463 1464 static void 1465 sg_system_release(void) 1466 { 1467 prom_interpret("sigb-sig! my-sigb-sig!", OS_SIG, OS_SIG, 0, 0, 0); 1468 } 1469 1470 static void 1471 sg_console_claim(void) 1472 { 1473 prom_serengeti_set_console_input(SGCN_OBP_STR); 1474 } 1475 1476 static void 1477 sg_console_release(void) 1478 { 1479 prom_serengeti_set_console_input(SGCN_CLNT_STR); 1480 } 1481 1482 void 1483 plat_kdi_init(kdi_t *kdi) 1484 { 1485 kdi->pkdi_system_claim = sg_system_claim; 1486 kdi->pkdi_system_release = sg_system_release; 1487 kdi->pkdi_console_claim = sg_console_claim; 1488 kdi->pkdi_console_release = sg_console_release; 1489 } 1490