1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_LIB4U_H 27 #define _SYS_PX_LIB4U_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Errors returned. 37 */ 38 #define H_EOK 0 /* Successful return */ 39 #define H_ENOINTR 1 /* Invalid interrupt id */ 40 #define H_EINVAL 2 /* Invalid argument */ 41 #define H_ENOACCESS 3 /* No access to resource */ 42 #define H_EIO 4 /* I/O error */ 43 #define H_ENOTSUPPORTED 5 /* Function not supported */ 44 #define H_ENOMAP 6 /* Mapping is not valid, */ 45 /* no translation exists */ 46 47 /* 48 * Register base definitions. 49 * 50 * The specific numeric values for CSR, XBUS, Configuration, 51 * Interrupt blocks and other register bases. 52 */ 53 typedef enum { 54 PX_REG_CSR = 0, 55 PX_REG_XBC, 56 PX_REG_CFG, 57 PX_REG_IC, 58 PX_REG_MAX 59 } px_reg_bank_t; 60 61 /* 62 * Registers/state/variables that need to be saved and restored during 63 * suspend/resume. 64 * 65 * SUN4U px specific data structure. 66 */ 67 68 /* Control block soft state structure */ 69 typedef struct px_cb_list { 70 px_t *pxp; 71 struct px_cb_list *next; 72 } px_cb_list_t; 73 74 /* IO chip type */ 75 typedef enum { 76 PX_CHIP_UNIDENTIFIED = 0, 77 PX_CHIP_FIRE = 1, 78 PX_CHIP_OBERON = 2 79 } px_chip_type_t; 80 81 #define PX_CHIP_TYPE(pxu_p) ((pxu_p)->chip_type) 82 83 typedef struct px_cb { 84 px_cb_list_t *pxl; /* linked list px */ 85 kmutex_t cb_mutex; /* lock for CB */ 86 sysino_t sysino; /* proxy sysino */ 87 cpuid_t cpuid; /* proxy cpuid */ 88 int attachcnt; /* number of attached px */ 89 uint_t (*px_cb_func)(caddr_t); /* CB intr dispatcher */ 90 } px_cb_t; 91 92 typedef struct pxu { 93 px_chip_type_t chip_type; 94 uint8_t portid; 95 uint16_t tsb_cookie; 96 uint32_t tsb_size; 97 uint64_t *tsb_vaddr; 98 uint64_t tsb_paddr; /* Only used for Oberon */ 99 sysino_t hp_sysino; /* Oberon hotplug interrupt */ 100 101 void *msiq_mapped_p; 102 px_cb_t *px_cb_p; 103 104 /* Soft state for suspend/resume */ 105 uint64_t *pec_config_state; 106 uint64_t *mmu_config_state; 107 uint64_t *ib_intr_map; 108 uint64_t *ib_config_state; 109 uint64_t *xcb_config_state; 110 uint64_t *msiq_config_state; 111 uint_t cpr_flag; 112 113 /* sun4u specific vars */ 114 caddr_t px_address[4]; 115 ddi_acc_handle_t px_ac[4]; 116 117 /* PCItool */ 118 caddr_t pcitool_addr; 119 } pxu_t; 120 121 #define PX2CB(px_p) (((pxu_t *)px_p->px_plat_p)->px_cb_p) 122 123 /* cpr_flag */ 124 #define PX_NOT_CPR 0 125 #define PX_ENTERED_CPR 1 126 127 /* 128 * Event Queue data structure. 129 */ 130 typedef struct eq_rec { 131 uint64_t eq_rec_rsvd0 : 1, /* DW 0 - 63 */ 132 eq_rec_fmt_type : 7, /* DW 0 - 62:56 */ 133 eq_rec_len : 10, /* DW 0 - 55:46 */ 134 eq_rec_addr0 : 14, /* DW 0 - 45:32 */ 135 eq_rec_rid : 16, /* DW 0 - 31:16 */ 136 eq_rec_data0 : 16; /* DW 0 - 15:00 */ 137 uint64_t eq_rec_addr1 : 48, /* DW 1 - 63:16 */ 138 eq_rec_data1 : 16; /* DW 1 - 15:0 */ 139 uint64_t eq_rec_rsvd[6]; /* DW 2-7 */ 140 } eq_rec_t; 141 142 /* 143 * EQ record type 144 * 145 * Upper 4 bits of eq_rec_fmt_type is used 146 * to identify the EQ record type. 147 */ 148 #define EQ_REC_MSG 0x6 /* MSG - 0x3X */ 149 #define EQ_REC_MSI32 0xB /* MSI32 - 0x58 */ 150 #define EQ_REC_MSI64 0xF /* MSI64 - 0x78 */ 151 152 /* EQ State */ 153 #define EQ_IDLE_STATE 0x1 /* IDLE */ 154 #define EQ_ACTIVE_STATE 0x2 /* ACTIVE */ 155 #define EQ_ERROR_STATE 0x4 /* ERROR */ 156 157 #define MMU_INVALID_TTE 0ull 158 #define MMU_TTE_VALID(tte) (((tte) & MMU_TTE_V) == MMU_TTE_V) 159 #define MMU_OBERON_PADDR_MASK 0x7fffffffffff 160 #define MMU_FIRE_PADDR_MASK 0x7ffffffffff 161 162 /* 163 * control register decoding 164 */ 165 /* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */ 166 #define MMU_CTL_TO_TSBSIZE(ctl) ((ctl) >> 16) 167 #define MMU_TSBSIZE_TO_TSBENTRIES(s) ((1 << (s)) << (13 - 3)) 168 169 /* 170 * For Fire mmu bypass addresses, bit 43 specifies cacheability. 171 */ 172 #define MMU_FIRE_BYPASS_NONCACHE (1ull << 43) 173 174 /* 175 * For Oberon mmu bypass addresses, bit 47 specifies cacheability. 176 */ 177 #define MMU_OBERON_BYPASS_NONCACHE (1ull << 47) 178 179 /* 180 * The following macros define the address ranges supported for DVMA 181 * and mmu bypass transfers. For Oberon, bit 63 is used for ordering. 182 */ 183 #define MMU_FIRE_BYPASS_BASE 0xFFFC000000000000ull 184 #define MMU_FIRE_BYPASS_END 0xFFFC03FFFFFFFFFFull 185 186 #define MMU_OBERON_BYPASS_BASE 0x7FFC000000000000ull 187 #define MMU_OBERON_BYPASS_END 0x7FFC7FFFFFFFFFFFull 188 189 #define MMU_TSB_PA_MASK 0x7FFFFFFFE000 190 191 /* 192 * The following macros are for loading and unloading io tte 193 * entries. 194 */ 195 #define MMU_TTE_SIZE 8 196 #define MMU_TTE_V (1ull << 63) 197 #define MMU_TTE_W (1ull << 1) 198 #define MMU_TTE_RO (1ull << 62) /* Oberon Relaxed Ordering */ 199 200 #define INO_BITS 6 /* INO#s are 6 bits long */ 201 #define INO_MASK 0x3F /* INO#s mask */ 202 203 #define SYSINO_TO_DEVINO(sysino) (sysino & INO_MASK) 204 205 #define FIRE_IGN_MASK 0x1F /* IGN#s mask, 5 bits long for Fire */ 206 #define OBERON_IGN_MASK 0xFF /* IGN#s mask, 8 bits long for Oberon */ 207 208 #define ID_TO_IGN(chip, portid) ((portid) & ((chip) == PX_CHIP_OBERON ? \ 209 OBERON_IGN_MASK : FIRE_IGN_MASK)) 210 211 #define DEVINO_TO_SYSINO(portid, devino) \ 212 (((portid) << INO_BITS) | ((devino) & INO_MASK)) 213 214 /* Interrupt states */ 215 #define INTERRUPT_IDLE_STATE 0 216 #define INTERRUPT_RECEIVED_STATE 1 217 #define INTERRUPT_PENDING_STATE 3 218 219 /* 220 * Defines for link width and max packet size for ACKBAK Latency Threshold Timer 221 * and TxLink Replay Timer Latency Table array sizes 222 * Num Link Width Packet Size 223 * 0 1 128 224 * 1 4 256 225 * 2 8 512 226 * 3 16 1024 227 * 4 - 2048 228 * 5 - 4096 229 */ 230 #define LINK_WIDTH_ARR_SIZE 4 231 #define LINK_MAX_PKT_ARR_SIZE 6 232 233 /* 234 * Defines for registers which have multi-bit fields. 235 */ 236 #define TLU_LINK_CONTROL_ASPM_DISABLED 0x0 237 #define TLU_LINK_CONTROL_ASPM_L0S_EN 0x1 238 #define TLU_LINK_CONTROL_ASPM_L1_EN 0x2 239 #define TLU_LINK_CONTROL_ASPM_L0S_L1_EN 0x3 240 241 #define TLU_CONTROL_CONFIG_DEFAULT 0x1 242 #define TLU_CONTROL_L0S_TIM_DEFAULT 0xdaull 243 #define TLU_CONTROL_MPS_MASK 0x1C 244 #define TLU_CONTROL_MPS_SHIFT 2 245 246 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_0 0x0 247 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_1 0x1 248 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_2 0x2 249 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_3 0x3 250 251 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR_DEFAULT 0xFFFFull 252 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR_DEFAULT 0x0ull 253 254 #define LPU_TXLINK_SEQUENCE_COUNTER_ACK_SEQ_CNTR_DEFAULT 0xFFF 255 #define LPU_TXLINK_SEQUENCE_COUNTER_NXT_TX_SEQ_CNTR_DEFAULT 0x0 256 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_DEF 0x157 257 258 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_TLPTR_DEFAULT 0xFFF 259 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_HDPTR_DEFAULT 0x0 260 261 #define LPU_LTSSM_CONFIG1_LTSSM_8_TO_DEFAULT 0x2 262 #define LPU_LTSSM_CONFIG1_LTSSM_20_TO_DEFAULT 0x5 263 #define LPU_LTSSM_CONFIG2_LTSSM_12_TO_DEFAULT 0x2DC6C0 264 #define LPU_LTSSM_CONFIG3_LTSSM_2_TO_DEFAULT 0x7A120 265 #define LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT 0x2 266 #define LPU_LTSSM_CONFIG4_N_FTS_DEFAULT 0x8c 267 268 /* LPU LTSSM states */ 269 #define LPU_LTSSM_L0 0x0 270 #define LPU_LTSSM_L1_IDLE 0x15 271 272 /* TLU Control register bits */ 273 #define TLU_REMAIN_DETECT_QUIET 8 274 275 /* PX BDF Shift in a Phyiscal Address - used FMA Fabric only */ 276 #define PX_PA_BDF_SHIFT 12 277 #define PX_BDF_TO_CFGADDR(bdf, offset) (((bdf) << PX_PA_BDF_SHIFT) + (offset)) 278 279 /* 280 * Fire hardware specific version definitions. 281 * All Fire versions > 2.0 will be numerically greater than FIRE_MOD_REV_20 282 */ 283 #define FIRE_MOD_REV_20 0x03 284 285 /* 286 * Oberon specific definitions. 287 */ 288 #define OBERON_RANGE_PROP_MASK 0x7fff 289 290 /* 291 * HW specific paddr mask. 292 */ 293 extern uint64_t px_paddr_mask; 294 295 extern void hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p); 296 extern void hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p); 297 extern void hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p); 298 extern void hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p); 299 300 extern uint64_t hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p, 301 devino_t devino, sysino_t *sysino); 302 extern uint64_t hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino, 303 intr_valid_state_t *intr_valid_state); 304 extern uint64_t hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino, 305 intr_valid_state_t intr_valid_state); 306 extern uint64_t hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino, 307 intr_state_t *intr_state); 308 extern uint64_t hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino, 309 intr_state_t intr_state); 310 extern uint64_t hvio_intr_gettarget(devhandle_t dev_hdl, pxu_t *pxu_p, 311 sysino_t sysino, cpuid_t *cpuid); 312 extern uint64_t hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p, 313 sysino_t sysino, cpuid_t cpuid); 314 315 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, 316 pages_t pages, io_attributes_t attr, void *addr, size_t pfn_index, 317 int flags); 318 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, 319 tsbid_t tsbid, pages_t pages); 320 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, 321 tsbid_t tsbid, io_attributes_t *attr_p, r_addr_t *r_addr_p); 322 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, pxu_t *pxu_p, 323 r_addr_t ra, io_attributes_t attr, io_addr_t *io_addr_p); 324 extern uint64_t hvio_get_bypass_base(pxu_t *pxu_p); 325 extern uint64_t hvio_get_bypass_end(pxu_t *pxu_p); 326 extern uint64_t px_get_range_prop(px_t *px_p, px_ranges_t *rp, int bank); 327 328 329 /* 330 * MSIQ Functions: 331 */ 332 extern uint64_t hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p); 333 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 334 pci_msiq_valid_state_t *msiq_valid_state); 335 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 336 pci_msiq_valid_state_t msiq_valid_state); 337 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 338 pci_msiq_state_t *msiq_state); 339 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 340 pci_msiq_state_t msiq_state); 341 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 342 msiqhead_t *msiq_head); 343 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 344 msiqhead_t msiq_head); 345 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 346 msiqtail_t *msiq_tail); 347 348 /* 349 * MSI Functions: 350 */ 351 extern uint64_t hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32, 352 uint64_t addr64); 353 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 354 msiqid_t *msiq_id); 355 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 356 msiqid_t msiq_id); 357 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 358 pci_msi_valid_state_t *msi_valid_state); 359 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 360 pci_msi_valid_state_t msi_valid_state); 361 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 362 pci_msi_state_t *msi_state); 363 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 364 pci_msi_state_t msi_state); 365 366 /* 367 * MSG Functions: 368 */ 369 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 370 msiqid_t *msiq_id); 371 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 372 msiqid_t msiq_id); 373 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 374 pcie_msg_valid_state_t *msg_valid_state); 375 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 376 pcie_msg_valid_state_t msg_valid_state); 377 378 /* 379 * Suspend/Resume Functions: 380 */ 381 extern uint64_t hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 382 extern void hvio_resume(devhandle_t dev_hdl, 383 devino_t devino, pxu_t *pxu_p); 384 extern uint64_t hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 385 extern void hvio_cb_resume(devhandle_t pci_dev_hdl, devhandle_t xbus_dev_hdl, 386 devino_t devino, pxu_t *pxu_p); 387 extern int px_send_pme_turnoff(caddr_t csr_base); 388 extern int px_link_wait4l1idle(caddr_t csr_base); 389 extern int px_link_retrain(caddr_t csr_base); 390 extern void px_enable_detect_quiet(caddr_t csr_base); 391 392 extern void px_lib_clr_errs(px_t *px_p, dev_info_t *rdip, uint64_t addr); 393 394 /* 395 * Hotplug functions: 396 */ 397 extern int hvio_hotplug_init(dev_info_t *dip, void *arg); 398 extern int hvio_hotplug_uninit(dev_info_t *dip); 399 400 #ifdef __cplusplus 401 } 402 #endif 403 404 #endif /* _SYS_PX_LIB4U_H */ 405