1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PX_LIB4U_H 28 #define _SYS_PX_LIB4U_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Errors returned. 38 */ 39 #define H_EOK 0 /* Successful return */ 40 #define H_ENOINTR 1 /* Invalid interrupt id */ 41 #define H_EINVAL 2 /* Invalid argument */ 42 #define H_ENOACCESS 3 /* No access to resource */ 43 #define H_EIO 4 /* I/O error */ 44 #define H_ENOTSUPPORTED 5 /* Function not supported */ 45 #define H_ENOMAP 6 /* Mapping is not valid, */ 46 /* no translation exists */ 47 48 /* 49 * Register base definitions. 50 * 51 * The specific numeric values for CSR, XBUS, Configuration, 52 * Interrupt blocks and other register bases. 53 */ 54 typedef enum { 55 PX_REG_CSR = 0, 56 PX_REG_XBC, 57 PX_REG_CFG, 58 PX_REG_IC, 59 PX_REG_MAX 60 } px_reg_bank_t; 61 62 /* 63 * Registers/state/variables that need to be saved and restored during 64 * suspend/resume. 65 * 66 * SUN4U px specific data structure. 67 */ 68 typedef struct pxu { 69 uint32_t chip_id; 70 uint8_t portid; 71 uint16_t tsb_cookie; 72 uint32_t tsb_size; 73 uint64_t *tsb_vaddr; 74 void *msiq_mapped_p; 75 76 /* Soft state for suspend/resume */ 77 uint64_t *pec_config_state; 78 uint64_t *mmu_config_state; 79 uint64_t *ib_intr_map; 80 uint64_t *ib_config_state; 81 uint64_t *xcb_config_state; 82 uint64_t *msiq_config_state; 83 84 /* sun4u specific vars */ 85 caddr_t px_address[4]; 86 ddi_acc_handle_t px_ac[4]; 87 } pxu_t; 88 89 /* 90 * Event Queue data structure. 91 */ 92 typedef struct eq_rec { 93 uint64_t eq_rec_rsvd0 : 1, /* DW 0 - 63 */ 94 eq_rec_fmt_type : 7, /* DW 0 - 62:56 */ 95 eq_rec_len : 10, /* DW 0 - 55:46 */ 96 eq_rec_addr0 : 14, /* DW 0 - 45:32 */ 97 eq_rec_rid : 16, /* DW 0 - 31:16 */ 98 eq_rec_data0 : 16; /* DW 0 - 15:00 */ 99 uint64_t eq_rec_addr1 : 48, /* DW 1 - 63:16 */ 100 eq_rec_data1 : 16; /* DW 1 - 15:0 */ 101 uint64_t eq_rec_rsvd[6]; /* DW 2-7 */ 102 } eq_rec_t; 103 104 /* 105 * EQ record type 106 * 107 * Upper 4 bits of eq_rec_fmt_type is used 108 * to identify the EQ record type. 109 */ 110 #define EQ_REC_MSG 0x6 /* MSG - 0x3X */ 111 #define EQ_REC_MSI32 0xB /* MSI32 - 0x58 */ 112 #define EQ_REC_MSI64 0xF /* MSI64 - 0x78 */ 113 114 /* EQ State */ 115 #define EQ_IDLE_STATE 0x1 /* IDLE */ 116 #define EQ_ACTIVE_STATE 0x2 /* ACTIVE */ 117 #define EQ_ERROR_STATE 0x4 /* ERROR */ 118 119 #define MMU_INVALID_TTE 0ull 120 #define MMU_TTE_VALID(tte) (((tte) & MMU_TTE_V) == MMU_TTE_V) 121 #define MMU_TTETOPA(x) ((x & 0x7ffffffffff) >> MMU_PAGE_SHIFT) 122 123 /* 124 * control register decoding 125 */ 126 /* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */ 127 #define MMU_CTL_TO_TSBSIZE(ctl) ((ctl) >> 16) 128 #define MMU_TSBSIZE_TO_TSBENTRIES(s) ((1 << (s)) << (13 - 3)) 129 130 /* 131 * For mmu bypass addresses, bit 43 specifies cacheability. 132 */ 133 #define MMU_BYPASS_NONCACHE (1ull << 43) 134 135 /* 136 * The following macros define the address ranges supported for DVMA 137 * and mmu bypass transfers. 138 */ 139 #define MMU_BYPASS_BASE 0xFFFC000000000000ull 140 #define MMU_BYPASS_END 0xFFFC01FFFFFFFFFFull 141 142 /* 143 * The following macros are for loading and unloading io tte 144 * entries. 145 */ 146 #define MMU_TTE_SIZE 8 147 #define MMU_TTE_V (1ull << 63) 148 #define MMU_TTE_W (1ull << 1) 149 150 #define INO_BITS 6 /* INO#s are 6 bits long */ 151 #define IGN_BITS 5 /* IGN#s are 5 bits long */ 152 #define INO_MASK 0x3F /* INO#s mask */ 153 #define IGN_MASK 0x1F /* IGN#s mask */ 154 155 #define ID_TO_IGN(portid) ((uint16_t)((portid) & IGN_MASK)) 156 #define ID_TO_NODEID(portid) ((uint16_t)((portid) >> IGN_BITS)) 157 #define DEVINO_TO_SYSINO(portid, devino) \ 158 ((ID_TO_NODEID(portid) << (IGN_BITS + INO_BITS)) | \ 159 ((ID_TO_IGN(portid) << INO_BITS) | (devino & INO_MASK))) 160 #define SYSINO_TO_DEVINO(sysino) (sysino & INO_MASK) 161 162 /* Interrupt states */ 163 #define INTERRUPT_IDLE_STATE 0 164 #define INTERRUPT_RECEIVED_STATE 1 165 #define INTERRUPT_PENDING_STATE 3 166 167 /* 168 * Interrupt directives needed for reading proper interrupt diag register for 169 * given ino. 170 */ 171 #define PX_INTR_DIAG_REG(CSRBASE, INO) \ 172 (INO <= 32 ? CSRBASE + INTERRUPT_STATE_STATUS_1 : \ 173 CSRBASE + INTERRUPT_STATE_STATUS_2) 174 175 #define PX_INTR_STAT_BITMAP(INO) (0x3 << (INO & 0x1f)) 176 #define PX_INTR_STATUS(INTRDIAG_REG, INO) (((*INTRDIAG_REG) \ 177 & PX_INTR_STAT_BITMAP(INO)) >> (INO & 0x1f)) 178 179 /* 180 * Defines for link width and max packet size for ACKBAK Latency Threshold Timer 181 * and TxLink Replay Timer Latency Table array sizes 182 * Num Link Width Packet Size 183 * 0 1 128 184 * 1 4 256 185 * 2 8 512 186 * 3 16 1024 187 * 4 - 2048 188 * 5 - 4096 189 */ 190 #define LINK_WIDTH_ARR_SIZE 4 191 #define LINK_MAX_PKT_ARR_SIZE 6 192 193 /* 194 * Defines for registers which have multi-bit fields. 195 */ 196 #define TLU_LINK_CONTROL_ASPM_DISABLED 0x0 197 #define TLU_LINK_CONTROL_ASPM_L0S_EN 0x1 198 #define TLU_LINK_CONTROL_ASPM_L1_EN 0x2 199 #define TLU_LINK_CONTROL_ASPM_L0S_L1_EN 0x3 200 201 #define TLU_CONTROL_CONFIG_DEFAULT 0x1 202 #define TLU_CONTROL_L0S_TIM_DEFAULT 0xdaull 203 #define TLU_CONTROL_MPS_MASK 0x1C 204 #define TLU_CONTROL_MPS_SHIFT 2 205 206 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_0 0x0 207 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_1 0x1 208 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_2 0x2 209 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_3 0x3 210 211 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR_DEFAULT 0xFFFFull 212 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR_DEFAULT 0x0ull 213 214 #define LPU_TXLINK_SEQUENCE_COUNTER_ACK_SEQ_CNTR_DEFAULT 0xFFF 215 #define LPU_TXLINK_SEQUENCE_COUNTER_NXT_TX_SEQ_CNTR_DEFAULT 0x0 216 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_DEF 0x157 217 218 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_TLPTR_DEFAULT 0xFFF 219 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_HDPTR_DEFAULT 0x0 220 221 #define LPU_LTSSM_CONFIG1_LTSSM_8_TO_DEFAULT 0x2 222 #define LPU_LTSSM_CONFIG1_LTSSM_20_TO_DEFAULT 0x5 223 #define LPU_LTSSM_CONFIG2_LTSSM_12_TO_DEFAULT 0x2DC6C0 224 #define LPU_LTSSM_CONFIG3_LTSSM_2_TO_DEFAULT 0x7A120 225 #define LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT 0x2 226 #define LPU_LTSSM_CONFIG4_N_FTS_DEFAULT 0x8c 227 228 /* LPU LTSSM states */ 229 #define LPU_LTSSM_L0 0x0 230 #define LPU_LTSSM_L1_IDLE 0x15 231 232 /* TLU Control register bits */ 233 #define TLU_REMAIN_DETECT_QUIET 8 234 235 /* PX BDF Shift in a Phyiscal Address - used FMA Fabric only */ 236 #define PX_PA_BDF_SHIFT 12 237 #define PX_BDF_TO_CFGADDR(bdf, offset) (((bdf) << PX_PA_BDF_SHIFT) + (offset)) 238 239 /* 240 * The sequence of the chip_type appearance is significant. 241 * There are code depending on it: PX_CHIP_TYPE(pxu_p) < PX_CHIP_FIRE. 242 */ 243 typedef enum { 244 PX_CHIP_UNIDENTIFIED = 0, 245 PX_CHIP_FIRE = 1 246 } px_chip_id_t; 247 248 /* 249 * [msb] [lsb] 250 * 0x00 <chip_type> <version#> <module-revision#> 251 */ 252 #define PX_CHIP_ID(t, v, m) (((t) << 16) | ((v) << 8) | (m)) 253 #define PX_ID_CHIP_TYPE(id) ((id) >> 16) 254 #define PX_CHIP_TYPE(pxu_p) PX_ID_CHIP_TYPE(PX_CHIP_ID((pxu_p)->chip_id)) 255 #define PX_CHIP_REV(pxu_p) PX_CHIP_ID(((pxu_p)->chip_id) & 0xFF) 256 #define PX_CHIP_VER(pxu_p) PX_CHIP_ID((((pxu_p)->chip_id) >> 8) & 0xFF) 257 258 /* 259 * Fire hardware specific version definitions. 260 */ 261 #define FIRE_VER_10 PX_CHIP_ID(PX_CHIP_FIRE, 0x01, 0x00) 262 #define FIRE_VER_20 PX_CHIP_ID(PX_CHIP_FIRE, 0x03, 0x00) 263 264 extern void hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p); 265 extern void hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p); 266 extern void hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p); 267 extern void hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p); 268 269 extern uint64_t hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p, 270 devino_t devino, sysino_t *sysino); 271 extern uint64_t hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino, 272 intr_valid_state_t *intr_valid_state); 273 extern uint64_t hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino, 274 intr_valid_state_t intr_valid_state); 275 extern uint64_t hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino, 276 intr_state_t *intr_state); 277 extern uint64_t hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino, 278 intr_state_t intr_state); 279 extern uint64_t hvio_intr_gettarget(devhandle_t dev_hdl, sysino_t sysino, 280 cpuid_t *cpuid); 281 extern uint64_t hvio_intr_settarget(devhandle_t dev_hdl, sysino_t sysino, 282 cpuid_t cpuid); 283 284 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, 285 pages_t pages, io_attributes_t io_attributes, 286 void *addr, size_t pfn_index, int flag); 287 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, 288 tsbid_t tsbid, pages_t pages); 289 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, 290 tsbid_t tsbid, io_attributes_t *attributes_p, r_addr_t *r_addr_p); 291 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 292 io_attributes_t io_attributes, io_addr_t *io_addr_p); 293 294 /* 295 * MSIQ Functions: 296 */ 297 extern uint64_t hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p); 298 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 299 pci_msiq_valid_state_t *msiq_valid_state); 300 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 301 pci_msiq_valid_state_t msiq_valid_state); 302 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 303 pci_msiq_state_t *msiq_state); 304 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 305 pci_msiq_state_t msiq_state); 306 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 307 msiqhead_t *msiq_head); 308 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 309 msiqhead_t msiq_head); 310 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 311 msiqtail_t *msiq_tail); 312 313 /* 314 * MSI Functions: 315 */ 316 extern uint64_t hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32, 317 uint64_t addr64); 318 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 319 msiqid_t *msiq_id); 320 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 321 msiqid_t msiq_id); 322 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 323 pci_msi_valid_state_t *msi_valid_state); 324 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 325 pci_msi_valid_state_t msi_valid_state); 326 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 327 pci_msi_state_t *msi_state); 328 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 329 pci_msi_state_t msi_state); 330 331 /* 332 * MSG Functions: 333 */ 334 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 335 msiqid_t *msiq_id); 336 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 337 msiqid_t msiq_id); 338 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 339 pcie_msg_valid_state_t *msg_valid_state); 340 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 341 pcie_msg_valid_state_t msg_valid_state); 342 343 /* 344 * Suspend/Resume Functions: 345 */ 346 extern uint64_t hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 347 extern void hvio_resume(devhandle_t dev_hdl, 348 devino_t devino, pxu_t *pxu_p); 349 extern uint64_t hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 350 extern void hvio_cb_resume(devhandle_t pci_dev_hdl, devhandle_t xbus_dev_hdl, 351 devino_t devino, pxu_t *pxu_p); 352 extern int px_send_pme_turnoff(caddr_t csr_base); 353 extern int px_link_wait4l1idle(caddr_t csr_base); 354 extern int px_link_retrain(caddr_t csr_base); 355 extern void px_enable_detect_quiet(caddr_t csr_base); 356 357 #ifdef __cplusplus 358 } 359 #endif 360 361 #endif /* _SYS_PX_LIB4U_H */ 362