1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/cmn_err.h> 28 #include <sys/vmsystm.h> 29 #include <sys/vmem.h> 30 #include <sys/machsystm.h> /* lddphys() */ 31 #include <sys/iommutsb.h> 32 #include <px_obj.h> 33 #include <sys/hotplug/pci/pcie_hp.h> 34 #include "px_regs.h" 35 #include "oberon_regs.h" 36 #include "px_csr.h" 37 #include "px_lib4u.h" 38 #include "px_err.h" 39 40 /* 41 * Registers that need to be saved and restored during suspend/resume. 42 */ 43 44 /* 45 * Registers in the PEC Module. 46 * LPU_RESET should be set to 0ull during resume 47 * 48 * This array is in reg,chip form. PX_CHIP_UNIDENTIFIED is for all chips 49 * or PX_CHIP_FIRE for Fire only, or PX_CHIP_OBERON for Oberon only. 50 */ 51 static struct px_pec_regs { 52 uint64_t reg; 53 uint64_t chip; 54 } pec_config_state_regs[] = { 55 {PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE, PX_CHIP_UNIDENTIFIED}, 56 {ILU_ERROR_LOG_ENABLE, PX_CHIP_UNIDENTIFIED}, 57 {ILU_INTERRUPT_ENABLE, PX_CHIP_UNIDENTIFIED}, 58 {TLU_CONTROL, PX_CHIP_UNIDENTIFIED}, 59 {TLU_OTHER_EVENT_LOG_ENABLE, PX_CHIP_UNIDENTIFIED}, 60 {TLU_OTHER_EVENT_INTERRUPT_ENABLE, PX_CHIP_UNIDENTIFIED}, 61 {TLU_DEVICE_CONTROL, PX_CHIP_UNIDENTIFIED}, 62 {TLU_LINK_CONTROL, PX_CHIP_UNIDENTIFIED}, 63 {TLU_UNCORRECTABLE_ERROR_LOG_ENABLE, PX_CHIP_UNIDENTIFIED}, 64 {TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE, PX_CHIP_UNIDENTIFIED}, 65 {TLU_CORRECTABLE_ERROR_LOG_ENABLE, PX_CHIP_UNIDENTIFIED}, 66 {TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE, PX_CHIP_UNIDENTIFIED}, 67 {DLU_LINK_LAYER_CONFIG, PX_CHIP_OBERON}, 68 {DLU_FLOW_CONTROL_UPDATE_CONTROL, PX_CHIP_OBERON}, 69 {DLU_TXLINK_REPLAY_TIMER_THRESHOLD, PX_CHIP_OBERON}, 70 {LPU_LINK_LAYER_INTERRUPT_MASK, PX_CHIP_FIRE}, 71 {LPU_PHY_INTERRUPT_MASK, PX_CHIP_FIRE}, 72 {LPU_RECEIVE_PHY_INTERRUPT_MASK, PX_CHIP_FIRE}, 73 {LPU_TRANSMIT_PHY_INTERRUPT_MASK, PX_CHIP_FIRE}, 74 {LPU_GIGABLAZE_GLUE_INTERRUPT_MASK, PX_CHIP_FIRE}, 75 {LPU_LTSSM_INTERRUPT_MASK, PX_CHIP_FIRE}, 76 {LPU_RESET, PX_CHIP_FIRE}, 77 {LPU_DEBUG_CONFIG, PX_CHIP_FIRE}, 78 {LPU_INTERRUPT_MASK, PX_CHIP_FIRE}, 79 {LPU_LINK_LAYER_CONFIG, PX_CHIP_FIRE}, 80 {LPU_FLOW_CONTROL_UPDATE_CONTROL, PX_CHIP_FIRE}, 81 {LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD, PX_CHIP_FIRE}, 82 {LPU_TXLINK_REPLAY_TIMER_THRESHOLD, PX_CHIP_FIRE}, 83 {LPU_REPLAY_BUFFER_MAX_ADDRESS, PX_CHIP_FIRE}, 84 {LPU_TXLINK_RETRY_FIFO_POINTER, PX_CHIP_FIRE}, 85 {LPU_LTSSM_CONFIG2, PX_CHIP_FIRE}, 86 {LPU_LTSSM_CONFIG3, PX_CHIP_FIRE}, 87 {LPU_LTSSM_CONFIG4, PX_CHIP_FIRE}, 88 {LPU_LTSSM_CONFIG5, PX_CHIP_FIRE}, 89 {DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE, PX_CHIP_UNIDENTIFIED}, 90 {DMC_DEBUG_SELECT_FOR_PORT_A, PX_CHIP_UNIDENTIFIED}, 91 {DMC_DEBUG_SELECT_FOR_PORT_B, PX_CHIP_UNIDENTIFIED} 92 }; 93 94 #define PEC_KEYS \ 95 ((sizeof (pec_config_state_regs))/sizeof (struct px_pec_regs)) 96 97 #define PEC_SIZE (PEC_KEYS * sizeof (uint64_t)) 98 99 /* 100 * Registers for the MMU module. 101 * MMU_TTE_CACHE_INVALIDATE needs to be cleared. (-1ull) 102 */ 103 static uint64_t mmu_config_state_regs[] = { 104 MMU_TSB_CONTROL, 105 MMU_CONTROL_AND_STATUS, 106 MMU_ERROR_LOG_ENABLE, 107 MMU_INTERRUPT_ENABLE 108 }; 109 #define MMU_SIZE (sizeof (mmu_config_state_regs)) 110 #define MMU_KEYS (MMU_SIZE / sizeof (uint64_t)) 111 112 /* 113 * Registers for the IB Module 114 */ 115 static uint64_t ib_config_state_regs[] = { 116 IMU_ERROR_LOG_ENABLE, 117 IMU_INTERRUPT_ENABLE 118 }; 119 #define IB_SIZE (sizeof (ib_config_state_regs)) 120 #define IB_KEYS (IB_SIZE / sizeof (uint64_t)) 121 #define IB_MAP_SIZE (INTERRUPT_MAPPING_ENTRIES * sizeof (uint64_t)) 122 123 /* 124 * Registers for the JBC module. 125 * JBC_ERROR_STATUS_CLEAR needs to be cleared. (-1ull) 126 */ 127 static uint64_t jbc_config_state_regs[] = { 128 JBUS_PARITY_CONTROL, 129 JBC_FATAL_RESET_ENABLE, 130 JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE, 131 JBC_ERROR_LOG_ENABLE, 132 JBC_INTERRUPT_ENABLE 133 }; 134 #define JBC_SIZE (sizeof (jbc_config_state_regs)) 135 #define JBC_KEYS (JBC_SIZE / sizeof (uint64_t)) 136 137 /* 138 * Registers for the UBC module. 139 * UBC_ERROR_STATUS_CLEAR needs to be cleared. (-1ull) 140 */ 141 static uint64_t ubc_config_state_regs[] = { 142 UBC_ERROR_LOG_ENABLE, 143 UBC_INTERRUPT_ENABLE 144 }; 145 #define UBC_SIZE (sizeof (ubc_config_state_regs)) 146 #define UBC_KEYS (UBC_SIZE / sizeof (uint64_t)) 147 148 static uint64_t msiq_config_other_regs[] = { 149 ERR_COR_MAPPING, 150 ERR_NONFATAL_MAPPING, 151 ERR_FATAL_MAPPING, 152 PM_PME_MAPPING, 153 PME_TO_ACK_MAPPING, 154 MSI_32_BIT_ADDRESS, 155 MSI_64_BIT_ADDRESS 156 }; 157 #define MSIQ_OTHER_SIZE (sizeof (msiq_config_other_regs)) 158 #define MSIQ_OTHER_KEYS (MSIQ_OTHER_SIZE / sizeof (uint64_t)) 159 160 #define MSIQ_STATE_SIZE (EVENT_QUEUE_STATE_ENTRIES * sizeof (uint64_t)) 161 #define MSIQ_MAPPING_SIZE (MSI_MAPPING_ENTRIES * sizeof (uint64_t)) 162 163 /* OPL tuning variables for link unstable issue */ 164 int wait_perst = 5000000; /* step 9, default: 5s */ 165 int wait_enable_port = 30000; /* step 11, default: 30ms */ 166 int link_retry_count = 2; /* step 11, default: 2 */ 167 int link_status_check = 400000; /* step 11, default: 400ms */ 168 169 static uint64_t msiq_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 170 static void msiq_resume(devhandle_t dev_hdl, pxu_t *pxu_p); 171 static void jbc_init(caddr_t xbc_csr_base, pxu_t *pxu_p); 172 static void ubc_init(caddr_t xbc_csr_base, pxu_t *pxu_p); 173 174 extern int px_acknak_timer_table[LINK_MAX_PKT_ARR_SIZE][LINK_WIDTH_ARR_SIZE]; 175 extern int px_replay_timer_table[LINK_MAX_PKT_ARR_SIZE][LINK_WIDTH_ARR_SIZE]; 176 177 /* 178 * Initialize the bus, but do not enable interrupts. 179 */ 180 /* ARGSUSED */ 181 void 182 hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p) 183 { 184 switch (PX_CHIP_TYPE(pxu_p)) { 185 case PX_CHIP_OBERON: 186 ubc_init(xbc_csr_base, pxu_p); 187 break; 188 case PX_CHIP_FIRE: 189 jbc_init(xbc_csr_base, pxu_p); 190 break; 191 default: 192 DBG(DBG_CB, NULL, "hvio_cb_init - unknown chip type: 0x%x\n", 193 PX_CHIP_TYPE(pxu_p)); 194 break; 195 } 196 } 197 198 /* 199 * Initialize the JBC module, but do not enable interrupts. 200 */ 201 /* ARGSUSED */ 202 static void 203 jbc_init(caddr_t xbc_csr_base, pxu_t *pxu_p) 204 { 205 uint64_t val; 206 207 /* Check if we need to enable inverted parity */ 208 val = (1ULL << JBUS_PARITY_CONTROL_P_EN); 209 CSR_XS(xbc_csr_base, JBUS_PARITY_CONTROL, val); 210 DBG(DBG_CB, NULL, "jbc_init, JBUS_PARITY_CONTROL: 0x%llx\n", 211 CSR_XR(xbc_csr_base, JBUS_PARITY_CONTROL)); 212 213 val = (1 << JBC_FATAL_RESET_ENABLE_SPARE_P_INT_EN) | 214 (1 << JBC_FATAL_RESET_ENABLE_MB_PEA_P_INT_EN) | 215 (1 << JBC_FATAL_RESET_ENABLE_CPE_P_INT_EN) | 216 (1 << JBC_FATAL_RESET_ENABLE_APE_P_INT_EN) | 217 (1 << JBC_FATAL_RESET_ENABLE_PIO_CPE_INT_EN) | 218 (1 << JBC_FATAL_RESET_ENABLE_JTCEEW_P_INT_EN) | 219 (1 << JBC_FATAL_RESET_ENABLE_JTCEEI_P_INT_EN) | 220 (1 << JBC_FATAL_RESET_ENABLE_JTCEER_P_INT_EN); 221 CSR_XS(xbc_csr_base, JBC_FATAL_RESET_ENABLE, val); 222 DBG(DBG_CB, NULL, "jbc_init, JBC_FATAL_RESET_ENABLE: 0x%llx\n", 223 CSR_XR(xbc_csr_base, JBC_FATAL_RESET_ENABLE)); 224 225 /* 226 * Enable merge, jbc and dmc interrupts. 227 */ 228 CSR_XS(xbc_csr_base, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE, -1ull); 229 DBG(DBG_CB, NULL, 230 "jbc_init, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE: 0x%llx\n", 231 CSR_XR(xbc_csr_base, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE)); 232 233 /* 234 * CSR_V JBC's interrupt regs (log, enable, status, clear) 235 */ 236 DBG(DBG_CB, NULL, "jbc_init, JBC_ERROR_LOG_ENABLE: 0x%llx\n", 237 CSR_XR(xbc_csr_base, JBC_ERROR_LOG_ENABLE)); 238 239 DBG(DBG_CB, NULL, "jbc_init, JBC_INTERRUPT_ENABLE: 0x%llx\n", 240 CSR_XR(xbc_csr_base, JBC_INTERRUPT_ENABLE)); 241 242 DBG(DBG_CB, NULL, "jbc_init, JBC_INTERRUPT_STATUS: 0x%llx\n", 243 CSR_XR(xbc_csr_base, JBC_INTERRUPT_STATUS)); 244 245 DBG(DBG_CB, NULL, "jbc_init, JBC_ERROR_STATUS_CLEAR: 0x%llx\n", 246 CSR_XR(xbc_csr_base, JBC_ERROR_STATUS_CLEAR)); 247 } 248 249 /* 250 * Initialize the UBC module, but do not enable interrupts. 251 */ 252 /* ARGSUSED */ 253 static void 254 ubc_init(caddr_t xbc_csr_base, pxu_t *pxu_p) 255 { 256 /* 257 * Enable Uranus bus error log bits. 258 */ 259 CSR_XS(xbc_csr_base, UBC_ERROR_LOG_ENABLE, -1ull); 260 DBG(DBG_CB, NULL, "ubc_init, UBC_ERROR_LOG_ENABLE: 0x%llx\n", 261 CSR_XR(xbc_csr_base, UBC_ERROR_LOG_ENABLE)); 262 263 /* 264 * Clear Uranus bus errors. 265 */ 266 CSR_XS(xbc_csr_base, UBC_ERROR_STATUS_CLEAR, -1ull); 267 DBG(DBG_CB, NULL, "ubc_init, UBC_ERROR_STATUS_CLEAR: 0x%llx\n", 268 CSR_XR(xbc_csr_base, UBC_ERROR_STATUS_CLEAR)); 269 270 /* 271 * CSR_V UBC's interrupt regs (log, enable, status, clear) 272 */ 273 DBG(DBG_CB, NULL, "ubc_init, UBC_ERROR_LOG_ENABLE: 0x%llx\n", 274 CSR_XR(xbc_csr_base, UBC_ERROR_LOG_ENABLE)); 275 276 DBG(DBG_CB, NULL, "ubc_init, UBC_INTERRUPT_ENABLE: 0x%llx\n", 277 CSR_XR(xbc_csr_base, UBC_INTERRUPT_ENABLE)); 278 279 DBG(DBG_CB, NULL, "ubc_init, UBC_INTERRUPT_STATUS: 0x%llx\n", 280 CSR_XR(xbc_csr_base, UBC_INTERRUPT_STATUS)); 281 282 DBG(DBG_CB, NULL, "ubc_init, UBC_ERROR_STATUS_CLEAR: 0x%llx\n", 283 CSR_XR(xbc_csr_base, UBC_ERROR_STATUS_CLEAR)); 284 } 285 286 /* 287 * Initialize the module, but do not enable interrupts. 288 */ 289 /* ARGSUSED */ 290 void 291 hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p) 292 { 293 /* 294 * CSR_V IB's interrupt regs (log, enable, status, clear) 295 */ 296 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_ERROR_LOG_ENABLE: 0x%llx\n", 297 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE)); 298 299 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_INTERRUPT_ENABLE: 0x%llx\n", 300 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE)); 301 302 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_INTERRUPT_STATUS: 0x%llx\n", 303 CSR_XR(csr_base, IMU_INTERRUPT_STATUS)); 304 305 DBG(DBG_IB, NULL, "hvio_ib_init - IMU_ERROR_STATUS_CLEAR: 0x%llx\n", 306 CSR_XR(csr_base, IMU_ERROR_STATUS_CLEAR)); 307 } 308 309 /* 310 * Initialize the module, but do not enable interrupts. 311 */ 312 /* ARGSUSED */ 313 static void 314 ilu_init(caddr_t csr_base, pxu_t *pxu_p) 315 { 316 /* 317 * CSR_V ILU's interrupt regs (log, enable, status, clear) 318 */ 319 DBG(DBG_ILU, NULL, "ilu_init - ILU_ERROR_LOG_ENABLE: 0x%llx\n", 320 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE)); 321 322 DBG(DBG_ILU, NULL, "ilu_init - ILU_INTERRUPT_ENABLE: 0x%llx\n", 323 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE)); 324 325 DBG(DBG_ILU, NULL, "ilu_init - ILU_INTERRUPT_STATUS: 0x%llx\n", 326 CSR_XR(csr_base, ILU_INTERRUPT_STATUS)); 327 328 DBG(DBG_ILU, NULL, "ilu_init - ILU_ERROR_STATUS_CLEAR: 0x%llx\n", 329 CSR_XR(csr_base, ILU_ERROR_STATUS_CLEAR)); 330 } 331 332 /* 333 * Initialize the module, but do not enable interrupts. 334 */ 335 /* ARGSUSED */ 336 static void 337 tlu_init(caddr_t csr_base, pxu_t *pxu_p) 338 { 339 uint64_t val; 340 341 /* 342 * CSR_V TLU_CONTROL Expect OBP ??? 343 */ 344 345 /* 346 * L0s entry default timer value - 7.0 us 347 * Completion timeout select default value - 67.1 ms and 348 * OBP will set this value. 349 * 350 * Configuration - Bit 0 should always be 0 for upstream port. 351 * Bit 1 is clock - how is this related to the clock bit in TLU 352 * Link Control register? Both are hardware dependent and likely 353 * set by OBP. 354 * 355 * NOTE: Do not set the NPWR_EN bit. The desired value of this bit 356 * will be set by OBP. 357 */ 358 val = CSR_XR(csr_base, TLU_CONTROL); 359 val |= (TLU_CONTROL_L0S_TIM_DEFAULT << TLU_CONTROL_L0S_TIM) | 360 TLU_CONTROL_CONFIG_DEFAULT; 361 362 /* 363 * For Oberon, NPWR_EN is set to 0 to prevent PIO reads from blocking 364 * behind non-posted PIO writes. This blocking could cause a master or 365 * slave timeout on the host bus if multiple serialized PIOs were to 366 * suffer Completion Timeouts because the CTO delays for each PIO ahead 367 * of the read would accumulate. Since the Olympus processor can have 368 * only 1 PIO outstanding, there is no possibility of PIO accesses from 369 * a given CPU to a given device being re-ordered by the PCIe fabric; 370 * therefore turning off serialization should be safe from a PCIe 371 * ordering perspective. 372 */ 373 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) 374 val &= ~(1ull << TLU_CONTROL_NPWR_EN); 375 376 /* 377 * Set Detect.Quiet. This will disable automatic link 378 * re-training, if the link goes down e.g. power management 379 * turns off power to the downstream device. This will enable 380 * Fire to go to Drain state, after link down. The drain state 381 * forces a reset to the FC state machine, which is required for 382 * proper link re-training. 383 */ 384 val |= (1ull << TLU_REMAIN_DETECT_QUIET); 385 CSR_XS(csr_base, TLU_CONTROL, val); 386 DBG(DBG_TLU, NULL, "tlu_init - TLU_CONTROL: 0x%llx\n", 387 CSR_XR(csr_base, TLU_CONTROL)); 388 389 /* 390 * CSR_V TLU_STATUS Expect HW 0x4 391 */ 392 393 /* 394 * Only bit [7:0] are currently defined. Bits [2:0] 395 * are the state, which should likely be in state active, 396 * 100b. Bit three is 'recovery', which is not understood. 397 * All other bits are reserved. 398 */ 399 DBG(DBG_TLU, NULL, "tlu_init - TLU_STATUS: 0x%llx\n", 400 CSR_XR(csr_base, TLU_STATUS)); 401 402 /* 403 * CSR_V TLU_PME_TURN_OFF_GENERATE Expect HW 0x0 404 */ 405 DBG(DBG_TLU, NULL, "tlu_init - TLU_PME_TURN_OFF_GENERATE: 0x%llx\n", 406 CSR_XR(csr_base, TLU_PME_TURN_OFF_GENERATE)); 407 408 /* 409 * CSR_V TLU_INGRESS_CREDITS_INITIAL Expect HW 0x10000200C0 410 */ 411 412 /* 413 * Ingress credits initial register. Bits [39:32] should be 414 * 0x10, bits [19:12] should be 0x20, and bits [11:0] should 415 * be 0xC0. These are the reset values, and should be set by 416 * HW. 417 */ 418 DBG(DBG_TLU, NULL, "tlu_init - TLU_INGRESS_CREDITS_INITIAL: 0x%llx\n", 419 CSR_XR(csr_base, TLU_INGRESS_CREDITS_INITIAL)); 420 421 /* 422 * CSR_V TLU_DIAGNOSTIC Expect HW 0x0 423 */ 424 425 /* 426 * Diagnostic register - always zero unless we are debugging. 427 */ 428 DBG(DBG_TLU, NULL, "tlu_init - TLU_DIAGNOSTIC: 0x%llx\n", 429 CSR_XR(csr_base, TLU_DIAGNOSTIC)); 430 431 /* 432 * CSR_V TLU_EGRESS_CREDITS_CONSUMED Expect HW 0x0 433 */ 434 DBG(DBG_TLU, NULL, "tlu_init - TLU_EGRESS_CREDITS_CONSUMED: 0x%llx\n", 435 CSR_XR(csr_base, TLU_EGRESS_CREDITS_CONSUMED)); 436 437 /* 438 * CSR_V TLU_EGRESS_CREDIT_LIMIT Expect HW 0x0 439 */ 440 DBG(DBG_TLU, NULL, "tlu_init - TLU_EGRESS_CREDIT_LIMIT: 0x%llx\n", 441 CSR_XR(csr_base, TLU_EGRESS_CREDIT_LIMIT)); 442 443 /* 444 * CSR_V TLU_EGRESS_RETRY_BUFFER Expect HW 0x0 445 */ 446 DBG(DBG_TLU, NULL, "tlu_init - TLU_EGRESS_RETRY_BUFFER: 0x%llx\n", 447 CSR_XR(csr_base, TLU_EGRESS_RETRY_BUFFER)); 448 449 /* 450 * CSR_V TLU_INGRESS_CREDITS_ALLOCATED Expected HW 0x0 451 */ 452 DBG(DBG_TLU, NULL, 453 "tlu_init - TLU_INGRESS_CREDITS_ALLOCATED: 0x%llx\n", 454 CSR_XR(csr_base, TLU_INGRESS_CREDITS_ALLOCATED)); 455 456 /* 457 * CSR_V TLU_INGRESS_CREDITS_RECEIVED Expected HW 0x0 458 */ 459 DBG(DBG_TLU, NULL, 460 "tlu_init - TLU_INGRESS_CREDITS_RECEIVED: 0x%llx\n", 461 CSR_XR(csr_base, TLU_INGRESS_CREDITS_RECEIVED)); 462 463 /* 464 * CSR_V TLU's interrupt regs (log, enable, status, clear) 465 */ 466 DBG(DBG_TLU, NULL, 467 "tlu_init - TLU_OTHER_EVENT_LOG_ENABLE: 0x%llx\n", 468 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE)); 469 470 DBG(DBG_TLU, NULL, 471 "tlu_init - TLU_OTHER_EVENT_INTERRUPT_ENABLE: 0x%llx\n", 472 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE)); 473 474 DBG(DBG_TLU, NULL, 475 "tlu_init - TLU_OTHER_EVENT_INTERRUPT_STATUS: 0x%llx\n", 476 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_STATUS)); 477 478 DBG(DBG_TLU, NULL, 479 "tlu_init - TLU_OTHER_EVENT_STATUS_CLEAR: 0x%llx\n", 480 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_CLEAR)); 481 482 /* 483 * CSR_V TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG Expect HW 0x0 484 */ 485 DBG(DBG_TLU, NULL, 486 "tlu_init - TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG: 0x%llx\n", 487 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG)); 488 489 /* 490 * CSR_V TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG Expect HW 0x0 491 */ 492 DBG(DBG_TLU, NULL, 493 "tlu_init - TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG: 0x%llx\n", 494 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG)); 495 496 /* 497 * CSR_V TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG Expect HW 0x0 498 */ 499 DBG(DBG_TLU, NULL, 500 "tlu_init - TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG: 0x%llx\n", 501 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG)); 502 503 /* 504 * CSR_V TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG Expect HW 0x0 505 */ 506 DBG(DBG_TLU, NULL, 507 "tlu_init - TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG: 0x%llx\n", 508 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG)); 509 510 /* 511 * CSR_V TLU_PERFORMANCE_COUNTER_SELECT Expect HW 0x0 512 */ 513 DBG(DBG_TLU, NULL, 514 "tlu_init - TLU_PERFORMANCE_COUNTER_SELECT: 0x%llx\n", 515 CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_SELECT)); 516 517 /* 518 * CSR_V TLU_PERFORMANCE_COUNTER_ZERO Expect HW 0x0 519 */ 520 DBG(DBG_TLU, NULL, 521 "tlu_init - TLU_PERFORMANCE_COUNTER_ZERO: 0x%llx\n", 522 CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_ZERO)); 523 524 /* 525 * CSR_V TLU_PERFORMANCE_COUNTER_ONE Expect HW 0x0 526 */ 527 DBG(DBG_TLU, NULL, "tlu_init - TLU_PERFORMANCE_COUNTER_ONE: 0x%llx\n", 528 CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_ONE)); 529 530 /* 531 * CSR_V TLU_PERFORMANCE_COUNTER_TWO Expect HW 0x0 532 */ 533 DBG(DBG_TLU, NULL, "tlu_init - TLU_PERFORMANCE_COUNTER_TWO: 0x%llx\n", 534 CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_TWO)); 535 536 /* 537 * CSR_V TLU_DEBUG_SELECT_A Expect HW 0x0 538 */ 539 540 DBG(DBG_TLU, NULL, "tlu_init - TLU_DEBUG_SELECT_A: 0x%llx\n", 541 CSR_XR(csr_base, TLU_DEBUG_SELECT_A)); 542 543 /* 544 * CSR_V TLU_DEBUG_SELECT_B Expect HW 0x0 545 */ 546 DBG(DBG_TLU, NULL, "tlu_init - TLU_DEBUG_SELECT_B: 0x%llx\n", 547 CSR_XR(csr_base, TLU_DEBUG_SELECT_B)); 548 549 /* 550 * CSR_V TLU_DEVICE_CAPABILITIES Expect HW 0xFC2 551 */ 552 DBG(DBG_TLU, NULL, "tlu_init - TLU_DEVICE_CAPABILITIES: 0x%llx\n", 553 CSR_XR(csr_base, TLU_DEVICE_CAPABILITIES)); 554 555 /* 556 * CSR_V TLU_DEVICE_CONTROL Expect HW 0x0 557 */ 558 559 /* 560 * Bits [14:12] are the Max Read Request Size, which is always 64 561 * bytes which is 000b. Bits [7:5] are Max Payload Size, which 562 * start at 128 bytes which is 000b. This may be revisited if 563 * init_child finds greater values. 564 */ 565 val = 0x0ull; 566 CSR_XS(csr_base, TLU_DEVICE_CONTROL, val); 567 DBG(DBG_TLU, NULL, "tlu_init - TLU_DEVICE_CONTROL: 0x%llx\n", 568 CSR_XR(csr_base, TLU_DEVICE_CONTROL)); 569 570 /* 571 * CSR_V TLU_DEVICE_STATUS Expect HW 0x0 572 */ 573 DBG(DBG_TLU, NULL, "tlu_init - TLU_DEVICE_STATUS: 0x%llx\n", 574 CSR_XR(csr_base, TLU_DEVICE_STATUS)); 575 576 /* 577 * CSR_V TLU_LINK_CAPABILITIES Expect HW 0x15C81 578 */ 579 DBG(DBG_TLU, NULL, "tlu_init - TLU_LINK_CAPABILITIES: 0x%llx\n", 580 CSR_XR(csr_base, TLU_LINK_CAPABILITIES)); 581 582 /* 583 * CSR_V TLU_LINK_CONTROL Expect OBP 0x40 584 */ 585 586 /* 587 * The CLOCK bit should be set by OBP if the hardware dictates, 588 * and if it is set then ASPM should be used since then L0s exit 589 * latency should be lower than L1 exit latency. 590 * 591 * Note that we will not enable power management during bringup 592 * since it has not been test and is creating some problems in 593 * simulation. 594 */ 595 val = (1ull << TLU_LINK_CONTROL_CLOCK); 596 597 CSR_XS(csr_base, TLU_LINK_CONTROL, val); 598 DBG(DBG_TLU, NULL, "tlu_init - TLU_LINK_CONTROL: 0x%llx\n", 599 CSR_XR(csr_base, TLU_LINK_CONTROL)); 600 601 /* 602 * CSR_V TLU_LINK_STATUS Expect OBP 0x1011 603 */ 604 605 /* 606 * Not sure if HW or OBP will be setting this read only 607 * register. Bit 12 is Clock, and it should always be 1 608 * signifying that the component uses the same physical 609 * clock as the platform. Bits [9:4] are for the width, 610 * with the expected value above signifying a x1 width. 611 * Bits [3:0] are the speed, with 1b signifying 2.5 Gb/s, 612 * the only speed as yet supported by the PCI-E spec. 613 */ 614 DBG(DBG_TLU, NULL, "tlu_init - TLU_LINK_STATUS: 0x%llx\n", 615 CSR_XR(csr_base, TLU_LINK_STATUS)); 616 617 /* 618 * CSR_V TLU_SLOT_CAPABILITIES Expect OBP ??? 619 */ 620 621 /* 622 * Power Limits for the slots. Will be platform 623 * dependent, and OBP will need to set after consulting 624 * with the HW guys. 625 * 626 * Bits [16:15] are power limit scale, which most likely 627 * will be 0b signifying 1x. Bits [14:7] are the Set 628 * Power Limit Value, which is a number which is multiplied 629 * by the power limit scale to get the actual power limit. 630 */ 631 DBG(DBG_TLU, NULL, "tlu_init - TLU_SLOT_CAPABILITIES: 0x%llx\n", 632 CSR_XR(csr_base, TLU_SLOT_CAPABILITIES)); 633 634 /* 635 * CSR_V TLU_UNCORRECTABLE_ERROR_LOG_ENABLE Expect Kernel 0x17F011 636 */ 637 DBG(DBG_TLU, NULL, 638 "tlu_init - TLU_UNCORRECTABLE_ERROR_LOG_ENABLE: 0x%llx\n", 639 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE)); 640 641 /* 642 * CSR_V TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE Expect 643 * Kernel 0x17F0110017F011 644 */ 645 DBG(DBG_TLU, NULL, 646 "tlu_init - TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE: 0x%llx\n", 647 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE)); 648 649 /* 650 * CSR_V TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS Expect HW 0x0 651 */ 652 DBG(DBG_TLU, NULL, 653 "tlu_init - TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS: 0x%llx\n", 654 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS)); 655 656 /* 657 * CSR_V TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR Expect HW 0x0 658 */ 659 DBG(DBG_TLU, NULL, 660 "tlu_init - TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR: 0x%llx\n", 661 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR)); 662 663 /* 664 * CSR_V TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG HW 0x0 665 */ 666 DBG(DBG_TLU, NULL, 667 "tlu_init - TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG: 0x%llx\n", 668 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG)); 669 670 /* 671 * CSR_V TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG HW 0x0 672 */ 673 DBG(DBG_TLU, NULL, 674 "tlu_init - TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG: 0x%llx\n", 675 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG)); 676 677 /* 678 * CSR_V TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG HW 0x0 679 */ 680 DBG(DBG_TLU, NULL, 681 "tlu_init - TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG: 0x%llx\n", 682 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG)); 683 684 /* 685 * CSR_V TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG HW 0x0 686 */ 687 DBG(DBG_TLU, NULL, 688 "tlu_init - TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG: 0x%llx\n", 689 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG)); 690 691 692 /* 693 * CSR_V TLU's CE interrupt regs (log, enable, status, clear) 694 * Plus header logs 695 */ 696 697 /* 698 * CSR_V TLU_CORRECTABLE_ERROR_LOG_ENABLE Expect Kernel 0x11C1 699 */ 700 DBG(DBG_TLU, NULL, 701 "tlu_init - TLU_CORRECTABLE_ERROR_LOG_ENABLE: 0x%llx\n", 702 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE)); 703 704 /* 705 * CSR_V TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE Kernel 0x11C1000011C1 706 */ 707 DBG(DBG_TLU, NULL, 708 "tlu_init - TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE: 0x%llx\n", 709 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE)); 710 711 /* 712 * CSR_V TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS Expect HW 0x0 713 */ 714 DBG(DBG_TLU, NULL, 715 "tlu_init - TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS: 0x%llx\n", 716 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS)); 717 718 /* 719 * CSR_V TLU_CORRECTABLE_ERROR_STATUS_CLEAR Expect HW 0x0 720 */ 721 DBG(DBG_TLU, NULL, 722 "tlu_init - TLU_CORRECTABLE_ERROR_STATUS_CLEAR: 0x%llx\n", 723 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_CLEAR)); 724 } 725 726 /* ARGSUSED */ 727 static void 728 lpu_init(caddr_t csr_base, pxu_t *pxu_p) 729 { 730 /* Variables used to set the ACKNAK Latency Timer and Replay Timer */ 731 int link_width, max_payload; 732 733 uint64_t val; 734 735 /* 736 * Get the Link Width. See table above LINK_WIDTH_ARR_SIZE #define 737 * Only Link Widths of x1, x4, and x8 are supported. 738 * If any width is reported other than x8, set default to x8. 739 */ 740 link_width = CSR_FR(csr_base, TLU_LINK_STATUS, WIDTH); 741 DBG(DBG_LPU, NULL, "lpu_init - Link Width: x%d\n", link_width); 742 743 /* 744 * Convert link_width to match timer array configuration. 745 */ 746 switch (link_width) { 747 case 1: 748 link_width = 0; 749 break; 750 case 4: 751 link_width = 1; 752 break; 753 case 8: 754 link_width = 2; 755 break; 756 case 16: 757 link_width = 3; 758 break; 759 default: 760 link_width = 0; 761 } 762 763 /* 764 * Get the Max Payload Size. 765 * See table above LINK_MAX_PKT_ARR_SIZE #define 766 */ 767 max_payload = ((CSR_FR(csr_base, TLU_CONTROL, CONFIG) & 768 TLU_CONTROL_MPS_MASK) >> TLU_CONTROL_MPS_SHIFT); 769 770 DBG(DBG_LPU, NULL, "lpu_init - May Payload: %d\n", 771 (0x80 << max_payload)); 772 773 /* Make sure the packet size is not greater than 4096 */ 774 max_payload = (max_payload >= LINK_MAX_PKT_ARR_SIZE) ? 775 (LINK_MAX_PKT_ARR_SIZE - 1) : max_payload; 776 777 /* 778 * CSR_V LPU_ID Expect HW 0x0 779 */ 780 781 /* 782 * This register has link id, phy id and gigablaze id. 783 * Should be set by HW. 784 */ 785 DBG(DBG_LPU, NULL, "lpu_init - LPU_ID: 0x%llx\n", 786 CSR_XR(csr_base, LPU_ID)); 787 788 /* 789 * CSR_V LPU_RESET Expect Kernel 0x0 790 */ 791 792 /* 793 * No reason to have any reset bits high until an error is 794 * detected on the link. 795 */ 796 val = 0ull; 797 CSR_XS(csr_base, LPU_RESET, val); 798 DBG(DBG_LPU, NULL, "lpu_init - LPU_RESET: 0x%llx\n", 799 CSR_XR(csr_base, LPU_RESET)); 800 801 /* 802 * CSR_V LPU_DEBUG_STATUS Expect HW 0x0 803 */ 804 805 /* 806 * Bits [15:8] are Debug B, and bit [7:0] are Debug A. 807 * They are read-only. What do the 8 bits mean, and 808 * how do they get set if they are read only? 809 */ 810 DBG(DBG_LPU, NULL, "lpu_init - LPU_DEBUG_STATUS: 0x%llx\n", 811 CSR_XR(csr_base, LPU_DEBUG_STATUS)); 812 813 /* 814 * CSR_V LPU_DEBUG_CONFIG Expect Kernel 0x0 815 */ 816 DBG(DBG_LPU, NULL, "lpu_init - LPU_DEBUG_CONFIG: 0x%llx\n", 817 CSR_XR(csr_base, LPU_DEBUG_CONFIG)); 818 819 /* 820 * CSR_V LPU_LTSSM_CONTROL Expect HW 0x0 821 */ 822 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONTROL: 0x%llx\n", 823 CSR_XR(csr_base, LPU_LTSSM_CONTROL)); 824 825 /* 826 * CSR_V LPU_LINK_STATUS Expect HW 0x101 827 */ 828 829 /* 830 * This register has bits [9:4] for link width, and the 831 * default 0x10, means a width of x16. The problem is 832 * this width is not supported according to the TLU 833 * link status register. 834 */ 835 DBG(DBG_LPU, NULL, "lpu_init - LPU_LINK_STATUS: 0x%llx\n", 836 CSR_XR(csr_base, LPU_LINK_STATUS)); 837 838 /* 839 * CSR_V LPU_INTERRUPT_STATUS Expect HW 0x0 840 */ 841 DBG(DBG_LPU, NULL, "lpu_init - LPU_INTERRUPT_STATUS: 0x%llx\n", 842 CSR_XR(csr_base, LPU_INTERRUPT_STATUS)); 843 844 /* 845 * CSR_V LPU_INTERRUPT_MASK Expect HW 0x0 846 */ 847 DBG(DBG_LPU, NULL, "lpu_init - LPU_INTERRUPT_MASK: 0x%llx\n", 848 CSR_XR(csr_base, LPU_INTERRUPT_MASK)); 849 850 /* 851 * CSR_V LPU_LINK_PERFORMANCE_COUNTER_SELECT Expect HW 0x0 852 */ 853 DBG(DBG_LPU, NULL, 854 "lpu_init - LPU_LINK_PERFORMANCE_COUNTER_SELECT: 0x%llx\n", 855 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER_SELECT)); 856 857 /* 858 * CSR_V LPU_LINK_PERFORMANCE_COUNTER_CONTROL Expect HW 0x0 859 */ 860 DBG(DBG_LPU, NULL, 861 "lpu_init - LPU_LINK_PERFORMANCE_COUNTER_CONTROL: 0x%llx\n", 862 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER_CONTROL)); 863 864 /* 865 * CSR_V LPU_LINK_PERFORMANCE_COUNTER1 Expect HW 0x0 866 */ 867 DBG(DBG_LPU, NULL, 868 "lpu_init - LPU_LINK_PERFORMANCE_COUNTER1: 0x%llx\n", 869 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER1)); 870 871 /* 872 * CSR_V LPU_LINK_PERFORMANCE_COUNTER1_TEST Expect HW 0x0 873 */ 874 DBG(DBG_LPU, NULL, 875 "lpu_init - LPU_LINK_PERFORMANCE_COUNTER1_TEST: 0x%llx\n", 876 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER1_TEST)); 877 878 /* 879 * CSR_V LPU_LINK_PERFORMANCE_COUNTER2 Expect HW 0x0 880 */ 881 DBG(DBG_LPU, NULL, 882 "lpu_init - LPU_LINK_PERFORMANCE_COUNTER2: 0x%llx\n", 883 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER2)); 884 885 /* 886 * CSR_V LPU_LINK_PERFORMANCE_COUNTER2_TEST Expect HW 0x0 887 */ 888 DBG(DBG_LPU, NULL, 889 "lpu_init - LPU_LINK_PERFORMANCE_COUNTER2_TEST: 0x%llx\n", 890 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER2_TEST)); 891 892 /* 893 * CSR_V LPU_LINK_LAYER_CONFIG Expect HW 0x100 894 */ 895 896 /* 897 * This is another place where Max Payload can be set, 898 * this time for the link layer. It will be set to 899 * 128B, which is the default, but this will need to 900 * be revisited. 901 */ 902 val = (1ull << LPU_LINK_LAYER_CONFIG_VC0_EN); 903 CSR_XS(csr_base, LPU_LINK_LAYER_CONFIG, val); 904 DBG(DBG_LPU, NULL, "lpu_init - LPU_LINK_LAYER_CONFIG: 0x%llx\n", 905 CSR_XR(csr_base, LPU_LINK_LAYER_CONFIG)); 906 907 /* 908 * CSR_V LPU_LINK_LAYER_STATUS Expect OBP 0x5 909 */ 910 911 /* 912 * Another R/W status register. Bit 3, DL up Status, will 913 * be set high. The link state machine status bits [2:0] 914 * are set to 0x1, but the status bits are not defined in the 915 * PRM. What does 0x1 mean, what others values are possible 916 * and what are thier meanings? 917 * 918 * This register has been giving us problems in simulation. 919 * It has been mentioned that software should not program 920 * any registers with WE bits except during debug. So 921 * this register will no longer be programmed. 922 */ 923 924 DBG(DBG_LPU, NULL, "lpu_init - LPU_LINK_LAYER_STATUS: 0x%llx\n", 925 CSR_XR(csr_base, LPU_LINK_LAYER_STATUS)); 926 927 /* 928 * CSR_V LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 929 */ 930 DBG(DBG_LPU, NULL, 931 "lpu_init - LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 932 CSR_XR(csr_base, LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST)); 933 934 /* 935 * CSR_V LPU Link Layer interrupt regs (mask, status) 936 */ 937 DBG(DBG_LPU, NULL, 938 "lpu_init - LPU_LINK_LAYER_INTERRUPT_MASK: 0x%llx\n", 939 CSR_XR(csr_base, LPU_LINK_LAYER_INTERRUPT_MASK)); 940 941 DBG(DBG_LPU, NULL, 942 "lpu_init - LPU_LINK_LAYER_INTERRUPT_AND_STATUS: 0x%llx\n", 943 CSR_XR(csr_base, LPU_LINK_LAYER_INTERRUPT_AND_STATUS)); 944 945 /* 946 * CSR_V LPU_FLOW_CONTROL_UPDATE_CONTROL Expect OBP 0x7 947 */ 948 949 /* 950 * The PRM says that only the first two bits will be set 951 * high by default, which will enable flow control for 952 * posted and non-posted updates, but NOT completetion 953 * updates. 954 */ 955 val = (1ull << LPU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_NP_EN) | 956 (1ull << LPU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_P_EN); 957 CSR_XS(csr_base, LPU_FLOW_CONTROL_UPDATE_CONTROL, val); 958 DBG(DBG_LPU, NULL, 959 "lpu_init - LPU_FLOW_CONTROL_UPDATE_CONTROL: 0x%llx\n", 960 CSR_XR(csr_base, LPU_FLOW_CONTROL_UPDATE_CONTROL)); 961 962 /* 963 * CSR_V LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE 964 * Expect OBP 0x1D4C 965 */ 966 967 /* 968 * This should be set by OBP. We'll check to make sure. 969 */ 970 DBG(DBG_LPU, NULL, "lpu_init - " 971 "LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE: 0x%llx\n", 972 CSR_XR(csr_base, 973 LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE)); 974 975 /* 976 * CSR_V LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0 Expect OBP ??? 977 */ 978 979 /* 980 * This register has Flow Control Update Timer values for 981 * non-posted and posted requests, bits [30:16] and bits 982 * [14:0], respectively. These are read-only to SW so 983 * either HW or OBP needs to set them. 984 */ 985 DBG(DBG_LPU, NULL, "lpu_init - " 986 "LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0: 0x%llx\n", 987 CSR_XR(csr_base, 988 LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0)); 989 990 /* 991 * CSR_V LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1 Expect OBP ??? 992 */ 993 994 /* 995 * Same as timer0 register above, except for bits [14:0] 996 * have the timer values for completetions. Read-only to 997 * SW; OBP or HW need to set it. 998 */ 999 DBG(DBG_LPU, NULL, "lpu_init - " 1000 "LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1: 0x%llx\n", 1001 CSR_XR(csr_base, 1002 LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1)); 1003 1004 /* 1005 * CSR_V LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD 1006 */ 1007 val = px_acknak_timer_table[max_payload][link_width]; 1008 CSR_XS(csr_base, LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD, val); 1009 1010 DBG(DBG_LPU, NULL, "lpu_init - " 1011 "LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD: 0x%llx\n", 1012 CSR_XR(csr_base, LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD)); 1013 1014 /* 1015 * CSR_V LPU_TXLINK_ACKNAK_LATENCY_TIMER Expect HW 0x0 1016 */ 1017 DBG(DBG_LPU, NULL, 1018 "lpu_init - LPU_TXLINK_ACKNAK_LATENCY_TIMER: 0x%llx\n", 1019 CSR_XR(csr_base, LPU_TXLINK_ACKNAK_LATENCY_TIMER)); 1020 1021 /* 1022 * CSR_V LPU_TXLINK_REPLAY_TIMER_THRESHOLD 1023 */ 1024 val = px_replay_timer_table[max_payload][link_width]; 1025 CSR_XS(csr_base, LPU_TXLINK_REPLAY_TIMER_THRESHOLD, val); 1026 1027 DBG(DBG_LPU, NULL, 1028 "lpu_init - LPU_TXLINK_REPLAY_TIMER_THRESHOLD: 0x%llx\n", 1029 CSR_XR(csr_base, LPU_TXLINK_REPLAY_TIMER_THRESHOLD)); 1030 1031 /* 1032 * CSR_V LPU_TXLINK_REPLAY_TIMER Expect HW 0x0 1033 */ 1034 DBG(DBG_LPU, NULL, "lpu_init - LPU_TXLINK_REPLAY_TIMER: 0x%llx\n", 1035 CSR_XR(csr_base, LPU_TXLINK_REPLAY_TIMER)); 1036 1037 /* 1038 * CSR_V LPU_TXLINK_REPLAY_NUMBER_STATUS Expect OBP 0x3 1039 */ 1040 DBG(DBG_LPU, NULL, 1041 "lpu_init - LPU_TXLINK_REPLAY_NUMBER_STATUS: 0x%llx\n", 1042 CSR_XR(csr_base, LPU_TXLINK_REPLAY_NUMBER_STATUS)); 1043 1044 /* 1045 * CSR_V LPU_REPLAY_BUFFER_MAX_ADDRESS Expect OBP 0xB3F 1046 */ 1047 DBG(DBG_LPU, NULL, 1048 "lpu_init - LPU_REPLAY_BUFFER_MAX_ADDRESS: 0x%llx\n", 1049 CSR_XR(csr_base, LPU_REPLAY_BUFFER_MAX_ADDRESS)); 1050 1051 /* 1052 * CSR_V LPU_TXLINK_RETRY_FIFO_POINTER Expect OBP 0xFFFF0000 1053 */ 1054 val = ((LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR_DEFAULT << 1055 LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR) | 1056 (LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR_DEFAULT << 1057 LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR)); 1058 1059 CSR_XS(csr_base, LPU_TXLINK_RETRY_FIFO_POINTER, val); 1060 DBG(DBG_LPU, NULL, 1061 "lpu_init - LPU_TXLINK_RETRY_FIFO_POINTER: 0x%llx\n", 1062 CSR_XR(csr_base, LPU_TXLINK_RETRY_FIFO_POINTER)); 1063 1064 /* 1065 * CSR_V LPU_TXLINK_RETRY_FIFO_R_W_POINTER Expect OBP 0x0 1066 */ 1067 DBG(DBG_LPU, NULL, 1068 "lpu_init - LPU_TXLINK_RETRY_FIFO_R_W_POINTER: 0x%llx\n", 1069 CSR_XR(csr_base, LPU_TXLINK_RETRY_FIFO_R_W_POINTER)); 1070 1071 /* 1072 * CSR_V LPU_TXLINK_RETRY_FIFO_CREDIT Expect HW 0x1580 1073 */ 1074 DBG(DBG_LPU, NULL, 1075 "lpu_init - LPU_TXLINK_RETRY_FIFO_CREDIT: 0x%llx\n", 1076 CSR_XR(csr_base, LPU_TXLINK_RETRY_FIFO_CREDIT)); 1077 1078 /* 1079 * CSR_V LPU_TXLINK_SEQUENCE_COUNTER Expect OBP 0xFFF0000 1080 */ 1081 DBG(DBG_LPU, NULL, "lpu_init - LPU_TXLINK_SEQUENCE_COUNTER: 0x%llx\n", 1082 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNTER)); 1083 1084 /* 1085 * CSR_V LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER Expect HW 0xFFF 1086 */ 1087 DBG(DBG_LPU, NULL, 1088 "lpu_init - LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER: 0x%llx\n", 1089 CSR_XR(csr_base, LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER)); 1090 1091 /* 1092 * CSR_V LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR Expect OBP 0x157 1093 */ 1094 1095 /* 1096 * Test only register. Will not be programmed. 1097 */ 1098 DBG(DBG_LPU, NULL, 1099 "lpu_init - LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR: 0x%llx\n", 1100 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR)); 1101 1102 /* 1103 * CSR_V LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS Expect HW 0xFFF0000 1104 */ 1105 1106 /* 1107 * Test only register. Will not be programmed. 1108 */ 1109 DBG(DBG_LPU, NULL, 1110 "lpu_init - LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS: 0x%llx\n", 1111 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS)); 1112 1113 /* 1114 * CSR_V LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS Expect HW 0x0 1115 */ 1116 DBG(DBG_LPU, NULL, 1117 "lpu_init - LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS: 0x%llx\n", 1118 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS)); 1119 1120 /* 1121 * CSR_V LPU_TXLINK_TEST_CONTROL Expect HW 0x0 1122 */ 1123 DBG(DBG_LPU, NULL, "lpu_init - LPU_TXLINK_TEST_CONTROL: 0x%llx\n", 1124 CSR_XR(csr_base, LPU_TXLINK_TEST_CONTROL)); 1125 1126 /* 1127 * CSR_V LPU_TXLINK_MEMORY_ADDRESS_CONTROL Expect HW 0x0 1128 */ 1129 1130 /* 1131 * Test only register. Will not be programmed. 1132 */ 1133 DBG(DBG_LPU, NULL, 1134 "lpu_init - LPU_TXLINK_MEMORY_ADDRESS_CONTROL: 0x%llx\n", 1135 CSR_XR(csr_base, LPU_TXLINK_MEMORY_ADDRESS_CONTROL)); 1136 1137 /* 1138 * CSR_V LPU_TXLINK_MEMORY_DATA_LOAD0 Expect HW 0x0 1139 */ 1140 DBG(DBG_LPU, NULL, 1141 "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD0: 0x%llx\n", 1142 CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD0)); 1143 1144 /* 1145 * CSR_V LPU_TXLINK_MEMORY_DATA_LOAD1 Expect HW 0x0 1146 */ 1147 DBG(DBG_LPU, NULL, 1148 "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD1: 0x%llx\n", 1149 CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD1)); 1150 1151 /* 1152 * CSR_V LPU_TXLINK_MEMORY_DATA_LOAD2 Expect HW 0x0 1153 */ 1154 DBG(DBG_LPU, NULL, 1155 "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD2: 0x%llx\n", 1156 CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD2)); 1157 1158 /* 1159 * CSR_V LPU_TXLINK_MEMORY_DATA_LOAD3 Expect HW 0x0 1160 */ 1161 DBG(DBG_LPU, NULL, 1162 "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD3: 0x%llx\n", 1163 CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD3)); 1164 1165 /* 1166 * CSR_V LPU_TXLINK_MEMORY_DATA_LOAD4 Expect HW 0x0 1167 */ 1168 DBG(DBG_LPU, NULL, 1169 "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD4: 0x%llx\n", 1170 CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD4)); 1171 1172 /* 1173 * CSR_V LPU_TXLINK_RETRY_DATA_COUNT Expect HW 0x0 1174 */ 1175 1176 /* 1177 * Test only register. Will not be programmed. 1178 */ 1179 DBG(DBG_LPU, NULL, "lpu_init - LPU_TXLINK_RETRY_DATA_COUNT: 0x%llx\n", 1180 CSR_XR(csr_base, LPU_TXLINK_RETRY_DATA_COUNT)); 1181 1182 /* 1183 * CSR_V LPU_TXLINK_SEQUENCE_BUFFER_COUNT Expect HW 0x0 1184 */ 1185 1186 /* 1187 * Test only register. Will not be programmed. 1188 */ 1189 DBG(DBG_LPU, NULL, 1190 "lpu_init - LPU_TXLINK_SEQUENCE_BUFFER_COUNT: 0x%llx\n", 1191 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_BUFFER_COUNT)); 1192 1193 /* 1194 * CSR_V LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA Expect HW 0x0 1195 */ 1196 1197 /* 1198 * Test only register. 1199 */ 1200 DBG(DBG_LPU, NULL, 1201 "lpu_init - LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA: 0x%llx\n", 1202 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA)); 1203 1204 /* 1205 * CSR_V LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER Expect HW 0x0 1206 */ 1207 DBG(DBG_LPU, NULL, "lpu_init - " 1208 "LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER: 0x%llx\n", 1209 CSR_XR(csr_base, LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER)); 1210 1211 /* 1212 * CSR_V LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED Expect HW 0x0 1213 */ 1214 1215 /* 1216 * test only register. 1217 */ 1218 DBG(DBG_LPU, NULL, 1219 "lpu_init - LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED: 0x%llx\n", 1220 CSR_XR(csr_base, LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED)); 1221 1222 /* 1223 * CSR_V LPU_RXLINK_TEST_CONTROL Expect HW 0x0 1224 */ 1225 1226 /* 1227 * test only register. 1228 */ 1229 DBG(DBG_LPU, NULL, "lpu_init - LPU_RXLINK_TEST_CONTROL: 0x%llx\n", 1230 CSR_XR(csr_base, LPU_RXLINK_TEST_CONTROL)); 1231 1232 /* 1233 * CSR_V LPU_PHYSICAL_LAYER_CONFIGURATION Expect HW 0x10 1234 */ 1235 DBG(DBG_LPU, NULL, 1236 "lpu_init - LPU_PHYSICAL_LAYER_CONFIGURATION: 0x%llx\n", 1237 CSR_XR(csr_base, LPU_PHYSICAL_LAYER_CONFIGURATION)); 1238 1239 /* 1240 * CSR_V LPU_PHY_LAYER_STATUS Expect HW 0x0 1241 */ 1242 DBG(DBG_LPU, NULL, "lpu_init - LPU_PHY_LAYER_STATUS: 0x%llx\n", 1243 CSR_XR(csr_base, LPU_PHY_LAYER_STATUS)); 1244 1245 /* 1246 * CSR_V LPU_PHY_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 1247 */ 1248 DBG(DBG_LPU, NULL, 1249 "lpu_init - LPU_PHY_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 1250 CSR_XR(csr_base, LPU_PHY_INTERRUPT_AND_STATUS_TEST)); 1251 1252 /* 1253 * CSR_V LPU PHY LAYER interrupt regs (mask, status) 1254 */ 1255 DBG(DBG_LPU, NULL, "lpu_init - LPU_PHY_INTERRUPT_MASK: 0x%llx\n", 1256 CSR_XR(csr_base, LPU_PHY_INTERRUPT_MASK)); 1257 1258 DBG(DBG_LPU, NULL, 1259 "lpu_init - LPU_PHY_LAYER_INTERRUPT_AND_STATUS: 0x%llx\n", 1260 CSR_XR(csr_base, LPU_PHY_LAYER_INTERRUPT_AND_STATUS)); 1261 1262 /* 1263 * CSR_V LPU_RECEIVE_PHY_CONFIG Expect HW 0x0 1264 */ 1265 1266 /* 1267 * This also needs some explanation. What is the best value 1268 * for the water mark? Test mode enables which test mode? 1269 * Programming model needed for the Receiver Reset Lane N 1270 * bits. 1271 */ 1272 DBG(DBG_LPU, NULL, "lpu_init - LPU_RECEIVE_PHY_CONFIG: 0x%llx\n", 1273 CSR_XR(csr_base, LPU_RECEIVE_PHY_CONFIG)); 1274 1275 /* 1276 * CSR_V LPU_RECEIVE_PHY_STATUS1 Expect HW 0x0 1277 */ 1278 DBG(DBG_LPU, NULL, "lpu_init - LPU_RECEIVE_PHY_STATUS1: 0x%llx\n", 1279 CSR_XR(csr_base, LPU_RECEIVE_PHY_STATUS1)); 1280 1281 /* 1282 * CSR_V LPU_RECEIVE_PHY_STATUS2 Expect HW 0x0 1283 */ 1284 DBG(DBG_LPU, NULL, "lpu_init - LPU_RECEIVE_PHY_STATUS2: 0x%llx\n", 1285 CSR_XR(csr_base, LPU_RECEIVE_PHY_STATUS2)); 1286 1287 /* 1288 * CSR_V LPU_RECEIVE_PHY_STATUS3 Expect HW 0x0 1289 */ 1290 DBG(DBG_LPU, NULL, "lpu_init - LPU_RECEIVE_PHY_STATUS3: 0x%llx\n", 1291 CSR_XR(csr_base, LPU_RECEIVE_PHY_STATUS3)); 1292 1293 /* 1294 * CSR_V LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 1295 */ 1296 DBG(DBG_LPU, NULL, 1297 "lpu_init - LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 1298 CSR_XR(csr_base, LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST)); 1299 1300 /* 1301 * CSR_V LPU RX LAYER interrupt regs (mask, status) 1302 */ 1303 DBG(DBG_LPU, NULL, 1304 "lpu_init - LPU_RECEIVE_PHY_INTERRUPT_MASK: 0x%llx\n", 1305 CSR_XR(csr_base, LPU_RECEIVE_PHY_INTERRUPT_MASK)); 1306 1307 DBG(DBG_LPU, NULL, 1308 "lpu_init - LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS: 0x%llx\n", 1309 CSR_XR(csr_base, LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS)); 1310 1311 /* 1312 * CSR_V LPU_TRANSMIT_PHY_CONFIG Expect HW 0x0 1313 */ 1314 DBG(DBG_LPU, NULL, "lpu_init - LPU_TRANSMIT_PHY_CONFIG: 0x%llx\n", 1315 CSR_XR(csr_base, LPU_TRANSMIT_PHY_CONFIG)); 1316 1317 /* 1318 * CSR_V LPU_TRANSMIT_PHY_STATUS Expect HW 0x0 1319 */ 1320 DBG(DBG_LPU, NULL, "lpu_init - LPU_TRANSMIT_PHY_STATUS: 0x%llx\n", 1321 CSR_XR(csr_base, LPU_TRANSMIT_PHY_STATUS)); 1322 1323 /* 1324 * CSR_V LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 1325 */ 1326 DBG(DBG_LPU, NULL, 1327 "lpu_init - LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 1328 CSR_XR(csr_base, 1329 LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST)); 1330 1331 /* 1332 * CSR_V LPU TX LAYER interrupt regs (mask, status) 1333 */ 1334 DBG(DBG_LPU, NULL, 1335 "lpu_init - LPU_TRANSMIT_PHY_INTERRUPT_MASK: 0x%llx\n", 1336 CSR_XR(csr_base, LPU_TRANSMIT_PHY_INTERRUPT_MASK)); 1337 1338 DBG(DBG_LPU, NULL, 1339 "lpu_init - LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS: 0x%llx\n", 1340 CSR_XR(csr_base, LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS)); 1341 1342 /* 1343 * CSR_V LPU_TRANSMIT_PHY_STATUS_2 Expect HW 0x0 1344 */ 1345 DBG(DBG_LPU, NULL, "lpu_init - LPU_TRANSMIT_PHY_STATUS_2: 0x%llx\n", 1346 CSR_XR(csr_base, LPU_TRANSMIT_PHY_STATUS_2)); 1347 1348 /* 1349 * CSR_V LPU_LTSSM_CONFIG1 Expect OBP 0x205 1350 */ 1351 1352 /* 1353 * The new PRM has values for LTSSM 8 ns timeout value and 1354 * LTSSM 20 ns timeout value. But what do these values mean? 1355 * Most of the other bits are questions as well. 1356 * 1357 * As such we will use the reset value. 1358 */ 1359 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG1: 0x%llx\n", 1360 CSR_XR(csr_base, LPU_LTSSM_CONFIG1)); 1361 1362 /* 1363 * CSR_V LPU_LTSSM_CONFIG2 Expect OBP 0x2DC6C0 1364 */ 1365 1366 /* 1367 * Again, what does '12 ms timeout value mean'? 1368 */ 1369 val = (LPU_LTSSM_CONFIG2_LTSSM_12_TO_DEFAULT << 1370 LPU_LTSSM_CONFIG2_LTSSM_12_TO); 1371 CSR_XS(csr_base, LPU_LTSSM_CONFIG2, val); 1372 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG2: 0x%llx\n", 1373 CSR_XR(csr_base, LPU_LTSSM_CONFIG2)); 1374 1375 /* 1376 * CSR_V LPU_LTSSM_CONFIG3 Expect OBP 0x7A120 1377 */ 1378 val = (LPU_LTSSM_CONFIG3_LTSSM_2_TO_DEFAULT << 1379 LPU_LTSSM_CONFIG3_LTSSM_2_TO); 1380 CSR_XS(csr_base, LPU_LTSSM_CONFIG3, val); 1381 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG3: 0x%llx\n", 1382 CSR_XR(csr_base, LPU_LTSSM_CONFIG3)); 1383 1384 /* 1385 * CSR_V LPU_LTSSM_CONFIG4 Expect OBP 0x21300 1386 */ 1387 val = ((LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT << 1388 LPU_LTSSM_CONFIG4_DATA_RATE) | 1389 (LPU_LTSSM_CONFIG4_N_FTS_DEFAULT << 1390 LPU_LTSSM_CONFIG4_N_FTS)); 1391 1392 CSR_XS(csr_base, LPU_LTSSM_CONFIG4, val); 1393 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG4: 0x%llx\n", 1394 CSR_XR(csr_base, LPU_LTSSM_CONFIG4)); 1395 1396 /* 1397 * CSR_V LPU_LTSSM_CONFIG5 Expect OBP 0x0 1398 */ 1399 val = 0ull; 1400 CSR_XS(csr_base, LPU_LTSSM_CONFIG5, val); 1401 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG5: 0x%llx\n", 1402 CSR_XR(csr_base, LPU_LTSSM_CONFIG5)); 1403 1404 /* 1405 * CSR_V LPU_LTSSM_STATUS1 Expect OBP 0x0 1406 */ 1407 1408 /* 1409 * LTSSM Status registers are test only. 1410 */ 1411 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_STATUS1: 0x%llx\n", 1412 CSR_XR(csr_base, LPU_LTSSM_STATUS1)); 1413 1414 /* 1415 * CSR_V LPU_LTSSM_STATUS2 Expect OBP 0x0 1416 */ 1417 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_STATUS2: 0x%llx\n", 1418 CSR_XR(csr_base, LPU_LTSSM_STATUS2)); 1419 1420 /* 1421 * CSR_V LPU_LTSSM_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 1422 */ 1423 DBG(DBG_LPU, NULL, 1424 "lpu_init - LPU_LTSSM_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 1425 CSR_XR(csr_base, LPU_LTSSM_INTERRUPT_AND_STATUS_TEST)); 1426 1427 /* 1428 * CSR_V LPU LTSSM LAYER interrupt regs (mask, status) 1429 */ 1430 DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_INTERRUPT_MASK: 0x%llx\n", 1431 CSR_XR(csr_base, LPU_LTSSM_INTERRUPT_MASK)); 1432 1433 DBG(DBG_LPU, NULL, 1434 "lpu_init - LPU_LTSSM_INTERRUPT_AND_STATUS: 0x%llx\n", 1435 CSR_XR(csr_base, LPU_LTSSM_INTERRUPT_AND_STATUS)); 1436 1437 /* 1438 * CSR_V LPU_LTSSM_STATUS_WRITE_ENABLE Expect OBP 0x0 1439 */ 1440 DBG(DBG_LPU, NULL, 1441 "lpu_init - LPU_LTSSM_STATUS_WRITE_ENABLE: 0x%llx\n", 1442 CSR_XR(csr_base, LPU_LTSSM_STATUS_WRITE_ENABLE)); 1443 1444 /* 1445 * CSR_V LPU_GIGABLAZE_GLUE_CONFIG1 Expect OBP 0x88407 1446 */ 1447 DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_CONFIG1: 0x%llx\n", 1448 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG1)); 1449 1450 /* 1451 * CSR_V LPU_GIGABLAZE_GLUE_CONFIG2 Expect OBP 0x35 1452 */ 1453 DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_CONFIG2: 0x%llx\n", 1454 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG2)); 1455 1456 /* 1457 * CSR_V LPU_GIGABLAZE_GLUE_CONFIG3 Expect OBP 0x4400FA 1458 */ 1459 DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_CONFIG3: 0x%llx\n", 1460 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG3)); 1461 1462 /* 1463 * CSR_V LPU_GIGABLAZE_GLUE_CONFIG4 Expect OBP 0x1E848 1464 */ 1465 DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_CONFIG4: 0x%llx\n", 1466 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG4)); 1467 1468 /* 1469 * CSR_V LPU_GIGABLAZE_GLUE_STATUS Expect OBP 0x0 1470 */ 1471 DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_STATUS: 0x%llx\n", 1472 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_STATUS)); 1473 1474 /* 1475 * CSR_V LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST Expect OBP 0x0 1476 */ 1477 DBG(DBG_LPU, NULL, "lpu_init - " 1478 "LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 1479 CSR_XR(csr_base, 1480 LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST)); 1481 1482 /* 1483 * CSR_V LPU GIGABLASE LAYER interrupt regs (mask, status) 1484 */ 1485 DBG(DBG_LPU, NULL, 1486 "lpu_init - LPU_GIGABLAZE_GLUE_INTERRUPT_MASK: 0x%llx\n", 1487 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_INTERRUPT_MASK)); 1488 1489 DBG(DBG_LPU, NULL, 1490 "lpu_init - LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS: 0x%llx\n", 1491 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS)); 1492 1493 /* 1494 * CSR_V LPU_GIGABLAZE_GLUE_POWER_DOWN1 Expect HW 0x0 1495 */ 1496 DBG(DBG_LPU, NULL, 1497 "lpu_init - LPU_GIGABLAZE_GLUE_POWER_DOWN1: 0x%llx\n", 1498 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_POWER_DOWN1)); 1499 1500 /* 1501 * CSR_V LPU_GIGABLAZE_GLUE_POWER_DOWN2 Expect HW 0x0 1502 */ 1503 DBG(DBG_LPU, NULL, 1504 "lpu_init - LPU_GIGABLAZE_GLUE_POWER_DOWN2: 0x%llx\n", 1505 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_POWER_DOWN2)); 1506 1507 /* 1508 * CSR_V LPU_GIGABLAZE_GLUE_CONFIG5 Expect OBP 0x0 1509 */ 1510 DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_CONFIG5: 0x%llx\n", 1511 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG5)); 1512 } 1513 1514 /* ARGSUSED */ 1515 static void 1516 dlu_init(caddr_t csr_base, pxu_t *pxu_p) 1517 { 1518 uint64_t val; 1519 1520 CSR_XS(csr_base, DLU_INTERRUPT_MASK, 0ull); 1521 DBG(DBG_TLU, NULL, "dlu_init - DLU_INTERRUPT_MASK: 0x%llx\n", 1522 CSR_XR(csr_base, DLU_INTERRUPT_MASK)); 1523 1524 val = (1ull << DLU_LINK_LAYER_CONFIG_VC0_EN); 1525 CSR_XS(csr_base, DLU_LINK_LAYER_CONFIG, val); 1526 DBG(DBG_TLU, NULL, "dlu_init - DLU_LINK_LAYER_CONFIG: 0x%llx\n", 1527 CSR_XR(csr_base, DLU_LINK_LAYER_CONFIG)); 1528 1529 val = (1ull << DLU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_NP_EN) | 1530 (1ull << DLU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_P_EN); 1531 1532 CSR_XS(csr_base, DLU_FLOW_CONTROL_UPDATE_CONTROL, val); 1533 DBG(DBG_TLU, NULL, "dlu_init - DLU_FLOW_CONTROL_UPDATE_CONTROL: " 1534 "0x%llx\n", CSR_XR(csr_base, DLU_FLOW_CONTROL_UPDATE_CONTROL)); 1535 1536 val = (DLU_TXLINK_REPLAY_TIMER_THRESHOLD_DEFAULT << 1537 DLU_TXLINK_REPLAY_TIMER_THRESHOLD_RPLAY_TMR_THR); 1538 1539 CSR_XS(csr_base, DLU_TXLINK_REPLAY_TIMER_THRESHOLD, val); 1540 1541 DBG(DBG_TLU, NULL, "dlu_init - DLU_TXLINK_REPLAY_TIMER_THRESHOLD: " 1542 "0x%llx\n", CSR_XR(csr_base, DLU_TXLINK_REPLAY_TIMER_THRESHOLD)); 1543 } 1544 1545 /* ARGSUSED */ 1546 static void 1547 dmc_init(caddr_t csr_base, pxu_t *pxu_p) 1548 { 1549 uint64_t val; 1550 1551 /* 1552 * CSR_V DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE Expect OBP 0x8000000000000003 1553 */ 1554 1555 val = -1ull; 1556 CSR_XS(csr_base, DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE, val); 1557 DBG(DBG_DMC, NULL, 1558 "dmc_init - DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE: 0x%llx\n", 1559 CSR_XR(csr_base, DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE)); 1560 1561 /* 1562 * CSR_V DMC_CORE_AND_BLOCK_ERROR_STATUS Expect HW 0x0 1563 */ 1564 DBG(DBG_DMC, NULL, 1565 "dmc_init - DMC_CORE_AND_BLOCK_ERROR_STATUS: 0x%llx\n", 1566 CSR_XR(csr_base, DMC_CORE_AND_BLOCK_ERROR_STATUS)); 1567 1568 /* 1569 * CSR_V DMC_DEBUG_SELECT_FOR_PORT_A Expect HW 0x0 1570 */ 1571 val = 0x0ull; 1572 CSR_XS(csr_base, DMC_DEBUG_SELECT_FOR_PORT_A, val); 1573 DBG(DBG_DMC, NULL, "dmc_init - DMC_DEBUG_SELECT_FOR_PORT_A: 0x%llx\n", 1574 CSR_XR(csr_base, DMC_DEBUG_SELECT_FOR_PORT_A)); 1575 1576 /* 1577 * CSR_V DMC_DEBUG_SELECT_FOR_PORT_B Expect HW 0x0 1578 */ 1579 val = 0x0ull; 1580 CSR_XS(csr_base, DMC_DEBUG_SELECT_FOR_PORT_B, val); 1581 DBG(DBG_DMC, NULL, "dmc_init - DMC_DEBUG_SELECT_FOR_PORT_B: 0x%llx\n", 1582 CSR_XR(csr_base, DMC_DEBUG_SELECT_FOR_PORT_B)); 1583 } 1584 1585 void 1586 hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p) 1587 { 1588 uint64_t val; 1589 1590 ilu_init(csr_base, pxu_p); 1591 tlu_init(csr_base, pxu_p); 1592 1593 switch (PX_CHIP_TYPE(pxu_p)) { 1594 case PX_CHIP_OBERON: 1595 dlu_init(csr_base, pxu_p); 1596 break; 1597 case PX_CHIP_FIRE: 1598 lpu_init(csr_base, pxu_p); 1599 break; 1600 default: 1601 DBG(DBG_PEC, NULL, "hvio_pec_init - unknown chip type: 0x%x\n", 1602 PX_CHIP_TYPE(pxu_p)); 1603 break; 1604 } 1605 1606 dmc_init(csr_base, pxu_p); 1607 1608 /* 1609 * CSR_V PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE Expect Kernel 0x800000000000000F 1610 */ 1611 1612 val = -1ull; 1613 CSR_XS(csr_base, PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE, val); 1614 DBG(DBG_PEC, NULL, 1615 "hvio_pec_init - PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE: 0x%llx\n", 1616 CSR_XR(csr_base, PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE)); 1617 1618 /* 1619 * CSR_V PEC_CORE_AND_BLOCK_INTERRUPT_STATUS Expect HW 0x0 1620 */ 1621 DBG(DBG_PEC, NULL, 1622 "hvio_pec_init - PEC_CORE_AND_BLOCK_INTERRUPT_STATUS: 0x%llx\n", 1623 CSR_XR(csr_base, PEC_CORE_AND_BLOCK_INTERRUPT_STATUS)); 1624 } 1625 1626 /* 1627 * Convert a TTE to physical address 1628 */ 1629 static r_addr_t 1630 mmu_tte_to_pa(uint64_t tte, pxu_t *pxu_p) 1631 { 1632 uint64_t pa_mask; 1633 1634 switch (PX_CHIP_TYPE(pxu_p)) { 1635 case PX_CHIP_OBERON: 1636 pa_mask = MMU_OBERON_PADDR_MASK; 1637 break; 1638 case PX_CHIP_FIRE: 1639 pa_mask = MMU_FIRE_PADDR_MASK; 1640 break; 1641 default: 1642 DBG(DBG_MMU, NULL, "mmu_tte_to_pa - unknown chip type: 0x%x\n", 1643 PX_CHIP_TYPE(pxu_p)); 1644 pa_mask = 0; 1645 break; 1646 } 1647 return ((tte & pa_mask) >> MMU_PAGE_SHIFT); 1648 } 1649 1650 /* 1651 * Return MMU bypass noncache bit for chip 1652 */ 1653 static r_addr_t 1654 mmu_bypass_noncache(pxu_t *pxu_p) 1655 { 1656 r_addr_t bypass_noncache_bit; 1657 1658 switch (PX_CHIP_TYPE(pxu_p)) { 1659 case PX_CHIP_OBERON: 1660 bypass_noncache_bit = MMU_OBERON_BYPASS_NONCACHE; 1661 break; 1662 case PX_CHIP_FIRE: 1663 bypass_noncache_bit = MMU_FIRE_BYPASS_NONCACHE; 1664 break; 1665 default: 1666 DBG(DBG_MMU, NULL, 1667 "mmu_bypass_nocache - unknown chip type: 0x%x\n", 1668 PX_CHIP_TYPE(pxu_p)); 1669 bypass_noncache_bit = 0; 1670 break; 1671 } 1672 return (bypass_noncache_bit); 1673 } 1674 1675 /* 1676 * Calculate number of TSB entries for the chip. 1677 */ 1678 /* ARGSUSED */ 1679 static uint_t 1680 mmu_tsb_entries(caddr_t csr_base, pxu_t *pxu_p) 1681 { 1682 uint64_t tsb_ctrl; 1683 uint_t obp_tsb_entries, obp_tsb_size; 1684 1685 tsb_ctrl = CSR_XR(csr_base, MMU_TSB_CONTROL); 1686 1687 obp_tsb_size = tsb_ctrl & 0xF; 1688 1689 obp_tsb_entries = MMU_TSBSIZE_TO_TSBENTRIES(obp_tsb_size); 1690 1691 return (obp_tsb_entries); 1692 } 1693 1694 /* 1695 * Initialize the module, but do not enable interrupts. 1696 */ 1697 void 1698 hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p) 1699 { 1700 uint64_t val, i, obp_tsb_pa, *base_tte_addr; 1701 uint_t obp_tsb_entries; 1702 1703 bzero(pxu_p->tsb_vaddr, pxu_p->tsb_size); 1704 1705 /* 1706 * Preserve OBP's TSB 1707 */ 1708 obp_tsb_pa = CSR_XR(csr_base, MMU_TSB_CONTROL) & MMU_TSB_PA_MASK; 1709 1710 obp_tsb_entries = mmu_tsb_entries(csr_base, pxu_p); 1711 1712 base_tte_addr = pxu_p->tsb_vaddr + 1713 ((pxu_p->tsb_size >> 3) - obp_tsb_entries); 1714 1715 for (i = 0; i < obp_tsb_entries; i++) { 1716 uint64_t tte = lddphys(obp_tsb_pa + i * 8); 1717 1718 if (!MMU_TTE_VALID(tte)) 1719 continue; 1720 1721 base_tte_addr[i] = tte; 1722 } 1723 1724 /* 1725 * Invalidate the TLB through the diagnostic register. 1726 */ 1727 1728 CSR_XS(csr_base, MMU_TTE_CACHE_INVALIDATE, -1ull); 1729 1730 /* 1731 * Configure the Fire MMU TSB Control Register. Determine 1732 * the encoding for either 8KB pages (0) or 64KB pages (1). 1733 * 1734 * Write the most significant 30 bits of the TSB physical address 1735 * and the encoded TSB table size. 1736 */ 1737 for (i = 8; i && (pxu_p->tsb_size < (0x2000 << i)); i--) 1738 ; 1739 1740 val = (((((va_to_pa(pxu_p->tsb_vaddr)) >> 13) << 13) | 1741 ((MMU_PAGE_SHIFT == 13) ? 0 : 1) << 8) | i); 1742 1743 CSR_XS(csr_base, MMU_TSB_CONTROL, val); 1744 1745 /* 1746 * Enable the MMU, set the "TSB Cache Snoop Enable", 1747 * the "Cache Mode", the "Bypass Enable" and 1748 * the "Translation Enable" bits. 1749 */ 1750 val = CSR_XR(csr_base, MMU_CONTROL_AND_STATUS); 1751 val |= ((1ull << MMU_CONTROL_AND_STATUS_SE) 1752 | (MMU_CONTROL_AND_STATUS_ROE_BIT63_ENABLE << 1753 MMU_CONTROL_AND_STATUS_ROE) 1754 | (MMU_CONTROL_AND_STATUS_CM_MASK << MMU_CONTROL_AND_STATUS_CM) 1755 | (1ull << MMU_CONTROL_AND_STATUS_BE) 1756 | (1ull << MMU_CONTROL_AND_STATUS_TE)); 1757 1758 CSR_XS(csr_base, MMU_CONTROL_AND_STATUS, val); 1759 1760 /* 1761 * Read the register here to ensure that the previous writes to 1762 * the Fire MMU registers have been flushed. (Technically, this 1763 * is not entirely necessary here as we will likely do later reads 1764 * during Fire initialization, but it is a small price to pay for 1765 * more modular code.) 1766 */ 1767 (void) CSR_XR(csr_base, MMU_CONTROL_AND_STATUS); 1768 1769 /* 1770 * CSR_V TLU's UE interrupt regs (log, enable, status, clear) 1771 * Plus header logs 1772 */ 1773 DBG(DBG_MMU, NULL, "mmu_init - MMU_ERROR_LOG_ENABLE: 0x%llx\n", 1774 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE)); 1775 1776 DBG(DBG_MMU, NULL, "mmu_init - MMU_INTERRUPT_ENABLE: 0x%llx\n", 1777 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE)); 1778 1779 DBG(DBG_MMU, NULL, "mmu_init - MMU_INTERRUPT_STATUS: 0x%llx\n", 1780 CSR_XR(csr_base, MMU_INTERRUPT_STATUS)); 1781 1782 DBG(DBG_MMU, NULL, "mmu_init - MMU_ERROR_STATUS_CLEAR: 0x%llx\n", 1783 CSR_XR(csr_base, MMU_ERROR_STATUS_CLEAR)); 1784 } 1785 1786 /* 1787 * Generic IOMMU Servies 1788 */ 1789 1790 /* ARGSUSED */ 1791 uint64_t 1792 hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, pages_t pages, 1793 io_attributes_t io_attr, void *addr, size_t pfn_index, int flags) 1794 { 1795 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 1796 uint64_t attr = MMU_TTE_V; 1797 int i; 1798 1799 if (io_attr & PCI_MAP_ATTR_WRITE) 1800 attr |= MMU_TTE_W; 1801 1802 if ((PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) && 1803 (io_attr & PCI_MAP_ATTR_RO)) 1804 attr |= MMU_TTE_RO; 1805 1806 if (attr & MMU_TTE_RO) { 1807 DBG(DBG_MMU, NULL, "hvio_iommu_map: pfn_index=0x%x " 1808 "pages=0x%x attr = 0x%lx\n", pfn_index, pages, attr); 1809 } 1810 1811 if (flags & MMU_MAP_PFN) { 1812 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)addr; 1813 for (i = 0; i < pages; i++, pfn_index++, tsb_index++) { 1814 px_iopfn_t pfn = PX_GET_MP_PFN(mp, pfn_index); 1815 pxu_p->tsb_vaddr[tsb_index] = MMU_PTOB(pfn) | attr; 1816 1817 /* 1818 * Oberon will need to flush the corresponding TTEs in 1819 * Cache. We only need to flush every cache line. 1820 * Extra PIO's are expensive. 1821 */ 1822 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 1823 if ((i == (pages-1))||!((tsb_index+1) & 0x7)) { 1824 CSR_XS(dev_hdl, 1825 MMU_TTE_CACHE_FLUSH_ADDRESS, 1826 (pxu_p->tsb_paddr+ 1827 (tsb_index*MMU_TTE_SIZE))); 1828 } 1829 } 1830 } 1831 } else { 1832 caddr_t a = (caddr_t)addr; 1833 for (i = 0; i < pages; i++, a += MMU_PAGE_SIZE, tsb_index++) { 1834 px_iopfn_t pfn = hat_getpfnum(kas.a_hat, a); 1835 pxu_p->tsb_vaddr[tsb_index] = MMU_PTOB(pfn) | attr; 1836 1837 /* 1838 * Oberon will need to flush the corresponding TTEs in 1839 * Cache. We only need to flush every cache line. 1840 * Extra PIO's are expensive. 1841 */ 1842 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 1843 if ((i == (pages-1))||!((tsb_index+1) & 0x7)) { 1844 CSR_XS(dev_hdl, 1845 MMU_TTE_CACHE_FLUSH_ADDRESS, 1846 (pxu_p->tsb_paddr+ 1847 (tsb_index*MMU_TTE_SIZE))); 1848 } 1849 } 1850 } 1851 } 1852 1853 return (H_EOK); 1854 } 1855 1856 /* ARGSUSED */ 1857 uint64_t 1858 hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, 1859 pages_t pages) 1860 { 1861 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 1862 int i; 1863 1864 for (i = 0; i < pages; i++, tsb_index++) { 1865 pxu_p->tsb_vaddr[tsb_index] = MMU_INVALID_TTE; 1866 1867 /* 1868 * Oberon will need to flush the corresponding TTEs in 1869 * Cache. We only need to flush every cache line. 1870 * Extra PIO's are expensive. 1871 */ 1872 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 1873 if ((i == (pages-1))||!((tsb_index+1) & 0x7)) { 1874 CSR_XS(dev_hdl, 1875 MMU_TTE_CACHE_FLUSH_ADDRESS, 1876 (pxu_p->tsb_paddr+ 1877 (tsb_index*MMU_TTE_SIZE))); 1878 } 1879 } 1880 } 1881 1882 return (H_EOK); 1883 } 1884 1885 /* ARGSUSED */ 1886 uint64_t 1887 hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, 1888 io_attributes_t *attr_p, r_addr_t *r_addr_p) 1889 { 1890 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 1891 uint64_t *tte_addr; 1892 uint64_t ret = H_EOK; 1893 1894 tte_addr = (uint64_t *)(pxu_p->tsb_vaddr) + tsb_index; 1895 1896 if (*tte_addr & MMU_TTE_V) { 1897 *r_addr_p = mmu_tte_to_pa(*tte_addr, pxu_p); 1898 *attr_p = (*tte_addr & MMU_TTE_W) ? 1899 PCI_MAP_ATTR_WRITE:PCI_MAP_ATTR_READ; 1900 } else { 1901 *r_addr_p = 0; 1902 *attr_p = 0; 1903 ret = H_ENOMAP; 1904 } 1905 1906 return (ret); 1907 } 1908 1909 /* ARGSUSED */ 1910 uint64_t 1911 hvio_get_bypass_base(pxu_t *pxu_p) 1912 { 1913 uint64_t base; 1914 1915 switch (PX_CHIP_TYPE(pxu_p)) { 1916 case PX_CHIP_OBERON: 1917 base = MMU_OBERON_BYPASS_BASE; 1918 break; 1919 case PX_CHIP_FIRE: 1920 base = MMU_FIRE_BYPASS_BASE; 1921 break; 1922 default: 1923 DBG(DBG_MMU, NULL, 1924 "hvio_get_bypass_base - unknown chip type: 0x%x\n", 1925 PX_CHIP_TYPE(pxu_p)); 1926 base = 0; 1927 break; 1928 } 1929 return (base); 1930 } 1931 1932 /* ARGSUSED */ 1933 uint64_t 1934 hvio_get_bypass_end(pxu_t *pxu_p) 1935 { 1936 uint64_t end; 1937 1938 switch (PX_CHIP_TYPE(pxu_p)) { 1939 case PX_CHIP_OBERON: 1940 end = MMU_OBERON_BYPASS_END; 1941 break; 1942 case PX_CHIP_FIRE: 1943 end = MMU_FIRE_BYPASS_END; 1944 break; 1945 default: 1946 DBG(DBG_MMU, NULL, 1947 "hvio_get_bypass_end - unknown chip type: 0x%x\n", 1948 PX_CHIP_TYPE(pxu_p)); 1949 end = 0; 1950 break; 1951 } 1952 return (end); 1953 } 1954 1955 /* ARGSUSED */ 1956 uint64_t 1957 hvio_iommu_getbypass(devhandle_t dev_hdl, pxu_t *pxu_p, r_addr_t ra, 1958 io_attributes_t attr, io_addr_t *io_addr_p) 1959 { 1960 uint64_t pfn = MMU_BTOP(ra); 1961 1962 *io_addr_p = hvio_get_bypass_base(pxu_p) | ra | 1963 (pf_is_memory(pfn) ? 0 : mmu_bypass_noncache(pxu_p)); 1964 1965 return (H_EOK); 1966 } 1967 1968 /* 1969 * Generic IO Interrupt Servies 1970 */ 1971 1972 /* 1973 * Converts a device specific interrupt number given by the 1974 * arguments devhandle and devino into a system specific ino. 1975 */ 1976 /* ARGSUSED */ 1977 uint64_t 1978 hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p, devino_t devino, 1979 sysino_t *sysino) 1980 { 1981 if (devino > INTERRUPT_MAPPING_ENTRIES) { 1982 DBG(DBG_IB, NULL, "ino %x is invalid\n", devino); 1983 return (H_ENOINTR); 1984 } 1985 1986 *sysino = DEVINO_TO_SYSINO(pxu_p->portid, devino); 1987 1988 return (H_EOK); 1989 } 1990 1991 /* 1992 * Returns state in intr_valid_state if the interrupt defined by sysino 1993 * is valid (enabled) or not-valid (disabled). 1994 */ 1995 uint64_t 1996 hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino, 1997 intr_valid_state_t *intr_valid_state) 1998 { 1999 if (CSRA_BR((caddr_t)dev_hdl, INTERRUPT_MAPPING, 2000 SYSINO_TO_DEVINO(sysino), ENTRIES_V)) { 2001 *intr_valid_state = INTR_VALID; 2002 } else { 2003 *intr_valid_state = INTR_NOTVALID; 2004 } 2005 2006 return (H_EOK); 2007 } 2008 2009 /* 2010 * Sets the 'valid' state of the interrupt defined by 2011 * the argument sysino to the state defined by the 2012 * argument intr_valid_state. 2013 */ 2014 uint64_t 2015 hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino, 2016 intr_valid_state_t intr_valid_state) 2017 { 2018 switch (intr_valid_state) { 2019 case INTR_VALID: 2020 CSRA_BS((caddr_t)dev_hdl, INTERRUPT_MAPPING, 2021 SYSINO_TO_DEVINO(sysino), ENTRIES_V); 2022 break; 2023 case INTR_NOTVALID: 2024 CSRA_BC((caddr_t)dev_hdl, INTERRUPT_MAPPING, 2025 SYSINO_TO_DEVINO(sysino), ENTRIES_V); 2026 break; 2027 default: 2028 return (EINVAL); 2029 } 2030 2031 return (H_EOK); 2032 } 2033 2034 /* 2035 * Returns the current state of the interrupt given by the sysino 2036 * argument. 2037 */ 2038 uint64_t 2039 hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino, 2040 intr_state_t *intr_state) 2041 { 2042 intr_state_t state; 2043 2044 state = CSRA_FR((caddr_t)dev_hdl, INTERRUPT_CLEAR, 2045 SYSINO_TO_DEVINO(sysino), ENTRIES_INT_STATE); 2046 2047 switch (state) { 2048 case INTERRUPT_IDLE_STATE: 2049 *intr_state = INTR_IDLE_STATE; 2050 break; 2051 case INTERRUPT_RECEIVED_STATE: 2052 *intr_state = INTR_RECEIVED_STATE; 2053 break; 2054 case INTERRUPT_PENDING_STATE: 2055 *intr_state = INTR_DELIVERED_STATE; 2056 break; 2057 default: 2058 return (EINVAL); 2059 } 2060 2061 return (H_EOK); 2062 2063 } 2064 2065 /* 2066 * Sets the current state of the interrupt given by the sysino 2067 * argument to the value given in the argument intr_state. 2068 * 2069 * Note: Setting the state to INTR_IDLE clears any pending 2070 * interrupt for sysino. 2071 */ 2072 uint64_t 2073 hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino, 2074 intr_state_t intr_state) 2075 { 2076 intr_state_t state; 2077 2078 switch (intr_state) { 2079 case INTR_IDLE_STATE: 2080 state = INTERRUPT_IDLE_STATE; 2081 break; 2082 case INTR_DELIVERED_STATE: 2083 state = INTERRUPT_PENDING_STATE; 2084 break; 2085 default: 2086 return (EINVAL); 2087 } 2088 2089 CSRA_FS((caddr_t)dev_hdl, INTERRUPT_CLEAR, 2090 SYSINO_TO_DEVINO(sysino), ENTRIES_INT_STATE, state); 2091 2092 return (H_EOK); 2093 } 2094 2095 /* 2096 * Returns the cpuid that is the current target of the 2097 * interrupt given by the sysino argument. 2098 * 2099 * The cpuid value returned is undefined if the target 2100 * has not been set via intr_settarget. 2101 */ 2102 uint64_t 2103 hvio_intr_gettarget(devhandle_t dev_hdl, pxu_t *pxu_p, sysino_t sysino, 2104 cpuid_t *cpuid) 2105 { 2106 switch (PX_CHIP_TYPE(pxu_p)) { 2107 case PX_CHIP_OBERON: 2108 *cpuid = CSRA_FR((caddr_t)dev_hdl, INTERRUPT_MAPPING, 2109 SYSINO_TO_DEVINO(sysino), ENTRIES_T_DESTID); 2110 break; 2111 case PX_CHIP_FIRE: 2112 *cpuid = CSRA_FR((caddr_t)dev_hdl, INTERRUPT_MAPPING, 2113 SYSINO_TO_DEVINO(sysino), ENTRIES_T_JPID); 2114 break; 2115 default: 2116 DBG(DBG_CB, NULL, "hvio_intr_gettarget - " 2117 "unknown chip type: 0x%x\n", PX_CHIP_TYPE(pxu_p)); 2118 return (EINVAL); 2119 } 2120 2121 return (H_EOK); 2122 } 2123 2124 /* 2125 * Set the target cpu for the interrupt defined by the argument 2126 * sysino to the target cpu value defined by the argument cpuid. 2127 */ 2128 uint64_t 2129 hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p, sysino_t sysino, 2130 cpuid_t cpuid) 2131 { 2132 uint64_t val, intr_controller; 2133 uint32_t ino = SYSINO_TO_DEVINO(sysino); 2134 2135 /* 2136 * For now, we assign interrupt controller in a round 2137 * robin fashion. Later, we may need to come up with 2138 * a more efficient assignment algorithm. 2139 */ 2140 intr_controller = 0x1ull << (cpuid % 4); 2141 2142 switch (PX_CHIP_TYPE(pxu_p)) { 2143 case PX_CHIP_OBERON: 2144 val = (((cpuid & 2145 INTERRUPT_MAPPING_ENTRIES_T_DESTID_MASK) << 2146 INTERRUPT_MAPPING_ENTRIES_T_DESTID) | 2147 ((intr_controller & 2148 INTERRUPT_MAPPING_ENTRIES_INT_CNTRL_NUM_MASK) 2149 << INTERRUPT_MAPPING_ENTRIES_INT_CNTRL_NUM)); 2150 break; 2151 case PX_CHIP_FIRE: 2152 val = (((cpuid & INTERRUPT_MAPPING_ENTRIES_T_JPID_MASK) << 2153 INTERRUPT_MAPPING_ENTRIES_T_JPID) | 2154 ((intr_controller & 2155 INTERRUPT_MAPPING_ENTRIES_INT_CNTRL_NUM_MASK) 2156 << INTERRUPT_MAPPING_ENTRIES_INT_CNTRL_NUM)); 2157 break; 2158 default: 2159 DBG(DBG_CB, NULL, "hvio_intr_settarget - " 2160 "unknown chip type: 0x%x\n", PX_CHIP_TYPE(pxu_p)); 2161 return (EINVAL); 2162 } 2163 2164 /* For EQ interrupts, set DATA MONDO bit */ 2165 if ((ino >= EQ_1ST_DEVINO) && (ino < (EQ_1ST_DEVINO + EQ_CNT))) 2166 val |= (0x1ull << INTERRUPT_MAPPING_ENTRIES_MDO_MODE); 2167 2168 CSRA_XS((caddr_t)dev_hdl, INTERRUPT_MAPPING, ino, val); 2169 2170 return (H_EOK); 2171 } 2172 2173 /* 2174 * MSIQ Functions: 2175 */ 2176 uint64_t 2177 hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p) 2178 { 2179 CSRA_XS((caddr_t)dev_hdl, EVENT_QUEUE_BASE_ADDRESS, 0, 2180 (uint64_t)pxu_p->msiq_mapped_p); 2181 DBG(DBG_IB, NULL, 2182 "hvio_msiq_init: EVENT_QUEUE_BASE_ADDRESS 0x%llx\n", 2183 CSR_XR((caddr_t)dev_hdl, EVENT_QUEUE_BASE_ADDRESS)); 2184 2185 CSRA_XS((caddr_t)dev_hdl, INTERRUPT_MONDO_DATA_0, 0, 2186 (uint64_t)ID_TO_IGN(PX_CHIP_TYPE(pxu_p), 2187 pxu_p->portid) << INO_BITS); 2188 DBG(DBG_IB, NULL, "hvio_msiq_init: " 2189 "INTERRUPT_MONDO_DATA_0: 0x%llx\n", 2190 CSR_XR((caddr_t)dev_hdl, INTERRUPT_MONDO_DATA_0)); 2191 2192 return (H_EOK); 2193 } 2194 2195 uint64_t 2196 hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 2197 pci_msiq_valid_state_t *msiq_valid_state) 2198 { 2199 uint32_t eq_state; 2200 uint64_t ret = H_EOK; 2201 2202 eq_state = CSRA_FR((caddr_t)dev_hdl, EVENT_QUEUE_STATE, 2203 msiq_id, ENTRIES_STATE); 2204 2205 switch (eq_state) { 2206 case EQ_IDLE_STATE: 2207 *msiq_valid_state = PCI_MSIQ_INVALID; 2208 break; 2209 case EQ_ACTIVE_STATE: 2210 case EQ_ERROR_STATE: 2211 *msiq_valid_state = PCI_MSIQ_VALID; 2212 break; 2213 default: 2214 ret = H_EIO; 2215 break; 2216 } 2217 2218 return (ret); 2219 } 2220 2221 uint64_t 2222 hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 2223 pci_msiq_valid_state_t msiq_valid_state) 2224 { 2225 uint64_t ret = H_EOK; 2226 2227 switch (msiq_valid_state) { 2228 case PCI_MSIQ_INVALID: 2229 CSRA_BS((caddr_t)dev_hdl, EVENT_QUEUE_CONTROL_CLEAR, 2230 msiq_id, ENTRIES_DIS); 2231 break; 2232 case PCI_MSIQ_VALID: 2233 CSRA_BS((caddr_t)dev_hdl, EVENT_QUEUE_CONTROL_SET, 2234 msiq_id, ENTRIES_EN); 2235 break; 2236 default: 2237 ret = H_EINVAL; 2238 break; 2239 } 2240 2241 return (ret); 2242 } 2243 2244 uint64_t 2245 hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 2246 pci_msiq_state_t *msiq_state) 2247 { 2248 uint32_t eq_state; 2249 uint64_t ret = H_EOK; 2250 2251 eq_state = CSRA_FR((caddr_t)dev_hdl, EVENT_QUEUE_STATE, 2252 msiq_id, ENTRIES_STATE); 2253 2254 switch (eq_state) { 2255 case EQ_IDLE_STATE: 2256 case EQ_ACTIVE_STATE: 2257 *msiq_state = PCI_MSIQ_STATE_IDLE; 2258 break; 2259 case EQ_ERROR_STATE: 2260 *msiq_state = PCI_MSIQ_STATE_ERROR; 2261 break; 2262 default: 2263 ret = H_EIO; 2264 } 2265 2266 return (ret); 2267 } 2268 2269 uint64_t 2270 hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 2271 pci_msiq_state_t msiq_state) 2272 { 2273 uint32_t eq_state; 2274 uint64_t ret = H_EOK; 2275 2276 eq_state = CSRA_FR((caddr_t)dev_hdl, EVENT_QUEUE_STATE, 2277 msiq_id, ENTRIES_STATE); 2278 2279 switch (eq_state) { 2280 case EQ_IDLE_STATE: 2281 if (msiq_state == PCI_MSIQ_STATE_ERROR) 2282 ret = H_EIO; 2283 break; 2284 case EQ_ACTIVE_STATE: 2285 if (msiq_state == PCI_MSIQ_STATE_ERROR) 2286 CSRA_BS((caddr_t)dev_hdl, EVENT_QUEUE_CONTROL_SET, 2287 msiq_id, ENTRIES_ENOVERR); 2288 else 2289 ret = H_EIO; 2290 break; 2291 case EQ_ERROR_STATE: 2292 if (msiq_state == PCI_MSIQ_STATE_IDLE) 2293 CSRA_BS((caddr_t)dev_hdl, EVENT_QUEUE_CONTROL_CLEAR, 2294 msiq_id, ENTRIES_E2I); 2295 else 2296 ret = H_EIO; 2297 break; 2298 default: 2299 ret = H_EIO; 2300 } 2301 2302 return (ret); 2303 } 2304 2305 uint64_t 2306 hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 2307 msiqhead_t *msiq_head) 2308 { 2309 *msiq_head = CSRA_FR((caddr_t)dev_hdl, EVENT_QUEUE_HEAD, 2310 msiq_id, ENTRIES_HEAD); 2311 2312 return (H_EOK); 2313 } 2314 2315 uint64_t 2316 hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 2317 msiqhead_t msiq_head) 2318 { 2319 CSRA_FS((caddr_t)dev_hdl, EVENT_QUEUE_HEAD, msiq_id, 2320 ENTRIES_HEAD, msiq_head); 2321 2322 return (H_EOK); 2323 } 2324 2325 uint64_t 2326 hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 2327 msiqtail_t *msiq_tail) 2328 { 2329 *msiq_tail = CSRA_FR((caddr_t)dev_hdl, EVENT_QUEUE_TAIL, 2330 msiq_id, ENTRIES_TAIL); 2331 2332 return (H_EOK); 2333 } 2334 2335 /* 2336 * MSI Functions: 2337 */ 2338 uint64_t 2339 hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32, uint64_t addr64) 2340 { 2341 /* PCI MEM 32 resources to perform 32 bit MSI transactions */ 2342 CSRA_FS((caddr_t)dev_hdl, MSI_32_BIT_ADDRESS, 0, 2343 ADDR, (uint64_t)addr32 >> MSI_32_BIT_ADDRESS_ADDR); 2344 DBG(DBG_IB, NULL, "hvio_msi_init: MSI_32_BIT_ADDRESS: 0x%llx\n", 2345 CSR_XR((caddr_t)dev_hdl, MSI_32_BIT_ADDRESS)); 2346 2347 /* Reserve PCI MEM 64 resources to perform 64 bit MSI transactions */ 2348 CSRA_FS((caddr_t)dev_hdl, MSI_64_BIT_ADDRESS, 0, 2349 ADDR, (uint64_t)addr64 >> MSI_64_BIT_ADDRESS_ADDR); 2350 DBG(DBG_IB, NULL, "hvio_msi_init: MSI_64_BIT_ADDRESS: 0x%llx\n", 2351 CSR_XR((caddr_t)dev_hdl, MSI_64_BIT_ADDRESS)); 2352 2353 return (H_EOK); 2354 } 2355 2356 uint64_t 2357 hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 2358 msiqid_t *msiq_id) 2359 { 2360 *msiq_id = CSRA_FR((caddr_t)dev_hdl, MSI_MAPPING, 2361 msi_num, ENTRIES_EQNUM); 2362 2363 return (H_EOK); 2364 } 2365 2366 uint64_t 2367 hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 2368 msiqid_t msiq_id) 2369 { 2370 CSRA_FS((caddr_t)dev_hdl, MSI_MAPPING, msi_num, 2371 ENTRIES_EQNUM, msiq_id); 2372 2373 return (H_EOK); 2374 } 2375 2376 uint64_t 2377 hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 2378 pci_msi_valid_state_t *msi_valid_state) 2379 { 2380 *msi_valid_state = CSRA_BR((caddr_t)dev_hdl, MSI_MAPPING, 2381 msi_num, ENTRIES_V); 2382 2383 return (H_EOK); 2384 } 2385 2386 uint64_t 2387 hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 2388 pci_msi_valid_state_t msi_valid_state) 2389 { 2390 uint64_t ret = H_EOK; 2391 2392 switch (msi_valid_state) { 2393 case PCI_MSI_VALID: 2394 CSRA_BS((caddr_t)dev_hdl, MSI_MAPPING, msi_num, 2395 ENTRIES_V); 2396 break; 2397 case PCI_MSI_INVALID: 2398 CSRA_BC((caddr_t)dev_hdl, MSI_MAPPING, msi_num, 2399 ENTRIES_V); 2400 break; 2401 default: 2402 ret = H_EINVAL; 2403 } 2404 2405 return (ret); 2406 } 2407 2408 uint64_t 2409 hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 2410 pci_msi_state_t *msi_state) 2411 { 2412 *msi_state = CSRA_BR((caddr_t)dev_hdl, MSI_MAPPING, 2413 msi_num, ENTRIES_EQWR_N); 2414 2415 return (H_EOK); 2416 } 2417 2418 uint64_t 2419 hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 2420 pci_msi_state_t msi_state) 2421 { 2422 uint64_t ret = H_EOK; 2423 2424 switch (msi_state) { 2425 case PCI_MSI_STATE_IDLE: 2426 CSRA_BS((caddr_t)dev_hdl, MSI_CLEAR, msi_num, 2427 ENTRIES_EQWR_N); 2428 break; 2429 case PCI_MSI_STATE_DELIVERED: 2430 default: 2431 ret = H_EINVAL; 2432 break; 2433 } 2434 2435 return (ret); 2436 } 2437 2438 /* 2439 * MSG Functions: 2440 */ 2441 uint64_t 2442 hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 2443 msiqid_t *msiq_id) 2444 { 2445 uint64_t ret = H_EOK; 2446 2447 switch (msg_type) { 2448 case PCIE_PME_MSG: 2449 *msiq_id = CSR_FR((caddr_t)dev_hdl, PM_PME_MAPPING, EQNUM); 2450 break; 2451 case PCIE_PME_ACK_MSG: 2452 *msiq_id = CSR_FR((caddr_t)dev_hdl, PME_TO_ACK_MAPPING, 2453 EQNUM); 2454 break; 2455 case PCIE_CORR_MSG: 2456 *msiq_id = CSR_FR((caddr_t)dev_hdl, ERR_COR_MAPPING, EQNUM); 2457 break; 2458 case PCIE_NONFATAL_MSG: 2459 *msiq_id = CSR_FR((caddr_t)dev_hdl, ERR_NONFATAL_MAPPING, 2460 EQNUM); 2461 break; 2462 case PCIE_FATAL_MSG: 2463 *msiq_id = CSR_FR((caddr_t)dev_hdl, ERR_FATAL_MAPPING, EQNUM); 2464 break; 2465 default: 2466 ret = H_EINVAL; 2467 break; 2468 } 2469 2470 return (ret); 2471 } 2472 2473 uint64_t 2474 hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 2475 msiqid_t msiq_id) 2476 { 2477 uint64_t ret = H_EOK; 2478 2479 switch (msg_type) { 2480 case PCIE_PME_MSG: 2481 CSR_FS((caddr_t)dev_hdl, PM_PME_MAPPING, EQNUM, msiq_id); 2482 break; 2483 case PCIE_PME_ACK_MSG: 2484 CSR_FS((caddr_t)dev_hdl, PME_TO_ACK_MAPPING, EQNUM, msiq_id); 2485 break; 2486 case PCIE_CORR_MSG: 2487 CSR_FS((caddr_t)dev_hdl, ERR_COR_MAPPING, EQNUM, msiq_id); 2488 break; 2489 case PCIE_NONFATAL_MSG: 2490 CSR_FS((caddr_t)dev_hdl, ERR_NONFATAL_MAPPING, EQNUM, msiq_id); 2491 break; 2492 case PCIE_FATAL_MSG: 2493 CSR_FS((caddr_t)dev_hdl, ERR_FATAL_MAPPING, EQNUM, msiq_id); 2494 break; 2495 default: 2496 ret = H_EINVAL; 2497 break; 2498 } 2499 2500 return (ret); 2501 } 2502 2503 uint64_t 2504 hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 2505 pcie_msg_valid_state_t *msg_valid_state) 2506 { 2507 uint64_t ret = H_EOK; 2508 2509 switch (msg_type) { 2510 case PCIE_PME_MSG: 2511 *msg_valid_state = CSR_BR((caddr_t)dev_hdl, PM_PME_MAPPING, V); 2512 break; 2513 case PCIE_PME_ACK_MSG: 2514 *msg_valid_state = CSR_BR((caddr_t)dev_hdl, 2515 PME_TO_ACK_MAPPING, V); 2516 break; 2517 case PCIE_CORR_MSG: 2518 *msg_valid_state = CSR_BR((caddr_t)dev_hdl, ERR_COR_MAPPING, V); 2519 break; 2520 case PCIE_NONFATAL_MSG: 2521 *msg_valid_state = CSR_BR((caddr_t)dev_hdl, 2522 ERR_NONFATAL_MAPPING, V); 2523 break; 2524 case PCIE_FATAL_MSG: 2525 *msg_valid_state = CSR_BR((caddr_t)dev_hdl, ERR_FATAL_MAPPING, 2526 V); 2527 break; 2528 default: 2529 ret = H_EINVAL; 2530 break; 2531 } 2532 2533 return (ret); 2534 } 2535 2536 uint64_t 2537 hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 2538 pcie_msg_valid_state_t msg_valid_state) 2539 { 2540 uint64_t ret = H_EOK; 2541 2542 switch (msg_valid_state) { 2543 case PCIE_MSG_VALID: 2544 switch (msg_type) { 2545 case PCIE_PME_MSG: 2546 CSR_BS((caddr_t)dev_hdl, PM_PME_MAPPING, V); 2547 break; 2548 case PCIE_PME_ACK_MSG: 2549 CSR_BS((caddr_t)dev_hdl, PME_TO_ACK_MAPPING, V); 2550 break; 2551 case PCIE_CORR_MSG: 2552 CSR_BS((caddr_t)dev_hdl, ERR_COR_MAPPING, V); 2553 break; 2554 case PCIE_NONFATAL_MSG: 2555 CSR_BS((caddr_t)dev_hdl, ERR_NONFATAL_MAPPING, V); 2556 break; 2557 case PCIE_FATAL_MSG: 2558 CSR_BS((caddr_t)dev_hdl, ERR_FATAL_MAPPING, V); 2559 break; 2560 default: 2561 ret = H_EINVAL; 2562 break; 2563 } 2564 2565 break; 2566 case PCIE_MSG_INVALID: 2567 switch (msg_type) { 2568 case PCIE_PME_MSG: 2569 CSR_BC((caddr_t)dev_hdl, PM_PME_MAPPING, V); 2570 break; 2571 case PCIE_PME_ACK_MSG: 2572 CSR_BC((caddr_t)dev_hdl, PME_TO_ACK_MAPPING, V); 2573 break; 2574 case PCIE_CORR_MSG: 2575 CSR_BC((caddr_t)dev_hdl, ERR_COR_MAPPING, V); 2576 break; 2577 case PCIE_NONFATAL_MSG: 2578 CSR_BC((caddr_t)dev_hdl, ERR_NONFATAL_MAPPING, V); 2579 break; 2580 case PCIE_FATAL_MSG: 2581 CSR_BC((caddr_t)dev_hdl, ERR_FATAL_MAPPING, V); 2582 break; 2583 default: 2584 ret = H_EINVAL; 2585 break; 2586 } 2587 break; 2588 default: 2589 ret = H_EINVAL; 2590 } 2591 2592 return (ret); 2593 } 2594 2595 /* 2596 * Suspend/Resume Functions: 2597 * (pec, mmu, ib) 2598 * cb 2599 * Registers saved have all been touched in the XXX_init functions. 2600 */ 2601 uint64_t 2602 hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p) 2603 { 2604 uint64_t *config_state; 2605 int total_size; 2606 int i; 2607 2608 if (msiq_suspend(dev_hdl, pxu_p) != H_EOK) 2609 return (H_EIO); 2610 2611 total_size = PEC_SIZE + MMU_SIZE + IB_SIZE + IB_MAP_SIZE; 2612 config_state = kmem_zalloc(total_size, KM_NOSLEEP); 2613 2614 if (config_state == NULL) { 2615 return (H_EIO); 2616 } 2617 2618 /* 2619 * Soft state for suspend/resume from pxu_t 2620 * uint64_t *pec_config_state; 2621 * uint64_t *mmu_config_state; 2622 * uint64_t *ib_intr_map; 2623 * uint64_t *ib_config_state; 2624 * uint64_t *xcb_config_state; 2625 */ 2626 2627 /* Save the PEC configuration states */ 2628 pxu_p->pec_config_state = config_state; 2629 for (i = 0; i < PEC_KEYS; i++) { 2630 if ((pec_config_state_regs[i].chip == PX_CHIP_TYPE(pxu_p)) || 2631 (pec_config_state_regs[i].chip == PX_CHIP_UNIDENTIFIED)) { 2632 pxu_p->pec_config_state[i] = 2633 CSR_XR((caddr_t)dev_hdl, 2634 pec_config_state_regs[i].reg); 2635 } 2636 } 2637 2638 /* Save the MMU configuration states */ 2639 pxu_p->mmu_config_state = pxu_p->pec_config_state + PEC_KEYS; 2640 for (i = 0; i < MMU_KEYS; i++) { 2641 pxu_p->mmu_config_state[i] = 2642 CSR_XR((caddr_t)dev_hdl, mmu_config_state_regs[i]); 2643 } 2644 2645 /* Save the interrupt mapping registers */ 2646 pxu_p->ib_intr_map = pxu_p->mmu_config_state + MMU_KEYS; 2647 for (i = 0; i < INTERRUPT_MAPPING_ENTRIES; i++) { 2648 pxu_p->ib_intr_map[i] = 2649 CSRA_XR((caddr_t)dev_hdl, INTERRUPT_MAPPING, i); 2650 } 2651 2652 /* Save the IB configuration states */ 2653 pxu_p->ib_config_state = pxu_p->ib_intr_map + INTERRUPT_MAPPING_ENTRIES; 2654 for (i = 0; i < IB_KEYS; i++) { 2655 pxu_p->ib_config_state[i] = 2656 CSR_XR((caddr_t)dev_hdl, ib_config_state_regs[i]); 2657 } 2658 2659 return (H_EOK); 2660 } 2661 2662 void 2663 hvio_resume(devhandle_t dev_hdl, devino_t devino, pxu_t *pxu_p) 2664 { 2665 int total_size; 2666 sysino_t sysino; 2667 int i; 2668 uint64_t ret; 2669 2670 /* Make sure that suspend actually did occur */ 2671 if (!pxu_p->pec_config_state) { 2672 return; 2673 } 2674 2675 /* Restore IB configuration states */ 2676 for (i = 0; i < IB_KEYS; i++) { 2677 CSR_XS((caddr_t)dev_hdl, ib_config_state_regs[i], 2678 pxu_p->ib_config_state[i]); 2679 } 2680 2681 /* 2682 * Restore the interrupt mapping registers 2683 * And make sure the intrs are idle. 2684 */ 2685 for (i = 0; i < INTERRUPT_MAPPING_ENTRIES; i++) { 2686 CSRA_FS((caddr_t)dev_hdl, INTERRUPT_CLEAR, i, 2687 ENTRIES_INT_STATE, INTERRUPT_IDLE_STATE); 2688 CSRA_XS((caddr_t)dev_hdl, INTERRUPT_MAPPING, i, 2689 pxu_p->ib_intr_map[i]); 2690 } 2691 2692 /* Restore MMU configuration states */ 2693 /* Clear the cache. */ 2694 CSR_XS((caddr_t)dev_hdl, MMU_TTE_CACHE_INVALIDATE, -1ull); 2695 2696 for (i = 0; i < MMU_KEYS; i++) { 2697 CSR_XS((caddr_t)dev_hdl, mmu_config_state_regs[i], 2698 pxu_p->mmu_config_state[i]); 2699 } 2700 2701 /* Restore PEC configuration states */ 2702 /* Make sure all reset bits are low until error is detected */ 2703 CSR_XS((caddr_t)dev_hdl, LPU_RESET, 0ull); 2704 2705 for (i = 0; i < PEC_KEYS; i++) { 2706 if ((pec_config_state_regs[i].chip == PX_CHIP_TYPE(pxu_p)) || 2707 (pec_config_state_regs[i].chip == PX_CHIP_UNIDENTIFIED)) { 2708 CSR_XS((caddr_t)dev_hdl, pec_config_state_regs[i].reg, 2709 pxu_p->pec_config_state[i]); 2710 } 2711 } 2712 2713 /* Enable PCI-E interrupt */ 2714 if ((ret = hvio_intr_devino_to_sysino(dev_hdl, pxu_p, devino, 2715 &sysino)) != H_EOK) { 2716 cmn_err(CE_WARN, 2717 "hvio_resume: hvio_intr_devino_to_sysino failed, " 2718 "ret 0x%lx", ret); 2719 } 2720 2721 if ((ret = hvio_intr_setstate(dev_hdl, sysino, INTR_IDLE_STATE)) 2722 != H_EOK) { 2723 cmn_err(CE_WARN, 2724 "hvio_resume: hvio_intr_setstate failed, " 2725 "ret 0x%lx", ret); 2726 } 2727 2728 total_size = PEC_SIZE + MMU_SIZE + IB_SIZE + IB_MAP_SIZE; 2729 kmem_free(pxu_p->pec_config_state, total_size); 2730 2731 pxu_p->pec_config_state = NULL; 2732 pxu_p->mmu_config_state = NULL; 2733 pxu_p->ib_config_state = NULL; 2734 pxu_p->ib_intr_map = NULL; 2735 2736 msiq_resume(dev_hdl, pxu_p); 2737 } 2738 2739 uint64_t 2740 hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p) 2741 { 2742 uint64_t *config_state, *cb_regs; 2743 int i, cb_size, cb_keys; 2744 2745 switch (PX_CHIP_TYPE(pxu_p)) { 2746 case PX_CHIP_OBERON: 2747 cb_size = UBC_SIZE; 2748 cb_keys = UBC_KEYS; 2749 cb_regs = ubc_config_state_regs; 2750 break; 2751 case PX_CHIP_FIRE: 2752 cb_size = JBC_SIZE; 2753 cb_keys = JBC_KEYS; 2754 cb_regs = jbc_config_state_regs; 2755 break; 2756 default: 2757 DBG(DBG_CB, NULL, "hvio_cb_suspend - unknown chip type: 0x%x\n", 2758 PX_CHIP_TYPE(pxu_p)); 2759 break; 2760 } 2761 2762 config_state = kmem_zalloc(cb_size, KM_NOSLEEP); 2763 2764 if (config_state == NULL) { 2765 return (H_EIO); 2766 } 2767 2768 /* Save the configuration states */ 2769 pxu_p->xcb_config_state = config_state; 2770 for (i = 0; i < cb_keys; i++) { 2771 pxu_p->xcb_config_state[i] = 2772 CSR_XR((caddr_t)dev_hdl, cb_regs[i]); 2773 } 2774 2775 return (H_EOK); 2776 } 2777 2778 void 2779 hvio_cb_resume(devhandle_t pci_dev_hdl, devhandle_t xbus_dev_hdl, 2780 devino_t devino, pxu_t *pxu_p) 2781 { 2782 sysino_t sysino; 2783 uint64_t *cb_regs; 2784 int i, cb_size, cb_keys; 2785 uint64_t ret; 2786 2787 switch (PX_CHIP_TYPE(pxu_p)) { 2788 case PX_CHIP_OBERON: 2789 cb_size = UBC_SIZE; 2790 cb_keys = UBC_KEYS; 2791 cb_regs = ubc_config_state_regs; 2792 /* 2793 * No reason to have any reset bits high until an error is 2794 * detected on the link. 2795 */ 2796 CSR_XS((caddr_t)xbus_dev_hdl, UBC_ERROR_STATUS_CLEAR, -1ull); 2797 break; 2798 case PX_CHIP_FIRE: 2799 cb_size = JBC_SIZE; 2800 cb_keys = JBC_KEYS; 2801 cb_regs = jbc_config_state_regs; 2802 /* 2803 * No reason to have any reset bits high until an error is 2804 * detected on the link. 2805 */ 2806 CSR_XS((caddr_t)xbus_dev_hdl, JBC_ERROR_STATUS_CLEAR, -1ull); 2807 break; 2808 default: 2809 DBG(DBG_CB, NULL, "hvio_cb_resume - unknown chip type: 0x%x\n", 2810 PX_CHIP_TYPE(pxu_p)); 2811 break; 2812 } 2813 2814 ASSERT(pxu_p->xcb_config_state); 2815 2816 /* Restore the configuration states */ 2817 for (i = 0; i < cb_keys; i++) { 2818 CSR_XS((caddr_t)xbus_dev_hdl, cb_regs[i], 2819 pxu_p->xcb_config_state[i]); 2820 } 2821 2822 /* Enable XBC interrupt */ 2823 if ((ret = hvio_intr_devino_to_sysino(pci_dev_hdl, pxu_p, devino, 2824 &sysino)) != H_EOK) { 2825 cmn_err(CE_WARN, 2826 "hvio_cb_resume: hvio_intr_devino_to_sysino failed, " 2827 "ret 0x%lx", ret); 2828 } 2829 2830 if ((ret = hvio_intr_setstate(pci_dev_hdl, sysino, INTR_IDLE_STATE)) 2831 != H_EOK) { 2832 cmn_err(CE_WARN, 2833 "hvio_cb_resume: hvio_intr_setstate failed, " 2834 "ret 0x%lx", ret); 2835 } 2836 2837 kmem_free(pxu_p->xcb_config_state, cb_size); 2838 2839 pxu_p->xcb_config_state = NULL; 2840 } 2841 2842 static uint64_t 2843 msiq_suspend(devhandle_t dev_hdl, pxu_t *pxu_p) 2844 { 2845 size_t bufsz; 2846 volatile uint64_t *cur_p; 2847 int i; 2848 2849 bufsz = MSIQ_STATE_SIZE + MSIQ_MAPPING_SIZE + MSIQ_OTHER_SIZE; 2850 if ((pxu_p->msiq_config_state = kmem_zalloc(bufsz, KM_NOSLEEP)) == 2851 NULL) 2852 return (H_EIO); 2853 2854 cur_p = pxu_p->msiq_config_state; 2855 2856 /* Save each EQ state */ 2857 for (i = 0; i < EVENT_QUEUE_STATE_ENTRIES; i++, cur_p++) 2858 *cur_p = CSRA_XR((caddr_t)dev_hdl, EVENT_QUEUE_STATE, i); 2859 2860 /* Save MSI mapping registers */ 2861 for (i = 0; i < MSI_MAPPING_ENTRIES; i++, cur_p++) 2862 *cur_p = CSRA_XR((caddr_t)dev_hdl, MSI_MAPPING, i); 2863 2864 /* Save all other MSIQ registers */ 2865 for (i = 0; i < MSIQ_OTHER_KEYS; i++, cur_p++) 2866 *cur_p = CSR_XR((caddr_t)dev_hdl, msiq_config_other_regs[i]); 2867 return (H_EOK); 2868 } 2869 2870 static void 2871 msiq_resume(devhandle_t dev_hdl, pxu_t *pxu_p) 2872 { 2873 size_t bufsz; 2874 uint64_t *cur_p, state; 2875 int i; 2876 uint64_t ret; 2877 2878 bufsz = MSIQ_STATE_SIZE + MSIQ_MAPPING_SIZE + MSIQ_OTHER_SIZE; 2879 cur_p = pxu_p->msiq_config_state; 2880 /* 2881 * Initialize EQ base address register and 2882 * Interrupt Mondo Data 0 register. 2883 */ 2884 if ((ret = hvio_msiq_init(dev_hdl, pxu_p)) != H_EOK) { 2885 cmn_err(CE_WARN, 2886 "msiq_resume: hvio_msiq_init failed, " 2887 "ret 0x%lx", ret); 2888 } 2889 2890 /* Restore EQ states */ 2891 for (i = 0; i < EVENT_QUEUE_STATE_ENTRIES; i++, cur_p++) { 2892 state = (*cur_p) & EVENT_QUEUE_STATE_ENTRIES_STATE_MASK; 2893 if ((state == EQ_ACTIVE_STATE) || (state == EQ_ERROR_STATE)) 2894 CSRA_BS((caddr_t)dev_hdl, EVENT_QUEUE_CONTROL_SET, 2895 i, ENTRIES_EN); 2896 } 2897 2898 /* Restore MSI mapping */ 2899 for (i = 0; i < MSI_MAPPING_ENTRIES; i++, cur_p++) 2900 CSRA_XS((caddr_t)dev_hdl, MSI_MAPPING, i, *cur_p); 2901 2902 /* 2903 * Restore all other registers. MSI 32 bit address and 2904 * MSI 64 bit address are restored as part of this. 2905 */ 2906 for (i = 0; i < MSIQ_OTHER_KEYS; i++, cur_p++) 2907 CSR_XS((caddr_t)dev_hdl, msiq_config_other_regs[i], *cur_p); 2908 2909 kmem_free(pxu_p->msiq_config_state, bufsz); 2910 pxu_p->msiq_config_state = NULL; 2911 } 2912 2913 /* 2914 * sends PME_Turn_Off message to put the link in L2/L3 ready state. 2915 * called by px_goto_l23ready. 2916 * returns DDI_SUCCESS or DDI_FAILURE 2917 */ 2918 int 2919 px_send_pme_turnoff(caddr_t csr_base) 2920 { 2921 volatile uint64_t reg; 2922 2923 reg = CSR_XR(csr_base, TLU_PME_TURN_OFF_GENERATE); 2924 /* If already pending, return failure */ 2925 if (reg & (1ull << TLU_PME_TURN_OFF_GENERATE_PTO)) { 2926 DBG(DBG_PWR, NULL, "send_pme_turnoff: pending PTO bit " 2927 "tlu_pme_turn_off_generate = %x\n", reg); 2928 return (DDI_FAILURE); 2929 } 2930 2931 /* write to PME_Turn_off reg to boradcast */ 2932 reg |= (1ull << TLU_PME_TURN_OFF_GENERATE_PTO); 2933 CSR_XS(csr_base, TLU_PME_TURN_OFF_GENERATE, reg); 2934 2935 return (DDI_SUCCESS); 2936 } 2937 2938 /* 2939 * Checks for link being in L1idle state. 2940 * Returns 2941 * DDI_SUCCESS - if the link is in L1idle 2942 * DDI_FAILURE - if the link is not in L1idle 2943 */ 2944 int 2945 px_link_wait4l1idle(caddr_t csr_base) 2946 { 2947 uint8_t ltssm_state; 2948 int ntries = px_max_l1_tries; 2949 2950 while (ntries > 0) { 2951 ltssm_state = CSR_FR(csr_base, LPU_LTSSM_STATUS1, LTSSM_STATE); 2952 if (ltssm_state == LPU_LTSSM_L1_IDLE || (--ntries <= 0)) 2953 break; 2954 delay(1); 2955 } 2956 DBG(DBG_PWR, NULL, "check_for_l1idle: ltssm_state %x\n", ltssm_state); 2957 return ((ltssm_state == LPU_LTSSM_L1_IDLE) ? DDI_SUCCESS : DDI_FAILURE); 2958 } 2959 2960 /* 2961 * Tranisition the link to L0, after it is down. 2962 */ 2963 int 2964 px_link_retrain(caddr_t csr_base) 2965 { 2966 volatile uint64_t reg; 2967 2968 reg = CSR_XR(csr_base, TLU_CONTROL); 2969 if (!(reg & (1ull << TLU_REMAIN_DETECT_QUIET))) { 2970 DBG(DBG_PWR, NULL, "retrain_link: detect.quiet bit not set\n"); 2971 return (DDI_FAILURE); 2972 } 2973 2974 /* Clear link down bit in TLU Other Event Clear Status Register. */ 2975 CSR_BS(csr_base, TLU_OTHER_EVENT_STATUS_CLEAR, LDN_P); 2976 2977 /* Clear Drain bit in TLU Status Register */ 2978 CSR_BS(csr_base, TLU_STATUS, DRAIN); 2979 2980 /* Clear Remain in Detect.Quiet bit in TLU Control Register */ 2981 reg = CSR_XR(csr_base, TLU_CONTROL); 2982 reg &= ~(1ull << TLU_REMAIN_DETECT_QUIET); 2983 CSR_XS(csr_base, TLU_CONTROL, reg); 2984 2985 return (DDI_SUCCESS); 2986 } 2987 2988 void 2989 px_enable_detect_quiet(caddr_t csr_base) 2990 { 2991 volatile uint64_t tlu_ctrl; 2992 2993 tlu_ctrl = CSR_XR(csr_base, TLU_CONTROL); 2994 tlu_ctrl |= (1ull << TLU_REMAIN_DETECT_QUIET); 2995 CSR_XS(csr_base, TLU_CONTROL, tlu_ctrl); 2996 } 2997 2998 static uint_t 2999 oberon_hp_pwron(caddr_t csr_base) 3000 { 3001 volatile uint64_t reg; 3002 boolean_t link_retry, link_up; 3003 int loop, i; 3004 3005 DBG(DBG_HP, NULL, "oberon_hp_pwron the slot\n"); 3006 3007 /* Check Leaf Reset status */ 3008 reg = CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE); 3009 if (!(reg & (1ull << ILU_ERROR_LOG_ENABLE_SPARE3))) { 3010 DBG(DBG_HP, NULL, "oberon_hp_pwron fails: leaf not reset\n"); 3011 goto fail; 3012 } 3013 3014 /* Check HP Capable */ 3015 if (!CSR_BR(csr_base, TLU_SLOT_CAPABILITIES, HP)) { 3016 DBG(DBG_HP, NULL, "oberon_hp_pwron fails: leaf not " 3017 "hotplugable\n"); 3018 goto fail; 3019 } 3020 3021 /* Check Slot status */ 3022 reg = CSR_XR(csr_base, TLU_SLOT_STATUS); 3023 if (!(reg & (1ull << TLU_SLOT_STATUS_PSD)) || 3024 (reg & (1ull << TLU_SLOT_STATUS_MRLS))) { 3025 DBG(DBG_HP, NULL, "oberon_hp_pwron fails: slot status %lx\n", 3026 reg); 3027 goto fail; 3028 } 3029 3030 /* Blink power LED, this is done from pciehpc already */ 3031 3032 /* Turn on slot power */ 3033 CSR_BS(csr_base, HOTPLUG_CONTROL, PWREN); 3034 3035 /* power fault detection */ 3036 delay(drv_usectohz(25000)); 3037 CSR_BS(csr_base, TLU_SLOT_STATUS, PWFD); 3038 CSR_BC(csr_base, HOTPLUG_CONTROL, PWREN); 3039 3040 /* wait to check power state */ 3041 delay(drv_usectohz(25000)); 3042 3043 if (!CSR_BR(csr_base, TLU_SLOT_STATUS, PWFD)) { 3044 DBG(DBG_HP, NULL, "oberon_hp_pwron fails: power fault\n"); 3045 goto fail1; 3046 } 3047 3048 /* power is good */ 3049 CSR_BS(csr_base, HOTPLUG_CONTROL, PWREN); 3050 3051 delay(drv_usectohz(25000)); 3052 CSR_BS(csr_base, TLU_SLOT_STATUS, PWFD); 3053 CSR_BS(csr_base, TLU_SLOT_CONTROL, PWFDEN); 3054 3055 /* Turn on slot clock */ 3056 CSR_BS(csr_base, HOTPLUG_CONTROL, CLKEN); 3057 3058 link_up = B_FALSE; 3059 link_retry = B_FALSE; 3060 3061 for (loop = 0; (loop < link_retry_count) && (link_up == B_FALSE); 3062 loop++) { 3063 if (link_retry == B_TRUE) { 3064 DBG(DBG_HP, NULL, "oberon_hp_pwron : retry link loop " 3065 "%d\n", loop); 3066 CSR_BS(csr_base, TLU_CONTROL, DRN_TR_DIS); 3067 CSR_XS(csr_base, FLP_PORT_CONTROL, 0x1); 3068 delay(drv_usectohz(10000)); 3069 CSR_BC(csr_base, TLU_CONTROL, DRN_TR_DIS); 3070 CSR_BS(csr_base, TLU_DIAGNOSTIC, IFC_DIS); 3071 CSR_BC(csr_base, HOTPLUG_CONTROL, N_PERST); 3072 delay(drv_usectohz(50000)); 3073 } 3074 3075 /* Release PCI-E Reset */ 3076 delay(drv_usectohz(wait_perst)); 3077 CSR_BS(csr_base, HOTPLUG_CONTROL, N_PERST); 3078 3079 /* 3080 * Open events' mask 3081 * This should be done from pciehpc already 3082 */ 3083 3084 /* Enable PCIE port */ 3085 delay(drv_usectohz(wait_enable_port)); 3086 CSR_BS(csr_base, TLU_CONTROL, DRN_TR_DIS); 3087 CSR_XS(csr_base, FLP_PORT_CONTROL, 0x20); 3088 3089 /* wait for the link up */ 3090 /* BEGIN CSTYLED */ 3091 for (i = 0; (i < 2) && (link_up == B_FALSE); i++) { 3092 delay(drv_usectohz(link_status_check)); 3093 reg = CSR_XR(csr_base, DLU_LINK_LAYER_STATUS); 3094 3095 if ((((reg >> DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS) & 3096 DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_MASK) == 3097 DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS_FC_INIT_DONE) && 3098 (reg & (1ull << DLU_LINK_LAYER_STATUS_DLUP_STS)) && 3099 ((reg & 3100 DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_MASK) == 3101 DLU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_DL_ACTIVE)) { 3102 DBG(DBG_HP, NULL, "oberon_hp_pwron : " 3103 "link is up\n"); 3104 link_up = B_TRUE; 3105 } else 3106 link_retry = B_TRUE; 3107 3108 } 3109 /* END CSTYLED */ 3110 } 3111 3112 if (link_up == B_FALSE) { 3113 DBG(DBG_HP, NULL, "oberon_hp_pwron fails to enable " 3114 "PCI-E port\n"); 3115 goto fail2; 3116 } 3117 3118 /* link is up */ 3119 CSR_BC(csr_base, TLU_DIAGNOSTIC, IFC_DIS); 3120 CSR_BS(csr_base, FLP_PORT_ACTIVE_STATUS, TRAIN_ERROR); 3121 CSR_BS(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR, TE_P); 3122 CSR_BS(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR, TE_S); 3123 CSR_BC(csr_base, TLU_CONTROL, DRN_TR_DIS); 3124 3125 /* Restore LUP/LDN */ 3126 reg = CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE); 3127 if (px_tlu_oe_log_mask & (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P)) 3128 reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P; 3129 if (px_tlu_oe_log_mask & (1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P)) 3130 reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P; 3131 if (px_tlu_oe_log_mask & (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S)) 3132 reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S; 3133 if (px_tlu_oe_log_mask & (1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S)) 3134 reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S; 3135 CSR_XS(csr_base, TLU_OTHER_EVENT_LOG_ENABLE, reg); 3136 3137 /* 3138 * Initialize Leaf 3139 * SPLS = 00b, SPLV = 11001b, i.e. 25W 3140 */ 3141 reg = CSR_XR(csr_base, TLU_SLOT_CAPABILITIES); 3142 reg &= ~(TLU_SLOT_CAPABILITIES_SPLS_MASK << 3143 TLU_SLOT_CAPABILITIES_SPLS); 3144 reg &= ~(TLU_SLOT_CAPABILITIES_SPLV_MASK << 3145 TLU_SLOT_CAPABILITIES_SPLV); 3146 reg |= (0x19 << TLU_SLOT_CAPABILITIES_SPLV); 3147 CSR_XS(csr_base, TLU_SLOT_CAPABILITIES, reg); 3148 3149 /* Turn on Power LED */ 3150 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL); 3151 reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK; 3152 reg = pcie_slotctl_pwr_indicator_set(reg, 3153 PCIE_SLOTCTL_INDICATOR_STATE_ON); 3154 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg); 3155 3156 /* Notify to SCF */ 3157 if (CSR_BR(csr_base, HOTPLUG_CONTROL, SLOTPON)) 3158 CSR_BC(csr_base, HOTPLUG_CONTROL, SLOTPON); 3159 else 3160 CSR_BS(csr_base, HOTPLUG_CONTROL, SLOTPON); 3161 3162 /* Wait for one second */ 3163 delay(drv_usectohz(1000000)); 3164 3165 return (DDI_SUCCESS); 3166 3167 fail2: 3168 /* Link up is failed */ 3169 CSR_BS(csr_base, FLP_PORT_CONTROL, PORT_DIS); 3170 CSR_BC(csr_base, HOTPLUG_CONTROL, N_PERST); 3171 delay(drv_usectohz(150)); 3172 3173 CSR_BC(csr_base, HOTPLUG_CONTROL, CLKEN); 3174 delay(drv_usectohz(100)); 3175 3176 fail1: 3177 CSR_BC(csr_base, TLU_SLOT_CONTROL, PWFDEN); 3178 3179 CSR_BC(csr_base, HOTPLUG_CONTROL, PWREN); 3180 3181 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL); 3182 reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK; 3183 reg = pcie_slotctl_pwr_indicator_set(reg, 3184 PCIE_SLOTCTL_INDICATOR_STATE_OFF); 3185 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg); 3186 3187 CSR_BC(csr_base, TLU_SLOT_STATUS, PWFD); 3188 3189 fail: 3190 return ((uint_t)DDI_FAILURE); 3191 } 3192 3193 hrtime_t oberon_leaf_reset_timeout = 120ll * NANOSEC; /* 120 seconds */ 3194 3195 static uint_t 3196 oberon_hp_pwroff(caddr_t csr_base) 3197 { 3198 volatile uint64_t reg; 3199 volatile uint64_t reg_tluue, reg_tluce; 3200 hrtime_t start_time, end_time; 3201 3202 DBG(DBG_HP, NULL, "oberon_hp_pwroff the slot\n"); 3203 3204 /* Blink power LED, this is done from pciehpc already */ 3205 3206 /* Clear Slot Event */ 3207 CSR_BS(csr_base, TLU_SLOT_STATUS, PSDC); 3208 CSR_BS(csr_base, TLU_SLOT_STATUS, PWFD); 3209 3210 /* DRN_TR_DIS on */ 3211 CSR_BS(csr_base, TLU_CONTROL, DRN_TR_DIS); 3212 delay(drv_usectohz(10000)); 3213 3214 /* Disable LUP/LDN */ 3215 reg = CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE); 3216 reg &= ~((1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P) | 3217 (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P) | 3218 (1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S) | 3219 (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S)); 3220 CSR_XS(csr_base, TLU_OTHER_EVENT_LOG_ENABLE, reg); 3221 3222 /* Save the TLU registers */ 3223 reg_tluue = CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE); 3224 reg_tluce = CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE); 3225 /* All clear */ 3226 CSR_XS(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE, 0); 3227 CSR_XS(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE, 0); 3228 3229 /* Disable port */ 3230 CSR_BS(csr_base, FLP_PORT_CONTROL, PORT_DIS); 3231 3232 /* PCIE reset */ 3233 delay(drv_usectohz(10000)); 3234 CSR_BC(csr_base, HOTPLUG_CONTROL, N_PERST); 3235 3236 /* PCIE clock stop */ 3237 delay(drv_usectohz(150)); 3238 CSR_BC(csr_base, HOTPLUG_CONTROL, CLKEN); 3239 3240 /* Turn off slot power */ 3241 delay(drv_usectohz(100)); 3242 CSR_BC(csr_base, TLU_SLOT_CONTROL, PWFDEN); 3243 CSR_BC(csr_base, HOTPLUG_CONTROL, PWREN); 3244 delay(drv_usectohz(25000)); 3245 CSR_BS(csr_base, TLU_SLOT_STATUS, PWFD); 3246 3247 /* write 0 to bit 7 of ILU Error Log Enable Register */ 3248 CSR_BC(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3); 3249 3250 /* Set back TLU registers */ 3251 CSR_XS(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE, reg_tluue); 3252 CSR_XS(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE, reg_tluce); 3253 3254 /* Power LED off */ 3255 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL); 3256 reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK; 3257 reg = pcie_slotctl_pwr_indicator_set(reg, 3258 PCIE_SLOTCTL_INDICATOR_STATE_OFF); 3259 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg); 3260 3261 /* Indicator LED blink */ 3262 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL); 3263 reg &= ~PCIE_SLOTCTL_ATTN_INDICATOR_MASK; 3264 reg = pcie_slotctl_attn_indicator_set(reg, 3265 PCIE_SLOTCTL_INDICATOR_STATE_BLINK); 3266 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg); 3267 3268 /* Notify to SCF */ 3269 if (CSR_BR(csr_base, HOTPLUG_CONTROL, SLOTPON)) 3270 CSR_BC(csr_base, HOTPLUG_CONTROL, SLOTPON); 3271 else 3272 CSR_BS(csr_base, HOTPLUG_CONTROL, SLOTPON); 3273 3274 start_time = gethrtime(); 3275 /* Check Leaf Reset status */ 3276 while (!(CSR_BR(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3))) { 3277 if ((end_time = (gethrtime() - start_time)) > 3278 oberon_leaf_reset_timeout) { 3279 cmn_err(CE_WARN, "Oberon leaf reset is not completed, " 3280 "even after waiting %llx ticks", end_time); 3281 3282 break; 3283 } 3284 3285 /* Wait for one second */ 3286 delay(drv_usectohz(1000000)); 3287 } 3288 3289 /* Indicator LED off */ 3290 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL); 3291 reg &= ~PCIE_SLOTCTL_ATTN_INDICATOR_MASK; 3292 reg = pcie_slotctl_attn_indicator_set(reg, 3293 PCIE_SLOTCTL_INDICATOR_STATE_OFF); 3294 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg); 3295 3296 return (DDI_SUCCESS); 3297 } 3298 3299 static uint_t 3300 oberon_hpreg_get(void *cookie, off_t off) 3301 { 3302 caddr_t csr_base = *(caddr_t *)cookie; 3303 volatile uint64_t val = -1ull; 3304 3305 switch (off) { 3306 case PCIE_SLOTCAP: 3307 val = CSR_XR(csr_base, TLU_SLOT_CAPABILITIES); 3308 break; 3309 case PCIE_SLOTCTL: 3310 val = CSR_XR(csr_base, TLU_SLOT_CONTROL); 3311 3312 /* Get the power state */ 3313 val |= (CSR_XR(csr_base, HOTPLUG_CONTROL) & 3314 (1ull << HOTPLUG_CONTROL_PWREN)) ? 3315 0 : PCIE_SLOTCTL_PWR_CONTROL; 3316 break; 3317 case PCIE_SLOTSTS: 3318 val = CSR_XR(csr_base, TLU_SLOT_STATUS); 3319 break; 3320 case PCIE_LINKCAP: 3321 val = CSR_XR(csr_base, TLU_LINK_CAPABILITIES); 3322 break; 3323 case PCIE_LINKSTS: 3324 val = CSR_XR(csr_base, TLU_LINK_STATUS); 3325 break; 3326 default: 3327 DBG(DBG_HP, NULL, "oberon_hpreg_get(): " 3328 "unsupported offset 0x%lx\n", off); 3329 break; 3330 } 3331 3332 return ((uint_t)val); 3333 } 3334 3335 static uint_t 3336 oberon_hpreg_put(void *cookie, off_t off, uint_t val) 3337 { 3338 caddr_t csr_base = *(caddr_t *)cookie; 3339 volatile uint64_t pwr_state_on, pwr_fault; 3340 uint_t pwr_off, ret = DDI_SUCCESS; 3341 3342 DBG(DBG_HP, NULL, "oberon_hpreg_put 0x%lx: cur %x, new %x\n", 3343 off, oberon_hpreg_get(cookie, off), val); 3344 3345 switch (off) { 3346 case PCIE_SLOTCTL: 3347 /* 3348 * Depending on the current state, insertion or removal 3349 * will go through their respective sequences. 3350 */ 3351 pwr_state_on = CSR_BR(csr_base, HOTPLUG_CONTROL, PWREN); 3352 pwr_off = val & PCIE_SLOTCTL_PWR_CONTROL; 3353 3354 if (!pwr_off && !pwr_state_on) 3355 ret = oberon_hp_pwron(csr_base); 3356 else if (pwr_off && pwr_state_on) { 3357 pwr_fault = CSR_XR(csr_base, TLU_SLOT_STATUS) & 3358 (1ull << TLU_SLOT_STATUS_PWFD); 3359 3360 if (pwr_fault) { 3361 DBG(DBG_HP, NULL, "oberon_hpreg_put: power " 3362 "off because of power fault\n"); 3363 CSR_BC(csr_base, HOTPLUG_CONTROL, PWREN); 3364 } 3365 else 3366 ret = oberon_hp_pwroff(csr_base); 3367 } else 3368 CSR_XS(csr_base, TLU_SLOT_CONTROL, val); 3369 break; 3370 case PCIE_SLOTSTS: 3371 CSR_XS(csr_base, TLU_SLOT_STATUS, val); 3372 break; 3373 default: 3374 DBG(DBG_HP, NULL, "oberon_hpreg_put(): " 3375 "unsupported offset 0x%lx\n", off); 3376 ret = (uint_t)DDI_FAILURE; 3377 break; 3378 } 3379 3380 return (ret); 3381 } 3382 3383 int 3384 hvio_hotplug_init(dev_info_t *dip, void *arg) 3385 { 3386 pcie_hp_regops_t *regops = (pcie_hp_regops_t *)arg; 3387 px_t *px_p = DIP_TO_STATE(dip); 3388 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 3389 volatile uint64_t reg; 3390 3391 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 3392 if (!CSR_BR((caddr_t)pxu_p->px_address[PX_REG_CSR], 3393 TLU_SLOT_CAPABILITIES, HP)) { 3394 DBG(DBG_HP, NULL, "%s%d: hotplug capabale not set\n", 3395 ddi_driver_name(dip), ddi_get_instance(dip)); 3396 return (DDI_FAILURE); 3397 } 3398 3399 /* For empty or disconnected slot, disable LUP/LDN */ 3400 if (!CSR_BR((caddr_t)pxu_p->px_address[PX_REG_CSR], 3401 TLU_SLOT_STATUS, PSD) || 3402 !CSR_BR((caddr_t)pxu_p->px_address[PX_REG_CSR], 3403 HOTPLUG_CONTROL, PWREN)) { 3404 3405 reg = CSR_XR((caddr_t)pxu_p->px_address[PX_REG_CSR], 3406 TLU_OTHER_EVENT_LOG_ENABLE); 3407 reg &= ~((1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P) | 3408 (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P) | 3409 (1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S) | 3410 (1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S)); 3411 CSR_XS((caddr_t)pxu_p->px_address[PX_REG_CSR], 3412 TLU_OTHER_EVENT_LOG_ENABLE, reg); 3413 } 3414 3415 regops->get = oberon_hpreg_get; 3416 regops->put = oberon_hpreg_put; 3417 3418 /* cookie is the csr_base */ 3419 regops->cookie = (void *)&pxu_p->px_address[PX_REG_CSR]; 3420 3421 return (DDI_SUCCESS); 3422 } 3423 3424 return (DDI_ENOTSUP); 3425 } 3426 3427 int 3428 hvio_hotplug_uninit(dev_info_t *dip) 3429 { 3430 px_t *px_p = DIP_TO_STATE(dip); 3431 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 3432 3433 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) 3434 return (DDI_SUCCESS); 3435 3436 return (DDI_FAILURE); 3437 } 3438