1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * sun4u Fire Error Handling 30 */ 31 32 #include <sys/types.h> 33 #include <sys/ddi.h> 34 #include <sys/sunddi.h> 35 #include <sys/fm/protocol.h> 36 #include <sys/fm/util.h> 37 #include <sys/pcie.h> 38 #include <sys/pcie_impl.h> 39 #include "px_obj.h" 40 #include <px_regs.h> 41 #include <px_csr.h> 42 #include <sys/membar.h> 43 #include <sys/machcpuvar.h> 44 #include <sys/platform_module.h> 45 #include "pcie_pwr.h" 46 #include "px_lib4u.h" 47 #include "px_err.h" 48 #include "px_err_impl.h" 49 #include "oberon_regs.h" 50 51 uint64_t px_tlu_ue_intr_mask = PX_ERR_EN_ALL; 52 uint64_t px_tlu_ue_log_mask = PX_ERR_EN_ALL; 53 uint64_t px_tlu_ue_count_mask = PX_ERR_EN_ALL; 54 55 uint64_t px_tlu_ce_intr_mask = PX_ERR_MASK_NONE; 56 uint64_t px_tlu_ce_log_mask = PX_ERR_MASK_NONE; 57 uint64_t px_tlu_ce_count_mask = PX_ERR_MASK_NONE; 58 59 /* 60 * Do not enable Link Interrupts 61 */ 62 uint64_t px_tlu_oe_intr_mask = PX_ERR_EN_ALL & ~0x80000000800; 63 uint64_t px_tlu_oe_log_mask = PX_ERR_EN_ALL & ~0x80000000800; 64 uint64_t px_tlu_oe_count_mask = PX_ERR_EN_ALL; 65 66 uint64_t px_mmu_intr_mask = PX_ERR_EN_ALL; 67 uint64_t px_mmu_log_mask = PX_ERR_EN_ALL; 68 uint64_t px_mmu_count_mask = PX_ERR_EN_ALL; 69 70 uint64_t px_imu_intr_mask = PX_ERR_EN_ALL; 71 uint64_t px_imu_log_mask = PX_ERR_EN_ALL; 72 uint64_t px_imu_count_mask = PX_ERR_EN_ALL; 73 74 /* 75 * (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_S) | 76 * (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_P); 77 */ 78 uint64_t px_ilu_intr_mask = (((uint64_t)0x10 << 32) | 0x10); 79 uint64_t px_ilu_log_mask = (((uint64_t)0x10 << 32) | 0x10); 80 uint64_t px_ilu_count_mask = PX_ERR_EN_ALL; 81 82 uint64_t px_ubc_intr_mask = PX_ERR_EN_ALL; 83 uint64_t px_ubc_log_mask = PX_ERR_EN_ALL; 84 uint64_t px_ubc_count_mask = PX_ERR_EN_ALL; 85 86 uint64_t px_jbc_intr_mask = PX_ERR_EN_ALL; 87 uint64_t px_jbc_log_mask = PX_ERR_EN_ALL; 88 uint64_t px_jbc_count_mask = PX_ERR_EN_ALL; 89 90 /* 91 * LPU Intr Registers are reverse encoding from the registers above. 92 * 1 = disable 93 * 0 = enable 94 * 95 * Log and Count are however still the same. 96 */ 97 uint64_t px_lpul_intr_mask = LPU_INTR_DISABLE; 98 uint64_t px_lpul_log_mask = PX_ERR_EN_ALL; 99 uint64_t px_lpul_count_mask = PX_ERR_EN_ALL; 100 101 uint64_t px_lpup_intr_mask = LPU_INTR_DISABLE; 102 uint64_t px_lpup_log_mask = PX_ERR_EN_ALL; 103 uint64_t px_lpup_count_mask = PX_ERR_EN_ALL; 104 105 uint64_t px_lpur_intr_mask = LPU_INTR_DISABLE; 106 uint64_t px_lpur_log_mask = PX_ERR_EN_ALL; 107 uint64_t px_lpur_count_mask = PX_ERR_EN_ALL; 108 109 uint64_t px_lpux_intr_mask = LPU_INTR_DISABLE; 110 uint64_t px_lpux_log_mask = PX_ERR_EN_ALL; 111 uint64_t px_lpux_count_mask = PX_ERR_EN_ALL; 112 113 uint64_t px_lpus_intr_mask = LPU_INTR_DISABLE; 114 uint64_t px_lpus_log_mask = PX_ERR_EN_ALL; 115 uint64_t px_lpus_count_mask = PX_ERR_EN_ALL; 116 117 uint64_t px_lpug_intr_mask = LPU_INTR_DISABLE; 118 uint64_t px_lpug_log_mask = PX_ERR_EN_ALL; 119 uint64_t px_lpug_count_mask = PX_ERR_EN_ALL; 120 121 /* 122 * JBC error bit table 123 */ 124 #define JBC_BIT_DESC(bit, hdl, erpt) \ 125 JBC_INTERRUPT_STATUS_ ## bit ## _P, \ 126 0, \ 127 PX_ERR_BIT_HANDLE(hdl), \ 128 PX_ERPT_SEND(erpt), \ 129 PX_ERR_JBC_CLASS(bit) }, \ 130 { JBC_INTERRUPT_STATUS_ ## bit ## _S, \ 131 0, \ 132 PX_ERR_BIT_HANDLE(hdl), \ 133 PX_ERPT_SEND(erpt), \ 134 PX_ERR_JBC_CLASS(bit) 135 px_err_bit_desc_t px_err_jbc_tbl[] = { 136 /* JBC FATAL */ 137 { JBC_BIT_DESC(MB_PEA, hw_reset, jbc_fatal) }, 138 { JBC_BIT_DESC(CPE, hw_reset, jbc_fatal) }, 139 { JBC_BIT_DESC(APE, hw_reset, jbc_fatal) }, 140 { JBC_BIT_DESC(PIO_CPE, hw_reset, jbc_fatal) }, 141 { JBC_BIT_DESC(JTCEEW, hw_reset, jbc_fatal) }, 142 { JBC_BIT_DESC(JTCEEI, hw_reset, jbc_fatal) }, 143 { JBC_BIT_DESC(JTCEER, hw_reset, jbc_fatal) }, 144 145 /* JBC MERGE */ 146 { JBC_BIT_DESC(MB_PER, jbc_merge, jbc_merge) }, 147 { JBC_BIT_DESC(MB_PEW, jbc_merge, jbc_merge) }, 148 149 /* JBC Jbusint IN */ 150 { JBC_BIT_DESC(UE_ASYN, panic, jbc_in) }, 151 { JBC_BIT_DESC(CE_ASYN, no_error, jbc_in) }, 152 { JBC_BIT_DESC(JTE, panic, jbc_in) }, 153 { JBC_BIT_DESC(JBE, panic, jbc_in) }, 154 { JBC_BIT_DESC(JUE, panic, jbc_in) }, 155 { JBC_BIT_DESC(ICISE, panic, jbc_in) }, 156 { JBC_BIT_DESC(WR_DPE, jbc_jbusint_in, jbc_in) }, 157 { JBC_BIT_DESC(RD_DPE, jbc_jbusint_in, jbc_in) }, 158 { JBC_BIT_DESC(ILL_BMW, panic, jbc_in) }, 159 { JBC_BIT_DESC(ILL_BMR, panic, jbc_in) }, 160 { JBC_BIT_DESC(BJC, panic, jbc_in) }, 161 162 /* JBC Jbusint Out */ 163 { JBC_BIT_DESC(IJP, panic, jbc_out) }, 164 165 /* 166 * JBC Dmcint ODCD 167 * 168 * Error bits which can be set via a bad PCItool access go through 169 * jbc_safe_acc instead. 170 */ 171 { JBC_BIT_DESC(PIO_UNMAP_RD, jbc_safe_acc, jbc_odcd) }, 172 { JBC_BIT_DESC(ILL_ACC_RD, jbc_safe_acc, jbc_odcd) }, 173 { JBC_BIT_DESC(PIO_UNMAP, jbc_safe_acc, jbc_odcd) }, 174 { JBC_BIT_DESC(PIO_DPE, jbc_dmcint_odcd, jbc_odcd) }, 175 { JBC_BIT_DESC(PIO_CPE, hw_reset, jbc_odcd) }, 176 { JBC_BIT_DESC(ILL_ACC, jbc_safe_acc, jbc_odcd) }, 177 178 /* JBC Dmcint IDC */ 179 { JBC_BIT_DESC(UNSOL_RD, no_panic, jbc_idc) }, 180 { JBC_BIT_DESC(UNSOL_INTR, no_panic, jbc_idc) }, 181 182 /* JBC CSR */ 183 { JBC_BIT_DESC(EBUS_TO, panic, jbc_csr) } 184 }; 185 186 #define px_err_jbc_keys \ 187 (sizeof (px_err_jbc_tbl)) / (sizeof (px_err_bit_desc_t)) 188 189 /* 190 * UBC error bit table 191 */ 192 #define UBC_BIT_DESC(bit, hdl, erpt) \ 193 UBC_INTERRUPT_STATUS_ ## bit ## _P, \ 194 0, \ 195 PX_ERR_BIT_HANDLE(hdl), \ 196 PX_ERPT_SEND(erpt), \ 197 PX_ERR_UBC_CLASS(bit) }, \ 198 { UBC_INTERRUPT_STATUS_ ## bit ## _S, \ 199 0, \ 200 PX_ERR_BIT_HANDLE(hdl), \ 201 PX_ERPT_SEND(erpt), \ 202 PX_ERR_UBC_CLASS(bit) 203 px_err_bit_desc_t px_err_ubc_tbl[] = { 204 /* UBC FATAL */ 205 { UBC_BIT_DESC(DMARDUEA, no_panic, ubc_fatal) }, 206 { UBC_BIT_DESC(DMAWTUEA, panic, ubc_fatal) }, 207 { UBC_BIT_DESC(MEMRDAXA, panic, ubc_fatal) }, 208 { UBC_BIT_DESC(MEMWTAXA, panic, ubc_fatal) }, 209 { UBC_BIT_DESC(DMARDUEB, no_panic, ubc_fatal) }, 210 { UBC_BIT_DESC(DMAWTUEB, panic, ubc_fatal) }, 211 { UBC_BIT_DESC(MEMRDAXB, panic, ubc_fatal) }, 212 { UBC_BIT_DESC(MEMWTAXB, panic, ubc_fatal) }, 213 { UBC_BIT_DESC(PIOWTUE, panic, ubc_fatal) }, 214 { UBC_BIT_DESC(PIOWBEUE, panic, ubc_fatal) }, 215 { UBC_BIT_DESC(PIORBEUE, panic, ubc_fatal) } 216 }; 217 218 #define px_err_ubc_keys \ 219 (sizeof (px_err_ubc_tbl)) / (sizeof (px_err_bit_desc_t)) 220 221 222 char *ubc_class_eid_qualifier[] = { 223 "-mem", 224 "-channel", 225 "-cpu", 226 "-path" 227 }; 228 229 230 /* 231 * DMC error bit tables 232 */ 233 #define IMU_BIT_DESC(bit, hdl, erpt) \ 234 IMU_INTERRUPT_STATUS_ ## bit ## _P, \ 235 0, \ 236 PX_ERR_BIT_HANDLE(hdl), \ 237 PX_ERPT_SEND(erpt), \ 238 PX_ERR_DMC_CLASS(bit) }, \ 239 { IMU_INTERRUPT_STATUS_ ## bit ## _S, \ 240 0, \ 241 PX_ERR_BIT_HANDLE(hdl), \ 242 PX_ERPT_SEND(erpt), \ 243 PX_ERR_DMC_CLASS(bit) 244 px_err_bit_desc_t px_err_imu_tbl[] = { 245 /* DMC IMU RDS */ 246 { IMU_BIT_DESC(MSI_MAL_ERR, panic, imu_rds) }, 247 { IMU_BIT_DESC(MSI_PAR_ERR, panic, imu_rds) }, 248 { IMU_BIT_DESC(PMEACK_MES_NOT_EN, panic, imu_rds) }, 249 { IMU_BIT_DESC(PMPME_MES_NOT_EN, panic, imu_rds) }, 250 { IMU_BIT_DESC(FATAL_MES_NOT_EN, panic, imu_rds) }, 251 { IMU_BIT_DESC(NONFATAL_MES_NOT_EN, panic, imu_rds) }, 252 { IMU_BIT_DESC(COR_MES_NOT_EN, panic, imu_rds) }, 253 { IMU_BIT_DESC(MSI_NOT_EN, panic, imu_rds) }, 254 255 /* DMC IMU SCS */ 256 { IMU_BIT_DESC(EQ_NOT_EN, panic, imu_scs) }, 257 258 /* DMC IMU */ 259 { IMU_BIT_DESC(EQ_OVER, imu_eq_ovfl, imu) } 260 }; 261 262 #define px_err_imu_keys (sizeof (px_err_imu_tbl)) / (sizeof (px_err_bit_desc_t)) 263 264 /* mmu errors */ 265 #define MMU_BIT_DESC(bit, hdl, erpt) \ 266 MMU_INTERRUPT_STATUS_ ## bit ## _P, \ 267 0, \ 268 PX_ERR_BIT_HANDLE(hdl), \ 269 PX_ERPT_SEND(erpt), \ 270 PX_ERR_DMC_CLASS(bit) }, \ 271 { MMU_INTERRUPT_STATUS_ ## bit ## _S, \ 272 0, \ 273 PX_ERR_BIT_HANDLE(hdl), \ 274 PX_ERPT_SEND(erpt), \ 275 PX_ERR_DMC_CLASS(bit) 276 px_err_bit_desc_t px_err_mmu_tbl[] = { 277 /* DMC MMU TFAR/TFSR */ 278 { MMU_BIT_DESC(BYP_ERR, mmu_rbne, mmu_tfar_tfsr) }, 279 { MMU_BIT_DESC(BYP_OOR, mmu_tfa, mmu_tfar_tfsr) }, 280 { MMU_BIT_DESC(TRN_ERR, panic, mmu_tfar_tfsr) }, 281 { MMU_BIT_DESC(TRN_OOR, mmu_tfa, mmu_tfar_tfsr) }, 282 { MMU_BIT_DESC(TTE_INV, mmu_tfa, mmu_tfar_tfsr) }, 283 { MMU_BIT_DESC(TTE_PRT, mmu_tfa, mmu_tfar_tfsr) }, 284 { MMU_BIT_DESC(TTC_DPE, mmu_parity, mmu_tfar_tfsr) }, 285 { MMU_BIT_DESC(TBW_DME, panic, mmu_tfar_tfsr) }, 286 { MMU_BIT_DESC(TBW_UDE, panic, mmu_tfar_tfsr) }, 287 { MMU_BIT_DESC(TBW_ERR, panic, mmu_tfar_tfsr) }, 288 { MMU_BIT_DESC(TBW_DPE, mmu_parity, mmu_tfar_tfsr) }, 289 290 /* DMC MMU */ 291 { MMU_BIT_DESC(TTC_CAE, panic, mmu) } 292 }; 293 #define px_err_mmu_keys (sizeof (px_err_mmu_tbl)) / (sizeof (px_err_bit_desc_t)) 294 295 296 /* 297 * PEC error bit tables 298 */ 299 #define ILU_BIT_DESC(bit, hdl, erpt) \ 300 ILU_INTERRUPT_STATUS_ ## bit ## _P, \ 301 0, \ 302 PX_ERR_BIT_HANDLE(hdl), \ 303 PX_ERPT_SEND(erpt), \ 304 PX_ERR_PEC_CLASS(bit) }, \ 305 { ILU_INTERRUPT_STATUS_ ## bit ## _S, \ 306 0, \ 307 PX_ERR_BIT_HANDLE(hdl), \ 308 PX_ERPT_SEND(erpt), \ 309 PX_ERR_PEC_CLASS(bit) 310 px_err_bit_desc_t px_err_ilu_tbl[] = { 311 /* PEC ILU none */ 312 { ILU_BIT_DESC(IHB_PE, panic, pec_ilu) } 313 }; 314 #define px_err_ilu_keys \ 315 (sizeof (px_err_ilu_tbl)) / (sizeof (px_err_bit_desc_t)) 316 317 /* 318 * PEC UE errors implementation is incomplete pending PCIE generic 319 * fabric rules. Must handle both PRIMARY and SECONDARY errors. 320 */ 321 /* pec ue errors */ 322 #define TLU_UC_BIT_DESC(bit, hdl, erpt) \ 323 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 324 0, \ 325 PX_ERR_BIT_HANDLE(hdl), \ 326 PX_ERPT_SEND(erpt), \ 327 PX_ERR_PEC_CLASS(bit) }, \ 328 { TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 329 0, \ 330 PX_ERR_BIT_HANDLE(hdl), \ 331 PX_ERPT_SEND(erpt), \ 332 PX_ERR_PEC_CLASS(bit) 333 #define TLU_UC_OB_BIT_DESC(bit, hdl, erpt) \ 334 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 335 0, \ 336 PX_ERR_BIT_HANDLE(hdl), \ 337 PX_ERPT_SEND(erpt), \ 338 PX_ERR_PEC_OB_CLASS(bit) }, \ 339 { TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 340 0, \ 341 PX_ERR_BIT_HANDLE(hdl), \ 342 PX_ERPT_SEND(erpt), \ 343 PX_ERR_PEC_CLASS(bit) 344 px_err_bit_desc_t px_err_tlu_ue_tbl[] = { 345 /* PCI-E Receive Uncorrectable Errors */ 346 { TLU_UC_BIT_DESC(UR, pciex_ue, pciex_rx_ue) }, 347 { TLU_UC_BIT_DESC(UC, pciex_ue, pciex_rx_ue) }, 348 349 /* PCI-E Transmit Uncorrectable Errors */ 350 { TLU_UC_OB_BIT_DESC(ECRC, pciex_ue, pciex_rx_ue) }, 351 { TLU_UC_BIT_DESC(CTO, pciex_ue, pciex_tx_ue) }, 352 { TLU_UC_BIT_DESC(ROF, pciex_ue, pciex_tx_ue) }, 353 354 /* PCI-E Rx/Tx Uncorrectable Errors */ 355 { TLU_UC_BIT_DESC(MFP, pciex_ue, pciex_rx_tx_ue) }, 356 { TLU_UC_BIT_DESC(PP, pciex_ue, pciex_rx_tx_ue) }, 357 358 /* Other PCI-E Uncorrectable Errors */ 359 { TLU_UC_BIT_DESC(FCP, pciex_ue, pciex_ue) }, 360 { TLU_UC_BIT_DESC(DLP, pciex_ue, pciex_ue) }, 361 { TLU_UC_BIT_DESC(TE, pciex_ue, pciex_ue) }, 362 363 /* Not used */ 364 { TLU_UC_BIT_DESC(CA, pciex_ue, do_not) } 365 }; 366 #define px_err_tlu_ue_keys \ 367 (sizeof (px_err_tlu_ue_tbl)) / (sizeof (px_err_bit_desc_t)) 368 369 370 /* 371 * PEC CE errors implementation is incomplete pending PCIE generic 372 * fabric rules. 373 */ 374 /* pec ce errors */ 375 #define TLU_CE_BIT_DESC(bit, hdl, erpt) \ 376 TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 377 0, \ 378 PX_ERR_BIT_HANDLE(hdl), \ 379 PX_ERPT_SEND(erpt), \ 380 PX_ERR_PEC_CLASS(bit) }, \ 381 { TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 382 0, \ 383 PX_ERR_BIT_HANDLE(hdl), \ 384 PX_ERPT_SEND(erpt), \ 385 PX_ERR_PEC_CLASS(bit) 386 px_err_bit_desc_t px_err_tlu_ce_tbl[] = { 387 /* PCI-E Correctable Errors */ 388 { TLU_CE_BIT_DESC(RTO, pciex_ce, pciex_ce) }, 389 { TLU_CE_BIT_DESC(RNR, pciex_ce, pciex_ce) }, 390 { TLU_CE_BIT_DESC(BDP, pciex_ce, pciex_ce) }, 391 { TLU_CE_BIT_DESC(BTP, pciex_ce, pciex_ce) }, 392 { TLU_CE_BIT_DESC(RE, pciex_ce, pciex_ce) } 393 }; 394 #define px_err_tlu_ce_keys \ 395 (sizeof (px_err_tlu_ce_tbl)) / (sizeof (px_err_bit_desc_t)) 396 397 398 /* pec oe errors */ 399 #define TLU_OE_BIT_DESC(bit, hdl, erpt) \ 400 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 401 0, \ 402 PX_ERR_BIT_HANDLE(hdl), \ 403 PX_ERPT_SEND(erpt), \ 404 PX_ERR_PEC_CLASS(bit) }, \ 405 { TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _S, \ 406 0, \ 407 PX_ERR_BIT_HANDLE(hdl), \ 408 PX_ERPT_SEND(erpt), \ 409 PX_ERR_PEC_CLASS(bit) 410 #define TLU_OE_OB_BIT_DESC(bit, hdl, erpt) \ 411 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 412 0, \ 413 PX_ERR_BIT_HANDLE(hdl), \ 414 PX_ERPT_SEND(erpt), \ 415 PX_ERR_PEC_OB_CLASS(bit) }, \ 416 { TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _S, \ 417 0, \ 418 PX_ERR_BIT_HANDLE(hdl), \ 419 PX_ERPT_SEND(erpt), \ 420 PX_ERR_PEC_OB_CLASS(bit) 421 px_err_bit_desc_t px_err_tlu_oe_tbl[] = { 422 /* TLU Other Event Status (receive only) */ 423 { TLU_OE_BIT_DESC(MRC, hw_reset, pciex_rx_oe) }, 424 425 /* TLU Other Event Status (rx + tx) */ 426 { TLU_OE_BIT_DESC(WUC, wuc_ruc, pciex_rx_tx_oe) }, 427 { TLU_OE_BIT_DESC(RUC, wuc_ruc, pciex_rx_tx_oe) }, 428 { TLU_OE_BIT_DESC(CRS, no_panic, pciex_rx_tx_oe) }, 429 430 /* TLU Other Event */ 431 { TLU_OE_BIT_DESC(IIP, panic, pciex_oe) }, 432 { TLU_OE_BIT_DESC(EDP, panic, pciex_oe) }, 433 { TLU_OE_BIT_DESC(EHP, panic, pciex_oe) }, 434 { TLU_OE_OB_BIT_DESC(TLUEITMO, panic, pciex_oe) }, 435 { TLU_OE_BIT_DESC(LIN, no_panic, pciex_oe) }, 436 { TLU_OE_BIT_DESC(LRS, no_panic, pciex_oe) }, 437 { TLU_OE_BIT_DESC(LDN, tlu_ldn, pciex_oe) }, 438 { TLU_OE_BIT_DESC(LUP, tlu_lup, pciex_oe) }, 439 { TLU_OE_BIT_DESC(ERU, panic, pciex_oe) }, 440 { TLU_OE_BIT_DESC(ERO, panic, pciex_oe) }, 441 { TLU_OE_BIT_DESC(EMP, panic, pciex_oe) }, 442 { TLU_OE_BIT_DESC(EPE, panic, pciex_oe) }, 443 { TLU_OE_BIT_DESC(ERP, panic, pciex_oe) }, 444 { TLU_OE_BIT_DESC(EIP, panic, pciex_oe) } 445 }; 446 447 #define px_err_tlu_oe_keys \ 448 (sizeof (px_err_tlu_oe_tbl)) / (sizeof (px_err_bit_desc_t)) 449 450 451 /* 452 * All the following tables below are for LPU Interrupts. These interrupts 453 * are *NOT* error interrupts, but event status interrupts. 454 * 455 * These events are probably of most interest to: 456 * o Hotplug 457 * o Power Management 458 * o etc... 459 * 460 * There are also a few events that would be interresting for FMA. 461 * Again none of the regiseters below state that an error has occured 462 * or that data has been lost. If anything, they give status that an 463 * error is *about* to occur. examples 464 * o INT_SKP_ERR - indicates clock between fire and child is too far 465 * off and is most unlikely able to compensate 466 * o INT_TX_PAR_ERR - A parity error occured in ONE lane. This is 467 * HW recoverable, but will like end up as a future 468 * fabric error as well. 469 * 470 * For now, we don't care about any of these errors and should be ignore, 471 * but cleared. 472 */ 473 474 /* LPU Link Interrupt Table */ 475 #define LPUL_BIT_DESC(bit, hdl, erpt) \ 476 LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 477 0, \ 478 NULL, \ 479 NULL, \ 480 "" 481 px_err_bit_desc_t px_err_lpul_tbl[] = { 482 { LPUL_BIT_DESC(LINK_ERR_ACT, NULL, NULL) } 483 }; 484 #define px_err_lpul_keys \ 485 (sizeof (px_err_lpul_tbl)) / (sizeof (px_err_bit_desc_t)) 486 487 /* LPU Physical Interrupt Table */ 488 #define LPUP_BIT_DESC(bit, hdl, erpt) \ 489 LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 490 0, \ 491 NULL, \ 492 NULL, \ 493 "" 494 px_err_bit_desc_t px_err_lpup_tbl[] = { 495 { LPUP_BIT_DESC(PHY_LAYER_ERR, NULL, NULL) } 496 }; 497 #define px_err_lpup_keys \ 498 (sizeof (px_err_lpup_tbl)) / (sizeof (px_err_bit_desc_t)) 499 500 /* LPU Receive Interrupt Table */ 501 #define LPUR_BIT_DESC(bit, hdl, erpt) \ 502 LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 503 0, \ 504 NULL, \ 505 NULL, \ 506 "" 507 px_err_bit_desc_t px_err_lpur_tbl[] = { 508 { LPUR_BIT_DESC(RCV_PHY, NULL, NULL) } 509 }; 510 #define px_err_lpur_keys \ 511 (sizeof (px_err_lpur_tbl)) / (sizeof (px_err_bit_desc_t)) 512 513 /* LPU Transmit Interrupt Table */ 514 #define LPUX_BIT_DESC(bit, hdl, erpt) \ 515 LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 516 0, \ 517 NULL, \ 518 NULL, \ 519 "" 520 px_err_bit_desc_t px_err_lpux_tbl[] = { 521 { LPUX_BIT_DESC(UNMSK, NULL, NULL) } 522 }; 523 #define px_err_lpux_keys \ 524 (sizeof (px_err_lpux_tbl)) / (sizeof (px_err_bit_desc_t)) 525 526 /* LPU LTSSM Interrupt Table */ 527 #define LPUS_BIT_DESC(bit, hdl, erpt) \ 528 LPU_LTSSM_INTERRUPT_AND_STATUS_INT_ ## bit, \ 529 0, \ 530 NULL, \ 531 NULL, \ 532 "" 533 px_err_bit_desc_t px_err_lpus_tbl[] = { 534 { LPUS_BIT_DESC(ANY, NULL, NULL) } 535 }; 536 #define px_err_lpus_keys \ 537 (sizeof (px_err_lpus_tbl)) / (sizeof (px_err_bit_desc_t)) 538 539 /* LPU Gigablaze Glue Interrupt Table */ 540 #define LPUG_BIT_DESC(bit, hdl, erpt) \ 541 LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_ ## bit, \ 542 0, \ 543 NULL, \ 544 NULL, \ 545 "" 546 px_err_bit_desc_t px_err_lpug_tbl[] = { 547 { LPUG_BIT_DESC(GLOBL_UNMSK, NULL, NULL) } 548 }; 549 #define px_err_lpug_keys \ 550 (sizeof (px_err_lpug_tbl)) / (sizeof (px_err_bit_desc_t)) 551 552 553 /* Mask and Tables */ 554 #define MnT6X(pre) \ 555 &px_ ## pre ## _intr_mask, \ 556 &px_ ## pre ## _log_mask, \ 557 &px_ ## pre ## _count_mask, \ 558 px_err_ ## pre ## _tbl, \ 559 px_err_ ## pre ## _keys, \ 560 PX_REG_XBC, \ 561 0 562 563 #define MnT6(pre) \ 564 &px_ ## pre ## _intr_mask, \ 565 &px_ ## pre ## _log_mask, \ 566 &px_ ## pre ## _count_mask, \ 567 px_err_ ## pre ## _tbl, \ 568 px_err_ ## pre ## _keys, \ 569 PX_REG_CSR, \ 570 0 571 572 /* LPU Registers Addresses */ 573 #define LR4(pre) \ 574 NULL, \ 575 LPU_ ## pre ## _INTERRUPT_MASK, \ 576 LPU_ ## pre ## _INTERRUPT_AND_STATUS, \ 577 LPU_ ## pre ## _INTERRUPT_AND_STATUS 578 579 /* LPU Registers Addresses with Irregularities */ 580 #define LR4_FIXME(pre) \ 581 NULL, \ 582 LPU_ ## pre ## _INTERRUPT_MASK, \ 583 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS, \ 584 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS 585 586 /* TLU Registers Addresses */ 587 #define TR4(pre) \ 588 TLU_ ## pre ## _LOG_ENABLE, \ 589 TLU_ ## pre ## _INTERRUPT_ENABLE, \ 590 TLU_ ## pre ## _INTERRUPT_STATUS, \ 591 TLU_ ## pre ## _STATUS_CLEAR 592 593 /* Registers Addresses for JBC, UBC, MMU, IMU and ILU */ 594 #define R4(pre) \ 595 pre ## _ERROR_LOG_ENABLE, \ 596 pre ## _INTERRUPT_ENABLE, \ 597 pre ## _INTERRUPT_STATUS, \ 598 pre ## _ERROR_STATUS_CLEAR 599 600 /* Bits in chip_mask, set according to type. */ 601 #define CHP_O BITMASK(PX_CHIP_OBERON) 602 #define CHP_F BITMASK(PX_CHIP_FIRE) 603 #define CHP_FO (CHP_F | CHP_O) 604 605 /* 606 * Register error handling tables. 607 * The ID Field (first field) is identified by an enum px_err_id_t. 608 * It is located in px_err.h 609 */ 610 static const 611 px_err_reg_desc_t px_err_reg_tbl[] = { 612 { CHP_F, MnT6X(jbc), R4(JBC), "JBC Error"}, 613 { CHP_O, MnT6X(ubc), R4(UBC), "UBC Error"}, 614 { CHP_FO, MnT6(mmu), R4(MMU), "MMU Error"}, 615 { CHP_FO, MnT6(imu), R4(IMU), "IMU Error"}, 616 { CHP_FO, MnT6(tlu_ue), TR4(UNCORRECTABLE_ERROR), "TLU UE"}, 617 { CHP_FO, MnT6(tlu_ce), TR4(CORRECTABLE_ERROR), "TLU CE"}, 618 { CHP_FO, MnT6(tlu_oe), TR4(OTHER_EVENT), "TLU OE"}, 619 { CHP_FO, MnT6(ilu), R4(ILU), "ILU Error"}, 620 { CHP_F, MnT6(lpul), LR4(LINK_LAYER), "LPU Link Layer"}, 621 { CHP_F, MnT6(lpup), LR4_FIXME(PHY), "LPU Phy Layer"}, 622 { CHP_F, MnT6(lpur), LR4(RECEIVE_PHY), "LPU RX Phy Layer"}, 623 { CHP_F, MnT6(lpux), LR4(TRANSMIT_PHY), "LPU TX Phy Layer"}, 624 { CHP_F, MnT6(lpus), LR4(LTSSM), "LPU LTSSM"}, 625 { CHP_F, MnT6(lpug), LR4(GIGABLAZE_GLUE), "LPU GigaBlaze Glue"}, 626 }; 627 628 #define PX_ERR_REG_KEYS (sizeof (px_err_reg_tbl)) / (sizeof (px_err_reg_tbl[0])) 629 630 typedef struct px_err_ss { 631 uint64_t err_status[PX_ERR_REG_KEYS]; 632 } px_err_ss_t; 633 634 static void px_err_snapshot(px_t *px_p, px_err_ss_t *ss, int block); 635 static int px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, 636 px_err_ss_t *ss); 637 static int px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, 638 int err, int caller); 639 640 /* 641 * px_err_cb_intr: 642 * Interrupt handler for the JBC/UBC block. 643 * o lock 644 * o create derr 645 * o px_err_cmn_intr 646 * o unlock 647 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 648 */ 649 uint_t 650 px_err_cb_intr(caddr_t arg) 651 { 652 px_fault_t *px_fault_p = (px_fault_t *)arg; 653 dev_info_t *rpdip = px_fault_p->px_fh_dip; 654 px_t *px_p = DIP_TO_STATE(rpdip); 655 int err; 656 ddi_fm_error_t derr; 657 658 /* Create the derr */ 659 bzero(&derr, sizeof (ddi_fm_error_t)); 660 derr.fme_version = DDI_FME_VERSION; 661 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 662 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 663 664 mutex_enter(&px_p->px_fm_mutex); 665 666 err = px_err_cmn_intr(px_p, &derr, PX_INTR_CALL, PX_FM_BLOCK_HOST); 667 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 668 INTR_IDLE_STATE); 669 670 mutex_exit(&px_p->px_fm_mutex); 671 672 px_err_panic(err, PX_HB, PX_NO_ERROR); 673 674 return (DDI_INTR_CLAIMED); 675 } 676 677 /* 678 * px_err_dmc_pec_intr: 679 * Interrupt handler for the DMC/PEC block. 680 * o lock 681 * o create derr 682 * o px_err_cmn_intr(leaf, with out cb) 683 * o pcie_scan_fabric (leaf) 684 * o unlock 685 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 686 */ 687 uint_t 688 px_err_dmc_pec_intr(caddr_t arg) 689 { 690 px_fault_t *px_fault_p = (px_fault_t *)arg; 691 dev_info_t *rpdip = px_fault_p->px_fh_dip; 692 px_t *px_p = DIP_TO_STATE(rpdip); 693 int rc_err, fab_err = PF_NO_PANIC; 694 ddi_fm_error_t derr; 695 696 /* Create the derr */ 697 bzero(&derr, sizeof (ddi_fm_error_t)); 698 derr.fme_version = DDI_FME_VERSION; 699 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 700 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 701 702 mutex_enter(&px_p->px_fm_mutex); 703 704 /* send ereport/handle/clear fire registers */ 705 rc_err = px_err_cmn_intr(px_p, &derr, PX_INTR_CALL, PX_FM_BLOCK_PCIE); 706 707 /* Check all child devices for errors */ 708 if (!px_lib_is_in_drain_state(px_p)) { 709 fab_err = pf_scan_fabric(rpdip, &derr, px_p->px_dq_p, 710 &px_p->px_dq_tail); 711 } 712 713 /* Set the interrupt state to idle */ 714 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 715 INTR_IDLE_STATE); 716 717 mutex_exit(&px_p->px_fm_mutex); 718 719 px_err_panic(rc_err, PX_RC, fab_err); 720 721 return (DDI_INTR_CLAIMED); 722 } 723 724 /* 725 * Proper csr_base is responsibility of the caller. (Called from px_lib_dev_init 726 * via px_err_reg_setup_all for pcie error registers; called from 727 * px_cb_add_intr for jbc/ubc from px_cb_attach.) 728 * 729 * Note: reg_id is passed in instead of reg_desc since this function is called 730 * from px_lib4u.c, which doesn't know about the structure of the table. 731 */ 732 void 733 px_err_reg_enable(px_err_id_t reg_id, caddr_t csr_base) 734 { 735 const px_err_reg_desc_t *reg_desc_p = &px_err_reg_tbl[reg_id]; 736 uint64_t intr_mask = *reg_desc_p->intr_mask_p; 737 uint64_t log_mask = *reg_desc_p->log_mask_p; 738 739 /* Enable logs if it exists */ 740 if (reg_desc_p->log_addr != NULL) 741 CSR_XS(csr_base, reg_desc_p->log_addr, log_mask); 742 743 /* 744 * For readability you in code you set 1 to enable an interrupt. 745 * But in Fire it's backwards. You set 1 to *disable* an intr. 746 * Reverse the user tunable intr mask field. 747 * 748 * Disable All Errors 749 * Clear All Errors 750 * Enable Errors 751 */ 752 CSR_XS(csr_base, reg_desc_p->enable_addr, 0); 753 CSR_XS(csr_base, reg_desc_p->clear_addr, -1); 754 CSR_XS(csr_base, reg_desc_p->enable_addr, intr_mask); 755 DBG(DBG_ATTACH, NULL, "%s Mask: 0x%llx\n", reg_desc_p->msg, 756 CSR_XR(csr_base, reg_desc_p->enable_addr)); 757 DBG(DBG_ATTACH, NULL, "%s Status: 0x%llx\n", reg_desc_p->msg, 758 CSR_XR(csr_base, reg_desc_p->status_addr)); 759 DBG(DBG_ATTACH, NULL, "%s Clear: 0x%llx\n", reg_desc_p->msg, 760 CSR_XR(csr_base, reg_desc_p->clear_addr)); 761 if (reg_desc_p->log_addr != NULL) { 762 DBG(DBG_ATTACH, NULL, "%s Log: 0x%llx\n", reg_desc_p->msg, 763 CSR_XR(csr_base, reg_desc_p->log_addr)); 764 } 765 } 766 767 void 768 px_err_reg_disable(px_err_id_t reg_id, caddr_t csr_base) 769 { 770 const px_err_reg_desc_t *reg_desc_p = &px_err_reg_tbl[reg_id]; 771 uint64_t val = (reg_id >= PX_ERR_LPU_LINK) ? -1 : 0; 772 773 if (reg_desc_p->log_addr != NULL) 774 CSR_XS(csr_base, reg_desc_p->log_addr, val); 775 CSR_XS(csr_base, reg_desc_p->enable_addr, val); 776 } 777 778 /* 779 * Set up pcie error registers. 780 */ 781 void 782 px_err_reg_setup_pcie(uint8_t chip_mask, caddr_t csr_base, boolean_t enable) 783 { 784 px_err_id_t reg_id; 785 const px_err_reg_desc_t *reg_desc_p; 786 void (*px_err_reg_func)(px_err_id_t, caddr_t); 787 788 /* 789 * JBC or XBC are enabled during adding of common block interrupts, 790 * not done here. 791 */ 792 px_err_reg_func = (enable ? px_err_reg_enable : px_err_reg_disable); 793 for (reg_id = 0; reg_id < PX_ERR_REG_KEYS; reg_id++) { 794 reg_desc_p = &px_err_reg_tbl[reg_id]; 795 if ((reg_desc_p->chip_mask & chip_mask) && 796 (reg_desc_p->reg_bank == PX_REG_CSR)) 797 px_err_reg_func(reg_id, csr_base); 798 } 799 } 800 801 /* 802 * px_err_cmn_intr: 803 * Common function called by trap, mondo and fabric intr. 804 * o Snap shot current fire registers 805 * o check for safe access 806 * o send ereport and clear snap shot registers 807 * o create and queue RC info for later use in fabric scan. 808 * o RUC/WUC, PTLP, MMU Errors(CA), UR 809 * o check severity of snap shot registers 810 * 811 * @param px_p leaf in which to check access 812 * @param derr fm err data structure to be updated 813 * @param caller PX_TRAP_CALL | PX_INTR_CALL 814 * @param block PX_FM_BLOCK_HOST | PX_FM_BLOCK_PCIE | PX_FM_BLOCK_ALL 815 * @return err PX_NO_PANIC | PX_PANIC | PX_HW_RESET | PX_PROTECTED 816 */ 817 int 818 px_err_cmn_intr(px_t *px_p, ddi_fm_error_t *derr, int caller, int block) 819 { 820 px_err_ss_t ss = {0}; 821 int err; 822 823 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 824 825 /* check for safe access */ 826 px_err_safeacc_check(px_p, derr); 827 828 /* snap shot the current fire registers */ 829 px_err_snapshot(px_p, &ss, block); 830 831 /* send ereports/handle/clear registers */ 832 err = px_err_erpt_and_clr(px_p, derr, &ss); 833 834 /* check for error severity */ 835 err = px_err_check_severity(px_p, derr, err, caller); 836 837 /* Mark the On Trap Handle if an error occured */ 838 if (err != PX_NO_ERROR) { 839 px_pec_t *pec_p = px_p->px_pec_p; 840 on_trap_data_t *otd = pec_p->pec_ontrap_data; 841 842 if ((otd != NULL) && (otd->ot_prot & OT_DATA_ACCESS)) 843 otd->ot_trap |= OT_DATA_ACCESS; 844 } 845 846 return (err); 847 } 848 849 /* 850 * Static function 851 */ 852 853 /* 854 * px_err_snapshot: 855 * Take a current snap shot of all the fire error registers. This includes 856 * JBC/UBC, DMC, and PEC depending on the block flag 857 * 858 * @param px_p leaf in which to take the snap shot. 859 * @param ss pre-allocated memory to store the snap shot. 860 * @param chk_cb boolean on whether to store jbc/ubc register. 861 */ 862 static void 863 px_err_snapshot(px_t *px_p, px_err_ss_t *ss_p, int block) 864 { 865 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 866 caddr_t xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 867 caddr_t pec_csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 868 caddr_t csr_base; 869 uint8_t chip_mask = 1 << PX_CHIP_TYPE(pxu_p); 870 const px_err_reg_desc_t *reg_desc_p = px_err_reg_tbl; 871 px_err_id_t reg_id; 872 873 for (reg_id = 0; reg_id < PX_ERR_REG_KEYS; reg_id++, reg_desc_p++) { 874 if (!(reg_desc_p->chip_mask & chip_mask)) 875 continue; 876 877 if ((block & PX_FM_BLOCK_HOST) && 878 (reg_desc_p->reg_bank == PX_REG_XBC)) 879 csr_base = xbc_csr_base; 880 else if ((block & PX_FM_BLOCK_PCIE) && 881 (reg_desc_p->reg_bank == PX_REG_CSR)) 882 csr_base = pec_csr_base; 883 else { 884 ss_p->err_status[reg_id] = 0; 885 continue; 886 } 887 888 ss_p->err_status[reg_id] = CSR_XR(csr_base, 889 reg_desc_p->status_addr); 890 } 891 } 892 893 /* 894 * px_err_erpt_and_clr: 895 * This function does the following thing to all the fire registers based 896 * on an earlier snap shot. 897 * o Send ereport 898 * o Handle the error 899 * o Clear the error 900 * 901 * @param px_p leaf in which to take the snap shot. 902 * @param derr fm err in which the ereport is to be based on 903 * @param ss_p pre-allocated memory to store the snap shot. 904 */ 905 static int 906 px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, px_err_ss_t *ss_p) 907 { 908 dev_info_t *rpdip = px_p->px_dip; 909 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 910 caddr_t csr_base; 911 const px_err_reg_desc_t *err_reg_tbl; 912 px_err_bit_desc_t *err_bit_tbl; 913 px_err_bit_desc_t *err_bit_desc; 914 915 uint64_t *count_mask; 916 uint64_t clear_addr; 917 uint64_t ss_reg; 918 919 int (*err_handler)(); 920 int (*erpt_handler)(); 921 int reg_id, key; 922 int err = PX_NO_ERROR; 923 int biterr = 0; 924 925 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 926 927 /* send erport/handle/clear JBC errors */ 928 for (reg_id = 0; reg_id < PX_ERR_REG_KEYS; reg_id++) { 929 /* Get the correct register description table */ 930 err_reg_tbl = &px_err_reg_tbl[reg_id]; 931 932 /* Only look at enabled groups. */ 933 if (!(BIT_TST(err_reg_tbl->chip_mask, PX_CHIP_TYPE(pxu_p)))) 934 continue; 935 936 /* Get the correct CSR BASE */ 937 csr_base = (caddr_t)pxu_p->px_address[err_reg_tbl->reg_bank]; 938 939 /* If there are no errors in this register, continue */ 940 ss_reg = ss_p->err_status[reg_id]; 941 if (!ss_reg) 942 continue; 943 944 /* Get pointers to masks and register addresses */ 945 count_mask = err_reg_tbl->count_mask_p; 946 clear_addr = err_reg_tbl->clear_addr; 947 948 /* Get the register BIT description table */ 949 err_bit_tbl = err_reg_tbl->err_bit_tbl; 950 951 /* For each known bit in the register send erpt and handle */ 952 for (key = 0; key < err_reg_tbl->err_bit_keys; key++) { 953 /* 954 * If the ss_reg is set for this bit, 955 * send ereport and handle 956 */ 957 err_bit_desc = &err_bit_tbl[key]; 958 if (!BIT_TST(ss_reg, err_bit_desc->bit)) 959 continue; 960 961 /* Increment the counter if necessary */ 962 if (BIT_TST(*count_mask, err_bit_desc->bit)) { 963 err_bit_desc->counter++; 964 } 965 966 /* Error Handle for this bit */ 967 err_handler = err_bit_desc->err_handler; 968 if (err_handler) { 969 biterr = err_handler(rpdip, csr_base, derr, 970 err_reg_tbl, err_bit_desc); 971 err |= biterr; 972 } 973 974 /* 975 * Send the ereport if it's an UNEXPECTED err. 976 * This is the only place where PX_EXPECTED is utilized. 977 */ 978 erpt_handler = err_bit_desc->erpt_handler; 979 if ((derr->fme_flag != DDI_FM_ERR_UNEXPECTED) || 980 (biterr == PX_EXPECTED)) 981 continue; 982 983 if (erpt_handler) 984 (void) erpt_handler(rpdip, csr_base, ss_reg, 985 derr, err_bit_desc->bit, 986 err_bit_desc->class_name); 987 } 988 989 /* Clear the register and error */ 990 CSR_XS(csr_base, clear_addr, ss_reg); 991 } 992 993 return (err); 994 } 995 996 /* 997 * px_err_check_severity: 998 * Check the severity of the fire error based on an earlier snapshot 999 * 1000 * @param px_p leaf in which to take the snap shot. 1001 * @param derr fm err in which the ereport is to be based on 1002 * @param err fire register error status 1003 * @param caller PX_TRAP_CALL | PX_INTR_CALL | PX_LIB_CALL 1004 */ 1005 static int 1006 px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, int err, int caller) 1007 { 1008 px_pec_t *pec_p = px_p->px_pec_p; 1009 boolean_t is_safeacc = B_FALSE; 1010 1011 /* 1012 * Nothing to do if called with no error. 1013 * The err could have already been set to PX_NO_PANIC, which means the 1014 * system doesn't need to panic, but PEEK/POKE still failed. 1015 */ 1016 if (err == PX_NO_ERROR) 1017 return (err); 1018 1019 /* Cautious access error handling */ 1020 switch (derr->fme_flag) { 1021 case DDI_FM_ERR_EXPECTED: 1022 if (caller == PX_TRAP_CALL) { 1023 /* 1024 * for ddi_caut_get treat all events as nonfatal 1025 * The trampoline will set err_ena = 0, 1026 * err_status = NONFATAL. 1027 */ 1028 derr->fme_status = DDI_FM_NONFATAL; 1029 is_safeacc = B_TRUE; 1030 } else { 1031 /* 1032 * For ddi_caut_put treat all events as nonfatal. Here 1033 * we have the handle and can call ndi_fm_acc_err_set(). 1034 */ 1035 derr->fme_status = DDI_FM_NONFATAL; 1036 ndi_fm_acc_err_set(pec_p->pec_acc_hdl, derr); 1037 is_safeacc = B_TRUE; 1038 } 1039 break; 1040 case DDI_FM_ERR_PEEK: 1041 case DDI_FM_ERR_POKE: 1042 /* 1043 * For ddi_peek/poke treat all events as nonfatal. 1044 */ 1045 is_safeacc = B_TRUE; 1046 break; 1047 default: 1048 is_safeacc = B_FALSE; 1049 } 1050 1051 /* re-adjust error status from safe access, forgive all errors */ 1052 if (is_safeacc) 1053 return (PX_NO_PANIC); 1054 1055 return (err); 1056 } 1057 1058 /* predefined convenience functions */ 1059 /* ARGSUSED */ 1060 void 1061 px_err_log_handle(dev_info_t *rpdip, px_err_reg_desc_t *err_reg_descr, 1062 px_err_bit_desc_t *err_bit_descr, char *msg) 1063 { 1064 DBG(DBG_ERR_INTR, rpdip, 1065 "Bit %d, %s, at %s(0x%x) has occured %d times with a severity " 1066 "of \"%s\"\n", 1067 err_bit_descr->bit, err_bit_descr->class_name, 1068 err_reg_descr->msg, err_reg_descr->status_addr, 1069 err_bit_descr->counter, msg); 1070 } 1071 1072 /* ARGSUSED */ 1073 int 1074 px_err_hw_reset_handle(dev_info_t *rpdip, caddr_t csr_base, 1075 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1076 px_err_bit_desc_t *err_bit_descr) 1077 { 1078 if (px_log & PX_HW_RESET) { 1079 px_err_log_handle(rpdip, err_reg_descr, err_bit_descr, 1080 "HW RESET"); 1081 } 1082 1083 return (PX_HW_RESET); 1084 } 1085 1086 /* ARGSUSED */ 1087 int 1088 px_err_panic_handle(dev_info_t *rpdip, caddr_t csr_base, 1089 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1090 px_err_bit_desc_t *err_bit_descr) 1091 { 1092 if (px_log & PX_PANIC) { 1093 px_err_log_handle(rpdip, err_reg_descr, err_bit_descr, "PANIC"); 1094 } 1095 1096 return (PX_PANIC); 1097 } 1098 1099 /* ARGSUSED */ 1100 int 1101 px_err_protected_handle(dev_info_t *rpdip, caddr_t csr_base, 1102 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1103 px_err_bit_desc_t *err_bit_descr) 1104 { 1105 if (px_log & PX_PROTECTED) { 1106 px_err_log_handle(rpdip, err_reg_descr, err_bit_descr, 1107 "PROTECTED"); 1108 } 1109 1110 return (PX_PROTECTED); 1111 } 1112 1113 /* ARGSUSED */ 1114 int 1115 px_err_no_panic_handle(dev_info_t *rpdip, caddr_t csr_base, 1116 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1117 px_err_bit_desc_t *err_bit_descr) 1118 { 1119 if (px_log & PX_NO_PANIC) { 1120 px_err_log_handle(rpdip, err_reg_descr, err_bit_descr, 1121 "NO PANIC"); 1122 } 1123 1124 return (PX_NO_PANIC); 1125 } 1126 1127 /* ARGSUSED */ 1128 int 1129 px_err_no_error_handle(dev_info_t *rpdip, caddr_t csr_base, 1130 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1131 px_err_bit_desc_t *err_bit_descr) 1132 { 1133 if (px_log & PX_NO_ERROR) { 1134 px_err_log_handle(rpdip, err_reg_descr, err_bit_descr, 1135 "NO ERROR"); 1136 } 1137 1138 return (PX_NO_ERROR); 1139 } 1140 1141 /* ARGSUSED */ 1142 PX_ERPT_SEND_DEC(do_not) 1143 { 1144 return (PX_NO_ERROR); 1145 } 1146 1147 1148 /* UBC FATAL - see io erpt doc, section 1.1 */ 1149 /* ARGSUSED */ 1150 PX_ERPT_SEND_DEC(ubc_fatal) 1151 { 1152 char buf[FM_MAX_CLASS]; 1153 uint64_t memory_ue_log, marked; 1154 char unum[FM_MAX_CLASS]; 1155 int unum_length; 1156 uint64_t device_id = 0; 1157 uint8_t cpu_version = 0; 1158 nvlist_t *resource = NULL; 1159 1160 unum[0] = '\0'; 1161 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1162 1163 memory_ue_log = CSR_XR(csr_base, UBC_MEMORY_UE_LOG); 1164 marked = (memory_ue_log >> UBC_MEMORY_UE_LOG_MARKED) & 1165 UBC_MEMORY_UE_LOG_MARKED_MASK; 1166 1167 if ((strstr(class_name, "ubc.piowtue") != NULL) || 1168 (strstr(class_name, "ubc.piowbeue") != NULL) || 1169 (strstr(class_name, "ubc.piorbeue") != NULL) || 1170 (strstr(class_name, "ubc.dmarduea") != NULL) || 1171 (strstr(class_name, "ubc.dmardueb") != NULL)) { 1172 int eid = (memory_ue_log >> UBC_MEMORY_UE_LOG_EID) & 1173 UBC_MEMORY_UE_LOG_EID_MASK; 1174 (void) strncat(buf, ubc_class_eid_qualifier[eid], 1175 FM_MAX_CLASS); 1176 1177 if (eid == UBC_EID_MEM) { 1178 uint64_t phys_addr = memory_ue_log & 1179 MMU_OBERON_PADDR_MASK; 1180 uint64_t offset = (uint64_t)-1; 1181 1182 resource = fm_nvlist_create(NULL); 1183 if (&plat_get_mem_unum) { 1184 if ((plat_get_mem_unum(0, 1185 phys_addr, 0, B_TRUE, 0, unum, 1186 FM_MAX_CLASS, &unum_length)) != 0) 1187 unum[0] = '\0'; 1188 } 1189 fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, 1190 NULL, unum, NULL, offset); 1191 1192 } else if (eid == UBC_EID_CPU) { 1193 int cpuid = (marked & UBC_MARKED_MAX_CPUID_MASK); 1194 char sbuf[21]; /* sizeof (UINT64_MAX) + '\0' */ 1195 1196 resource = fm_nvlist_create(NULL); 1197 cpu_version = cpunodes[cpuid].version; 1198 device_id = cpunodes[cpuid].device_id; 1199 (void) snprintf(sbuf, sizeof (sbuf), "%lX", 1200 device_id); 1201 (void) fm_fmri_cpu_set(resource, 1202 FM_CPU_SCHEME_VERSION, NULL, cpuid, 1203 &cpu_version, sbuf); 1204 } 1205 } 1206 1207 if (resource) { 1208 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1209 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1210 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1211 OBERON_UBC_ELE, DATA_TYPE_UINT64, 1212 CSR_XR(csr_base, UBC_ERROR_LOG_ENABLE), 1213 OBERON_UBC_IE, DATA_TYPE_UINT64, 1214 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE), 1215 OBERON_UBC_IS, DATA_TYPE_UINT64, 1216 CSR_XR(csr_base, UBC_INTERRUPT_STATUS), 1217 OBERON_UBC_ESS, DATA_TYPE_UINT64, 1218 CSR_XR(csr_base, UBC_ERROR_STATUS_SET), 1219 OBERON_UBC_MUE, DATA_TYPE_UINT64, memory_ue_log, 1220 OBERON_UBC_UNUM, DATA_TYPE_STRING, unum, 1221 OBERON_UBC_DID, DATA_TYPE_UINT64, device_id, 1222 OBERON_UBC_CPUV, DATA_TYPE_UINT32, cpu_version, 1223 OBERON_UBC_RESOURCE, DATA_TYPE_NVLIST, resource, 1224 NULL); 1225 fm_nvlist_destroy(resource, FM_NVA_FREE); 1226 } else { 1227 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1228 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1229 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1230 OBERON_UBC_ELE, DATA_TYPE_UINT64, 1231 CSR_XR(csr_base, UBC_ERROR_LOG_ENABLE), 1232 OBERON_UBC_IE, DATA_TYPE_UINT64, 1233 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE), 1234 OBERON_UBC_IS, DATA_TYPE_UINT64, 1235 CSR_XR(csr_base, UBC_INTERRUPT_STATUS), 1236 OBERON_UBC_ESS, DATA_TYPE_UINT64, 1237 CSR_XR(csr_base, UBC_ERROR_STATUS_SET), 1238 OBERON_UBC_MUE, DATA_TYPE_UINT64, memory_ue_log, 1239 OBERON_UBC_UNUM, DATA_TYPE_STRING, unum, 1240 OBERON_UBC_DID, DATA_TYPE_UINT64, device_id, 1241 OBERON_UBC_CPUV, DATA_TYPE_UINT32, cpu_version, 1242 NULL); 1243 } 1244 1245 return (PX_NO_PANIC); 1246 } 1247 1248 /* JBC FATAL */ 1249 PX_ERPT_SEND_DEC(jbc_fatal) 1250 { 1251 char buf[FM_MAX_CLASS]; 1252 boolean_t pri = PX_ERR_IS_PRI(bit); 1253 1254 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1255 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1256 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1257 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1258 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1259 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1260 FIRE_JBC_IE, DATA_TYPE_UINT64, 1261 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1262 FIRE_JBC_IS, DATA_TYPE_UINT64, 1263 ss_reg, 1264 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1265 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1266 FIRE_JBC_FEL1, DATA_TYPE_UINT64, 1267 CSR_XR(csr_base, FATAL_ERROR_LOG_1), 1268 FIRE_JBC_FEL2, DATA_TYPE_UINT64, 1269 CSR_XR(csr_base, FATAL_ERROR_LOG_2), 1270 NULL); 1271 1272 return (PX_NO_PANIC); 1273 } 1274 1275 /* JBC MERGE */ 1276 PX_ERPT_SEND_DEC(jbc_merge) 1277 { 1278 char buf[FM_MAX_CLASS]; 1279 boolean_t pri = PX_ERR_IS_PRI(bit); 1280 1281 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1282 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1283 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1284 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1285 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1286 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1287 FIRE_JBC_IE, DATA_TYPE_UINT64, 1288 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1289 FIRE_JBC_IS, DATA_TYPE_UINT64, 1290 ss_reg, 1291 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1292 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1293 FIRE_JBC_MTEL, DATA_TYPE_UINT64, 1294 CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG), 1295 NULL); 1296 1297 return (PX_NO_PANIC); 1298 } 1299 1300 /* 1301 * JBC Merge buffer retryable errors: 1302 * Merge buffer parity error (rd_buf): PIO or DMA 1303 * Merge buffer parity error (wr_buf): PIO or DMA 1304 */ 1305 /* ARGSUSED */ 1306 int 1307 px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 1308 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1309 px_err_bit_desc_t *err_bit_descr) 1310 { 1311 /* 1312 * Holder function to attempt error recovery. When the features 1313 * are in place, look up the address of the transaction in: 1314 * 1315 * paddr = CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG); 1316 * paddr &= MERGE_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1317 * 1318 * If the error is a secondary error, there is no log information 1319 * just panic as it is unknown which address has been affected. 1320 * 1321 * Remember the address is pretranslation and might be hard to look 1322 * up the appropriate driver based on the PA. 1323 */ 1324 return (px_err_panic_handle(rpdip, csr_base, derr, err_reg_descr, 1325 err_bit_descr)); 1326 } 1327 1328 /* JBC Jbusint IN */ 1329 PX_ERPT_SEND_DEC(jbc_in) 1330 { 1331 char buf[FM_MAX_CLASS]; 1332 boolean_t pri = PX_ERR_IS_PRI(bit); 1333 1334 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1335 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1336 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1337 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1338 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1339 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1340 FIRE_JBC_IE, DATA_TYPE_UINT64, 1341 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1342 FIRE_JBC_IS, DATA_TYPE_UINT64, 1343 ss_reg, 1344 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1345 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1346 FIRE_JBC_JITEL1, DATA_TYPE_UINT64, 1347 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG), 1348 FIRE_JBC_JITEL2, DATA_TYPE_UINT64, 1349 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG_2), 1350 NULL); 1351 1352 return (PX_NO_PANIC); 1353 } 1354 1355 /* 1356 * JBC Jbusint IN retryable errors 1357 * Log Reg[42:0]. 1358 * Write Data Parity Error: PIO Writes 1359 * Read Data Parity Error: DMA Reads 1360 */ 1361 int 1362 px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 1363 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1364 px_err_bit_desc_t *err_bit_descr) 1365 { 1366 /* 1367 * Holder function to attempt error recovery. When the features 1368 * are in place, look up the address of the transaction in: 1369 * 1370 * paddr = CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG); 1371 * paddr &= JBCINT_IN_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1372 * 1373 * If the error is a secondary error, there is no log information 1374 * just panic as it is unknown which address has been affected. 1375 * 1376 * Remember the address is pretranslation and might be hard to look 1377 * up the appropriate driver based on the PA. 1378 */ 1379 return (px_err_panic_handle(rpdip, csr_base, derr, err_reg_descr, 1380 err_bit_descr)); 1381 } 1382 1383 1384 /* JBC Jbusint Out */ 1385 PX_ERPT_SEND_DEC(jbc_out) 1386 { 1387 char buf[FM_MAX_CLASS]; 1388 boolean_t pri = PX_ERR_IS_PRI(bit); 1389 1390 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1391 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1392 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1393 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1394 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1395 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1396 FIRE_JBC_IE, DATA_TYPE_UINT64, 1397 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1398 FIRE_JBC_IS, DATA_TYPE_UINT64, 1399 ss_reg, 1400 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1401 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1402 FIRE_JBC_JOTEL1, DATA_TYPE_UINT64, 1403 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG), 1404 FIRE_JBC_JOTEL2, DATA_TYPE_UINT64, 1405 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG_2), 1406 NULL); 1407 1408 return (PX_NO_PANIC); 1409 } 1410 1411 /* JBC Dmcint ODCD */ 1412 PX_ERPT_SEND_DEC(jbc_odcd) 1413 { 1414 char buf[FM_MAX_CLASS]; 1415 boolean_t pri = PX_ERR_IS_PRI(bit); 1416 1417 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1418 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1419 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1420 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1421 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1422 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1423 FIRE_JBC_IE, DATA_TYPE_UINT64, 1424 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1425 FIRE_JBC_IS, DATA_TYPE_UINT64, 1426 ss_reg, 1427 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1428 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1429 FIRE_JBC_DMC_ODCD, DATA_TYPE_UINT64, 1430 CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG), 1431 NULL); 1432 1433 return (PX_NO_PANIC); 1434 } 1435 1436 /* 1437 * JBC Dmcint ODCO nonfatal errer handling - 1438 * PIO data parity error: PIO 1439 */ 1440 /* ARGSUSED */ 1441 int 1442 px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 1443 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1444 px_err_bit_desc_t *err_bit_descr) 1445 { 1446 /* 1447 * Holder function to attempt error recovery. When the features 1448 * are in place, look up the address of the transaction in: 1449 * 1450 * paddr = CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG); 1451 * paddr &= DMCINT_ODCD_ERROR_LOG_ADDRESS_MASK; 1452 * 1453 * If the error is a secondary error, there is no log information 1454 * just panic as it is unknown which address has been affected. 1455 * 1456 * Remember the address is pretranslation and might be hard to look 1457 * up the appropriate driver based on the PA. 1458 */ 1459 return (px_err_panic_handle(rpdip, csr_base, derr, err_reg_descr, 1460 err_bit_descr)); 1461 } 1462 1463 /* Does address in DMCINT error log register match address of pcitool access? */ 1464 static boolean_t 1465 px_jbc_pcitool_addr_match(dev_info_t *rpdip, caddr_t csr_base) 1466 { 1467 px_t *px_p = DIP_TO_STATE(rpdip); 1468 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1469 caddr_t pcitool_addr = pxu_p->pcitool_addr; 1470 caddr_t errlog_addr = 1471 (caddr_t)CSR_FR(csr_base, DMCINT_ODCD_ERROR_LOG, ADDRESS); 1472 1473 return (pcitool_addr == errlog_addr); 1474 } 1475 1476 /* 1477 * JBC Dmcint ODCD errer handling for errors which are forgivable during a safe 1478 * access. (This will be most likely be a PCItool access.) If not a safe 1479 * access context, treat like jbc_dmcint_odcd. 1480 * Unmapped PIO read error: pio:read:M:nonfatal 1481 * Unmapped PIO write error: pio:write:M:nonfatal 1482 * Invalid PIO write to PCIe cfg/io, csr, ebus or i2c bus: pio:write:nonfatal 1483 * Invalid PIO read to PCIe cfg/io, csr, ebus or i2c bus: pio:read:nonfatal 1484 */ 1485 /* ARGSUSED */ 1486 int 1487 px_err_jbc_safe_acc_handle(dev_info_t *rpdip, caddr_t csr_base, 1488 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1489 px_err_bit_desc_t *err_bit_descr) 1490 { 1491 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1492 1493 if (!pri) 1494 return (px_err_panic_handle(rpdip, csr_base, derr, 1495 err_reg_descr, err_bit_descr)); 1496 /* 1497 * Got an error which is forgivable during a PCItool access. 1498 * 1499 * Don't do handler check since the error may otherwise be unfairly 1500 * attributed to a device. Just return. 1501 * 1502 * Note: There is a hole here in that a legitimate error can come in 1503 * while a PCItool access is in play and be forgiven. This is possible 1504 * though not likely. 1505 */ 1506 if ((derr->fme_flag != DDI_FM_ERR_UNEXPECTED) && 1507 (px_jbc_pcitool_addr_match(rpdip, csr_base))) 1508 return (px_err_protected_handle(rpdip, csr_base, derr, 1509 err_reg_descr, err_bit_descr)); 1510 1511 return (px_err_jbc_dmcint_odcd_handle(rpdip, csr_base, derr, 1512 err_reg_descr, err_bit_descr)); 1513 } 1514 1515 /* JBC Dmcint IDC */ 1516 PX_ERPT_SEND_DEC(jbc_idc) 1517 { 1518 char buf[FM_MAX_CLASS]; 1519 boolean_t pri = PX_ERR_IS_PRI(bit); 1520 1521 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1522 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1523 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1524 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1525 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1526 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1527 FIRE_JBC_IE, DATA_TYPE_UINT64, 1528 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1529 FIRE_JBC_IS, DATA_TYPE_UINT64, 1530 ss_reg, 1531 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1532 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1533 FIRE_JBC_DMC_IDC, DATA_TYPE_UINT64, 1534 CSR_XR(csr_base, DMCINT_IDC_ERROR_LOG), 1535 NULL); 1536 1537 return (PX_NO_PANIC); 1538 } 1539 1540 /* JBC CSR */ 1541 PX_ERPT_SEND_DEC(jbc_csr) 1542 { 1543 char buf[FM_MAX_CLASS]; 1544 boolean_t pri = PX_ERR_IS_PRI(bit); 1545 1546 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1547 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1548 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1549 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1550 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1551 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1552 FIRE_JBC_IE, DATA_TYPE_UINT64, 1553 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1554 FIRE_JBC_IS, DATA_TYPE_UINT64, 1555 ss_reg, 1556 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1557 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1558 "jbc-error-reg", DATA_TYPE_UINT64, 1559 CSR_XR(csr_base, CSR_ERROR_LOG), 1560 NULL); 1561 1562 return (PX_NO_PANIC); 1563 } 1564 1565 /* DMC IMU RDS */ 1566 PX_ERPT_SEND_DEC(imu_rds) 1567 { 1568 char buf[FM_MAX_CLASS]; 1569 boolean_t pri = PX_ERR_IS_PRI(bit); 1570 1571 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1572 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1573 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1574 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1575 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1576 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1577 FIRE_IMU_IE, DATA_TYPE_UINT64, 1578 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1579 FIRE_IMU_IS, DATA_TYPE_UINT64, 1580 ss_reg, 1581 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1582 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1583 FIRE_IMU_RDS, DATA_TYPE_UINT64, 1584 CSR_XR(csr_base, IMU_RDS_ERROR_LOG), 1585 NULL); 1586 1587 return (PX_NO_PANIC); 1588 } 1589 1590 /* handle EQ overflow */ 1591 /* ARGSUSED */ 1592 int 1593 px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 1594 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1595 px_err_bit_desc_t *err_bit_descr) 1596 { 1597 px_t *px_p = DIP_TO_STATE(rpdip); 1598 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1599 int err = px_err_check_eq(rpdip); 1600 1601 if ((err == PX_PANIC) && (pxu_p->cpr_flag == PX_NOT_CPR)) { 1602 return (px_err_panic_handle(rpdip, csr_base, derr, 1603 err_reg_descr, err_bit_descr)); 1604 } else { 1605 return (px_err_no_panic_handle(rpdip, csr_base, derr, 1606 err_reg_descr, err_bit_descr)); 1607 } 1608 } 1609 1610 /* DMC IMU SCS */ 1611 PX_ERPT_SEND_DEC(imu_scs) 1612 { 1613 char buf[FM_MAX_CLASS]; 1614 boolean_t pri = PX_ERR_IS_PRI(bit); 1615 1616 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1617 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1618 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1619 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1620 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1621 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1622 FIRE_IMU_IE, DATA_TYPE_UINT64, 1623 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1624 FIRE_IMU_IS, DATA_TYPE_UINT64, 1625 ss_reg, 1626 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1627 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1628 FIRE_IMU_SCS, DATA_TYPE_UINT64, 1629 CSR_XR(csr_base, IMU_SCS_ERROR_LOG), 1630 NULL); 1631 1632 return (PX_NO_PANIC); 1633 } 1634 1635 /* DMC IMU */ 1636 PX_ERPT_SEND_DEC(imu) 1637 { 1638 char buf[FM_MAX_CLASS]; 1639 boolean_t pri = PX_ERR_IS_PRI(bit); 1640 1641 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1642 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1643 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1644 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1645 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1646 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1647 FIRE_IMU_IE, DATA_TYPE_UINT64, 1648 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1649 FIRE_IMU_IS, DATA_TYPE_UINT64, 1650 ss_reg, 1651 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1652 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1653 NULL); 1654 1655 return (PX_NO_PANIC); 1656 } 1657 1658 /* DMC MMU TFAR/TFSR */ 1659 PX_ERPT_SEND_DEC(mmu_tfar_tfsr) 1660 { 1661 char buf[FM_MAX_CLASS]; 1662 boolean_t pri = PX_ERR_IS_PRI(bit); 1663 px_t *px_p = DIP_TO_STATE(rpdip); 1664 pcie_req_id_t fault_bdf = 0; 1665 uint16_t s_status = 0; 1666 1667 if (pri) { 1668 fault_bdf = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_STATUS) 1669 & (MMU_TRANSLATION_FAULT_STATUS_ID_MASK << 1670 MMU_TRANSLATION_FAULT_STATUS_ID); 1671 s_status = PCI_STAT_S_TARG_AB; 1672 1673 /* Only PIO Fault Addresses are valid, this is DMA */ 1674 (void) px_rp_en_q(px_p, fault_bdf, NULL, s_status); 1675 } 1676 1677 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1678 1679 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1680 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1681 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1682 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1683 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1684 FIRE_MMU_IE, DATA_TYPE_UINT64, 1685 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1686 FIRE_MMU_IS, DATA_TYPE_UINT64, 1687 ss_reg, 1688 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1689 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1690 FIRE_MMU_TFAR, DATA_TYPE_UINT64, 1691 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS), 1692 FIRE_MMU_TFSR, DATA_TYPE_UINT64, 1693 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_STATUS), 1694 NULL); 1695 1696 return (PX_NO_PANIC); 1697 } 1698 1699 /* DMC MMU */ 1700 PX_ERPT_SEND_DEC(mmu) 1701 { 1702 char buf[FM_MAX_CLASS]; 1703 boolean_t pri = PX_ERR_IS_PRI(bit); 1704 1705 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1706 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1707 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1708 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1709 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1710 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1711 FIRE_MMU_IE, DATA_TYPE_UINT64, 1712 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1713 FIRE_MMU_IS, DATA_TYPE_UINT64, 1714 ss_reg, 1715 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1716 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1717 NULL); 1718 1719 return (PX_NO_PANIC); 1720 } 1721 1722 /* 1723 * IMU function to handle all Received but Not Enabled errors. 1724 * 1725 * These errors are due to transactions modes in which the PX driver was not 1726 * setup to be able to do. If possible, inform the driver that their DMA has 1727 * failed by marking their DMA handle as failed, but do not panic the system. 1728 * Most likely the address is not valid, as Fire wasn't setup to handle them in 1729 * the first place. 1730 * 1731 * These errors are not retryable, unless the PX mode has changed, otherwise the 1732 * same error will occur again. 1733 */ 1734 int 1735 px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1736 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1737 px_err_bit_desc_t *err_bit_descr) 1738 { 1739 pcie_req_id_t bdf; 1740 1741 if (!PX_ERR_IS_PRI(err_bit_descr->bit)) 1742 goto done; 1743 1744 bdf = (pcie_req_id_t)CSR_FR(csr_base, MMU_TRANSLATION_FAULT_STATUS, ID); 1745 (void) pf_hdl_lookup(rpdip, derr->fme_ena, PF_DMA_ADDR, NULL, 1746 bdf); 1747 1748 done: 1749 return (px_err_no_panic_handle(rpdip, csr_base, derr, err_reg_descr, 1750 err_bit_descr)); 1751 } 1752 1753 /* 1754 * IMU function to handle all invalid address errors. 1755 * 1756 * These errors are due to transactions in which the address is not recognized. 1757 * If possible, inform the driver that all DMAs have failed by marking their DMA 1758 * handles. Fire should not panic the system, it'll be up to the driver to 1759 * panic. The address logged is invalid. 1760 * 1761 * These errors are not retryable since retrying the same transaction with the 1762 * same invalid address will result in the same error. 1763 */ 1764 /* ARGSUSED */ 1765 int 1766 px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 1767 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1768 px_err_bit_desc_t *err_bit_descr) 1769 { 1770 pcie_req_id_t bdf; 1771 1772 if (!PX_ERR_IS_PRI(err_bit_descr->bit)) 1773 goto done; 1774 1775 bdf = (pcie_req_id_t)CSR_FR(csr_base, MMU_TRANSLATION_FAULT_STATUS, ID); 1776 (void) pf_hdl_lookup(rpdip, derr->fme_ena, PF_DMA_ADDR, NULL, 1777 bdf); 1778 1779 done: 1780 return (px_err_no_panic_handle(rpdip, csr_base, derr, err_reg_descr, 1781 err_bit_descr)); 1782 } 1783 1784 /* 1785 * IMU function to handle normal transactions that encounter a parity error. 1786 * 1787 * These errors are due to transactions that enouter a parity error. If 1788 * possible, inform the driver that their DMA have failed and that they should 1789 * retry. If Fire is unable to contact the leaf driver, panic the system. 1790 * Otherwise, it'll be up to the device to determine is this is a panicable 1791 * error. 1792 */ 1793 /* ARGSUSED */ 1794 int 1795 px_err_mmu_parity_handle(dev_info_t *rpdip, caddr_t csr_base, 1796 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1797 px_err_bit_desc_t *err_bit_descr) 1798 { 1799 uint64_t mmu_tfa; 1800 pcie_req_id_t bdf; 1801 int status = DDI_FM_UNKNOWN; 1802 1803 if (!PX_ERR_IS_PRI(err_bit_descr->bit)) 1804 goto done; 1805 1806 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1807 bdf = (pcie_req_id_t)CSR_FR(csr_base, MMU_TRANSLATION_FAULT_STATUS, ID); 1808 status = pf_hdl_lookup(rpdip, derr->fme_ena, PF_DMA_ADDR, 1809 (uint32_t)mmu_tfa, bdf); 1810 1811 done: 1812 if (status == DDI_FM_UNKNOWN) 1813 return (px_err_panic_handle(rpdip, csr_base, derr, 1814 err_reg_descr, err_bit_descr)); 1815 else 1816 return (px_err_no_panic_handle(rpdip, csr_base, derr, 1817 err_reg_descr, err_bit_descr)); 1818 } 1819 1820 /* 1821 * wuc/ruc event - Mark the handle of the failed PIO access. Return "no_panic" 1822 */ 1823 /* ARGSUSED */ 1824 int 1825 px_err_wuc_ruc_handle(dev_info_t *rpdip, caddr_t csr_base, 1826 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1827 px_err_bit_desc_t *err_bit_descr) 1828 { 1829 px_t *px_p = DIP_TO_STATE(rpdip); 1830 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1831 uint64_t data; 1832 uint32_t addr, hdr; 1833 pcie_tlp_hdr_t *tlp; 1834 int sts = PF_HDL_NOTFOUND; 1835 1836 if (!PX_ERR_IS_PRI(err_bit_descr->bit)) 1837 goto done; 1838 1839 data = CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG); 1840 hdr = (uint32_t)(data >> 32); 1841 tlp = (pcie_tlp_hdr_t *)&hdr; 1842 data = CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG); 1843 addr = (uint32_t)(data >> 32); 1844 1845 switch (tlp->type) { 1846 case PCIE_TLP_TYPE_IO: 1847 case PCIE_TLP_TYPE_MEM: 1848 case PCIE_TLP_TYPE_MEMLK: 1849 sts = pf_hdl_lookup(rpdip, derr->fme_ena, PF_PIO_ADDR, 1850 addr, NULL); 1851 break; 1852 case PCIE_TLP_TYPE_CFG0: 1853 case PCIE_TLP_TYPE_CFG1: 1854 sts = pf_hdl_lookup(rpdip, derr->fme_ena, PF_CFG_ADDR, 1855 addr, (addr >> 16)); 1856 break; 1857 } 1858 1859 done: 1860 if ((sts == PF_HDL_NOTFOUND) && (pxu_p->cpr_flag == PX_NOT_CPR)) 1861 return (px_err_protected_handle(rpdip, csr_base, derr, 1862 err_reg_descr, err_bit_descr)); 1863 1864 return (px_err_no_panic_handle(rpdip, csr_base, derr, 1865 err_reg_descr, err_bit_descr)); 1866 } 1867 1868 /* 1869 * TLU LUP event - if caused by power management activity, then it is expected. 1870 * In all other cases, it is an error. 1871 */ 1872 /* ARGSUSED */ 1873 int 1874 px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base, 1875 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1876 px_err_bit_desc_t *err_bit_descr) 1877 { 1878 px_t *px_p = DIP_TO_STATE(rpdip); 1879 1880 /* 1881 * power management code is currently the only segment that sets 1882 * px_lup_pending to indicate its expectation for a healthy LUP 1883 * event. For all other occasions, LUP event should be flaged as 1884 * error condition. 1885 */ 1886 return ((atomic_cas_32(&px_p->px_lup_pending, 1, 0) == 0) ? 1887 PX_NO_PANIC : PX_EXPECTED); 1888 } 1889 1890 /* 1891 * TLU LDN event - if caused by power management activity, then it is expected. 1892 * In all other cases, it is an error. 1893 */ 1894 /* ARGSUSED */ 1895 int 1896 px_err_tlu_ldn_handle(dev_info_t *rpdip, caddr_t csr_base, 1897 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1898 px_err_bit_desc_t *err_bit_descr) 1899 { 1900 px_t *px_p = DIP_TO_STATE(rpdip); 1901 return ((px_p->px_pm_flags & PX_LDN_EXPECTED) ? PX_EXPECTED : 1902 PX_NO_PANIC); 1903 } 1904 1905 /* PEC ILU none - see io erpt doc, section 3.1 */ 1906 PX_ERPT_SEND_DEC(pec_ilu) 1907 { 1908 char buf[FM_MAX_CLASS]; 1909 boolean_t pri = PX_ERR_IS_PRI(bit); 1910 1911 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1912 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1913 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1914 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1915 FIRE_ILU_ELE, DATA_TYPE_UINT64, 1916 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE), 1917 FIRE_ILU_IE, DATA_TYPE_UINT64, 1918 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE), 1919 FIRE_ILU_IS, DATA_TYPE_UINT64, 1920 ss_reg, 1921 FIRE_ILU_ESS, DATA_TYPE_UINT64, 1922 CSR_XR(csr_base, ILU_ERROR_STATUS_SET), 1923 NULL); 1924 1925 return (PX_NO_PANIC); 1926 } 1927 1928 /* PCIEX UE Errors */ 1929 /* ARGSUSED */ 1930 int 1931 px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base, 1932 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1933 px_err_bit_desc_t *err_bit_descr) 1934 { 1935 px_err_pcie_t regs = {0}; 1936 uint32_t err_bit; 1937 int err; 1938 uint64_t log; 1939 1940 if (err_bit_descr->bit < 32) { 1941 err_bit = (uint32_t)BITMASK(err_bit_descr->bit); 1942 regs.ue_reg = err_bit; 1943 regs.primary_ue = err_bit; 1944 1945 /* 1946 * Log the Received Log for PTLP and UR. The PTLP most likely 1947 * is a poisoned completion. The original transaction will be 1948 * logged inthe Transmit Log. 1949 */ 1950 if (err_bit & (PCIE_AER_UCE_PTLP | PCIE_AER_UCE_UR)) { 1951 log = CSR_XR(csr_base, 1952 TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG); 1953 regs.rx_hdr1 = (uint32_t)(log >> 32); 1954 regs.rx_hdr2 = (uint32_t)(log && 0xFFFFFFFF); 1955 1956 log = CSR_XR(csr_base, 1957 TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG); 1958 regs.rx_hdr3 = (uint32_t)(log >> 32); 1959 regs.rx_hdr4 = (uint32_t)(log && 0xFFFFFFFF); 1960 } 1961 1962 if (err_bit & (PCIE_AER_UCE_PTLP)) { 1963 log = CSR_XR(csr_base, 1964 TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG); 1965 regs.tx_hdr1 = (uint32_t)(log >> 32); 1966 regs.tx_hdr2 = (uint32_t)(log && 0xFFFFFFFF); 1967 1968 log = CSR_XR(csr_base, 1969 TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG); 1970 regs.tx_hdr3 = (uint32_t)(log >> 32); 1971 regs.tx_hdr4 = (uint32_t)(log && 0xFFFFFFFF); 1972 } 1973 } else { 1974 regs.ue_reg = (uint32_t)BITMASK(err_bit_descr->bit - 32); 1975 } 1976 1977 err = px_err_check_pcie(rpdip, derr, ®s); 1978 1979 if (err == PX_PANIC) { 1980 return (px_err_panic_handle(rpdip, csr_base, derr, 1981 err_reg_descr, err_bit_descr)); 1982 } else { 1983 return (px_err_no_panic_handle(rpdip, csr_base, derr, 1984 err_reg_descr, err_bit_descr)); 1985 } 1986 } 1987 1988 /* PCI-E Uncorrectable Errors */ 1989 PX_ERPT_SEND_DEC(pciex_rx_ue) 1990 { 1991 char buf[FM_MAX_CLASS]; 1992 boolean_t pri = PX_ERR_IS_PRI(bit); 1993 1994 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1995 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1996 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1997 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1998 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1999 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2000 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2001 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2002 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2003 ss_reg, 2004 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2005 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2006 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 2007 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 2008 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 2009 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 2010 NULL); 2011 2012 return (PX_NO_PANIC); 2013 } 2014 2015 /* PCI-E Uncorrectable Errors */ 2016 PX_ERPT_SEND_DEC(pciex_tx_ue) 2017 { 2018 char buf[FM_MAX_CLASS]; 2019 boolean_t pri = PX_ERR_IS_PRI(bit); 2020 2021 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2022 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2023 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2024 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2025 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2026 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2027 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2028 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2029 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2030 ss_reg, 2031 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2032 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2033 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 2034 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 2035 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 2036 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 2037 NULL); 2038 2039 return (PX_NO_PANIC); 2040 } 2041 2042 /* PCI-E Uncorrectable Errors */ 2043 PX_ERPT_SEND_DEC(pciex_rx_tx_ue) 2044 { 2045 char buf[FM_MAX_CLASS]; 2046 boolean_t pri = PX_ERR_IS_PRI(bit); 2047 2048 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2049 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2050 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2051 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2052 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2053 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2054 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2055 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2056 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2057 ss_reg, 2058 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2059 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2060 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 2061 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 2062 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 2063 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 2064 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 2065 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 2066 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 2067 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 2068 NULL); 2069 2070 return (PX_NO_PANIC); 2071 } 2072 2073 /* PCI-E Uncorrectable Errors */ 2074 PX_ERPT_SEND_DEC(pciex_ue) 2075 { 2076 char buf[FM_MAX_CLASS]; 2077 boolean_t pri = PX_ERR_IS_PRI(bit); 2078 2079 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2080 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2081 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2082 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2083 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2084 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2085 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2086 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2087 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2088 ss_reg, 2089 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2090 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2091 NULL); 2092 2093 return (PX_NO_PANIC); 2094 } 2095 2096 /* PCIEX UE Errors */ 2097 /* ARGSUSED */ 2098 int 2099 px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base, 2100 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 2101 px_err_bit_desc_t *err_bit_descr) 2102 { 2103 px_err_pcie_t regs = {0}; 2104 int err; 2105 2106 if (err_bit_descr->bit < 32) 2107 regs.ce_reg = (uint32_t)BITMASK(err_bit_descr->bit); 2108 else 2109 regs.ce_reg = (uint32_t)BITMASK(err_bit_descr->bit - 32); 2110 2111 err = px_err_check_pcie(rpdip, derr, ®s); 2112 2113 if (err == PX_PANIC) { 2114 return (px_err_panic_handle(rpdip, csr_base, derr, 2115 err_reg_descr, err_bit_descr)); 2116 } else { 2117 return (px_err_no_panic_handle(rpdip, csr_base, derr, 2118 err_reg_descr, err_bit_descr)); 2119 } 2120 } 2121 2122 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 2123 PX_ERPT_SEND_DEC(pciex_ce) 2124 { 2125 char buf[FM_MAX_CLASS]; 2126 boolean_t pri = PX_ERR_IS_PRI(bit); 2127 2128 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2129 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2130 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2131 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2132 FIRE_TLU_CELE, DATA_TYPE_UINT64, 2133 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE), 2134 FIRE_TLU_CIE, DATA_TYPE_UINT64, 2135 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE), 2136 FIRE_TLU_CIS, DATA_TYPE_UINT64, 2137 ss_reg, 2138 FIRE_TLU_CESS, DATA_TYPE_UINT64, 2139 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_SET), 2140 NULL); 2141 2142 return (PX_NO_PANIC); 2143 } 2144 2145 /* TLU Other Event Status (receive only) - see io erpt doc, section 3.7 */ 2146 PX_ERPT_SEND_DEC(pciex_rx_oe) 2147 { 2148 char buf[FM_MAX_CLASS]; 2149 boolean_t pri = PX_ERR_IS_PRI(bit); 2150 2151 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2152 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2153 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2154 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2155 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 2156 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 2157 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 2158 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 2159 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 2160 ss_reg, 2161 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 2162 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 2163 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 2164 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 2165 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 2166 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 2167 NULL); 2168 2169 return (PX_NO_PANIC); 2170 } 2171 2172 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 2173 PX_ERPT_SEND_DEC(pciex_rx_tx_oe) 2174 { 2175 char buf[FM_MAX_CLASS]; 2176 boolean_t pri = PX_ERR_IS_PRI(bit); 2177 px_t *px_p = DIP_TO_STATE(rpdip); 2178 uint32_t trans_type, fault_addr = 0; 2179 uint64_t rx_h1, rx_h2, tx_h1, tx_h2; 2180 uint16_t s_status; 2181 int sts; 2182 pcie_req_id_t fault_bdf = 0; 2183 pcie_cpl_t *cpl; 2184 pf_data_t pf_data = {0}; 2185 2186 rx_h1 = CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG); 2187 rx_h2 = CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG); 2188 tx_h1 = CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG); 2189 tx_h2 = CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG); 2190 2191 if ((bit == TLU_OTHER_EVENT_STATUS_SET_RUC_P) || 2192 (bit == TLU_OTHER_EVENT_STATUS_SET_WUC_P)) { 2193 pf_data.aer_h0 = (uint32_t)(rx_h1 >> 32); 2194 pf_data.aer_h1 = (uint32_t)rx_h1; 2195 pf_data.aer_h2 = (uint32_t)(rx_h2 >> 32); 2196 pf_data.aer_h3 = (uint32_t)rx_h2; 2197 2198 /* get completer bdf (fault bdf) from rx logs */ 2199 cpl = (pcie_cpl_t *)&pf_data.aer_h1; 2200 fault_bdf = cpl->cid; 2201 2202 /* Figure out if UR/CA from rx logs */ 2203 if (cpl->status == PCIE_CPL_STS_UR) 2204 s_status = PCI_STAT_R_MAST_AB; 2205 else if (cpl->status == PCIE_CPL_STS_CA) 2206 s_status = PCI_STAT_R_TARG_AB; 2207 2208 2209 pf_data.aer_h0 = (uint32_t)(tx_h1 >> 32); 2210 pf_data.aer_h1 = (uint32_t)tx_h1; 2211 pf_data.aer_h2 = (uint32_t)(tx_h2 >> 32); 2212 pf_data.aer_h3 = (uint32_t)tx_h2; 2213 2214 /* get fault addr from tx logs */ 2215 sts = pf_tlp_decode(rpdip, &pf_data, 0, &fault_addr, 2216 &trans_type); 2217 2218 if (sts == DDI_SUCCESS) 2219 (void) px_rp_en_q(px_p, fault_bdf, fault_addr, 2220 s_status); 2221 } 2222 2223 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2224 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2225 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2226 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2227 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 2228 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 2229 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 2230 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 2231 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 2232 ss_reg, 2233 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 2234 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 2235 FIRE_TLU_ROEEH1L, DATA_TYPE_UINT64, rx_h1, 2236 FIRE_TLU_ROEEH2L, DATA_TYPE_UINT64, rx_h2, 2237 FIRE_TLU_TOEEH1L, DATA_TYPE_UINT64, tx_h1, 2238 FIRE_TLU_TOEEH2L, DATA_TYPE_UINT64, tx_h2, 2239 NULL); 2240 2241 return (PX_NO_PANIC); 2242 } 2243 2244 /* TLU Other Event - see io erpt doc, section 3.9 */ 2245 PX_ERPT_SEND_DEC(pciex_oe) 2246 { 2247 char buf[FM_MAX_CLASS]; 2248 boolean_t pri = PX_ERR_IS_PRI(bit); 2249 2250 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2251 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2252 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2253 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2254 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 2255 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 2256 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 2257 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 2258 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 2259 ss_reg, 2260 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 2261 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 2262 NULL); 2263 2264 return (PX_NO_PANIC); 2265 } 2266