1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * Sun4u PCI to PCI bus bridge nexus driver 31 */ 32 33 #include <sys/conf.h> 34 #include <sys/kmem.h> 35 #include <sys/debug.h> 36 #include <sys/modctl.h> 37 #include <sys/autoconf.h> 38 #include <sys/ddi_impldefs.h> 39 #include <sys/ddi_subrdefs.h> 40 #include <sys/pci.h> 41 #include <sys/pci/pci_nexus.h> 42 #include <sys/pci/pci_regs.h> 43 #include <sys/ddi.h> 44 #include <sys/sunndi.h> 45 #include <sys/sunddi.h> 46 #include <sys/fm/protocol.h> 47 #include <sys/ddifm.h> 48 #include <sys/pci/pci_pwr.h> 49 #include <sys/pci/pci_debug.h> 50 #include <sys/hotplug/pci/pcihp.h> 51 #include <sys/open.h> 52 #include <sys/stat.h> 53 #include <sys/file.h> 54 55 #define NUM_LOGICAL_SLOTS 32 56 57 #define PPB_RANGE_LEN 2 58 59 #define PPB_32BIT_IO 1 60 #define PPB_32bit_MEM 1 61 62 #define PPB_MEMGRAIN 0x100000 63 #define PPB_IOGRAIN 0x1000 64 65 #define PPB_16bit_IOADDR(addr) ((uint16_t)(((uint8_t)(addr) & 0xF0) << 8)) 66 #define PPB_LADDR(lo, hi) (((uint16_t)(hi) << 16) | (uint16_t)(lo)) 67 #define PPB_32bit_MEMADDR(addr) (PPB_LADDR(0, ((uint16_t)(addr) & 0xFFF0))) 68 69 typedef struct slot_table { 70 uchar_t bus_id[128]; 71 uchar_t slot_name[32]; 72 uint8_t device_no; 73 uint8_t phys_slot_num; 74 } slot_table_t; 75 76 /* 77 * The following typedef is used to represent an entry in the "ranges" 78 * property of a device node. 79 */ 80 typedef struct { 81 uint32_t child_high; 82 uint32_t child_mid; 83 uint32_t child_low; 84 uint32_t parent_high; 85 uint32_t parent_mid; 86 uint32_t parent_low; 87 uint32_t size_high; 88 uint32_t size_low; 89 } ppb_ranges_t; 90 91 /* 92 * The variable controls the default setting of the command register 93 * for pci devices. See ppb_initchild() for details. 94 */ 95 static ushort_t ppb_command_default = PCI_COMM_SERR_ENABLE | 96 PCI_COMM_WAIT_CYC_ENAB | 97 PCI_COMM_PARITY_DETECT | 98 PCI_COMM_ME | 99 PCI_COMM_MAE | 100 PCI_COMM_IO; 101 102 static int ppb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *, 103 off_t, off_t, caddr_t *); 104 static int ppb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t, 105 void *, void *); 106 static int ppb_intr_ops(dev_info_t *dip, dev_info_t *rdip, 107 ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 108 109 /* 110 * fm_init busop to initialize our children 111 */ 112 static int ppb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap, 113 ddi_iblock_cookie_t *ibc); 114 static void ppb_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle); 115 static void ppb_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle); 116 static int ppb_bus_power(dev_info_t *dip, void *impl_arg, pm_bus_power_op_t op, 117 void *arg, void *result); 118 119 struct bus_ops ppb_bus_ops = { 120 BUSO_REV, 121 ppb_bus_map, 122 0, 123 0, 124 0, 125 i_ddi_map_fault, 126 ddi_dma_map, 127 ddi_dma_allochdl, 128 ddi_dma_freehdl, 129 ddi_dma_bindhdl, 130 ddi_dma_unbindhdl, 131 ddi_dma_flush, 132 ddi_dma_win, 133 ddi_dma_mctl, 134 ppb_ctlops, 135 ddi_bus_prop_op, 136 ndi_busop_get_eventcookie, /* (*bus_get_eventcookie)(); */ 137 ndi_busop_add_eventcall, /* (*bus_add_eventcall)(); */ 138 ndi_busop_remove_eventcall, /* (*bus_remove_eventcall)(); */ 139 ndi_post_event, /* (*bus_post_event)(); */ 140 0, /* (*bus_intr_ctl)(); */ 141 0, /* (*bus_config)(); */ 142 0, /* (*bus_unconfig)(); */ 143 ppb_fm_init_child, /* (*bus_fm_init)(); */ 144 NULL, /* (*bus_fm_fini)(); */ 145 ppb_bus_enter, /* (*bus_enter)() */ 146 ppb_bus_exit, /* (*bus_exit)() */ 147 ppb_bus_power, /* (*bus_power)() */ 148 ppb_intr_ops /* (*bus_intr_op)(); */ 149 }; 150 151 static int ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp); 152 static int ppb_close(dev_t dev, int flags, int otyp, cred_t *credp); 153 static int ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, 154 cred_t *credp, int *rvalp); 155 static int ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 156 int flags, char *name, caddr_t valuep, int *lengthp); 157 158 static struct cb_ops ppb_cb_ops = { 159 ppb_open, /* open */ 160 ppb_close, /* close */ 161 nulldev, /* strategy */ 162 nulldev, /* print */ 163 nulldev, /* dump */ 164 nulldev, /* read */ 165 nulldev, /* write */ 166 ppb_ioctl, /* ioctl */ 167 nodev, /* devmap */ 168 nodev, /* mmap */ 169 nodev, /* segmap */ 170 nochpoll, /* poll */ 171 ppb_prop_op, /* cb_prop_op */ 172 NULL, /* streamtab */ 173 D_NEW | D_MP | D_HOTPLUG, /* Driver compatibility flag */ 174 CB_REV, /* rev */ 175 nodev, /* int (*cb_aread)() */ 176 nodev /* int (*cb_awrite)() */ 177 }; 178 179 static int ppb_probe(dev_info_t *); 180 static int ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd); 181 static int ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 182 static int ppb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, 183 void *arg, void **result); 184 static int ppb_pwr(dev_info_t *dip, int component, int level); 185 186 struct dev_ops ppb_ops = { 187 DEVO_REV, /* devo_rev */ 188 0, /* refcnt */ 189 ppb_info, /* info */ 190 nulldev, /* identify */ 191 ppb_probe, /* probe */ 192 ppb_attach, /* attach */ 193 ppb_detach, /* detach */ 194 nulldev, /* reset */ 195 &ppb_cb_ops, /* driver operations */ 196 &ppb_bus_ops, /* bus operations */ 197 ppb_pwr 198 }; 199 200 /* 201 * Module linkage information for the kernel. 202 */ 203 204 static struct modldrv modldrv = { 205 &mod_driverops, /* Type of module */ 206 "Standard PCI to PCI bridge nexus driver %I%", 207 &ppb_ops, /* driver ops */ 208 }; 209 210 static struct modlinkage modlinkage = { 211 MODREV_1, 212 (void *)&modldrv, 213 NULL 214 }; 215 216 /* 217 * soft state pointer and structure template: 218 */ 219 static void *ppb_state; 220 221 static struct ppb_cfg_state { 222 dev_info_t *dip; 223 ushort_t command; 224 uchar_t cache_line_size; 225 uchar_t latency_timer; 226 uchar_t header_type; 227 uchar_t sec_latency_timer; 228 ushort_t bridge_control; 229 }; 230 231 typedef struct { 232 233 dev_info_t *dip; 234 235 /* 236 * configuration register state for the bus: 237 */ 238 uchar_t ppb_cache_line_size; 239 uchar_t ppb_latency_timer; 240 241 /* 242 * PM support 243 */ 244 ddi_acc_handle_t ppb_conf_hdl; 245 uint8_t ppb_pmcsr_offset; 246 pci_pwr_t *ppb_pwr_p; 247 248 /* 249 * HP support 250 */ 251 boolean_t hotplug_capable; 252 253 kmutex_t ppb_mutex; 254 uint_t ppb_soft_state; 255 #define PPB_SOFT_STATE_CLOSED 0x00 256 #define PPB_SOFT_STATE_OPEN 0x01 257 #define PPB_SOFT_STATE_OPEN_EXCL 0x02 258 int fm_cap; 259 ddi_iblock_cookie_t fm_ibc; 260 } ppb_devstate_t; 261 262 /* 263 * The following variable enables a workaround for the following obp bug: 264 * 265 * 1234181 - obp should set latency timer registers in pci 266 * configuration header 267 * 268 * Until this bug gets fixed in the obp, the following workaround should 269 * be enabled. 270 */ 271 static uint_t ppb_set_latency_timer_register = 1; 272 273 /* 274 * The following variable enables a workaround for an obp bug to be 275 * submitted. A bug requesting a workaround fof this problem has 276 * been filed: 277 * 278 * 1235094 - need workarounds on positron nexus drivers to set cache 279 * line size registers 280 * 281 * Until this bug gets fixed in the obp, the following workaround should 282 * be enabled. 283 */ 284 static uint_t ppb_set_cache_line_size_register = 1; 285 286 /* 287 * forward function declarations: 288 */ 289 290 /* 291 * FMA error callback 292 * Register error handling callback with our parent. We will just call 293 * our children's error callbacks and return their status. 294 */ 295 static int ppb_err_callback(dev_info_t *dip, ddi_fm_error_t *derr, 296 const void *impl_data); 297 298 /* 299 * init/fini routines to alloc/dealloc fm structures and 300 * register/unregister our callback. 301 */ 302 static void ppb_fm_init(ppb_devstate_t *ppb_p); 303 static void ppb_fm_fini(ppb_devstate_t *ppb_p); 304 305 static void ppb_removechild(dev_info_t *); 306 static int ppb_initchild(dev_info_t *child); 307 static dev_info_t *get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip); 308 static void ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *dip); 309 static void ppb_pwr_teardown(ppb_devstate_t *ppb, dev_info_t *dip); 310 static void ppb_init_hotplug(ppb_devstate_t *ppb); 311 static void ppb_create_ranges_prop(dev_info_t *, ddi_acc_handle_t); 312 extern uint64_t pci_debug_flags = 0; 313 314 int 315 _init(void) 316 { 317 int e; 318 if ((e = ddi_soft_state_init(&ppb_state, sizeof (ppb_devstate_t), 319 1)) == 0 && (e = mod_install(&modlinkage)) != 0) 320 ddi_soft_state_fini(&ppb_state); 321 return (e); 322 } 323 324 int 325 _fini(void) 326 { 327 int e; 328 329 if ((e = mod_remove(&modlinkage)) == 0) 330 ddi_soft_state_fini(&ppb_state); 331 return (e); 332 } 333 334 int 335 _info(struct modinfo *modinfop) 336 { 337 return (mod_info(&modlinkage, modinfop)); 338 } 339 340 /*ARGSUSED*/ 341 static int 342 ppb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 343 { 344 ppb_devstate_t *ppb_p; /* per ppb state pointer */ 345 minor_t minor = getminor((dev_t)arg); 346 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 347 348 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 349 instance); 350 351 switch (infocmd) { 352 default: 353 return (DDI_FAILURE); 354 355 case DDI_INFO_DEVT2INSTANCE: 356 *result = (void *)instance; 357 return (DDI_SUCCESS); 358 359 case DDI_INFO_DEVT2DEVINFO: 360 if (ppb_p == NULL) 361 return (DDI_FAILURE); 362 *result = (void *)ppb_p->dip; 363 return (DDI_SUCCESS); 364 } 365 } 366 367 /*ARGSUSED*/ 368 static int 369 ppb_probe(register dev_info_t *devi) 370 { 371 return (DDI_PROBE_SUCCESS); 372 } 373 374 /*ARGSUSED*/ 375 static int 376 ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd) 377 { 378 int instance; 379 ppb_devstate_t *ppb; 380 ddi_acc_handle_t config_handle; 381 382 switch (cmd) { 383 case DDI_ATTACH: 384 385 /* 386 * Make sure the "device_type" property exists. 387 */ 388 (void) ddi_prop_update_string(DDI_DEV_T_NONE, devi, 389 "device_type", "pci"); 390 391 /* 392 * Allocate and get soft state structure. 393 */ 394 instance = ddi_get_instance(devi); 395 if (ddi_soft_state_zalloc(ppb_state, instance) != DDI_SUCCESS) 396 return (DDI_FAILURE); 397 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, instance); 398 ppb->dip = devi; 399 mutex_init(&ppb->ppb_mutex, NULL, MUTEX_DRIVER, NULL); 400 ppb->ppb_soft_state = PPB_SOFT_STATE_CLOSED; 401 if (pci_config_setup(devi, &config_handle) != DDI_SUCCESS) { 402 mutex_destroy(&ppb->ppb_mutex); 403 ddi_soft_state_free(ppb_state, instance); 404 return (DDI_FAILURE); 405 } 406 ppb_pwr_setup(ppb, devi); 407 408 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 409 mutex_enter(&ppb->ppb_pwr_p->pwr_mutex); 410 411 /* 412 * Before reading config registers, make sure power is 413 * on, and remains on. 414 */ 415 ppb->ppb_pwr_p->pwr_fp++; 416 417 pci_pwr_change(ppb->ppb_pwr_p, 418 ppb->ppb_pwr_p->current_lvl, 419 pci_pwr_new_lvl(ppb->ppb_pwr_p)); 420 } 421 422 ppb->ppb_cache_line_size = 423 pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ); 424 ppb->ppb_latency_timer = 425 pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER); 426 427 /* 428 * Check whether the "ranges" property is present. 429 * Otherwise create the ranges property by reading 430 * the configuration registers 431 */ 432 if (ddi_prop_exists(DDI_DEV_T_ANY, devi, DDI_PROP_DONTPASS, 433 "ranges") == 0) { 434 ppb_create_ranges_prop(devi, config_handle); 435 } 436 437 pci_config_teardown(&config_handle); 438 439 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 440 ppb->ppb_pwr_p->pwr_fp--; 441 442 pci_pwr_change(ppb->ppb_pwr_p, 443 ppb->ppb_pwr_p->current_lvl, 444 pci_pwr_new_lvl(ppb->ppb_pwr_p)); 445 446 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 447 } 448 449 /* 450 * Initialize hotplug support on this bus. At minimum 451 * (for non hotplug bus) this would create ":devctl" minor 452 * node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls 453 * to this bus. This all takes place if this nexus has hot-plug 454 * slots and successfully initializes Hot Plug Framework. 455 */ 456 ppb->hotplug_capable = B_FALSE; 457 ppb_init_hotplug(ppb); 458 if (ppb->hotplug_capable == B_FALSE) { 459 /* 460 * create minor node for devctl interfaces 461 */ 462 if (ddi_create_minor_node(devi, "devctl", S_IFCHR, 463 PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR), 464 DDI_NT_NEXUS, 0) != DDI_SUCCESS) { 465 if (ppb->ppb_pwr_p != NULL) { 466 ppb_pwr_teardown(ppb, devi); 467 } 468 mutex_destroy(&ppb->ppb_mutex); 469 ddi_soft_state_free(ppb_state, instance); 470 return (DDI_FAILURE); 471 } 472 } 473 474 DEBUG1(DBG_ATTACH, devi, 475 "ppb_attach(): this nexus %s hotplug slots\n", 476 ppb->hotplug_capable == B_TRUE ? "has":"has no"); 477 478 ppb_fm_init(ppb); 479 ddi_report_dev(devi); 480 481 return (DDI_SUCCESS); 482 483 case DDI_RESUME: 484 /* 485 * Get the soft state structure for the bridge. 486 */ 487 ppb = (ppb_devstate_t *) 488 ddi_get_soft_state(ppb_state, ddi_get_instance(devi)); 489 490 pci_pwr_resume(devi, ppb->ppb_pwr_p); 491 492 return (DDI_SUCCESS); 493 } 494 return (DDI_FAILURE); 495 } 496 497 /*ARGSUSED*/ 498 static int 499 ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 500 { 501 ppb_devstate_t *ppb; 502 503 switch (cmd) { 504 case DDI_DETACH: 505 /* 506 * And finally free the per-pci soft state after 507 * uninitializing hotplug support for this bus. 508 */ 509 ppb = (ppb_devstate_t *) 510 ddi_get_soft_state(ppb_state, ddi_get_instance(devi)); 511 512 ppb_fm_fini(ppb); 513 514 if (ppb->hotplug_capable == B_TRUE) 515 if (pcihp_uninit(devi) == DDI_FAILURE) 516 return (DDI_FAILURE); 517 else 518 ddi_remove_minor_node(devi, "devctl"); 519 520 (void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type"); 521 522 if (ppb->ppb_pwr_p != NULL) { 523 ppb_pwr_teardown(ppb, devi); 524 } 525 mutex_destroy(&ppb->ppb_mutex); 526 ddi_soft_state_free(ppb_state, ddi_get_instance(devi)); 527 528 return (DDI_SUCCESS); 529 530 case DDI_SUSPEND: 531 ppb = (ppb_devstate_t *) 532 ddi_get_soft_state(ppb_state, ddi_get_instance(devi)); 533 534 pci_pwr_suspend(devi, ppb->ppb_pwr_p); 535 536 return (DDI_SUCCESS); 537 } 538 return (DDI_FAILURE); 539 } 540 541 /*ARGSUSED*/ 542 static int 543 ppb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 544 off_t offset, off_t len, caddr_t *vaddrp) 545 { 546 register dev_info_t *pdip; 547 548 pdip = (dev_info_t *)DEVI(dip)->devi_parent; 549 return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map) 550 (pdip, rdip, mp, offset, len, vaddrp)); 551 } 552 553 /*ARGSUSED*/ 554 static int 555 ppb_ctlops(dev_info_t *dip, dev_info_t *rdip, 556 ddi_ctl_enum_t ctlop, void *arg, void *result) 557 { 558 pci_regspec_t *drv_regp; 559 int reglen; 560 int rn; 561 562 int totreg; 563 564 switch (ctlop) { 565 case DDI_CTLOPS_REPORTDEV: 566 if (rdip == (dev_info_t *)0) 567 return (DDI_FAILURE); 568 cmn_err(CE_CONT, "?PCI-device: %s@%s, %s%d\n", 569 ddi_node_name(rdip), ddi_get_name_addr(rdip), 570 ddi_driver_name(rdip), 571 ddi_get_instance(rdip)); 572 return (DDI_SUCCESS); 573 574 case DDI_CTLOPS_INITCHILD: 575 return (ppb_initchild((dev_info_t *)arg)); 576 577 case DDI_CTLOPS_UNINITCHILD: 578 ppb_removechild((dev_info_t *)arg); 579 return (DDI_SUCCESS); 580 581 case DDI_CTLOPS_SIDDEV: 582 return (DDI_SUCCESS); 583 584 case DDI_CTLOPS_REGSIZE: 585 case DDI_CTLOPS_NREGS: 586 if (rdip == (dev_info_t *)0) 587 return (DDI_FAILURE); 588 break; 589 default: 590 return (ddi_ctlops(dip, rdip, ctlop, arg, result)); 591 } 592 593 *(int *)result = 0; 594 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, 595 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg", 596 (caddr_t)&drv_regp, ®len) != DDI_SUCCESS) 597 return (DDI_FAILURE); 598 599 totreg = reglen / sizeof (pci_regspec_t); 600 if (ctlop == DDI_CTLOPS_NREGS) 601 *(int *)result = totreg; 602 else if (ctlop == DDI_CTLOPS_REGSIZE) { 603 rn = *(int *)arg; 604 if (rn >= totreg) { 605 kmem_free(drv_regp, reglen); 606 return (DDI_FAILURE); 607 } 608 *(off_t *)result = drv_regp[rn].pci_size_low | 609 ((uint64_t)drv_regp[rn].pci_size_hi << 32); 610 } 611 612 kmem_free(drv_regp, reglen); 613 return (DDI_SUCCESS); 614 } 615 616 617 static dev_info_t * 618 get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip) 619 { 620 dev_info_t *cdip = rdip; 621 622 for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip)) 623 ; 624 625 return (cdip); 626 } 627 628 629 static int 630 ppb_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 631 ddi_intr_handle_impl_t *hdlp, void *result) 632 { 633 dev_info_t *cdip = rdip; 634 pci_regspec_t *pci_rp; 635 int reglen, len; 636 uint32_t d, intr; 637 638 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED) 639 goto done; 640 641 /* 642 * If the interrupt-map property is defined at this 643 * node, it will have performed the interrupt 644 * translation as part of the property, so no 645 * rotation needs to be done. 646 */ 647 if (ddi_getproplen(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 648 "interrupt-map", &len) == DDI_PROP_SUCCESS) 649 goto done; 650 651 cdip = get_my_childs_dip(dip, rdip); 652 653 /* 654 * Use the devices reg property to determine its 655 * PCI bus number and device number. 656 */ 657 if (ddi_getlongprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 658 "reg", (caddr_t)&pci_rp, ®len) != DDI_SUCCESS) 659 return (DDI_FAILURE); 660 661 intr = hdlp->ih_vector; 662 663 /* Spin the interrupt */ 664 d = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi); 665 666 if ((intr >= PCI_INTA) && (intr <= PCI_INTD)) 667 hdlp->ih_vector = ((intr - 1 + (d % 4)) % 4 + 1); 668 else 669 cmn_err(CE_WARN, "%s%d: %s: PCI intr=%x out of range", 670 ddi_driver_name(rdip), ddi_get_instance(rdip), 671 ddi_driver_name(dip), intr); 672 673 kmem_free(pci_rp, reglen); 674 675 done: 676 /* Pass up the request to our parent. */ 677 return (i_ddi_intr_ops(dip, rdip, intr_op, hdlp, result)); 678 } 679 680 static int 681 ppb_bus_power(dev_info_t *dip, void *impl_arg, pm_bus_power_op_t op, 682 void *arg, void *result) 683 { 684 ppb_devstate_t *ppb; 685 686 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 687 ddi_get_instance(dip)); 688 689 return (pci_pwr_ops(ppb->ppb_pwr_p, dip, impl_arg, op, arg, result)); 690 } 691 692 693 /* 694 * name_child 695 * 696 * This function is called from init_child to name a node. It is 697 * also passed as a callback for node merging functions. 698 * 699 * return value: DDI_SUCCESS, DDI_FAILURE 700 */ 701 static int 702 ppb_name_child(dev_info_t *child, char *name, int namelen) 703 { 704 pci_regspec_t *pci_rp; 705 uint_t slot, func; 706 char **unit_addr; 707 uint_t n; 708 709 /* 710 * Pseudo nodes indicate a prototype node with per-instance 711 * properties to be merged into the real h/w device node. 712 * The interpretation of the unit-address is DD[,F] 713 * where DD is the device id and F is the function. 714 */ 715 if (ndi_dev_is_persistent_node(child) == 0) { 716 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child, 717 DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) != 718 DDI_PROP_SUCCESS) { 719 cmn_err(CE_WARN, "cannot name node from %s.conf", 720 ddi_driver_name(child)); 721 return (DDI_FAILURE); 722 } 723 if (n != 1 || *unit_addr == NULL || **unit_addr == 0) { 724 cmn_err(CE_WARN, "unit-address property in %s.conf" 725 " not well-formed", ddi_driver_name(child)); 726 ddi_prop_free(unit_addr); 727 return (DDI_FAILURE); 728 } 729 (void) snprintf(name, namelen, "%s", *unit_addr); 730 ddi_prop_free(unit_addr); 731 return (DDI_SUCCESS); 732 } 733 734 /* 735 * Get the address portion of the node name based on 736 * the function and device number. 737 */ 738 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 739 "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) { 740 return (DDI_FAILURE); 741 } 742 743 slot = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi); 744 func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi); 745 746 if (func != 0) 747 (void) snprintf(name, namelen, "%x,%x", slot, func); 748 else 749 (void) snprintf(name, namelen, "%x", slot); 750 751 ddi_prop_free(pci_rp); 752 return (DDI_SUCCESS); 753 } 754 755 static int 756 ppb_initchild(dev_info_t *child) 757 { 758 char name[MAXNAMELEN]; 759 ddi_acc_handle_t config_handle; 760 ushort_t command_preserve, command; 761 uint_t n; 762 ushort_t bcr; 763 uchar_t header_type; 764 uchar_t min_gnt, latency_timer; 765 ppb_devstate_t *ppb; 766 767 /* 768 * Name the child 769 */ 770 if (ppb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS) 771 return (DDI_FAILURE); 772 773 ddi_set_name_addr(child, name); 774 ddi_set_parent_data(child, NULL); 775 776 /* 777 * Pseudo nodes indicate a prototype node with per-instance 778 * properties to be merged into the real h/w device node. 779 * The interpretation of the unit-address is DD[,F] 780 * where DD is the device id and F is the function. 781 */ 782 if (ndi_dev_is_persistent_node(child) == 0) { 783 extern int pci_allow_pseudo_children; 784 785 /* 786 * Try to merge the properties from this prototype 787 * node into real h/w nodes. 788 */ 789 if (ndi_merge_node(child, ppb_name_child) == DDI_SUCCESS) { 790 /* 791 * Merged ok - return failure to remove the node. 792 */ 793 ppb_removechild(child); 794 return (DDI_FAILURE); 795 } 796 797 /* workaround for ddivs to run under PCI */ 798 if (pci_allow_pseudo_children) 799 return (DDI_SUCCESS); 800 801 /* 802 * The child was not merged into a h/w node, 803 * but there's not much we can do with it other 804 * than return failure to cause the node to be removed. 805 */ 806 cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged", 807 ddi_driver_name(child), ddi_get_name_addr(child), 808 ddi_driver_name(child)); 809 ppb_removechild(child); 810 return (DDI_NOT_WELL_FORMED); 811 } 812 813 ddi_set_parent_data(child, NULL); 814 815 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 816 ddi_get_instance(ddi_get_parent(child))); 817 818 /* 819 * If hardware is PM capable, set up the power info structure. 820 * This also ensures the the bus will not be off (0MHz) otherwise 821 * system panics during a bus access. 822 */ 823 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 824 /* 825 * Create a pwr_info struct for child. Bus will be 826 * at full speed after creating info. 827 */ 828 pci_pwr_create_info(ppb->ppb_pwr_p, child); 829 #ifdef DEBUG 830 ASSERT(ppb->ppb_pwr_p->current_lvl == PM_LEVEL_B0); 831 #endif 832 } 833 834 /* 835 * If configuration registers were previously saved by 836 * child (before it entered D3), then let the child do the 837 * restore to set up the config regs as it'll first need to 838 * power the device out of D3. 839 */ 840 if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 841 "config-regs-saved-by-child") == 1) { 842 DEBUG2(DBG_PWR, ddi_get_parent(child), 843 "INITCHILD: config regs to be restored by child" 844 " for %s@%s\n", ddi_node_name(child), 845 ddi_get_name_addr(child)); 846 847 return (DDI_SUCCESS); 848 } 849 850 DEBUG2(DBG_PWR, ddi_get_parent(child), 851 "INITCHILD: config regs setup for %s@%s\n", 852 ddi_node_name(child), ddi_get_name_addr(child)); 853 854 if (pci_config_setup(child, &config_handle) != DDI_SUCCESS) { 855 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 856 pci_pwr_rm_info(ppb->ppb_pwr_p, child); 857 } 858 859 return (DDI_FAILURE); 860 } 861 862 /* 863 * Determine the configuration header type. 864 */ 865 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 866 867 /* 868 * Support for the "command-preserve" property. 869 */ 870 command_preserve = ddi_prop_get_int(DDI_DEV_T_ANY, child, 871 DDI_PROP_DONTPASS, "command-preserve", 0); 872 command = pci_config_get16(config_handle, PCI_CONF_COMM); 873 command &= (command_preserve | PCI_COMM_BACK2BACK_ENAB); 874 command |= (ppb_command_default & ~command_preserve); 875 pci_config_put16(config_handle, PCI_CONF_COMM, command); 876 877 /* 878 * If the device has a bus control register then program it 879 * based on the settings in the command register. 880 */ 881 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) { 882 bcr = pci_config_get8(config_handle, PCI_BCNF_BCNTRL); 883 if (ppb_command_default & PCI_COMM_PARITY_DETECT) 884 bcr |= PCI_BCNF_BCNTRL_PARITY_ENABLE; 885 if (ppb_command_default & PCI_COMM_SERR_ENABLE) 886 bcr |= PCI_BCNF_BCNTRL_SERR_ENABLE; 887 bcr |= PCI_BCNF_BCNTRL_MAST_AB_MODE; 888 pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr); 889 } 890 891 /* 892 * Initialize cache-line-size configuration register if needed. 893 */ 894 if (ppb_set_cache_line_size_register && 895 ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 896 "cache-line-size", 0) == 0) { 897 pci_config_put8(config_handle, PCI_CONF_CACHE_LINESZ, 898 ppb->ppb_cache_line_size); 899 n = pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ); 900 if (n != 0) { 901 (void) ndi_prop_update_int(DDI_DEV_T_NONE, child, 902 "cache-line-size", n); 903 } 904 } 905 906 /* 907 * Initialize latency timer configuration registers if needed. 908 */ 909 if (ppb_set_latency_timer_register && 910 ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 911 "latency-timer", 0) == 0) { 912 913 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) { 914 latency_timer = ppb->ppb_latency_timer; 915 pci_config_put8(config_handle, PCI_BCNF_LATENCY_TIMER, 916 ppb->ppb_latency_timer); 917 } else { 918 min_gnt = pci_config_get8(config_handle, 919 PCI_CONF_MIN_G); 920 latency_timer = min_gnt * 8; 921 } 922 pci_config_put8(config_handle, PCI_CONF_LATENCY_TIMER, 923 latency_timer); 924 n = pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER); 925 if (n != 0) { 926 (void) ndi_prop_update_int(DDI_DEV_T_NONE, child, 927 "latency-timer", n); 928 } 929 } 930 931 /* 932 * Check to see if the XMITS/PCI-X workaround applies. 933 */ 934 n = ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_NOTPROM, 935 "pcix-update-cmd-reg", -1); 936 937 if (n != -1) { 938 extern void pcix_set_cmd_reg(dev_info_t *child, uint16_t value); 939 DEBUG1(DBG_INIT_CLD, child, "Turning on XMITS NCPQ " 940 "Workaround: value = %x\n", n); 941 pcix_set_cmd_reg(child, n); 942 } 943 944 pci_config_teardown(&config_handle); 945 946 return (DDI_SUCCESS); 947 } 948 949 static void 950 ppb_removechild(dev_info_t *dip) 951 { 952 ppb_devstate_t *ppb; 953 954 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 955 ddi_get_instance(ddi_get_parent(dip))); 956 957 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 958 959 DEBUG2(DBG_PWR, ddi_get_parent(dip), 960 "UNINITCHILD: removing pwr_info for %s@%s\n", 961 ddi_node_name(dip), ddi_get_name_addr(dip)); 962 pci_pwr_rm_info(ppb->ppb_pwr_p, dip); 963 } 964 965 ddi_set_name_addr(dip, NULL); 966 967 /* 968 * Strip the node to properly convert it back to prototype form 969 */ 970 ddi_remove_minor_node(dip, NULL); 971 972 impl_rem_dev_props(dip); 973 } 974 975 /* 976 * If bridge is PM capable, set up PM state for nexus. 977 */ 978 static void 979 ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *pdip) 980 { 981 char *comp_array[5]; 982 int i; 983 ddi_acc_handle_t conf_hdl; 984 uint8_t cap_ptr; 985 uint8_t cap_id; 986 uint8_t pmcsr_bse; 987 uint16_t pmcap; 988 989 /* 990 * Determine if bridge is PM capable. If not, leave ppb_pwr_p NULL 991 * and return. 992 */ 993 994 if (pci_config_setup(pdip, &ppb->ppb_conf_hdl) != DDI_SUCCESS) { 995 996 return; 997 } 998 999 conf_hdl = ppb->ppb_conf_hdl; 1000 1001 cap_ptr = pci_config_get8(conf_hdl, PCI_BCNF_CAP_PTR); 1002 1003 /* 1004 * Walk the capabilities searching for a PM entry. 1005 */ 1006 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) { 1007 cap_id = pci_config_get8(conf_hdl, 1008 cap_ptr + PCI_CAP_ID); 1009 if (cap_id == PCI_CAP_ID_PM) { 1010 break; 1011 } 1012 cap_ptr = pci_config_get8(conf_hdl, 1013 cap_ptr + PCI_CAP_NEXT_PTR); 1014 } 1015 1016 if (cap_ptr == 0) { 1017 DEBUG0(DBG_PWR, pdip, "bridge does not support PM. PCI" 1018 " PM data structure not found in config header\n"); 1019 pci_config_teardown(&conf_hdl); 1020 1021 return; 1022 } 1023 1024 /* 1025 * Allocate PM state structure for ppb. 1026 */ 1027 ppb->ppb_pwr_p = (pci_pwr_t *) 1028 kmem_zalloc(sizeof (pci_pwr_t), KM_SLEEP); 1029 ppb->ppb_pwr_p->pwr_fp = 0; 1030 1031 /* 1032 * Save offset to pmcsr for future references. 1033 */ 1034 ppb->ppb_pmcsr_offset = cap_ptr + PCI_PMCSR; 1035 1036 pmcsr_bse = pci_config_get8(conf_hdl, cap_ptr + PCI_PMCSR_BSE); 1037 1038 pmcap = pci_config_get16(conf_hdl, cap_ptr + PCI_PMCAP); 1039 1040 if (pmcap & PCI_PMCAP_D1) { 1041 DEBUG0(DBG_PWR, pdip, "setup: B1 state supported\n"); 1042 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B1_CAPABLE; 1043 } else { 1044 DEBUG0(DBG_PWR, pdip, "setup: B1 state NOT supported\n"); 1045 } 1046 if (pmcap & PCI_PMCAP_D2) { 1047 DEBUG0(DBG_PWR, pdip, "setup: B2 state supported\n"); 1048 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B2_CAPABLE; 1049 } else { 1050 DEBUG0(DBG_PWR, pdip, "setup: B2 via D2 NOT supported\n"); 1051 } 1052 1053 if (pmcsr_bse & PCI_PMCSR_BSE_BPCC_EN) { 1054 DEBUG0(DBG_PWR, pdip, 1055 "setup: bridge power/clock control enable\n"); 1056 } else { 1057 DEBUG0(DBG_PWR, pdip, 1058 "setup: bridge power/clock control disabled\n"); 1059 1060 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1061 ppb->ppb_pwr_p = NULL; 1062 pci_config_teardown(&conf_hdl); 1063 1064 return; 1065 } 1066 1067 /* 1068 * PCI states D0 and D3 always are supported for normal PCI 1069 * devices. D1 and D2 are optional which are checked for above. 1070 * Bridge function states D0-D3 correspond to secondary bus states 1071 * B0-B3, EXCEPT if PCI_PMCSR_BSE_B2_B3 is set. In this case, setting 1072 * the bridge function to D3 will set the bridge bus to state B2 instead 1073 * of B3. D2 will not correspond to B2 (and in fact, probably 1074 * won't be D2 capable). Implicitly, this means that if 1075 * PCI_PMCSR_BSE_B2_B3 is set, the bus will not be B3 capable. 1076 */ 1077 if (pmcsr_bse & PCI_PMCSR_BSE_B2_B3) { 1078 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B2_CAPABLE; 1079 DEBUG0(DBG_PWR, pdip, "B2 supported via D3\n"); 1080 } else { 1081 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B3_CAPABLE; 1082 DEBUG0(DBG_PWR, pdip, "B3 supported via D3\n"); 1083 } 1084 1085 ppb->ppb_pwr_p->pwr_dip = pdip; 1086 mutex_init(&ppb->ppb_pwr_p->pwr_mutex, NULL, MUTEX_DRIVER, NULL); 1087 1088 i = 0; 1089 comp_array[i++] = "NAME=PCI bridge PM"; 1090 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) { 1091 comp_array[i++] = "0=Clock/Power Off (B3)"; 1092 } 1093 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B2_CAPABLE) { 1094 comp_array[i++] = "1=Clock Off (B2)"; 1095 } 1096 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B1_CAPABLE) { 1097 comp_array[i++] = "2=Bus Inactive (B1)"; 1098 } 1099 comp_array[i++] = "3=Full Power (B0)"; 1100 1101 /* 1102 * Create pm-components property. It does not already exist. 1103 */ 1104 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, pdip, 1105 "pm-components", comp_array, i) != DDI_PROP_SUCCESS) { 1106 cmn_err(CE_WARN, 1107 "%s%d pm-components prop update failed", 1108 ddi_driver_name(pdip), ddi_get_instance(pdip)); 1109 pci_config_teardown(&conf_hdl); 1110 mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex); 1111 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1112 ppb->ppb_pwr_p = NULL; 1113 1114 return; 1115 } 1116 1117 if (ddi_prop_create(DDI_DEV_T_NONE, pdip, DDI_PROP_CANSLEEP, 1118 "pm-want-child-notification?", NULL, NULL) != DDI_PROP_SUCCESS) { 1119 cmn_err(CE_WARN, 1120 "%s%d fail to create pm-want-child-notification? prop", 1121 ddi_driver_name(pdip), ddi_get_instance(pdip)); 1122 1123 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, "pm-components"); 1124 pci_config_teardown(&conf_hdl); 1125 mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex); 1126 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1127 ppb->ppb_pwr_p = NULL; 1128 1129 return; 1130 } 1131 1132 ppb->ppb_pwr_p->current_lvl = 1133 pci_pwr_current_lvl(ppb->ppb_pwr_p); 1134 } 1135 1136 /* 1137 * Remove PM state for nexus. 1138 */ 1139 static void 1140 ppb_pwr_teardown(ppb_devstate_t *ppb, dev_info_t *dip) 1141 { 1142 int low_lvl; 1143 1144 /* 1145 * Determine the lowest power level supported. 1146 */ 1147 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) { 1148 low_lvl = PM_LEVEL_B3; 1149 } else { 1150 low_lvl = PM_LEVEL_B2; 1151 } 1152 1153 if (pm_lower_power(dip, PCI_PM_COMP_0, low_lvl) != DDI_SUCCESS) { 1154 cmn_err(CE_WARN, "%s%d failed to lower power", 1155 ddi_driver_name(dip), ddi_get_instance(dip)); 1156 } 1157 1158 pci_config_teardown(&ppb->ppb_conf_hdl); 1159 mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex); 1160 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1161 1162 if (ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components") != 1163 DDI_PROP_SUCCESS) { 1164 cmn_err(CE_WARN, "%s%d unable to remove prop pm-components", 1165 ddi_driver_name(dip), ddi_get_instance(dip)); 1166 } 1167 1168 if (ddi_prop_remove(DDI_DEV_T_NONE, dip, 1169 "pm-want-child-notification?") != DDI_PROP_SUCCESS) { 1170 cmn_err(CE_WARN, 1171 "%s%d unable to remove prop pm-want_child_notification?", 1172 ddi_driver_name(dip), ddi_get_instance(dip)); 1173 } 1174 } 1175 1176 /* 1177 * Examine the pmcsr register and return the software defined 1178 * state (the difference being whether D3 means B2 or B3). 1179 */ 1180 int 1181 pci_pwr_current_lvl(pci_pwr_t *pwr_p) 1182 { 1183 ppb_devstate_t *ppb; 1184 uint16_t pmcsr; 1185 1186 /* 1187 * Find out current power level 1188 */ 1189 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1190 ddi_get_instance(pwr_p->pwr_dip)); 1191 1192 pmcsr = pci_config_get16(ppb->ppb_conf_hdl, 1193 ppb->ppb_pmcsr_offset); 1194 1195 switch (pmcsr & PCI_PMCSR_STATE_MASK) { 1196 case PCI_PMCSR_D0: 1197 1198 return (PM_LEVEL_B0); 1199 case PCI_PMCSR_D1: 1200 1201 return (PM_LEVEL_B1); 1202 case PCI_PMCSR_D2: 1203 1204 return (PM_LEVEL_B2); 1205 case PCI_PMCSR_D3HOT: 1206 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) { 1207 1208 return (PM_LEVEL_B2); 1209 } else { 1210 1211 return (PM_LEVEL_B3); 1212 } 1213 } 1214 /*NOTREACHED*/ 1215 } 1216 1217 /* 1218 * Power entry point. Called by the PM framework to change the 1219 * current power state of the bus. This function must first verify that 1220 * the requested power change is still valid. 1221 */ 1222 /*ARGSUSED*/ 1223 static int 1224 ppb_pwr(dev_info_t *dip, int component, int lvl) 1225 { 1226 ppb_devstate_t *ppb; 1227 uint16_t pmcsr; 1228 char *str; 1229 int lowest_lvl; 1230 int old_lvl; 1231 int new_lvl; 1232 1233 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1234 ddi_get_instance(dip)); 1235 if (ppb == NULL) { 1236 cmn_err(CE_WARN, "%s%d ppb_pwr: can't get soft state", 1237 ddi_driver_name(dip), ddi_get_instance(dip)); 1238 1239 return (DDI_FAILURE); 1240 } 1241 1242 DEBUG1(DBG_PWR, dip, "ppb_pwr(): ENTER level = %d\n", lvl); 1243 1244 mutex_enter(&ppb->ppb_pwr_p->pwr_mutex); 1245 1246 /* 1247 * Find out if the power setting is possible. If it is not, 1248 * set component busy and return failure. If it is possible, 1249 * and it is the lowest pwr setting possible, set component 1250 * busy so that the framework does not try to lower any further. 1251 */ 1252 lowest_lvl = pci_pwr_new_lvl(ppb->ppb_pwr_p); 1253 if (lowest_lvl > lvl) { 1254 pci_pwr_component_busy(ppb->ppb_pwr_p); 1255 DEBUG2(DBG_PWR, dip, "ppb_pwr: failing power request " 1256 "lowest allowed is %d requested is %d\n", 1257 lowest_lvl, lvl); 1258 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1259 1260 return (DDI_FAILURE); 1261 } else if (lowest_lvl == lvl) { 1262 pci_pwr_component_busy(ppb->ppb_pwr_p); 1263 } else { 1264 pci_pwr_component_idle(ppb->ppb_pwr_p); 1265 } 1266 1267 pmcsr = pci_config_get16(ppb->ppb_conf_hdl, ppb->ppb_pmcsr_offset); 1268 1269 /* 1270 * Save the current power level. This is the actual function level, 1271 * not the translated bridge level stored in pwr_p->current_lvl 1272 */ 1273 old_lvl = pmcsr & PCI_PMCSR_STATE_MASK; 1274 1275 pmcsr &= ~PCI_PMCSR_STATE_MASK; 1276 switch (lvl) { 1277 case PM_LEVEL_B0: 1278 str = "PM_LEVEL_B0 (full speed)"; 1279 pmcsr |= PCI_PMCSR_D0; 1280 break; 1281 case PM_LEVEL_B1: 1282 str = "PM_LEVEL_B1 (light sleep. No bus traffic allowed)"; 1283 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B1_CAPABLE) == 0) { 1284 cmn_err(CE_WARN, "%s%d PCI PM state B1 not supported", 1285 ddi_driver_name(dip), ddi_get_instance(dip)); 1286 1287 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1288 return (DDI_FAILURE); 1289 } 1290 pmcsr |= PCI_PMCSR_D1; 1291 break; 1292 case PM_LEVEL_B2: 1293 str = "PM_LEVEL_B2 (clock off)"; 1294 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B2_CAPABLE) == 0) { 1295 cmn_err(CE_WARN, "%s%d PM state B2 not supported...", 1296 ddi_driver_name(dip), 1297 ddi_get_instance(dip)); 1298 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1299 1300 return (DDI_FAILURE); 1301 } 1302 1303 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) { 1304 /* 1305 * If B3 isn't supported, use D3 for B2 to avoid the 1306 * possible case that D2 for B2 isn't supported. 1307 * Saves and extra check and state flag.. 1308 */ 1309 pmcsr |= PCI_PMCSR_D3HOT; 1310 } else { 1311 pmcsr |= PCI_PMCSR_D2; 1312 } 1313 break; 1314 case PM_LEVEL_B3: 1315 str = "PM_LEVEL_B30 (clock and power off)"; 1316 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) { 1317 cmn_err(CE_WARN, "%s%d PM state B3 not supported...", 1318 ddi_driver_name(dip), 1319 ddi_get_instance(dip)); 1320 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1321 1322 return (DDI_FAILURE); 1323 } 1324 pmcsr |= PCI_PMCSR_D3HOT; 1325 1326 break; 1327 1328 default: 1329 cmn_err(CE_WARN, "%s%d Unknown PM state %d", 1330 ddi_driver_name(dip), ddi_get_instance(dip), lvl); 1331 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1332 1333 return (DDI_FAILURE); 1334 } 1335 1336 new_lvl = pmcsr & PCI_PMCSR_STATE_MASK; 1337 1338 /* 1339 * Save config regs if going into HW state D3 (B2 or B3) 1340 */ 1341 if ((old_lvl != PCI_PMCSR_D3HOT) && (new_lvl == PCI_PMCSR_D3HOT)) { 1342 DEBUG0(DBG_PWR, dip, "ppb_pwr(): SAVING CONFIG REGS\n"); 1343 if (pci_save_config_regs(dip) != DDI_SUCCESS) { 1344 cmn_err(CE_WARN, "%s%d Save config regs failed", 1345 ddi_driver_name(dip), ddi_get_instance(dip)); 1346 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1347 1348 return (DDI_FAILURE); 1349 } 1350 } 1351 1352 pci_config_put16(ppb->ppb_conf_hdl, ppb->ppb_pmcsr_offset, pmcsr); 1353 1354 /* 1355 * No bus transactions should occur without waiting for 1356 * settle time specified in PCI PM spec rev 2.1 sec 5.6.1 1357 * To make things simple, just use the max time specified for 1358 * all state transitions. 1359 */ 1360 delay(drv_usectohz(PCI_CLK_SETTLE_TIME)); 1361 1362 /* 1363 * Restore configuration registers if coming out of HW state D3 1364 */ 1365 if ((old_lvl == PCI_PMCSR_D3HOT) && (new_lvl != PCI_PMCSR_D3HOT)) { 1366 DEBUG0(DBG_PWR, dip, "ppb_pwr(): RESTORING CONFIG REGS\n"); 1367 if (pci_restore_config_regs(dip) != DDI_SUCCESS) { 1368 panic("%s%d restore config regs failed", 1369 ddi_driver_name(dip), ddi_get_instance(dip)); 1370 } 1371 /*NOTREACHED*/ 1372 } 1373 1374 ppb->ppb_pwr_p->current_lvl = lvl; 1375 1376 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1377 1378 DEBUG1(DBG_PWR, dip, "ppb_set_pwr: set PM state to %s\n\n", str); 1379 1380 return (DDI_SUCCESS); 1381 } 1382 1383 /* 1384 * Initialize hotplug framework if we are hotpluggable. 1385 * Sets flag in the soft state if Hot Plug is supported and initialized 1386 * properly. 1387 */ 1388 /*ARGSUSED*/ 1389 static void 1390 ppb_init_hotplug(ppb_devstate_t *ppb) 1391 { 1392 if (ddi_prop_exists(DDI_DEV_T_ANY, ppb->dip, DDI_PROP_DONTPASS, 1393 "hotplug-capable")) { 1394 (void) modload("misc", "pcihp"); 1395 1396 if (pcihp_init(ppb->dip) != DDI_SUCCESS) { 1397 cmn_err(CE_WARN, 1398 "%s #%d: Failed setting hotplug framework", 1399 ddi_driver_name(ppb->dip), 1400 ddi_get_instance(ppb->dip)); 1401 } else 1402 ppb->hotplug_capable = B_TRUE; 1403 } 1404 1405 } 1406 1407 static void 1408 ppb_create_ranges_prop(dev_info_t *dip, 1409 ddi_acc_handle_t config_handle) 1410 { 1411 uint32_t base, limit; 1412 ppb_ranges_t ranges[PPB_RANGE_LEN]; 1413 uint8_t io_base_lo, io_limit_lo; 1414 uint16_t io_base_hi, io_limit_hi, mem_base, mem_limit; 1415 int i = 0, rangelen = sizeof (ppb_ranges_t)/sizeof (int); 1416 1417 io_base_lo = pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW); 1418 io_limit_lo = pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW); 1419 io_base_hi = pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI); 1420 io_limit_hi = pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI); 1421 mem_base = pci_config_get16(config_handle, PCI_BCNF_MEM_BASE); 1422 mem_limit = pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT); 1423 1424 /* 1425 * Create ranges for IO space 1426 */ 1427 ranges[i].size_low = ranges[i].size_high = 0; 1428 ranges[i].parent_mid = ranges[i].child_mid = 1429 ranges[i].parent_high = 0; 1430 ranges[i].child_high = ranges[i].parent_high |= 1431 (PCI_REG_REL_M | PCI_ADDR_IO); 1432 base = PPB_16bit_IOADDR(io_base_lo); 1433 limit = PPB_16bit_IOADDR(io_limit_lo); 1434 1435 if ((io_base_lo & 0xf) == PPB_32BIT_IO) { 1436 base = PPB_LADDR(base, io_base_hi); 1437 } 1438 if ((io_limit_lo & 0xf) == PPB_32BIT_IO) { 1439 limit = PPB_LADDR(limit, io_limit_hi); 1440 } 1441 1442 if ((io_base_lo & PPB_32BIT_IO) && (io_limit_hi > 0)) { 1443 base = PPB_LADDR(base, io_base_hi); 1444 limit = PPB_LADDR(limit, io_limit_hi); 1445 } 1446 1447 /* 1448 * Create ranges for 32bit memory space 1449 */ 1450 base = PPB_32bit_MEMADDR(mem_base); 1451 limit = PPB_32bit_MEMADDR(mem_limit); 1452 ranges[i].size_low = ranges[i].size_high = 0; 1453 ranges[i].parent_mid = ranges[i].child_mid = 1454 ranges[i].parent_high = 0; 1455 ranges[i].child_high = ranges[i].parent_high |= 1456 (PCI_REG_REL_M | PCI_ADDR_MEM32); 1457 ranges[i].child_low = ranges[i].parent_low = base; 1458 if (limit >= base) { 1459 ranges[i].size_low = limit - base + PPB_MEMGRAIN; 1460 i++; 1461 } 1462 1463 if (i) { 1464 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "ranges", 1465 (int *)ranges, i * rangelen); 1466 } 1467 } 1468 1469 /* ARGSUSED */ 1470 static int 1471 ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp) 1472 { 1473 ppb_devstate_t *ppb_p; 1474 minor_t minor = getminor(*devp); 1475 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1476 1477 /* 1478 * Make sure the open is for the right file type. 1479 */ 1480 if (otyp != OTYP_CHR) 1481 return (EINVAL); 1482 1483 /* 1484 * Get the soft state structure for the device. 1485 */ 1486 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1487 instance); 1488 1489 if (ppb_p == NULL) 1490 return (ENXIO); 1491 1492 if (ppb_p->hotplug_capable == B_TRUE) 1493 return ((pcihp_get_cb_ops())->cb_open(devp, flags, 1494 otyp, credp)); 1495 1496 /* 1497 * Handle the open by tracking the device state. 1498 */ 1499 mutex_enter(&ppb_p->ppb_mutex); 1500 if (flags & FEXCL) { 1501 if (ppb_p->ppb_soft_state != PPB_SOFT_STATE_CLOSED) { 1502 mutex_exit(&ppb_p->ppb_mutex); 1503 return (EBUSY); 1504 } 1505 ppb_p->ppb_soft_state = PPB_SOFT_STATE_OPEN_EXCL; 1506 } else { 1507 if (ppb_p->ppb_soft_state == PPB_SOFT_STATE_OPEN_EXCL) { 1508 mutex_exit(&ppb_p->ppb_mutex); 1509 return (EBUSY); 1510 } 1511 ppb_p->ppb_soft_state = PPB_SOFT_STATE_OPEN; 1512 } 1513 mutex_exit(&ppb_p->ppb_mutex); 1514 return (0); 1515 } 1516 1517 1518 /* ARGSUSED */ 1519 static int 1520 ppb_close(dev_t dev, int flags, int otyp, cred_t *credp) 1521 { 1522 ppb_devstate_t *ppb_p; 1523 minor_t minor = getminor(dev); 1524 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1525 1526 if (otyp != OTYP_CHR) 1527 return (EINVAL); 1528 1529 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1530 instance); 1531 1532 if (ppb_p == NULL) 1533 return (ENXIO); 1534 1535 if (ppb_p->hotplug_capable == B_TRUE) 1536 return ((pcihp_get_cb_ops())->cb_close(dev, flags, 1537 otyp, credp)); 1538 1539 mutex_enter(&ppb_p->ppb_mutex); 1540 ppb_p->ppb_soft_state = PPB_SOFT_STATE_CLOSED; 1541 mutex_exit(&ppb_p->ppb_mutex); 1542 return (0); 1543 } 1544 1545 1546 /* 1547 * ppb_ioctl: devctl hotplug controls 1548 */ 1549 /* ARGSUSED */ 1550 static int 1551 ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 1552 int *rvalp) 1553 { 1554 ppb_devstate_t *ppb_p; 1555 dev_info_t *self; 1556 struct devctl_iocdata *dcp; 1557 uint_t bus_state; 1558 int rv = 0; 1559 minor_t minor = getminor(dev); 1560 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1561 1562 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1563 instance); 1564 1565 if (ppb_p == NULL) 1566 return (ENXIO); 1567 1568 if (ppb_p->hotplug_capable == B_TRUE) 1569 return ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd, 1570 arg, mode, credp, rvalp)); 1571 1572 self = ppb_p->dip; 1573 1574 /* 1575 * We can use the generic implementation for these ioctls 1576 */ 1577 switch (cmd) { 1578 case DEVCTL_DEVICE_GETSTATE: 1579 case DEVCTL_DEVICE_ONLINE: 1580 case DEVCTL_DEVICE_OFFLINE: 1581 case DEVCTL_BUS_GETSTATE: 1582 return (ndi_devctl_ioctl(self, cmd, arg, mode, 0)); 1583 } 1584 1585 /* 1586 * read devctl ioctl data 1587 */ 1588 if (ndi_dc_allochdl((void *)arg, &dcp) != NDI_SUCCESS) 1589 return (EFAULT); 1590 1591 switch (cmd) { 1592 1593 case DEVCTL_DEVICE_RESET: 1594 rv = ENOTSUP; 1595 break; 1596 1597 case DEVCTL_BUS_QUIESCE: 1598 if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS) 1599 if (bus_state == BUS_QUIESCED) 1600 break; 1601 (void) ndi_set_bus_state(self, BUS_QUIESCED); 1602 break; 1603 1604 case DEVCTL_BUS_UNQUIESCE: 1605 if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS) 1606 if (bus_state == BUS_ACTIVE) 1607 break; 1608 (void) ndi_set_bus_state(self, BUS_ACTIVE); 1609 break; 1610 1611 case DEVCTL_BUS_RESET: 1612 rv = ENOTSUP; 1613 break; 1614 1615 case DEVCTL_BUS_RESETALL: 1616 rv = ENOTSUP; 1617 break; 1618 1619 default: 1620 rv = ENOTTY; 1621 } 1622 1623 ndi_dc_freehdl(dcp); 1624 return (rv); 1625 } 1626 1627 static int ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 1628 int flags, char *name, caddr_t valuep, int *lengthp) 1629 { 1630 ppb_devstate_t *ppb_p; 1631 minor_t minor = getminor(dev); 1632 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1633 1634 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1635 instance); 1636 1637 if (ppb_p == NULL) 1638 return (ENXIO); 1639 1640 if (ppb_p->hotplug_capable == B_TRUE) 1641 return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip, prop_op, 1642 flags, name, valuep, lengthp)); 1643 1644 return (ddi_prop_op(dev, dip, prop_op, flags, name, valuep, lengthp)); 1645 } 1646 1647 /* 1648 * Initialize our FMA resources 1649 */ 1650 static void 1651 ppb_fm_init(ppb_devstate_t *ppb_p) 1652 { 1653 ddi_fm_error_t derr; 1654 1655 ppb_p->fm_cap = DDI_FM_EREPORT_CAPABLE | DDI_FM_ERRCB_CAPABLE | 1656 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE; 1657 1658 /* 1659 * Request our capability level and get our parents capability 1660 * and ibc. 1661 */ 1662 ddi_fm_init(ppb_p->dip, &ppb_p->fm_cap, &ppb_p->fm_ibc); 1663 ASSERT((ppb_p->fm_cap & DDI_FM_EREPORT_CAPABLE) && 1664 (ppb_p->fm_cap & DDI_FM_ERRCB_CAPABLE)); 1665 1666 pci_ereport_setup(ppb_p->dip); 1667 1668 /* 1669 * clear any outstanding error bits 1670 */ 1671 bzero(&derr, sizeof (ddi_fm_error_t)); 1672 derr.fme_version = DDI_FME_VERSION; 1673 derr.fme_flag = DDI_FM_ERR_EXPECTED; 1674 pci_ereport_post(ppb_p->dip, &derr, NULL); 1675 pci_bdg_ereport_post(ppb_p->dip, &derr, NULL); 1676 1677 /* 1678 * Register error callback with our parent. 1679 */ 1680 ddi_fm_handler_register(ppb_p->dip, ppb_err_callback, NULL); 1681 } 1682 1683 /* 1684 * Breakdown our FMA resources 1685 */ 1686 static void 1687 ppb_fm_fini(ppb_devstate_t *ppb_p) 1688 { 1689 /* 1690 * Clean up allocated fm structures 1691 */ 1692 ddi_fm_handler_unregister(ppb_p->dip); 1693 pci_ereport_teardown(ppb_p->dip); 1694 ddi_fm_fini(ppb_p->dip); 1695 } 1696 1697 /* 1698 * Initialize FMA resources for children devices. Called when 1699 * child calls ddi_fm_init(). 1700 */ 1701 /*ARGSUSED*/ 1702 static int 1703 ppb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap, 1704 ddi_iblock_cookie_t *ibc) 1705 { 1706 ppb_devstate_t *ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1707 ddi_get_instance(dip)); 1708 *ibc = ppb_p->fm_ibc; 1709 return (ppb_p->fm_cap); 1710 } 1711 1712 /* 1713 * FMA registered error callback 1714 */ 1715 static int 1716 ppb_err_callback(dev_info_t *dip, ddi_fm_error_t *derr, const void *impl_data) 1717 { 1718 uint16_t pci_cfg_stat, pci_cfg_sec_stat; 1719 1720 ASSERT(impl_data == NULL); 1721 pci_ereport_post(dip, derr, &pci_cfg_stat); 1722 pci_bdg_ereport_post(dip, derr, &pci_cfg_sec_stat); 1723 return (pci_bdg_check_status(dip, derr, pci_cfg_stat, 1724 pci_cfg_sec_stat)); 1725 } 1726 1727 static void 1728 ppb_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle) 1729 { 1730 i_ndi_busop_access_enter(dip, handle); 1731 } 1732 1733 /* ARGSUSED */ 1734 static void 1735 ppb_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle) 1736 { 1737 i_ndi_busop_access_exit(dip, handle); 1738 } 1739