xref: /titanic_52/usr/src/uts/sun4u/io/opl_cfg.c (revision c2580b931007758eab8cb5ae8726ebe1588e259b)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 #include <sys/conf.h>
29 #include <sys/kmem.h>
30 #include <sys/debug.h>
31 #include <sys/modctl.h>
32 #include <sys/autoconf.h>
33 #include <sys/hwconf.h>
34 #include <sys/ddi_impldefs.h>
35 #include <sys/ddi.h>
36 #include <sys/sunddi.h>
37 #include <sys/sunndi.h>
38 #include <sys/ndi_impldefs.h>
39 #include <sys/machsystm.h>
40 #include <sys/fcode.h>
41 #include <sys/promif.h>
42 #include <sys/promimpl.h>
43 #include <sys/opl_cfg.h>
44 #include <sys/scfd/scfostoescf.h>
45 
46 static unsigned int		opl_cfg_inited;
47 static opl_board_cfg_t		opl_boards[HWD_SBS_PER_DOMAIN];
48 
49 /*
50  * Module control operations
51  */
52 
53 extern struct mod_ops mod_miscops;
54 
55 static struct modlmisc modlmisc = {
56 	&mod_miscops,				/* Type of module */
57 	"OPL opl_cfg %I%"
58 };
59 
60 static struct modlinkage modlinkage = {
61 	MODREV_1, (void *)&modlmisc, NULL
62 };
63 
64 static int	opl_map_in(dev_info_t *, fco_handle_t, fc_ci_t *);
65 static int	opl_map_out(dev_info_t *, fco_handle_t, fc_ci_t *);
66 static int	opl_register_fetch(dev_info_t *, fco_handle_t, fc_ci_t *);
67 static int	opl_register_store(dev_info_t *, fco_handle_t, fc_ci_t *);
68 
69 static int	opl_claim_memory(dev_info_t *, fco_handle_t, fc_ci_t *);
70 static int	opl_release_memory(dev_info_t *, fco_handle_t, fc_ci_t *);
71 static int	opl_vtop(dev_info_t *, fco_handle_t, fc_ci_t *);
72 
73 static int	opl_config_child(dev_info_t *, fco_handle_t, fc_ci_t *);
74 
75 static int	opl_get_fcode_size(dev_info_t *, fco_handle_t, fc_ci_t *);
76 static int	opl_get_fcode(dev_info_t *, fco_handle_t, fc_ci_t *);
77 
78 static int	opl_map_phys(dev_info_t *, struct regspec *,  caddr_t *,
79 				ddi_device_acc_attr_t *, ddi_acc_handle_t *);
80 static void	opl_unmap_phys(ddi_acc_handle_t *);
81 static int	opl_get_hwd_va(dev_info_t *, fco_handle_t, fc_ci_t *);
82 static int	opl_master_interrupt(dev_info_t *, fco_handle_t, fc_ci_t *);
83 
84 extern int	prom_get_fcode_size(char *);
85 extern int	prom_get_fcode(char *, char *);
86 
87 static int	master_interrupt_init(uint32_t, uint32_t);
88 
89 #define	PROBE_STR_SIZE	64
90 #define	UNIT_ADDR_SIZE	64
91 
92 opl_fc_ops_t	opl_fc_ops[] = {
93 
94 	{	FC_MAP_IN,		opl_map_in},
95 	{	FC_MAP_OUT,		opl_map_out},
96 	{	"rx@",			opl_register_fetch},
97 	{	FC_RL_FETCH,		opl_register_fetch},
98 	{	FC_RW_FETCH,		opl_register_fetch},
99 	{	FC_RB_FETCH,		opl_register_fetch},
100 	{	"rx!",			opl_register_store},
101 	{	FC_RL_STORE,		opl_register_store},
102 	{	FC_RW_STORE,		opl_register_store},
103 	{	FC_RB_STORE,		opl_register_store},
104 	{	"claim-memory",		opl_claim_memory},
105 	{	"release-memory",	opl_release_memory},
106 	{	"vtop",			opl_vtop},
107 	{	FC_CONFIG_CHILD,	opl_config_child},
108 	{	FC_GET_FCODE_SIZE,	opl_get_fcode_size},
109 	{	FC_GET_FCODE,		opl_get_fcode},
110 	{	"get-hwd-va",		opl_get_hwd_va},
111 	{	"master-interrupt",	opl_master_interrupt},
112 	{	NULL,			NULL}
113 
114 };
115 
116 extern caddr_t	efcode_vaddr;
117 extern int	efcode_size;
118 
119 #ifdef DEBUG
120 #define	HWDDUMP_OFFSETS		1
121 #define	HWDDUMP_ALL_STATUS	2
122 #define	HWDDUMP_CHUNKS		3
123 #define	HWDDUMP_SBP		4
124 
125 int		hwddump_flags = HWDDUMP_SBP | HWDDUMP_CHUNKS;
126 #endif
127 
128 static int	master_interrupt_inited = 0;
129 
130 int
131 _init()
132 {
133 	int	err = 0;
134 
135 	/*
136 	 * Create a resource map for the contiguous memory allocated
137 	 * at start-of-day in startup.c
138 	 */
139 	err = ndi_ra_map_setup(ddi_root_node(), "opl-fcodemem");
140 	if (err == NDI_FAILURE) {
141 		cmn_err(CE_WARN, "Cannot setup resource map opl-fcodemem\n");
142 		return (1);
143 	}
144 
145 	/*
146 	 * Put the allocated memory into the pool.
147 	 */
148 	(void) ndi_ra_free(ddi_root_node(), (uint64_t)efcode_vaddr,
149 		(uint64_t)efcode_size, "opl-fcodemem", 0);
150 
151 	if ((err = mod_install(&modlinkage)) != 0) {
152 		cmn_err(CE_WARN, "opl_cfg failed to load, error=%d", err);
153 		(void) ndi_ra_map_destroy(ddi_root_node(), "opl-fcodemem");
154 	}
155 
156 	return (err);
157 }
158 
159 int
160 _fini(void)
161 {
162 	int ret;
163 
164 	ret = (mod_remove(&modlinkage));
165 	if (ret != 0)
166 		return (ret);
167 
168 	(void) ndi_ra_map_destroy(ddi_root_node(), "opl-fcodemem");
169 
170 	return (ret);
171 }
172 
173 int
174 _info(modinfop)
175 struct modinfo *modinfop;
176 {
177 	return (mod_info(&modlinkage, modinfop));
178 }
179 
180 #ifdef DEBUG
181 static void
182 opl_dump_hwd(opl_probe_t *probe)
183 {
184 	hwd_header_t		*hdrp;
185 	hwd_sb_status_t		*statp;
186 	hwd_domain_info_t	*dinfop;
187 	hwd_sb_t		*sbp;
188 	hwd_cpu_chip_t		*chips;
189 	hwd_pci_ch_t		*channels;
190 	int			board, i, status;
191 
192 	board = probe->pr_board;
193 
194 	hdrp = probe->pr_hdr;
195 	statp = probe->pr_sb_status;
196 	dinfop = probe->pr_dinfo;
197 	sbp = probe->pr_sb;
198 
199 	printf("HWD: board %d\n", board);
200 	printf("HWD:magic = 0x%x\n", hdrp->hdr_magic);
201 	printf("HWD:version = 0x%x.%x\n", hdrp->hdr_version.major,
202 	    hdrp->hdr_version.minor);
203 
204 	if (hwddump_flags & HWDDUMP_OFFSETS) {
205 		printf("HWD:status offset = 0x%x\n",
206 		    hdrp->hdr_sb_status_offset);
207 		printf("HWD:domain offset = 0x%x\n",
208 		    hdrp->hdr_domain_info_offset);
209 		printf("HWD:board offset = 0x%x\n", hdrp->hdr_sb_info_offset);
210 	}
211 
212 	if (hwddump_flags & HWDDUMP_SBP)
213 		printf("HWD:sb_t ptr = 0x%p\n", (void *)probe->pr_sb);
214 
215 	if (hwddump_flags & HWDDUMP_ALL_STATUS) {
216 		int bd;
217 		printf("HWD:board status =");
218 		for (bd = 0; bd < HWD_SBS_PER_DOMAIN; bd++)
219 			printf("%x ", statp->sb_status[bd]);
220 		printf("\n");
221 	} else {
222 		printf("HWD:board status = %d\n", statp->sb_status[board]);
223 	}
224 
225 	printf("HWD:banner name = %s\n", dinfop->dinf_banner_name);
226 	printf("HWD:platform = %s\n", dinfop->dinf_platform_token);
227 
228 	printf("HWD:chip status:\n");
229 	chips = &sbp->sb_cmu.cmu_cpu_chips[0];
230 	for (i = 0; i < HWD_CPU_CHIPS_PER_CMU; i++) {
231 
232 		status = chips[i].chip_status;
233 		printf("chip[%d] = ", i);
234 		if (HWD_STATUS_NONE(status))
235 			printf("none");
236 		else if (HWD_STATUS_FAILED(status))
237 			printf("fail");
238 		else if (HWD_STATUS_OK(status))
239 			printf("ok");
240 		printf("\n");
241 	}
242 
243 	if (hwddump_flags & HWDDUMP_CHUNKS) {
244 		int chunk;
245 		hwd_memory_t *mem = &sbp->sb_cmu.cmu_memory;
246 		printf("HWD:chunks:\n");
247 		for (chunk = 0; chunk < HWD_MAX_MEM_CHUNKS; chunk++)
248 			printf("\t%d 0x%lx 0x%lx\n", chunk,
249 			    mem->mem_chunks[chunk].chnk_start_address,
250 			    mem->mem_chunks[chunk].chnk_size);
251 	}
252 
253 	printf("HWD:channel status:\n");
254 	channels = &sbp->sb_pci_ch[0];
255 	for (i = 0; i < HWD_PCI_CHANNELS_PER_SB; i++) {
256 
257 		status = channels[i].pci_status;
258 		printf("channels[%d] = ", i);
259 		if (HWD_STATUS_NONE(status))
260 			printf("none");
261 		else if (HWD_STATUS_FAILED(status))
262 			printf("fail");
263 		else if (HWD_STATUS_OK(status))
264 			printf("ok");
265 		printf("\n");
266 	}
267 	printf("channels[%d] = ", i);
268 	status = sbp->sb_cmu.cmu_ch.chan_status;
269 	if (HWD_STATUS_NONE(status))
270 		printf("none");
271 	else if (HWD_STATUS_FAILED(status))
272 		printf("fail");
273 	else if (HWD_STATUS_OK(status))
274 		printf("ok");
275 	printf("\n");
276 }
277 #endif /* DEBUG */
278 
279 #ifdef UCTEST
280 	/*
281 	 * For SesamI debugging, just map the SRAM directly to a kernel
282 	 * VA and read it out from there
283 	 */
284 
285 #include <sys/vmem.h>
286 #include <vm/seg_kmem.h>
287 
288 /*
289  * 0x4081F1323000LL is the HWD base address for LSB 0. But we need to map
290  * at page boundaries. So, we use a base address of 0x4081F1322000LL.
291  * Note that this has to match the HWD base pa set in .sesami-common-defs.
292  *
293  * The size specified for the HWD in the SCF spec is 36K. But since
294  * we adjusted the base address by 4K, we need to use 40K for the
295  * mapping size to cover the HWD. And 40K is also a multiple of the
296  * base page size.
297  */
298 #define	OPL_HWD_BASE(lsb)       \
299 (0x4081F1322000LL | (((uint64_t)(lsb)) << 40))
300 
301 	void    *opl_hwd_vaddr;
302 #endif /* UCTEST */
303 
304 /*
305  * Get the hardware descriptor from SCF.
306  */
307 
308 /*ARGSUSED*/
309 int
310 opl_read_hwd(int board, hwd_header_t **hdrp, hwd_sb_status_t **statp,
311 	hwd_domain_info_t **dinfop, hwd_sb_t **sbp)
312 {
313 	static int (*getinfop)(uint32_t, uint8_t, uint32_t, uint32_t *,
314 	    void *) = NULL;
315 	void *hwdp;
316 
317 	uint32_t key = KEY_ESCF;	/* required value */
318 	uint8_t  type = 0x40;		/* SUB_OS_RECEIVE_HWD */
319 	uint32_t transid = board;
320 	uint32_t datasize = HWD_DATA_SIZE;
321 
322 	hwd_header_t		*hd;
323 	hwd_sb_status_t		*st;
324 	hwd_domain_info_t	*di;
325 	hwd_sb_t		*sb;
326 
327 	int	ret;
328 
329 	if (opl_boards[board].cfg_hwd == NULL) {
330 #ifdef UCTEST
331 		/*
332 		 * Just map the HWD in SRAM to a kernel VA
333 		 */
334 
335 		size_t			size;
336 		pfn_t			pfn;
337 
338 		size = 0xA000;
339 
340 		opl_hwd_vaddr = vmem_alloc(heap_arena, size, VM_SLEEP);
341 		if (opl_hwd_vaddr == NULL) {
342 			cmn_err(CE_NOTE, "No space for HWD");
343 			return (-1);
344 		}
345 
346 		pfn = btop(OPL_HWD_BASE(board));
347 		hat_devload(kas.a_hat, opl_hwd_vaddr, size, pfn, PROT_READ,
348 		    HAT_LOAD_NOCONSIST | HAT_LOAD_LOCK);
349 
350 		hwdp = (void *)((char *)opl_hwd_vaddr + 0x1000);
351 		opl_boards[board].cfg_hwd = hwdp;
352 		ret = 0;
353 #else
354 
355 		/* find the scf_service_getinfo() function */
356 		if (getinfop == NULL)
357 			getinfop = (int (*)(uint32_t, uint8_t, uint32_t,
358 			    uint32_t *,
359 			    void *))modgetsymvalue("scf_service_getinfo", 0);
360 
361 		if (getinfop == NULL)
362 			return (-1);
363 
364 		/* allocate memory to receive the data */
365 		hwdp = kmem_alloc(HWD_DATA_SIZE, KM_SLEEP);
366 
367 		/* get the HWD */
368 		ret = (*getinfop)(key, type, transid, &datasize, hwdp);
369 		if (ret == 0)
370 			opl_boards[board].cfg_hwd = hwdp;
371 		else
372 			kmem_free(hwdp, HWD_DATA_SIZE);
373 #endif
374 	} else {
375 		hwdp = opl_boards[board].cfg_hwd;
376 		ret = 0;
377 	}
378 
379 	/* copy the data to the destination */
380 	if (ret == 0) {
381 		hd = (hwd_header_t *)hwdp;
382 		st = (hwd_sb_status_t *)
383 		    ((char *)hwdp + hd->hdr_sb_status_offset);
384 		di = (hwd_domain_info_t *)
385 		    ((char *)hwdp + hd->hdr_domain_info_offset);
386 		sb = (hwd_sb_t *)
387 		    ((char *)hwdp + hd->hdr_sb_info_offset);
388 		if (hdrp != NULL)
389 			*hdrp = hd;
390 		if (statp != NULL)
391 			*statp = st;
392 		if (dinfop != NULL)
393 			*dinfop = di;
394 		if (sbp != NULL)
395 			*sbp = sb;
396 	}
397 
398 	return (ret);
399 }
400 
401 /*
402  * The opl_probe_t probe structure is used to pass all sorts of parameters
403  * to callback functions during probing. It also contains a snapshot of
404  * the hardware descriptor that is taken at the beginning of a probe.
405  */
406 static int
407 opl_probe_init(opl_probe_t *probe)
408 {
409 	hwd_header_t		**hdrp;
410 	hwd_sb_status_t		**statp;
411 	hwd_domain_info_t	**dinfop;
412 	hwd_sb_t		**sbp;
413 	int			board, ret;
414 
415 	board = probe->pr_board;
416 
417 	hdrp = &probe->pr_hdr;
418 	statp = &probe->pr_sb_status;
419 	dinfop = &probe->pr_dinfo;
420 	sbp = &probe->pr_sb;
421 
422 	/*
423 	 * Read the hardware descriptor.
424 	 */
425 	ret = opl_read_hwd(board, hdrp, statp, dinfop, sbp);
426 	if (ret != 0) {
427 
428 		cmn_err(CE_WARN, "IKP: failed to read HWD header");
429 		return (-1);
430 	}
431 
432 #ifdef DEBUG
433 	opl_dump_hwd(probe);
434 #endif
435 	return (0);
436 }
437 
438 /*
439  * This function is used to obtain pointers to relevant device nodes
440  * which are created by Solaris at boot time.
441  *
442  * This function walks the child nodes of a given node, extracts
443  * the "name" property, if it exists, and passes the node to a
444  * callback init function. The callback determines if this node is
445  * interesting or not. If it is, then a pointer to the node is
446  * stored away by the callback for use during unprobe.
447  *
448  * The DDI get property function allocates storage for the name
449  * property. That needs to be freed within this function.
450  */
451 static int
452 opl_init_nodes(dev_info_t *parent, opl_init_func_t init)
453 {
454 	dev_info_t	*node;
455 	char		*name;
456 	int 		circ, ret;
457 	int		len;
458 
459 	ASSERT(parent != NULL);
460 
461 	/*
462 	 * Hold parent node busy to walk its child list
463 	 */
464 	ndi_devi_enter(parent, &circ);
465 	node = ddi_get_child(parent);
466 
467 	while (node != NULL) {
468 
469 		ret = OPL_GET_PROP(string, node, "name", &name, &len);
470 		if (ret != DDI_PROP_SUCCESS) {
471 			/*
472 			 * The property does not exist for this node.
473 			 */
474 			node = ddi_get_next_sibling(node);
475 			continue;
476 		}
477 
478 		ret = init(node, name, len);
479 		kmem_free(name, len);
480 		if (ret != 0) {
481 
482 			ndi_devi_exit(parent, circ);
483 			return (-1);
484 		}
485 
486 		node = ddi_get_next_sibling(node);
487 	}
488 
489 	ndi_devi_exit(parent, circ);
490 
491 	return (0);
492 }
493 
494 /*
495  * This init function finds all the interesting nodes under the
496  * root node and stores pointers to them. The following nodes
497  * are considered interesting by this implementation:
498  *
499  *	"cmp"
500  *		These are nodes that represent processor chips.
501  *
502  *	"pci"
503  *		These are nodes that represent PCI leaves.
504  *
505  *	"pseudo-mc"
506  *		These are nodes that contain memory information.
507  */
508 static int
509 opl_init_root_nodes(dev_info_t *node, char *name, int len)
510 {
511 	int		portid, board, chip, channel, leaf;
512 	int		ret;
513 
514 	if (strncmp(name, OPL_CPU_CHIP_NODE, len) == 0) {
515 
516 		ret = OPL_GET_PROP(int, node, "portid", &portid, -1);
517 		if (ret != DDI_PROP_SUCCESS)
518 			return (-1);
519 
520 		ret = OPL_GET_PROP(int, node, "board#", &board, -1);
521 		if (ret != DDI_PROP_SUCCESS)
522 			return (-1);
523 
524 		chip = OPL_CPU_CHIP(portid);
525 		opl_boards[board].cfg_cpu_chips[chip] = node;
526 
527 	} else if (strncmp(name, OPL_PCI_LEAF_NODE, len) == 0) {
528 
529 		ret = OPL_GET_PROP(int, node, "portid", &portid, -1);
530 		if (ret != DDI_PROP_SUCCESS)
531 			return (-1);
532 
533 		board = OPL_IO_PORTID_TO_LSB(portid);
534 		channel = OPL_PORTID_TO_CHANNEL(portid);
535 
536 		if (channel == OPL_CMU_CHANNEL) {
537 
538 			opl_boards[board].cfg_cmuch_leaf = node;
539 
540 		} else {
541 
542 			leaf = OPL_PORTID_TO_LEAF(portid);
543 			opl_boards[board].cfg_pcich_leaf[channel][leaf] = node;
544 		}
545 	} else if (strncmp(name, OPL_PSEUDO_MC_NODE, len) == 0) {
546 
547 		ret = OPL_GET_PROP(int, node, "board#", &board, -1);
548 		if (ret != DDI_PROP_SUCCESS)
549 			return (-1);
550 
551 		ASSERT((board >= 0) && (board < HWD_SBS_PER_DOMAIN));
552 
553 		opl_boards[board].cfg_pseudo_mc = node;
554 	}
555 
556 	return (0);
557 }
558 
559 /*
560  * This function initializes the OPL IKP feature. Currently, all it does
561  * is find the interesting nodes that Solaris has created at boot time
562  * for boards present at boot time and store pointers to them. This
563  * is useful if those boards are unprobed by DR.
564  */
565 int
566 opl_init_cfg()
567 {
568 	dev_info_t	*root;
569 
570 	if (opl_cfg_inited == 0) {
571 
572 		root = ddi_root_node();
573 		if ((opl_init_nodes(root, opl_init_root_nodes) != 0)) {
574 			cmn_err(CE_WARN, "IKP: init failed");
575 			return (1);
576 		}
577 
578 		opl_cfg_inited = 1;
579 	}
580 
581 	return (0);
582 }
583 
584 /*
585  * When DR is initialized, we walk the device tree and acquire a hold on
586  * all the nodes that are interesting to IKP. This is so that the corresponding
587  * branches cannot be deleted.
588  *
589  * The following function informs the walk about which nodes are interesting
590  * so that it can hold the corresponding branches.
591  */
592 static int
593 opl_hold_node(char *name)
594 {
595 	/*
596 	 * We only need to hold/release the following nodes which
597 	 * represent separate branches that must be managed.
598 	 */
599 	return ((strcmp(name, OPL_CPU_CHIP_NODE) == 0) ||
600 		(strcmp(name, OPL_PSEUDO_MC_NODE) == 0) ||
601 		(strcmp(name, OPL_PCI_LEAF_NODE) == 0));
602 }
603 
604 static int
605 opl_hold_rele_devtree(dev_info_t *rdip, void *arg)
606 {
607 
608 	int	*holdp = (int *)arg;
609 	char	*name = ddi_node_name(rdip);
610 
611 	/*
612 	 * We only need to hold/release the following nodes which
613 	 * represent separate branches that must be managed.
614 	 */
615 	if (opl_hold_node(name) == 0) {
616 		/* Not of interest to us */
617 		return (DDI_WALK_PRUNECHILD);
618 	}
619 	if (*holdp) {
620 		ASSERT(!e_ddi_branch_held(rdip));
621 		e_ddi_branch_hold(rdip);
622 	} else {
623 		ASSERT(e_ddi_branch_held(rdip));
624 		e_ddi_branch_rele(rdip);
625 	}
626 
627 	return (DDI_WALK_PRUNECHILD);
628 }
629 
630 void
631 opl_hold_devtree()
632 {
633 	dev_info_t *dip;
634 	int circ;
635 	int hold = 1;
636 
637 	dip = ddi_root_node();
638 	ndi_devi_enter(dip, &circ);
639 	ddi_walk_devs(ddi_get_child(dip), opl_hold_rele_devtree, &hold);
640 	ndi_devi_exit(dip, circ);
641 }
642 
643 void
644 opl_release_devtree()
645 {
646 	dev_info_t *dip;
647 	int circ;
648 	int hold = 0;
649 
650 	dip = ddi_root_node();
651 	ndi_devi_enter(dip, &circ);
652 	ddi_walk_devs(ddi_get_child(dip), opl_hold_rele_devtree, &hold);
653 	ndi_devi_exit(dip, circ);
654 }
655 
656 /*
657  * This is a helper function that allows opl_create_node() to return a
658  * pointer to a newly created node to its caller.
659  */
660 /*ARGSUSED*/
661 static void
662 opl_set_node(dev_info_t *node, void *arg, uint_t flags)
663 {
664 	opl_probe_t	*probe;
665 
666 	probe = arg;
667 	probe->pr_node = node;
668 }
669 
670 /*
671  * Function to create a node in the device tree under a specified parent.
672  *
673  * e_ddi_branch_create() allows the creation of a whole branch with a
674  * single call of the function. However, we only use it to create one node
675  * at a time in the case of non-I/O device nodes. In other words, we
676  * create branches by repeatedly using this function. This makes the
677  * code more readable.
678  *
679  * The branch descriptor passed to e_ddi_branch_create() takes two
680  * callbacks. The create() callback is used to set the properties of a
681  * newly created node. The other callback is used to return a pointer
682  * to the newly created node. The create() callback is passed by the
683  * caller of this function based on the kind of node he wishes to
684  * create.
685  *
686  * e_ddi_branch_create() returns with the newly created node held. We
687  * only need to hold the top nodes of the branches we create. We release
688  * the hold for the others. E.g., the "cmp" node needs to be held. Since
689  * we hold the "cmp" node, there is no need to hold the "core" and "cpu"
690  * nodes below it.
691  */
692 static dev_info_t *
693 opl_create_node(opl_probe_t *probe)
694 {
695 	devi_branch_t	branch;
696 
697 	probe->pr_node = NULL;
698 
699 	branch.arg = probe;
700 	branch.type = DEVI_BRANCH_SID;
701 	branch.create.sid_branch_create = probe->pr_create;
702 	branch.devi_branch_callback = opl_set_node;
703 
704 	if (e_ddi_branch_create(probe->pr_parent, &branch, NULL, 0) != 0)
705 		return (NULL);
706 
707 	ASSERT(probe->pr_node != NULL);
708 
709 	if (probe->pr_hold == 0)
710 		e_ddi_branch_rele(probe->pr_node);
711 
712 	return (probe->pr_node);
713 }
714 
715 /*
716  * Function to tear down a whole branch rooted at the specified node.
717  *
718  * Although we create each node of a branch individually, we destroy
719  * a whole branch in one call. This is more efficient.
720  */
721 static int
722 opl_destroy_node(dev_info_t *node)
723 {
724 	if (e_ddi_branch_destroy(node, NULL, 0) != 0)
725 		return (-1);
726 
727 	return (0);
728 }
729 
730 /*
731  * Set the properties for a "cpu" node.
732  */
733 /*ARGSUSED*/
734 static int
735 opl_create_cpu(dev_info_t *node, void *arg, uint_t flags)
736 {
737 	opl_probe_t	*probe;
738 	hwd_cpu_chip_t	*chip;
739 	hwd_core_t	*core;
740 	hwd_cpu_t	*cpu;
741 	int		ret;
742 
743 	probe = arg;
744 	chip = &probe->pr_sb->sb_cmu.cmu_cpu_chips[probe->pr_cpu_chip];
745 	core = &chip->chip_cores[probe->pr_core];
746 	cpu = &core->core_cpus[probe->pr_cpu];
747 	OPL_UPDATE_PROP(string, node, "name", OPL_CPU_NODE);
748 	OPL_UPDATE_PROP(string, node, "device_type", OPL_CPU_NODE);
749 
750 	OPL_UPDATE_PROP(int, node, "cpuid", cpu->cpu_cpuid);
751 	OPL_UPDATE_PROP(int, node, "reg", probe->pr_cpu);
752 
753 	OPL_UPDATE_PROP(string, node, "status", "okay");
754 
755 	return (DDI_WALK_TERMINATE);
756 }
757 
758 /*
759  * Create "cpu" nodes as child nodes of a given "core" node.
760  */
761 static int
762 opl_probe_cpus(opl_probe_t *probe)
763 {
764 	int		i;
765 	hwd_cpu_chip_t	*chip;
766 	hwd_core_t	*core;
767 	hwd_cpu_t	*cpus;
768 
769 	chip = &probe->pr_sb->sb_cmu.cmu_cpu_chips[probe->pr_cpu_chip];
770 	core = &chip->chip_cores[probe->pr_core];
771 	cpus = &core->core_cpus[0];
772 
773 	for (i = 0; i < HWD_CPUS_PER_CORE; i++) {
774 
775 		/*
776 		 * Olympus-C has 2 cpus per core.
777 		 * Jupiter has 4 cpus per core.
778 		 * For the Olympus-C based platform, we expect the cpu_status
779 		 * of the non-existent cpus to be set to missing.
780 		 */
781 		if (!HWD_STATUS_OK(cpus[i].cpu_status))
782 			continue;
783 
784 		probe->pr_create = opl_create_cpu;
785 		probe->pr_cpu = i;
786 		if (opl_create_node(probe) == NULL) {
787 
788 			cmn_err(CE_WARN, "IKP: create cpu (%d-%d-%d-%d) failed",
789 				probe->pr_board, probe->pr_cpu_chip,
790 				probe->pr_core, probe->pr_cpu);
791 			return (-1);
792 		}
793 	}
794 
795 	return (0);
796 }
797 
798 /*
799  * Set the properties for a "core" node.
800  */
801 /*ARGSUSED*/
802 static int
803 opl_create_core(dev_info_t *node, void *arg, uint_t flags)
804 {
805 	opl_probe_t	*probe;
806 	hwd_cpu_chip_t	*chip;
807 	hwd_core_t	*core;
808 	int		sharing[2];
809 	int		ret;
810 
811 	probe = arg;
812 	chip = &probe->pr_sb->sb_cmu.cmu_cpu_chips[probe->pr_cpu_chip];
813 	core = &chip->chip_cores[probe->pr_core];
814 
815 	OPL_UPDATE_PROP(string, node, "name", OPL_CORE_NODE);
816 	OPL_UPDATE_PROP(string, node, "device_type", OPL_CORE_NODE);
817 	OPL_UPDATE_PROP(string, node, "compatible", chip->chip_compatible);
818 
819 	OPL_UPDATE_PROP(int, node, "reg", probe->pr_core);
820 	OPL_UPDATE_PROP(int, node, "manufacturer#", core->core_manufacturer);
821 	OPL_UPDATE_PROP(int, node, "implementation#",
822 	    core->core_implementation);
823 	OPL_UPDATE_PROP(int, node, "mask#", core->core_mask);
824 
825 	OPL_UPDATE_PROP(int, node, "sparc-version", core->core_version);
826 	OPL_UPDATE_PROP(int, node, "clock-frequency", core->core_frequency);
827 
828 	OPL_UPDATE_PROP(int, node, "l1-icache-size", core->core_l1_icache_size);
829 	OPL_UPDATE_PROP(int, node, "l1-icache-line-size",
830 	    core->core_l1_icache_line_size);
831 	OPL_UPDATE_PROP(int, node, "l1-icache-associativity",
832 	    core->core_l1_icache_associativity);
833 	OPL_UPDATE_PROP(int, node, "#itlb-entries",
834 	    core->core_num_itlb_entries);
835 
836 	OPL_UPDATE_PROP(int, node, "l1-dcache-size", core->core_l1_dcache_size);
837 	OPL_UPDATE_PROP(int, node, "l1-dcache-line-size",
838 	    core->core_l1_dcache_line_size);
839 	OPL_UPDATE_PROP(int, node, "l1-dcache-associativity",
840 	    core->core_l1_dcache_associativity);
841 	OPL_UPDATE_PROP(int, node, "#dtlb-entries",
842 	    core->core_num_dtlb_entries);
843 
844 	OPL_UPDATE_PROP(int, node, "l2-cache-size", core->core_l2_cache_size);
845 	OPL_UPDATE_PROP(int, node, "l2-cache-line-size",
846 	    core->core_l2_cache_line_size);
847 	OPL_UPDATE_PROP(int, node, "l2-cache-associativity",
848 	    core->core_l2_cache_associativity);
849 	sharing[0] = 0;
850 	sharing[1] = core->core_l2_cache_sharing;
851 	OPL_UPDATE_PROP_ARRAY(int, node, "l2-cache-sharing", sharing, 2);
852 
853 	OPL_UPDATE_PROP(string, node, "status", "okay");
854 
855 	return (DDI_WALK_TERMINATE);
856 }
857 
858 /*
859  * Create "core" nodes as child nodes of a given "cmp" node.
860  *
861  * Create the branch below each "core" node".
862  */
863 static int
864 opl_probe_cores(opl_probe_t *probe)
865 {
866 	int		i;
867 	hwd_cpu_chip_t	*chip;
868 	hwd_core_t	*cores;
869 	dev_info_t	*parent, *node;
870 
871 	chip = &probe->pr_sb->sb_cmu.cmu_cpu_chips[probe->pr_cpu_chip];
872 	cores = &chip->chip_cores[0];
873 	parent = probe->pr_parent;
874 
875 	for (i = 0; i < HWD_CORES_PER_CPU_CHIP; i++) {
876 
877 		if (!HWD_STATUS_OK(cores[i].core_status))
878 			continue;
879 
880 		probe->pr_parent = parent;
881 		probe->pr_create = opl_create_core;
882 		probe->pr_core = i;
883 		node = opl_create_node(probe);
884 		if (node == NULL) {
885 
886 			cmn_err(CE_WARN, "IKP: create core (%d-%d-%d) failed",
887 				probe->pr_board, probe->pr_cpu_chip,
888 				probe->pr_core);
889 			return (-1);
890 		}
891 
892 		/*
893 		 * Create "cpu" nodes below "core".
894 		 */
895 		probe->pr_parent = node;
896 		if (opl_probe_cpus(probe) != 0)
897 			return (-1);
898 	}
899 
900 	return (0);
901 }
902 
903 /*
904  * Set the properties for a "cmp" node.
905  */
906 /*ARGSUSED*/
907 static int
908 opl_create_cpu_chip(dev_info_t *node, void *arg, uint_t flags)
909 {
910 	opl_probe_t	*probe;
911 	hwd_cpu_chip_t	*chip;
912 	opl_range_t	range;
913 	uint64_t	dummy_addr;
914 	int		ret;
915 
916 	probe = arg;
917 	chip = &probe->pr_sb->sb_cmu.cmu_cpu_chips[probe->pr_cpu_chip];
918 
919 	OPL_UPDATE_PROP(string, node, "name", OPL_CPU_CHIP_NODE);
920 
921 	OPL_UPDATE_PROP(int, node, "portid", chip->chip_portid);
922 	OPL_UPDATE_PROP(int, node, "board#", probe->pr_board);
923 
924 	dummy_addr = OPL_PROC_AS(probe->pr_board, probe->pr_cpu_chip);
925 	range.rg_addr_hi = OPL_HI(dummy_addr);
926 	range.rg_addr_lo = OPL_LO(dummy_addr);
927 	range.rg_size_hi = 0;
928 	range.rg_size_lo = 0;
929 	OPL_UPDATE_PROP_ARRAY(int, node, "reg", (int *)&range, 4);
930 
931 	OPL_UPDATE_PROP(int, node, "#address-cells", 1);
932 	OPL_UPDATE_PROP(int, node, "#size-cells", 0);
933 
934 	OPL_UPDATE_PROP(string, node, "status", "okay");
935 
936 	return (DDI_WALK_TERMINATE);
937 }
938 
939 /*
940  * Create "cmp" nodes as child nodes of the root node.
941  *
942  * Create the branch below each "cmp" node.
943  */
944 static int
945 opl_probe_cpu_chips(opl_probe_t *probe)
946 {
947 	int		i;
948 	dev_info_t	**cfg_cpu_chips;
949 	hwd_cpu_chip_t	*chips;
950 	dev_info_t	*node;
951 
952 	cfg_cpu_chips = opl_boards[probe->pr_board].cfg_cpu_chips;
953 	chips = &probe->pr_sb->sb_cmu.cmu_cpu_chips[0];
954 
955 	for (i = 0; i < HWD_CPU_CHIPS_PER_CMU; i++) {
956 
957 		ASSERT(cfg_cpu_chips[i] == NULL);
958 
959 		if (!HWD_STATUS_OK(chips[i].chip_status))
960 			continue;
961 
962 		probe->pr_parent = ddi_root_node();
963 		probe->pr_create = opl_create_cpu_chip;
964 		probe->pr_cpu_chip = i;
965 		probe->pr_hold = 1;
966 		node = opl_create_node(probe);
967 		if (node == NULL) {
968 
969 			cmn_err(CE_WARN, "IKP: create chip (%d-%d) failed",
970 				probe->pr_board, probe->pr_cpu_chip);
971 			return (-1);
972 		}
973 
974 		cfg_cpu_chips[i] = node;
975 
976 		/*
977 		 * Create "core" nodes below "cmp".
978 		 * We hold the "cmp" node. So, there is no need to hold
979 		 * the "core" and "cpu" nodes below it.
980 		 */
981 		probe->pr_parent = node;
982 		probe->pr_hold = 0;
983 		if (opl_probe_cores(probe) != 0)
984 			return (-1);
985 	}
986 
987 	return (0);
988 }
989 
990 /*
991  * Set the properties for a "pseudo-mc" node.
992  */
993 /*ARGSUSED*/
994 static int
995 opl_create_pseudo_mc(dev_info_t *node, void *arg, uint_t flags)
996 {
997 	opl_probe_t	*probe;
998 	int		board, portid;
999 	hwd_bank_t	*bank;
1000 	hwd_memory_t	*mem;
1001 	opl_range_t	range;
1002 	opl_mc_addr_t	mc[HWD_BANKS_PER_CMU];
1003 	int		status[2][7];
1004 	int		i, j;
1005 	int		ret;
1006 
1007 	probe = arg;
1008 	board = probe->pr_board;
1009 
1010 	OPL_UPDATE_PROP(string, node, "name", OPL_PSEUDO_MC_NODE);
1011 	OPL_UPDATE_PROP(string, node, "device_type", "memory-controller");
1012 	OPL_UPDATE_PROP(string, node, "compatible", "FJSV,oplmc");
1013 
1014 	portid = OPL_LSB_TO_PSEUDOMC_PORTID(board);
1015 	OPL_UPDATE_PROP(int, node, "portid", portid);
1016 
1017 	range.rg_addr_hi = OPL_HI(OPL_MC_AS(board));
1018 	range.rg_addr_lo = 0x200;
1019 	range.rg_size_hi = 0;
1020 	range.rg_size_lo = 0;
1021 	OPL_UPDATE_PROP_ARRAY(int, node, "reg", (int *)&range, 4);
1022 
1023 	OPL_UPDATE_PROP(int, node, "board#", board);
1024 	OPL_UPDATE_PROP(int, node, "physical-board#",
1025 	    probe->pr_sb->sb_psb_number);
1026 
1027 	OPL_UPDATE_PROP(int, node, "#address-cells", 1);
1028 	OPL_UPDATE_PROP(int, node, "#size-cells", 2);
1029 
1030 	mem = &probe->pr_sb->sb_cmu.cmu_memory;
1031 
1032 	range.rg_addr_hi = OPL_HI(mem->mem_start_address);
1033 	range.rg_addr_lo = OPL_LO(mem->mem_start_address);
1034 	range.rg_size_hi = OPL_HI(mem->mem_size);
1035 	range.rg_size_lo = OPL_LO(mem->mem_size);
1036 	OPL_UPDATE_PROP_ARRAY(int, node, "sb-mem-ranges", (int *)&range, 4);
1037 
1038 	bank = probe->pr_sb->sb_cmu.cmu_memory.mem_banks;
1039 	for (i = 0, j = 0; i < HWD_BANKS_PER_CMU; i++) {
1040 
1041 		if (!HWD_STATUS_OK(bank[i].bank_status))
1042 			continue;
1043 
1044 		mc[j].mc_bank = i;
1045 		mc[j].mc_hi = OPL_HI(bank[i].bank_register_address);
1046 		mc[j].mc_lo = OPL_LO(bank[i].bank_register_address);
1047 		j++;
1048 	}
1049 	ASSERT(j > 0);
1050 	OPL_UPDATE_PROP_ARRAY(int, node, "mc-addr", (int *)mc, j*3);
1051 
1052 	OPL_UPDATE_PROP_ARRAY(byte, node, "cs0-mc-pa-trans-table",
1053 	    mem->mem_cs[0].cs_pa_mac_table, 64);
1054 	OPL_UPDATE_PROP_ARRAY(byte, node, "cs1-mc-pa-trans-table",
1055 	    mem->mem_cs[1].cs_pa_mac_table, 64);
1056 
1057 #define	CS_PER_MEM 2
1058 
1059 	for (i = 0, j = 0; i < CS_PER_MEM; i++) {
1060 		if (HWD_STATUS_OK(mem->mem_cs[i].cs_status) ||
1061 			HWD_STATUS_FAILED(mem->mem_cs[i].cs_status)) {
1062 			status[j][0] = i;
1063 			if (HWD_STATUS_OK(mem->mem_cs[i].cs_status))
1064 				status[j][1] = 0;
1065 			else
1066 				status[j][1] = 1;
1067 			status[j][2] =
1068 			    OPL_HI(mem->mem_cs[i].cs_available_capacity);
1069 			status[j][3] =
1070 			    OPL_LO(mem->mem_cs[i].cs_available_capacity);
1071 			status[j][4] = OPL_HI(mem->mem_cs[i].cs_dimm_capacity);
1072 			status[j][5] = OPL_LO(mem->mem_cs[i].cs_dimm_capacity);
1073 			status[j][6] = mem->mem_cs[i].cs_number_of_dimms;
1074 			j++;
1075 		}
1076 	}
1077 	ASSERT(j > 0);
1078 	OPL_UPDATE_PROP_ARRAY(int, node, "cs-status", (int *)status,
1079 	    j*7);
1080 
1081 	return (DDI_WALK_TERMINATE);
1082 }
1083 
1084 /*
1085  * Create "pseudo-mc" nodes
1086  */
1087 static int
1088 opl_probe_memory(opl_probe_t *probe)
1089 {
1090 	int		board;
1091 	opl_board_cfg_t	*board_cfg;
1092 	dev_info_t	*node;
1093 
1094 	board = probe->pr_board;
1095 	board_cfg = &opl_boards[board];
1096 
1097 	ASSERT(board_cfg->cfg_pseudo_mc == NULL);
1098 
1099 	probe->pr_parent = ddi_root_node();
1100 	probe->pr_create = opl_create_pseudo_mc;
1101 	probe->pr_hold = 1;
1102 	node = opl_create_node(probe);
1103 	if (node == NULL) {
1104 
1105 		cmn_err(CE_WARN, "IKP: create pseudo-mc (%d) failed", board);
1106 		return (-1);
1107 	}
1108 
1109 	board_cfg->cfg_pseudo_mc = node;
1110 
1111 	return (0);
1112 }
1113 
1114 /*
1115  * Allocate the fcode ops handle.
1116  */
1117 /*ARGSUSED*/
1118 static
1119 fco_handle_t
1120 opl_fc_ops_alloc_handle(dev_info_t *parent, dev_info_t *child,
1121 			void *fcode, size_t fcode_size, char *unit_address,
1122 			char *my_args)
1123 {
1124 	fco_handle_t	rp;
1125 	phandle_t	h;
1126 	char		*buf;
1127 
1128 	rp = kmem_zalloc(sizeof (struct fc_resource_list), KM_SLEEP);
1129 	rp->next_handle = fc_ops_alloc_handle(parent, child, fcode, fcode_size,
1130 	    unit_address, NULL);
1131 	rp->ap = parent;
1132 	rp->child = child;
1133 	rp->fcode = fcode;
1134 	rp->fcode_size = fcode_size;
1135 	rp->my_args = my_args;
1136 
1137 	if (unit_address) {
1138 		buf = kmem_zalloc(UNIT_ADDR_SIZE, KM_SLEEP);
1139 		(void) strcpy(buf, unit_address);
1140 		rp->unit_address = buf;
1141 	}
1142 
1143 	/*
1144 	 * Add the child's nodeid to our table...
1145 	 */
1146 	h = ddi_get_nodeid(rp->child);
1147 	fc_add_dip_to_phandle(fc_handle_to_phandle_head(rp), rp->child, h);
1148 
1149 	return (rp);
1150 }
1151 
1152 
1153 static void
1154 opl_fc_ops_free_handle(fco_handle_t rp)
1155 {
1156 	struct fc_resource	*resp, *nresp;
1157 
1158 	ASSERT(rp);
1159 
1160 	if (rp->next_handle)
1161 		fc_ops_free_handle(rp->next_handle);
1162 	if (rp->unit_address)
1163 		kmem_free(rp->unit_address, UNIT_ADDR_SIZE);
1164 
1165 	/*
1166 	 * Release all the resources from the resource list
1167 	 */
1168 	for (resp = rp->head; resp != NULL; resp = nresp) {
1169 		nresp = resp->next;
1170 		switch (resp->type) {
1171 
1172 		case RT_MAP:
1173 			break;
1174 
1175 		case RT_DMA:
1176 			/*
1177 			 * DMA has to be freed up at exit time.
1178 			 */
1179 			cmn_err(CE_CONT,
1180 			    "opl_fc_ops_free_handle: Unexpected DMA seen!");
1181 			break;
1182 
1183 		case RT_CONTIGIOUS:
1184 			FC_DEBUG2(1, CE_CONT, "opl_fc_ops_free: "
1185 			    "Free claim-memory resource 0x%lx size 0x%x\n",
1186 			    resp->fc_contig_virt, resp->fc_contig_len);
1187 
1188 			(void) ndi_ra_free(ddi_root_node(),
1189 			    (uint64_t)resp->fc_contig_virt,
1190 			    resp->fc_contig_len, "opl-fcodemem",
1191 			    NDI_RA_PASS);
1192 
1193 			break;
1194 
1195 		default:
1196 			cmn_err(CE_CONT, "opl_fc_ops_free: "
1197 			    "unknown resource type %d", resp->type);
1198 			break;
1199 		}
1200 		fc_rem_resource(rp, resp);
1201 		kmem_free(resp, sizeof (struct fc_resource));
1202 	}
1203 
1204 	kmem_free(rp, sizeof (struct fc_resource_list));
1205 }
1206 
1207 int
1208 opl_fc_do_op(dev_info_t *ap, fco_handle_t rp, fc_ci_t *cp)
1209 {
1210 	opl_fc_ops_t	*op;
1211 	char		*service = fc_cell2ptr(cp->svc_name);
1212 
1213 	ASSERT(rp);
1214 
1215 	FC_DEBUG1(1, CE_CONT, "opl_fc_do_op: <%s>\n", service);
1216 
1217 	/*
1218 	 * First try the generic fc_ops.
1219 	 */
1220 	if (fc_ops(ap, rp->next_handle, cp) == 0)
1221 		return (0);
1222 
1223 	/*
1224 	 * Now try the Jupiter-specific ops.
1225 	 */
1226 	for (op = opl_fc_ops; op->fc_service != NULL; ++op)
1227 		if (strcmp(op->fc_service, service) == 0)
1228 			return (op->fc_op(ap, rp, cp));
1229 
1230 	FC_DEBUG1(9, CE_CONT, "opl_fc_do_op: <%s> not serviced\n", service);
1231 
1232 	return (-1);
1233 }
1234 
1235 /*
1236  * map-in  (phys.lo phys.hi size -- virt)
1237  */
1238 static int
1239 opl_map_in(dev_info_t *ap, fco_handle_t rp, fc_ci_t *cp)
1240 {
1241 	size_t			len;
1242 	int			error;
1243 	caddr_t			virt;
1244 	struct fc_resource	*resp;
1245 	struct regspec		rspec;
1246 	ddi_device_acc_attr_t	acc;
1247 	ddi_acc_handle_t	h;
1248 
1249 	if (fc_cell2int(cp->nargs) != 3)
1250 		return (fc_syntax_error(cp, "nargs must be 3"));
1251 
1252 	if (fc_cell2int(cp->nresults) < 1)
1253 		return (fc_syntax_error(cp, "nresults must be >= 1"));
1254 
1255 	rspec.regspec_size = len = fc_cell2size(fc_arg(cp, 0));
1256 	rspec.regspec_bustype = fc_cell2uint(fc_arg(cp, 1));
1257 	rspec.regspec_addr = fc_cell2uint(fc_arg(cp, 2));
1258 
1259 	acc.devacc_attr_version = DDI_DEVICE_ATTR_V0;
1260 	acc.devacc_attr_endian_flags = DDI_STRUCTURE_BE_ACC;
1261 	acc.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
1262 
1263 	FC_DEBUG3(1, CE_CONT, "opl_map_in: attempting map in "
1264 	    "address 0x%08x.%08x length %x\n", rspec.regspec_bustype,
1265 	    rspec.regspec_addr, rspec.regspec_size);
1266 
1267 	error = opl_map_phys(rp->child, &rspec, &virt, &acc, &h);
1268 
1269 	if (error)  {
1270 		FC_DEBUG3(1, CE_CONT, "opl_map_in: map in failed - "
1271 		    "address 0x%08x.%08x length %x\n", rspec.regspec_bustype,
1272 		    rspec.regspec_addr, rspec.regspec_size);
1273 
1274 		return (fc_priv_error(cp, "opl map-in failed"));
1275 	}
1276 
1277 	FC_DEBUG1(3, CE_CONT, "opl_map_in: returning virt %p\n", virt);
1278 
1279 	cp->nresults = fc_int2cell(1);
1280 	fc_result(cp, 0) = fc_ptr2cell(virt);
1281 
1282 	/*
1283 	 * Log this resource ...
1284 	 */
1285 	resp = kmem_zalloc(sizeof (struct fc_resource), KM_SLEEP);
1286 	resp->type = RT_MAP;
1287 	resp->fc_map_virt = virt;
1288 	resp->fc_map_len = len;
1289 	resp->fc_map_handle = h;
1290 	fc_add_resource(rp, resp);
1291 
1292 	return (fc_success_op(ap, rp, cp));
1293 }
1294 
1295 /*
1296  * map-out (virt size -- )
1297  */
1298 static int
1299 opl_map_out(dev_info_t *ap, fco_handle_t rp, fc_ci_t *cp)
1300 {
1301 	caddr_t			virt;
1302 	size_t			len;
1303 	struct fc_resource	*resp;
1304 
1305 	if (fc_cell2int(cp->nargs) != 2)
1306 		return (fc_syntax_error(cp, "nargs must be 2"));
1307 
1308 	virt = fc_cell2ptr(fc_arg(cp, 1));
1309 
1310 	len = fc_cell2size(fc_arg(cp, 0));
1311 
1312 	FC_DEBUG2(1, CE_CONT, "opl_map_out: attempting map out %p %x\n",
1313 	    virt, len);
1314 
1315 	/*
1316 	 * Find if this request matches a mapping resource we set up.
1317 	 */
1318 	fc_lock_resource_list(rp);
1319 	for (resp = rp->head; resp != NULL; resp = resp->next) {
1320 		if (resp->type != RT_MAP)
1321 			continue;
1322 		if (resp->fc_map_virt != virt)
1323 			continue;
1324 		if (resp->fc_map_len == len)
1325 			break;
1326 	}
1327 	fc_unlock_resource_list(rp);
1328 
1329 	if (resp == NULL)
1330 		return (fc_priv_error(cp, "request doesn't match a "
1331 		    "known mapping"));
1332 
1333 	opl_unmap_phys(&resp->fc_map_handle);
1334 
1335 	/*
1336 	 * remove the resource from the list and release it.
1337 	 */
1338 	fc_rem_resource(rp, resp);
1339 	kmem_free(resp, sizeof (struct fc_resource));
1340 
1341 	cp->nresults = fc_int2cell(0);
1342 	return (fc_success_op(ap, rp, cp));
1343 }
1344 
1345 static int
1346 opl_register_fetch(dev_info_t *ap, fco_handle_t rp, fc_ci_t *cp)
1347 {
1348 	size_t			len;
1349 	caddr_t			virt;
1350 	int			error = 0;
1351 	uint64_t		v;
1352 	uint64_t		x;
1353 	uint32_t		l;
1354 	uint16_t		w;
1355 	uint8_t			b;
1356 	char			*service = fc_cell2ptr(cp->svc_name);
1357 	struct fc_resource	*resp;
1358 
1359 	if (fc_cell2int(cp->nargs) != 1)
1360 		return (fc_syntax_error(cp, "nargs must be 1"));
1361 
1362 	if (fc_cell2int(cp->nresults) < 1)
1363 		return (fc_syntax_error(cp, "nresults must be >= 1"));
1364 
1365 	virt = fc_cell2ptr(fc_arg(cp, 0));
1366 
1367 	/*
1368 	 * Determine the access width .. we can switch on the 2nd
1369 	 * character of the name which is "rx@", "rl@", "rb@" or "rw@"
1370 	 */
1371 	switch (*(service + 1)) {
1372 	case 'x':	len = sizeof (x); break;
1373 	case 'l':	len = sizeof (l); break;
1374 	case 'w':	len = sizeof (w); break;
1375 	case 'b':	len = sizeof (b); break;
1376 	}
1377 
1378 	/*
1379 	 * Check the alignment ...
1380 	 */
1381 	if (((intptr_t)virt & (len - 1)) != 0)
1382 		return (fc_priv_error(cp, "unaligned access"));
1383 
1384 	/*
1385 	 * Find if this virt is 'within' a request we know about
1386 	 */
1387 	fc_lock_resource_list(rp);
1388 	for (resp = rp->head; resp != NULL; resp = resp->next) {
1389 		if (resp->type == RT_MAP) {
1390 			if ((virt >= (caddr_t)resp->fc_map_virt) &&
1391 			    ((virt + len) <=
1392 			    ((caddr_t)resp->fc_map_virt + resp->fc_map_len)))
1393 				break;
1394 		} else if (resp->type == RT_CONTIGIOUS) {
1395 		    if ((virt >= (caddr_t)resp->fc_contig_virt) && ((virt + len)
1396 			<= ((caddr_t)resp->fc_contig_virt +
1397 			    resp->fc_contig_len)))
1398 				break;
1399 		}
1400 	}
1401 	fc_unlock_resource_list(rp);
1402 
1403 	if (resp == NULL) {
1404 		return (fc_priv_error(cp, "request not within "
1405 		    "known mappings"));
1406 	}
1407 
1408 	switch (len) {
1409 	case sizeof (x):
1410 		if (resp->type == RT_MAP)
1411 			error = ddi_peek64(rp->child,
1412 			(int64_t *)virt, (int64_t *)&x);
1413 		else /* RT_CONTIGIOUS */
1414 			x = *(int64_t *)virt;
1415 		v = x;
1416 		break;
1417 	case sizeof (l):
1418 		if (resp->type == RT_MAP)
1419 			error = ddi_peek32(rp->child,
1420 			(int32_t *)virt, (int32_t *)&l);
1421 		else /* RT_CONTIGIOUS */
1422 			l = *(int32_t *)virt;
1423 		v = l;
1424 		break;
1425 	case sizeof (w):
1426 		if (resp->type == RT_MAP)
1427 			error = ddi_peek16(rp->child,
1428 			(int16_t *)virt, (int16_t *)&w);
1429 		else /* RT_CONTIGIOUS */
1430 			w = *(int16_t *)virt;
1431 		v = w;
1432 		break;
1433 	case sizeof (b):
1434 		if (resp->type == RT_MAP)
1435 			error = ddi_peek8(rp->child,
1436 			(int8_t *)virt, (int8_t *)&b);
1437 		else /* RT_CONTIGIOUS */
1438 			b = *(int8_t *)virt;
1439 		v = b;
1440 		break;
1441 	}
1442 
1443 	if (error == DDI_FAILURE) {
1444 		FC_DEBUG2(1, CE_CONT, "opl_register_fetch: access error "
1445 		    "accessing virt %p len %d\n", virt, len);
1446 		return (fc_priv_error(cp, "access error"));
1447 	}
1448 
1449 	FC_DEBUG3(1, CE_CONT, "register_fetch (%s) %llx %llx\n",
1450 	    service, virt, v);
1451 
1452 	cp->nresults = fc_int2cell(1);
1453 	switch (len) {
1454 	case sizeof (x): fc_result(cp, 0) = x; break;
1455 	case sizeof (l): fc_result(cp, 0) = fc_uint32_t2cell(l); break;
1456 	case sizeof (w): fc_result(cp, 0) = fc_uint16_t2cell(w); break;
1457 	case sizeof (b): fc_result(cp, 0) = fc_uint8_t2cell(b); break;
1458 	}
1459 	return (fc_success_op(ap, rp, cp));
1460 }
1461 
1462 static int
1463 opl_register_store(dev_info_t *ap, fco_handle_t rp, fc_ci_t *cp)
1464 {
1465 	size_t			len;
1466 	caddr_t			virt;
1467 	uint64_t		v;
1468 	uint64_t		x;
1469 	uint32_t		l;
1470 	uint16_t		w;
1471 	uint8_t			b;
1472 	char			*service = fc_cell2ptr(cp->svc_name);
1473 	struct fc_resource	*resp;
1474 	int			error = 0;
1475 
1476 	if (fc_cell2int(cp->nargs) != 2)
1477 		return (fc_syntax_error(cp, "nargs must be 2"));
1478 
1479 	virt = fc_cell2ptr(fc_arg(cp, 0));
1480 
1481 	/*
1482 	 * Determine the access width .. we can switch on the 2nd
1483 	 * character of the name which is "rx!", "rl!", "rb!" or "rw!"
1484 	 */
1485 	switch (*(service + 1)) {
1486 	case 'x':
1487 		len = sizeof (x);
1488 		x = fc_arg(cp, 1);
1489 		v = x;
1490 		break;
1491 	case 'l':
1492 		len = sizeof (l);
1493 		l = fc_cell2uint32_t(fc_arg(cp, 1));
1494 		v = l;
1495 		break;
1496 	case 'w':
1497 		len = sizeof (w);
1498 		w = fc_cell2uint16_t(fc_arg(cp, 1));
1499 		v = w;
1500 		break;
1501 	case 'b':
1502 		len = sizeof (b);
1503 		b = fc_cell2uint8_t(fc_arg(cp, 1));
1504 		v = b;
1505 		break;
1506 	}
1507 
1508 	FC_DEBUG3(1, CE_CONT, "register_store (%s) %llx %llx\n",
1509 	    service, virt, v);
1510 
1511 	/*
1512 	 * Check the alignment ...
1513 	 */
1514 	if (((intptr_t)virt & (len - 1)) != 0)
1515 		return (fc_priv_error(cp, "unaligned access"));
1516 
1517 	/*
1518 	 * Find if this virt is 'within' a request we know about
1519 	 */
1520 	fc_lock_resource_list(rp);
1521 	for (resp = rp->head; resp != NULL; resp = resp->next) {
1522 		if (resp->type == RT_MAP) {
1523 			if ((virt >= (caddr_t)resp->fc_map_virt) &&
1524 			    ((virt + len) <=
1525 			    ((caddr_t)resp->fc_map_virt + resp->fc_map_len)))
1526 				break;
1527 		} else if (resp->type == RT_CONTIGIOUS) {
1528 		    if ((virt >= (caddr_t)resp->fc_contig_virt) && ((virt + len)
1529 			<= ((caddr_t)resp->fc_contig_virt +
1530 			    resp->fc_contig_len)))
1531 				break;
1532 		}
1533 	}
1534 	fc_unlock_resource_list(rp);
1535 
1536 	if (resp == NULL)
1537 		return (fc_priv_error(cp, "request not within"
1538 		    "known mappings"));
1539 
1540 	switch (len) {
1541 	case sizeof (x):
1542 		if (resp->type == RT_MAP)
1543 			error = ddi_poke64(rp->child, (int64_t *)virt, x);
1544 		else if (resp->type == RT_CONTIGIOUS)
1545 			*(uint64_t *)virt = x;
1546 		break;
1547 	case sizeof (l):
1548 		if (resp->type == RT_MAP)
1549 			error = ddi_poke32(rp->child, (int32_t *)virt, l);
1550 		else if (resp->type == RT_CONTIGIOUS)
1551 			*(uint32_t *)virt = l;
1552 		break;
1553 	case sizeof (w):
1554 		if (resp->type == RT_MAP)
1555 			error = ddi_poke16(rp->child, (int16_t *)virt, w);
1556 		else if (resp->type == RT_CONTIGIOUS)
1557 			*(uint16_t *)virt = w;
1558 		break;
1559 	case sizeof (b):
1560 		if (resp->type == RT_MAP)
1561 			error = ddi_poke8(rp->child, (int8_t *)virt, b);
1562 		else if (resp->type == RT_CONTIGIOUS)
1563 			*(uint8_t *)virt = b;
1564 		break;
1565 	}
1566 
1567 	if (error == DDI_FAILURE) {
1568 		FC_DEBUG2(1, CE_CONT, "opl_register_store: access error "
1569 		    "accessing virt %p len %d\n", virt, len);
1570 		return (fc_priv_error(cp, "access error"));
1571 	}
1572 
1573 	cp->nresults = fc_int2cell(0);
1574 	return (fc_success_op(ap, rp, cp));
1575 }
1576 
1577 /*
1578  * opl_claim_memory
1579  *
1580  * claim-memory (align size vhint -- vaddr)
1581  */
1582 static int
1583 opl_claim_memory(dev_info_t *ap, fco_handle_t rp, fc_ci_t *cp)
1584 {
1585 	int			align, size, vhint;
1586 	uint64_t		answer, alen;
1587 	ndi_ra_request_t	request;
1588 	struct fc_resource	*resp;
1589 
1590 	if (fc_cell2int(cp->nargs) != 3)
1591 		return (fc_syntax_error(cp, "nargs must be 3"));
1592 
1593 	if (fc_cell2int(cp->nresults) < 1)
1594 		return (fc_syntax_error(cp, "nresults must be >= 1"));
1595 
1596 	vhint = fc_cell2int(fc_arg(cp, 2));
1597 	size  = fc_cell2int(fc_arg(cp, 1));
1598 	align = fc_cell2int(fc_arg(cp, 0));
1599 
1600 	FC_DEBUG3(1, CE_CONT, "opl_claim_memory: align=0x%x size=0x%x "
1601 	    "vhint=0x%x\n", align, size, vhint);
1602 
1603 	if (size == 0) {
1604 		cmn_err(CE_WARN, "opl_claim_memory - unable to allocate "
1605 		    "contiguous memory of size zero\n");
1606 		return (fc_priv_error(cp, "allocation error"));
1607 	}
1608 
1609 	if (vhint) {
1610 		cmn_err(CE_WARN, "opl_claim_memory - vhint is not zero "
1611 		    "vhint=0x%x - Ignoring Argument\n", vhint);
1612 	}
1613 
1614 	bzero((caddr_t)&request, sizeof (ndi_ra_request_t));
1615 	request.ra_flags	= NDI_RA_ALLOC_BOUNDED;
1616 	request.ra_boundbase	= 0;
1617 	request.ra_boundlen	= 0xffffffff;
1618 	request.ra_len		= size;
1619 	request.ra_align_mask	= align - 1;
1620 
1621 	if (ndi_ra_alloc(ddi_root_node(), &request, &answer, &alen,
1622 	    "opl-fcodemem", NDI_RA_PASS) != NDI_SUCCESS) {
1623 		cmn_err(CE_WARN, "opl_claim_memory - unable to allocate "
1624 		    "contiguous memory\n");
1625 		return (fc_priv_error(cp, "allocation error"));
1626 	}
1627 
1628 	FC_DEBUG2(1, CE_CONT, "opl_claim_memory: address allocated=0x%lx "
1629 	    "size=0x%x\n", answer, alen);
1630 
1631 	cp->nresults = fc_int2cell(1);
1632 	fc_result(cp, 0) = answer;
1633 
1634 	/*
1635 	 * Log this resource ...
1636 	 */
1637 	resp = kmem_zalloc(sizeof (struct fc_resource), KM_SLEEP);
1638 	resp->type = RT_CONTIGIOUS;
1639 	resp->fc_contig_virt = (void *)answer;
1640 	resp->fc_contig_len = size;
1641 	fc_add_resource(rp, resp);
1642 
1643 	return (fc_success_op(ap, rp, cp));
1644 }
1645 
1646 /*
1647  * opl_release_memory
1648  *
1649  * release-memory (size vaddr -- )
1650  */
1651 static int
1652 opl_release_memory(dev_info_t *ap, fco_handle_t rp, fc_ci_t *cp)
1653 {
1654 	int32_t			vaddr, size;
1655 	struct fc_resource	*resp;
1656 
1657 	if (fc_cell2int(cp->nargs) != 2)
1658 		return (fc_syntax_error(cp, "nargs must be 2"));
1659 
1660 	if (fc_cell2int(cp->nresults) != 0)
1661 		return (fc_syntax_error(cp, "nresults must be 0"));
1662 
1663 	vaddr = fc_cell2int(fc_arg(cp, 1));
1664 	size  = fc_cell2int(fc_arg(cp, 0));
1665 
1666 	FC_DEBUG2(1, CE_CONT, "opl_release_memory: vaddr=0x%x size=0x%x\n",
1667 	    vaddr, size);
1668 
1669 	/*
1670 	 * Find if this request matches a mapping resource we set up.
1671 	 */
1672 	fc_lock_resource_list(rp);
1673 	for (resp = rp->head; resp != NULL; resp = resp->next) {
1674 		if (resp->type != RT_CONTIGIOUS)
1675 			continue;
1676 		if (resp->fc_contig_virt != (void *)(uintptr_t)vaddr)
1677 			continue;
1678 		if (resp->fc_contig_len == size)
1679 			break;
1680 	}
1681 	fc_unlock_resource_list(rp);
1682 
1683 	if (resp == NULL)
1684 		return (fc_priv_error(cp, "request doesn't match a "
1685 		    "known mapping"));
1686 
1687 	(void) ndi_ra_free(ddi_root_node(), vaddr, size,
1688 	    "opl-fcodemem", NDI_RA_PASS);
1689 
1690 	/*
1691 	 * remove the resource from the list and release it.
1692 	 */
1693 	fc_rem_resource(rp, resp);
1694 	kmem_free(resp, sizeof (struct fc_resource));
1695 
1696 	cp->nresults = fc_int2cell(0);
1697 
1698 	return (fc_success_op(ap, rp, cp));
1699 }
1700 
1701 /*
1702  * opl_vtop
1703  *
1704  * vtop (vaddr -- paddr.lo paddr.hi)
1705  */
1706 static int
1707 opl_vtop(dev_info_t *ap, fco_handle_t rp, fc_ci_t *cp)
1708 {
1709 	int			vaddr;
1710 	uint64_t		paddr;
1711 	struct fc_resource	*resp;
1712 
1713 	if (fc_cell2int(cp->nargs) != 1)
1714 		return (fc_syntax_error(cp, "nargs must be 1"));
1715 
1716 	if (fc_cell2int(cp->nresults) >= 3)
1717 		return (fc_syntax_error(cp, "nresults must be less than 2"));
1718 
1719 	vaddr = fc_cell2int(fc_arg(cp, 0));
1720 
1721 	/*
1722 	 * Find if this request matches a mapping resource we set up.
1723 	 */
1724 	fc_lock_resource_list(rp);
1725 	for (resp = rp->head; resp != NULL; resp = resp->next) {
1726 		if (resp->type != RT_CONTIGIOUS)
1727 			continue;
1728 		if (resp->fc_contig_virt == (void *)(uintptr_t)vaddr)
1729 			break;
1730 	}
1731 	fc_unlock_resource_list(rp);
1732 
1733 	if (resp == NULL)
1734 		return (fc_priv_error(cp, "request doesn't match a "
1735 		    "known mapping"));
1736 
1737 	paddr = va_to_pa((void *)(uintptr_t)vaddr);
1738 
1739 	FC_DEBUG2(1, CE_CONT, "opl_vtop: vaddr=0x%x paddr=0x%x\n",
1740 	    vaddr, paddr);
1741 
1742 	cp->nresults = fc_int2cell(2);
1743 
1744 	fc_result(cp, 0) = paddr;
1745 	fc_result(cp, 1) = 0;
1746 
1747 	return (fc_success_op(ap, rp, cp));
1748 }
1749 
1750 static int
1751 opl_config_child(dev_info_t *ap, fco_handle_t rp, fc_ci_t *cp)
1752 {
1753 	fc_phandle_t h;
1754 
1755 	if (fc_cell2int(cp->nargs) != 0)
1756 		return (fc_syntax_error(cp, "nargs must be 0"));
1757 
1758 	if (fc_cell2int(cp->nresults) < 1)
1759 		return (fc_syntax_error(cp, "nresults must be >= 1"));
1760 
1761 	h = fc_dip_to_phandle(fc_handle_to_phandle_head(rp), rp->child);
1762 
1763 	cp->nresults = fc_int2cell(1);
1764 	fc_result(cp, 0) = fc_phandle2cell(h);
1765 
1766 	return (fc_success_op(ap, rp, cp));
1767 }
1768 
1769 static int
1770 opl_get_fcode(dev_info_t *ap, fco_handle_t rp, fc_ci_t *cp)
1771 {
1772 	caddr_t		dropin_name_virt, fcode_virt;
1773 	char		*dropin_name, *fcode;
1774 	int		fcode_len, status;
1775 
1776 	if (fc_cell2int(cp->nargs) != 3)
1777 		return (fc_syntax_error(cp, "nargs must be 3"));
1778 
1779 	if (fc_cell2int(cp->nresults) < 1)
1780 		return (fc_syntax_error(cp, "nresults must be >= 1"));
1781 
1782 	dropin_name_virt = fc_cell2ptr(fc_arg(cp, 0));
1783 
1784 	fcode_virt = fc_cell2ptr(fc_arg(cp, 1));
1785 
1786 	fcode_len = fc_cell2int(fc_arg(cp, 2));
1787 
1788 	dropin_name = kmem_zalloc(FC_SVC_NAME_LEN, KM_SLEEP);
1789 
1790 	FC_DEBUG2(1, CE_CONT, "get_fcode: %x %d\n", fcode_virt, fcode_len);
1791 
1792 	if (copyinstr(fc_cell2ptr(dropin_name_virt), dropin_name,
1793 	    FC_SVC_NAME_LEN - 1, NULL))  {
1794 		FC_DEBUG1(1, CE_CONT, "opl_get_fcode: "
1795 		    "fault copying in drop in name %p\n", dropin_name_virt);
1796 		status = 0;
1797 	} else {
1798 		FC_DEBUG1(1, CE_CONT, "get_fcode: %s\n", dropin_name);
1799 
1800 		fcode = kmem_zalloc(fcode_len, KM_SLEEP);
1801 
1802 		if ((status = prom_get_fcode(dropin_name, fcode)) != 0) {
1803 
1804 			if (copyout((void *)fcode, (void *)fcode_virt,
1805 			    fcode_len)) {
1806 				cmn_err(CE_WARN, " opl_get_fcode: Unable "
1807 				    "to copy out fcode image");
1808 				status = 0;
1809 			}
1810 		}
1811 
1812 		kmem_free(fcode, fcode_len);
1813 	}
1814 
1815 	kmem_free(dropin_name, FC_SVC_NAME_LEN);
1816 
1817 	cp->nresults = fc_int2cell(1);
1818 	fc_result(cp, 0) = status;
1819 
1820 	return (fc_success_op(ap, rp, cp));
1821 }
1822 
1823 static int
1824 opl_get_fcode_size(dev_info_t *ap, fco_handle_t rp, fc_ci_t *cp)
1825 {
1826 	caddr_t		virt;
1827 	char		*dropin_name;
1828 	int		len;
1829 
1830 	if (fc_cell2int(cp->nargs) != 1)
1831 		return (fc_syntax_error(cp, "nargs must be 1"));
1832 
1833 	if (fc_cell2int(cp->nresults) < 1)
1834 		return (fc_syntax_error(cp, "nresults must be >= 1"));
1835 
1836 	virt = fc_cell2ptr(fc_arg(cp, 0));
1837 
1838 	dropin_name = kmem_zalloc(FC_SVC_NAME_LEN, KM_SLEEP);
1839 
1840 	FC_DEBUG0(1, CE_CONT, "opl_get_fcode_size:\n");
1841 
1842 	if (copyinstr(fc_cell2ptr(virt), dropin_name,
1843 	    FC_SVC_NAME_LEN - 1, NULL))  {
1844 		FC_DEBUG1(1, CE_CONT, "opl_get_fcode_size: "
1845 		    "fault copying in drop in name %p\n", virt);
1846 		len = 0;
1847 	} else {
1848 		FC_DEBUG1(1, CE_CONT, "opl_get_fcode_size: %s\n", dropin_name);
1849 
1850 		len = prom_get_fcode_size(dropin_name);
1851 	}
1852 
1853 	kmem_free(dropin_name, FC_SVC_NAME_LEN);
1854 
1855 	FC_DEBUG1(1, CE_CONT, "opl_get_fcode_size: fcode_len = %d\n", len);
1856 
1857 	cp->nresults = fc_int2cell(1);
1858 	fc_result(cp, 0) = len;
1859 
1860 	return (fc_success_op(ap, rp, cp));
1861 }
1862 
1863 static int
1864 opl_map_phys(dev_info_t *dip, struct regspec *phys_spec,
1865     caddr_t *addrp, ddi_device_acc_attr_t *accattrp,
1866     ddi_acc_handle_t *handlep)
1867 {
1868 	ddi_map_req_t 	mapreq;
1869 	ddi_acc_hdl_t	*acc_handlep;
1870 	int		result;
1871 	struct regspec	*rspecp;
1872 
1873 	*handlep = impl_acc_hdl_alloc(KM_SLEEP, NULL);
1874 	acc_handlep = impl_acc_hdl_get(*handlep);
1875 	acc_handlep->ah_vers = VERS_ACCHDL;
1876 	acc_handlep->ah_dip = dip;
1877 	acc_handlep->ah_rnumber = 0;
1878 	acc_handlep->ah_offset = 0;
1879 	acc_handlep->ah_len = 0;
1880 	acc_handlep->ah_acc = *accattrp;
1881 	rspecp = kmem_zalloc(sizeof (struct regspec), KM_SLEEP);
1882 	*rspecp = *phys_spec;
1883 	/*
1884 	 * cache a copy of the reg spec
1885 	 */
1886 	acc_handlep->ah_bus_private = rspecp;
1887 
1888 	mapreq.map_op = DDI_MO_MAP_LOCKED;
1889 	mapreq.map_type = DDI_MT_REGSPEC;
1890 	mapreq.map_obj.rp = (struct regspec *)phys_spec;
1891 	mapreq.map_prot = PROT_READ | PROT_WRITE;
1892 	mapreq.map_flags = DDI_MF_KERNEL_MAPPING;
1893 	mapreq.map_handlep = acc_handlep;
1894 	mapreq.map_vers = DDI_MAP_VERSION;
1895 
1896 	result = ddi_map(dip, &mapreq, 0, 0, addrp);
1897 
1898 	if (result != DDI_SUCCESS) {
1899 		impl_acc_hdl_free(*handlep);
1900 		*handlep = (ddi_acc_handle_t)NULL;
1901 	} else {
1902 		acc_handlep->ah_addr = *addrp;
1903 	}
1904 
1905 	return (result);
1906 }
1907 
1908 static void
1909 opl_unmap_phys(ddi_acc_handle_t *handlep)
1910 {
1911 	ddi_map_req_t	mapreq;
1912 	ddi_acc_hdl_t	*acc_handlep;
1913 	struct regspec	*rspecp;
1914 
1915 	acc_handlep = impl_acc_hdl_get(*handlep);
1916 	ASSERT(acc_handlep);
1917 	rspecp = acc_handlep->ah_bus_private;
1918 
1919 	mapreq.map_op = DDI_MO_UNMAP;
1920 	mapreq.map_type = DDI_MT_REGSPEC;
1921 	mapreq.map_obj.rp = (struct regspec *)rspecp;
1922 	mapreq.map_prot = PROT_READ | PROT_WRITE;
1923 	mapreq.map_flags = DDI_MF_KERNEL_MAPPING;
1924 	mapreq.map_handlep = acc_handlep;
1925 	mapreq.map_vers = DDI_MAP_VERSION;
1926 
1927 	(void) ddi_map(acc_handlep->ah_dip, &mapreq, acc_handlep->ah_offset,
1928 	    acc_handlep->ah_len, &acc_handlep->ah_addr);
1929 
1930 	impl_acc_hdl_free(*handlep);
1931 	/*
1932 	 * Free the cached copy
1933 	 */
1934 	kmem_free(rspecp, sizeof (struct regspec));
1935 	*handlep = (ddi_acc_handle_t)NULL;
1936 }
1937 
1938 static int
1939 opl_get_hwd_va(dev_info_t *ap, fco_handle_t rp, fc_ci_t *cp)
1940 {
1941 	uint32_t	portid;
1942 	void		*hwd_virt;
1943 	hwd_header_t	*hwd_h = NULL;
1944 	hwd_sb_t	*hwd_sb = NULL;
1945 	int		lsb, ch, leaf;
1946 	int		status = 1;
1947 
1948 	/* Check the argument */
1949 	if (fc_cell2int(cp->nargs) != 2)
1950 		return (fc_syntax_error(cp, "nargs must be 2"));
1951 
1952 	if (fc_cell2int(cp->nresults) < 1)
1953 		return (fc_syntax_error(cp, "nresults must be >= 1"));
1954 
1955 	/* Get the parameters */
1956 	portid = fc_cell2uint32_t(fc_arg(cp, 0));
1957 	hwd_virt = (void *)fc_cell2ptr(fc_arg(cp, 1));
1958 
1959 	/* Get the ID numbers */
1960 	lsb  = OPL_IO_PORTID_TO_LSB(portid);
1961 	ch   = OPL_PORTID_TO_CHANNEL(portid);
1962 	leaf = OPL_PORTID_TO_LEAF(portid);
1963 	ASSERT(OPL_IO_PORTID(lsb, ch, leaf) == portid);
1964 
1965 	/* Set the pointer of hwd. */
1966 	if ((hwd_h = (hwd_header_t *)opl_boards[lsb].cfg_hwd) == NULL) {
1967 		return (fc_priv_error(cp, "null hwd header"));
1968 	}
1969 	/* Set the pointer of hwd sb. */
1970 	if ((hwd_sb = (hwd_sb_t *)((char *)hwd_h + hwd_h->hdr_sb_info_offset))
1971 	    == NULL) {
1972 		return (fc_priv_error(cp, "null hwd sb"));
1973 	}
1974 
1975 	if (ch == OPL_CMU_CHANNEL) {
1976 		/* Copyout CMU-CH HW Descriptor */
1977 		if (copyout((void *)&hwd_sb->sb_cmu.cmu_ch,
1978 		    (void *)hwd_virt, sizeof (hwd_cmu_chan_t))) {
1979 			cmn_err(CE_WARN, "opl_get_hwd_va: "
1980 			"Unable to copy out cmuch descriptor for %x",
1981 			    portid);
1982 			status = 0;
1983 		}
1984 	} else {
1985 		/* Copyout PCI-CH HW Descriptor */
1986 		if (copyout((void *)&hwd_sb->sb_pci_ch[ch].pci_leaf[leaf],
1987 		    (void *)hwd_virt, sizeof (hwd_leaf_t))) {
1988 			cmn_err(CE_WARN, "opl_get_hwd_va: "
1989 			"Unable to copy out pcich descriptor for %x",
1990 			    portid);
1991 			status = 0;
1992 		}
1993 	}
1994 
1995 	cp->nresults = fc_int2cell(1);
1996 	fc_result(cp, 0) = status;
1997 
1998 	return (fc_success_op(ap, rp, cp));
1999 }
2000 
2001 /*
2002  * After Solaris boots, a user can enter OBP using L1A, etc. While in OBP,
2003  * interrupts may be received from PCI devices. These interrupts
2004  * cannot be handled meaningfully since the system is in OBP. These
2005  * interrupts need to be cleared on the CPU side so that the CPU may
2006  * continue with whatever it is doing. Devices that have raised the
2007  * interrupts are expected to reraise the interrupts after sometime
2008  * as they have not been handled. At that time, Solaris will have a
2009  * chance to properly service the interrupts.
2010  *
2011  * The location of the interrupt registers depends on what is present
2012  * at a port. OPL currently supports the Oberon and the CMU channel.
2013  * The following handler handles both kinds of ports and computes
2014  * interrupt register addresses from the specifications and Jupiter Bus
2015  * device bindings.
2016  *
2017  * Fcode drivers install their interrupt handler via a "master-interrupt"
2018  * service. For boot time devices, this takes place within OBP. In the case
2019  * of DR, OPL uses IKP. The Fcode drivers that run within the efcode framework
2020  * attempt to install their handler via the "master-interrupt" service.
2021  * However, we cannot meaningfully install the Fcode driver's handler.
2022  * Instead, we install our own handler in OBP which does the same thing.
2023  *
2024  * Note that the only handling done for interrupts here is to clear it
2025  * on the CPU side. If any device in the future requires more special
2026  * handling, we would have to put in some kind of framework for adding
2027  * device-specific handlers. This is *highly* unlikely, but possible.
2028  *
2029  * Finally, OBP provides a hook called "unix-interrupt-handler" to install
2030  * a Solaris-defined master-interrupt handler for a port. The default
2031  * definition for this method does nothing. Solaris may override this
2032  * with its own definition. This is the way the following handler gets
2033  * control from OBP when interrupts happen at a port after L1A, etc.
2034  */
2035 
2036 static char define_master_interrupt_handler[] =
2037 
2038 /*
2039  * This method translates an Oberon port id to the base (physical) address
2040  * of the interrupt clear registers for that port id.
2041  */
2042 
2043 ": pcich-mid>clear-int-pa   ( mid -- pa ) "
2044 "   dup 1 >> 7 and          ( mid ch# ) "
2045 "   over 4 >> h# 1f and     ( mid ch# lsb# ) "
2046 "   1 d# 46 <<              ( mid ch# lsb# pa ) "
2047 "   swap d# 40 << or        ( mid ch# pa ) "
2048 "   swap d# 37 << or        ( mid pa ) "
2049 "   swap 1 and if h# 70.0000 else h# 60.0000 then "
2050 "   or h# 1400 or           ( pa ) "
2051 "; "
2052 
2053 /*
2054  * This method translates a CMU channel port id to the base (physical) address
2055  * of the interrupt clear registers for that port id. There are two classes of
2056  * interrupts that need to be handled for a CMU channel:
2057  *	- obio interrupts
2058  *	- pci interrupts
2059  * So, there are two addresses that need to be computed.
2060  */
2061 
2062 ": cmuch-mid>clear-int-pa   ( mid -- obio-pa pci-pa ) "
2063 "   dup 1 >> 7 and          ( mid ch# ) "
2064 "   over 4 >> h# 1f and     ( mid ch# lsb# ) "
2065 "   1 d# 46 <<              ( mid ch# lsb# pa ) "
2066 "   swap d# 40 << or        ( mid ch# pa ) "
2067 "   swap d# 37 << or        ( mid pa ) "
2068 "   nip dup h# 1800 +       ( pa obio-pa ) "
2069 "   swap h# 1400 +          ( obio-pa pci-pa ) "
2070 "; "
2071 
2072 /*
2073  * This method checks if a given I/O port ID is valid or not.
2074  * For a given LSB,
2075  *	Oberon ports range from 0 - 3
2076  *	CMU ch ports range from 4 - 4
2077  *
2078  * Also, the Oberon supports leaves 0 and 1.
2079  * The CMU ch supports only one leaf, leaf 0.
2080  */
2081 
2082 ": valid-io-mid? ( mid -- flag ) "
2083 "   dup 1 >> 7 and                     ( mid ch# ) "
2084 "   dup 4 > if 2drop false exit then   ( mid ch# ) "
2085 "   4 = swap 1 and 1 = and not "
2086 "; "
2087 
2088 /*
2089  * This method checks if a given port id is a CMU ch.
2090  */
2091 
2092 ": cmuch? ( mid -- flag ) 1 >> 7 and 4 = ; "
2093 
2094 /*
2095  * Given the base address of the array of interrupt clear registers for
2096  * a port id, this method iterates over the given interrupt number bitmap
2097  * and resets the interrupt on the CPU side for every interrupt number
2098  * in the bitmap. Note that physical addresses are used to perform the
2099  * writes, not virtual addresses. This allows the handler to work without
2100  * any involvement from Solaris.
2101  */
2102 
2103 ": clear-ints ( pa bitmap count -- ) "
2104 "   0 do                            ( pa bitmap ) "
2105 "      dup 0= if 2drop unloop exit then "
2106 "      tuck                         ( bitmap pa bitmap ) "
2107 "      1 and if                     ( bitmap pa ) "
2108 "	 dup i 8 * + 0 swap         ( bitmap pa 0 pa' ) "
2109 "	 h# 15 spacex!              ( bitmap pa ) "
2110 "      then                         ( bitmap pa ) "
2111 "      swap 1 >>                    ( pa bitmap ) "
2112 "   loop "
2113 "; "
2114 
2115 /*
2116  * This method replaces the master-interrupt handler in OBP. Once
2117  * this method is plumbed into OBP, OBP transfers control to this
2118  * handler while returning to Solaris from OBP after L1A. This method's
2119  * task is to simply reset received interrupts on the CPU side.
2120  * When the devices reassert the interrupts later, Solaris will
2121  * be able to see them and handle them.
2122  *
2123  * For each port ID that has interrupts, this method is called
2124  * once by OBP. The input arguments are:
2125  *	mid	portid
2126  *	bitmap	bitmap of interrupts that have happened
2127  *
2128  * This method returns true, if it is able to handle the interrupts.
2129  * OBP does nothing further.
2130  *
2131  * This method returns false, if it encountered a problem. Currently,
2132  * the only problem could be an invalid port id. OBP needs to do
2133  * its own processing in that case. If this method returns false,
2134  * it preserves the mid and bitmap arguments for OBP.
2135  */
2136 
2137 ": unix-resend-mondos ( mid bitmap -- [ mid bitmap false ] | true ) "
2138 
2139 /*
2140  * Uncomment the following line if you want to display the input arguments.
2141  * This is meant for debugging.
2142  * "   .\" Bitmap=\" dup u. .\" MID=\" over u. cr "
2143  */
2144 
2145 /*
2146  * If the port id is not valid (according to the Oberon and CMU ch
2147  * specifications, then return false to OBP to continue further
2148  * processing.
2149  */
2150 
2151 "   over valid-io-mid? not if       ( mid bitmap ) "
2152 "      false exit "
2153 "   then "
2154 
2155 /*
2156  * If the port is a CMU ch, then the 64-bit bitmap represents
2157  * 2 32-bit bitmaps:
2158  *	- obio interrupt bitmap (20 bits)
2159  *	- pci interrupt bitmap (32 bits)
2160  *
2161  * - Split the bitmap into two
2162  * - Compute the base addresses of the interrupt clear registers
2163  *   for both pci interrupts and obio interrupts
2164  * - Clear obio interrupts
2165  * - Clear pci interrupts
2166  */
2167 
2168 "   over cmuch? if                  ( mid bitmap ) "
2169 "      xlsplit                      ( mid pci-bit obio-bit ) "
2170 "      rot cmuch-mid>clear-int-pa   ( pci-bit obio-bit obio-pa pci-pa ) "
2171 "      >r                           ( pci-bit obio-bit obio-pa ) ( r: pci-pa ) "
2172 "      swap d# 20 clear-ints        ( pci-bit ) ( r: pci-pa ) "
2173 "      r> swap d# 32 clear-ints     (  ) ( r: ) "
2174 
2175 /*
2176  * If the port is an Oberon, then the 64-bit bitmap is used fully.
2177  *
2178  * - Compute the base address of the interrupt clear registers
2179  * - Clear interrupts
2180  */
2181 
2182 "   else                            ( mid bitmap ) "
2183 "      swap pcich-mid>clear-int-pa  ( bitmap pa ) "
2184 "      swap d# 64 clear-ints        (  ) "
2185 "   then "
2186 
2187 /*
2188  * Always return true from here.
2189  */
2190 
2191 "   true                            ( true ) "
2192 "; "
2193 ;
2194 
2195 static char	install_master_interrupt_handler[] =
2196 	"' unix-resend-mondos to unix-interrupt-handler";
2197 static char	handler[] = "unix-interrupt-handler";
2198 static char	handler_defined[] = "p\" %s\" find nip swap l! ";
2199 
2200 /*ARGSUSED*/
2201 static int
2202 master_interrupt_init(uint32_t portid, uint32_t xt)
2203 {
2204 	uint_t	defined;
2205 	char	buf[sizeof (handler) + sizeof (handler_defined)];
2206 
2207 	if (master_interrupt_inited)
2208 		return (1);
2209 
2210 	/*
2211 	 * Check if the defer word "unix-interrupt-handler" is defined.
2212 	 * This must be defined for OPL systems. So, this is only a
2213 	 * sanity check.
2214 	 */
2215 	(void) sprintf(buf, handler_defined, handler);
2216 	prom_interpret(buf, (uintptr_t)&defined, 0, 0, 0, 0);
2217 	if (!defined) {
2218 		cmn_err(CE_WARN, "master_interrupt_init: "
2219 		    "%s is not defined\n", handler);
2220 		return (0);
2221 	}
2222 
2223 	/*
2224 	 * Install the generic master-interrupt handler. Note that
2225 	 * this is only done one time on the first DR operation.
2226 	 * This is because, for OPL, one, single generic handler
2227 	 * handles all ports (Oberon and CMU channel) and all
2228 	 * interrupt sources within each port.
2229 	 *
2230 	 * The current support is only for the Oberon and CMU-channel.
2231 	 * If any others need to be supported, the handler has to be
2232 	 * modified accordingly.
2233 	 */
2234 
2235 	/*
2236 	 * Define the OPL master interrupt handler
2237 	 */
2238 	prom_interpret(define_master_interrupt_handler, 0, 0, 0, 0, 0);
2239 
2240 	/*
2241 	 * Take over the master interrupt handler from OBP.
2242 	 */
2243 	prom_interpret(install_master_interrupt_handler, 0, 0, 0, 0, 0);
2244 
2245 	master_interrupt_inited = 1;
2246 
2247 	/*
2248 	 * prom_interpret() does not return a status. So, we assume
2249 	 * that the calls succeeded. In reality, the calls may fail
2250 	 * if there is a syntax error, etc in the strings.
2251 	 */
2252 
2253 	return (1);
2254 }
2255 
2256 /*
2257  * Install the master-interrupt handler for a device.
2258  */
2259 static int
2260 opl_master_interrupt(dev_info_t *ap, fco_handle_t rp, fc_ci_t *cp)
2261 {
2262 	uint32_t	portid, xt;
2263 	int		board, channel, leaf;
2264 	int		status;
2265 
2266 	/* Check the argument */
2267 	if (fc_cell2int(cp->nargs) != 2)
2268 		return (fc_syntax_error(cp, "nargs must be 2"));
2269 
2270 	if (fc_cell2int(cp->nresults) < 1)
2271 		return (fc_syntax_error(cp, "nresults must be >= 1"));
2272 
2273 	/* Get the parameters */
2274 	portid = fc_cell2uint32_t(fc_arg(cp, 0));
2275 	xt = fc_cell2uint32_t(fc_arg(cp, 1));
2276 
2277 	board = OPL_IO_PORTID_TO_LSB(portid);
2278 	channel = OPL_PORTID_TO_CHANNEL(portid);
2279 	leaf = OPL_PORTID_TO_LEAF(portid);
2280 
2281 	if ((board >= HWD_SBS_PER_DOMAIN) || !OPL_VALID_CHANNEL(channel) ||
2282 	    (OPL_OBERON_CHANNEL(channel) && !OPL_VALID_LEAF(leaf)) ||
2283 	    ((channel == OPL_CMU_CHANNEL) && (leaf != 0))) {
2284 		FC_DEBUG1(1, CE_CONT, "opl_master_interrupt: invalid port %x\n",
2285 		    portid);
2286 		status = 0;
2287 	} else {
2288 		status = master_interrupt_init(portid, xt);
2289 	}
2290 
2291 	cp->nresults = fc_int2cell(1);
2292 	fc_result(cp, 0) = status;
2293 
2294 	return (fc_success_op(ap, rp, cp));
2295 }
2296 
2297 /*
2298  * Set the properties for a leaf node (Oberon leaf or CMU channel leaf).
2299  */
2300 /*ARGSUSED*/
2301 static int
2302 opl_create_leaf(dev_info_t *node, void *arg, uint_t flags)
2303 {
2304 	int ret;
2305 
2306 	OPL_UPDATE_PROP(string, node, "name", OPL_PCI_LEAF_NODE);
2307 
2308 	OPL_UPDATE_PROP(string, node, "status", "okay");
2309 
2310 	return (DDI_WALK_TERMINATE);
2311 }
2312 
2313 static char *
2314 opl_get_probe_string(opl_probe_t *probe, int channel, int leaf)
2315 {
2316 	char 		*probe_string;
2317 	int		portid;
2318 
2319 	probe_string = kmem_zalloc(PROBE_STR_SIZE, KM_SLEEP);
2320 
2321 	if (channel == OPL_CMU_CHANNEL)
2322 		portid = probe->pr_sb->sb_cmu.cmu_ch.chan_portid;
2323 	else
2324 		portid = probe->
2325 		    pr_sb->sb_pci_ch[channel].pci_leaf[leaf].leaf_port_id;
2326 
2327 	(void) sprintf(probe_string, "%x", portid);
2328 
2329 	return (probe_string);
2330 }
2331 
2332 static int
2333 opl_probe_leaf(opl_probe_t *probe)
2334 {
2335 	int		channel, leaf, portid, error, circ;
2336 	int		board;
2337 	fco_handle_t	fco_handle, *cfg_handle;
2338 	dev_info_t	*parent, *leaf_node;
2339 	char		unit_address[UNIT_ADDR_SIZE];
2340 	char		*probe_string;
2341 	opl_board_cfg_t	*board_cfg;
2342 
2343 	board = probe->pr_board;
2344 	channel = probe->pr_channel;
2345 	leaf = probe->pr_leaf;
2346 	parent = ddi_root_node();
2347 	board_cfg = &opl_boards[board];
2348 
2349 	ASSERT(OPL_VALID_CHANNEL(channel));
2350 	ASSERT(OPL_VALID_LEAF(leaf));
2351 
2352 	if (channel == OPL_CMU_CHANNEL) {
2353 		portid = probe->pr_sb->sb_cmu.cmu_ch.chan_portid;
2354 		cfg_handle = &board_cfg->cfg_cmuch_handle;
2355 	} else {
2356 		portid = probe->
2357 		    pr_sb->sb_pci_ch[channel].pci_leaf[leaf].leaf_port_id;
2358 		cfg_handle = &board_cfg->cfg_pcich_handle[channel][leaf];
2359 	}
2360 
2361 	/*
2362 	 * Prevent any changes to leaf_node until we have bound
2363 	 * it to the correct driver.
2364 	 */
2365 	ndi_devi_enter(parent, &circ);
2366 
2367 	/*
2368 	 * Ideally, fcode would be run from the "sid_branch_create"
2369 	 * callback (that is the primary purpose of that callback).
2370 	 * However, the fcode interpreter was written with the
2371 	 * assumption that the "new_child" was linked into the
2372 	 * device tree. The callback is invoked with the devinfo node
2373 	 * in the DS_PROTO state. More investigation is needed before
2374 	 * we can invoke the interpreter from the callback. For now,
2375 	 * we create the "new_child" in the BOUND state, invoke the
2376 	 * fcode interpreter and then rebind the dip to use any
2377 	 * compatible properties created by fcode.
2378 	 */
2379 
2380 	probe->pr_parent = parent;
2381 	probe->pr_create = opl_create_leaf;
2382 	probe->pr_hold = 1;
2383 
2384 	leaf_node = opl_create_node(probe);
2385 	if (leaf_node == NULL) {
2386 
2387 		cmn_err(CE_WARN, "IKP: create leaf (%d-%d-%d) failed",
2388 			probe->pr_board, probe->pr_channel, probe->pr_leaf);
2389 		ndi_devi_exit(parent, circ);
2390 		return (-1);
2391 	}
2392 
2393 	/*
2394 	 * The platform DR interfaces created the dip in
2395 	 * bound state. Bring devinfo node down to linked
2396 	 * state and hold it there until compatible
2397 	 * properties are created.
2398 	 */
2399 	e_ddi_branch_rele(leaf_node);
2400 	(void) i_ndi_unconfig_node(leaf_node, DS_LINKED, 0);
2401 	ASSERT(i_ddi_node_state(leaf_node) == DS_LINKED);
2402 	e_ddi_branch_hold(leaf_node);
2403 
2404 	mutex_enter(&DEVI(leaf_node)->devi_lock);
2405 	DEVI(leaf_node)->devi_flags |= DEVI_NO_BIND;
2406 	mutex_exit(&DEVI(leaf_node)->devi_lock);
2407 
2408 	/*
2409 	 * Drop the busy-hold on parent before calling
2410 	 * fcode_interpreter to prevent potential deadlocks
2411 	 */
2412 	ndi_devi_exit(parent, circ);
2413 
2414 	(void) sprintf(unit_address, "%x", portid);
2415 
2416 	/*
2417 	 * Get the probe string
2418 	 */
2419 	probe_string = opl_get_probe_string(probe, channel, leaf);
2420 
2421 	/*
2422 	 * The fcode pointer specified here is NULL and the fcode
2423 	 * size specified here is 0. This causes the user-level
2424 	 * fcode interpreter to issue a request to the fcode
2425 	 * driver to get the Oberon/cmu-ch fcode.
2426 	 */
2427 	fco_handle = opl_fc_ops_alloc_handle(parent, leaf_node,
2428 	    NULL, 0, unit_address, probe_string);
2429 
2430 	error = fcode_interpreter(parent, &opl_fc_do_op, fco_handle);
2431 
2432 	if (error != 0) {
2433 		cmn_err(CE_WARN, "IKP: Unable to probe PCI leaf (%d-%d-%d)",
2434 			probe->pr_board, probe->pr_channel, probe->pr_leaf);
2435 
2436 		opl_fc_ops_free_handle(fco_handle);
2437 
2438 		if (probe_string != NULL)
2439 			kmem_free(probe_string, PROBE_STR_SIZE);
2440 
2441 		(void) opl_destroy_node(leaf_node);
2442 	} else {
2443 		*cfg_handle = fco_handle;
2444 
2445 		if (channel == OPL_CMU_CHANNEL)
2446 			board_cfg->cfg_cmuch_probe_str = probe_string;
2447 		else
2448 			board_cfg->cfg_pcich_probe_str[channel][leaf]
2449 			    = probe_string;
2450 
2451 		/*
2452 		 * Compatible properties (if any) have been created,
2453 		 * so bind driver.
2454 		 */
2455 		ndi_devi_enter(parent, &circ);
2456 		ASSERT(i_ddi_node_state(leaf_node) <= DS_LINKED);
2457 
2458 		mutex_enter(&DEVI(leaf_node)->devi_lock);
2459 		DEVI(leaf_node)->devi_flags &= ~DEVI_NO_BIND;
2460 		mutex_exit(&DEVI(leaf_node)->devi_lock);
2461 
2462 		ndi_devi_exit(parent, circ);
2463 
2464 		if (ndi_devi_bind_driver(leaf_node, 0) !=
2465 			DDI_SUCCESS) {
2466 			cmn_err(CE_WARN,
2467 				"IKP: Unable to bind PCI leaf (%d-%d-%d)",
2468 				probe->pr_board, probe->pr_channel,
2469 				probe->pr_leaf);
2470 		}
2471 	}
2472 
2473 	if ((error != 0) && (channel == OPL_CMU_CHANNEL))
2474 		return (-1);
2475 
2476 	return (0);
2477 }
2478 
2479 static void
2480 opl_init_leaves(int myboard)
2481 {
2482 	dev_info_t	*parent, *node;
2483 	char		*name;
2484 	int 		circ, ret;
2485 	int		len, portid, board, channel, leaf;
2486 	opl_board_cfg_t	*cfg;
2487 
2488 	parent = ddi_root_node();
2489 
2490 	/*
2491 	 * Hold parent node busy to walk its child list
2492 	 */
2493 	ndi_devi_enter(parent, &circ);
2494 
2495 	for (node = ddi_get_child(parent);
2496 		(node != NULL);
2497 		node = ddi_get_next_sibling(node)) {
2498 
2499 		ret = OPL_GET_PROP(string, node, "name", &name, &len);
2500 		if (ret != DDI_PROP_SUCCESS) {
2501 			/*
2502 			 * The property does not exist for this node.
2503 			 */
2504 			continue;
2505 		}
2506 
2507 		if (strncmp(name, OPL_PCI_LEAF_NODE, len) == 0) {
2508 
2509 			ret = OPL_GET_PROP(int, node, "portid", &portid, -1);
2510 			if (ret == DDI_PROP_SUCCESS) {
2511 
2512 				ret = OPL_GET_PROP(int, node, "board#",
2513 				    &board, -1);
2514 				if ((ret != DDI_PROP_SUCCESS) ||
2515 				    (board != myboard))
2516 					continue;
2517 
2518 				cfg = &opl_boards[board];
2519 				channel = OPL_PORTID_TO_CHANNEL(portid);
2520 				if (channel == OPL_CMU_CHANNEL) {
2521 
2522 					if (cfg->cfg_cmuch_handle != NULL)
2523 						cfg->cfg_cmuch_leaf = node;
2524 
2525 				} else {
2526 
2527 					leaf = OPL_PORTID_TO_LEAF(portid);
2528 					if (cfg->cfg_pcich_handle
2529 						[channel][leaf] != NULL)
2530 						cfg->cfg_pcich_leaf
2531 							[channel][leaf] = node;
2532 				}
2533 			}
2534 		}
2535 
2536 		kmem_free(name, len);
2537 		if (ret != DDI_PROP_SUCCESS)
2538 			break;
2539 	}
2540 
2541 	ndi_devi_exit(parent, circ);
2542 }
2543 
2544 /*
2545  * Create "pci" node and hierarchy for the Oberon channels and the
2546  * CMU channel.
2547  */
2548 /*ARGSUSED*/
2549 static int
2550 opl_probe_io(opl_probe_t *probe)
2551 {
2552 
2553 	int		i, j;
2554 	hwd_pci_ch_t	*channels;
2555 
2556 	if (HWD_STATUS_OK(probe->pr_sb->sb_cmu.cmu_ch.chan_status)) {
2557 
2558 		probe->pr_channel = HWD_CMU_CHANNEL;
2559 		probe->pr_channel_status =
2560 		    probe->pr_sb->sb_cmu.cmu_ch.chan_status;
2561 		probe->pr_leaf = 0;
2562 		probe->pr_leaf_status = probe->pr_channel_status;
2563 
2564 		if (opl_probe_leaf(probe) != 0)
2565 			return (-1);
2566 	}
2567 
2568 	channels = &probe->pr_sb->sb_pci_ch[0];
2569 
2570 	for (i = 0; i < HWD_PCI_CHANNELS_PER_SB; i++) {
2571 
2572 		if (!HWD_STATUS_OK(channels[i].pci_status))
2573 			continue;
2574 
2575 		probe->pr_channel = i;
2576 		probe->pr_channel_status = channels[i].pci_status;
2577 
2578 		for (j = 0; j < HWD_LEAVES_PER_PCI_CHANNEL; j++) {
2579 
2580 			probe->pr_leaf = j;
2581 			probe->pr_leaf_status =
2582 				channels[i].pci_leaf[j].leaf_status;
2583 
2584 			if (!HWD_STATUS_OK(probe->pr_leaf_status))
2585 				continue;
2586 
2587 			(void) opl_probe_leaf(probe);
2588 		}
2589 	}
2590 	opl_init_leaves(probe->pr_board);
2591 	return (0);
2592 }
2593 
2594 /*
2595  * Perform the probe in the following order:
2596  *
2597  *	processors
2598  *	memory
2599  *	IO
2600  *
2601  * Each probe function returns 0 on sucess and a non-zero value on failure.
2602  * What is a failure is determined by the implementor of the probe function.
2603  * For example, while probing CPUs, any error encountered during probe
2604  * is considered a failure and causes the whole probe operation to fail.
2605  * However, for I/O, an error encountered while probing one device
2606  * should not prevent other devices from being probed. It should not cause
2607  * the whole probe operation to fail.
2608  */
2609 int
2610 opl_probe_sb(int board)
2611 {
2612 	opl_probe_t	*probe;
2613 	int		ret;
2614 
2615 	if ((board < 0) || (board >= HWD_SBS_PER_DOMAIN))
2616 		return (-1);
2617 
2618 	ASSERT(opl_cfg_inited != 0);
2619 
2620 	/*
2621 	 * If the previous probe failed and left a partially configured
2622 	 * board, we need to unprobe the board and start with a clean slate.
2623 	 */
2624 	if ((opl_boards[board].cfg_hwd != NULL) &&
2625 	    (opl_unprobe_sb(board) != 0))
2626 		return (-1);
2627 
2628 	ret = 0;
2629 
2630 	probe = kmem_zalloc(sizeof (opl_probe_t), KM_SLEEP);
2631 	probe->pr_board = board;
2632 
2633 	if ((opl_probe_init(probe) != 0) ||
2634 
2635 	    (opl_probe_cpu_chips(probe) != 0) ||
2636 
2637 	    (opl_probe_memory(probe) != 0) ||
2638 
2639 	    (opl_probe_io(probe) != 0)) {
2640 
2641 		/*
2642 		 * Probe failed. Perform cleanup.
2643 		 */
2644 		(void) opl_unprobe_sb(board);
2645 		ret = -1;
2646 	}
2647 
2648 	kmem_free(probe, sizeof (opl_probe_t));
2649 
2650 	return (ret);
2651 }
2652 
2653 /*
2654  * This unprobing also includes CMU-CH.
2655  */
2656 /*ARGSUSED*/
2657 static int
2658 opl_unprobe_io(int board)
2659 {
2660 	int		i, j, ret;
2661 	opl_board_cfg_t	*board_cfg;
2662 	dev_info_t	**node;
2663 	fco_handle_t	*hand;
2664 	char		**probe_str;
2665 
2666 	board_cfg = &opl_boards[board];
2667 
2668 	for (i = 0; i < HWD_PCI_CHANNELS_PER_SB; i++) {
2669 
2670 		for (j = 0; j < HWD_LEAVES_PER_PCI_CHANNEL; j++) {
2671 
2672 			node = &board_cfg->cfg_pcich_leaf[i][j];
2673 			hand = &board_cfg->cfg_pcich_handle[i][j];
2674 			probe_str = &board_cfg->cfg_pcich_probe_str[i][j];
2675 
2676 			if (*node == NULL)
2677 				continue;
2678 
2679 			if (*hand != NULL) {
2680 				opl_fc_ops_free_handle(*hand);
2681 				*hand = NULL;
2682 			}
2683 
2684 			if (*probe_str != NULL) {
2685 				kmem_free(*probe_str, PROBE_STR_SIZE);
2686 				*probe_str = NULL;
2687 			}
2688 
2689 			ret = opl_destroy_node(*node);
2690 			if (ret != 0) {
2691 
2692 				cmn_err(CE_WARN,
2693 					"IKP: destroy pci (%d-%d-%d) failed",
2694 					board, i, j);
2695 				return (-1);
2696 			}
2697 
2698 			*node = NULL;
2699 
2700 		}
2701 	}
2702 
2703 	node = &board_cfg->cfg_cmuch_leaf;
2704 	hand = &board_cfg->cfg_cmuch_handle;
2705 	probe_str = &board_cfg->cfg_cmuch_probe_str;
2706 
2707 	if (*node == NULL)
2708 		return (0);
2709 
2710 	if (*hand != NULL) {
2711 		opl_fc_ops_free_handle(*hand);
2712 		*hand = NULL;
2713 	}
2714 
2715 	if (*probe_str != NULL) {
2716 		kmem_free(*probe_str, PROBE_STR_SIZE);
2717 		*probe_str = NULL;
2718 	}
2719 
2720 	if (opl_destroy_node(*node) != 0) {
2721 
2722 		cmn_err(CE_WARN, "IKP: destroy pci (%d-%d-%d) failed",
2723 			board, OPL_CMU_CHANNEL, 0);
2724 		return (-1);
2725 	}
2726 
2727 	*node = NULL;
2728 
2729 	return (0);
2730 }
2731 
2732 /*
2733  * Destroy the "pseudo-mc" node for a board.
2734  */
2735 static int
2736 opl_unprobe_memory(int board)
2737 {
2738 	opl_board_cfg_t	*board_cfg;
2739 
2740 	board_cfg = &opl_boards[board];
2741 
2742 	if (board_cfg->cfg_pseudo_mc == NULL)
2743 		return (0);
2744 
2745 	if (opl_destroy_node(board_cfg->cfg_pseudo_mc) != 0) {
2746 
2747 		cmn_err(CE_WARN, "IKP: destroy pseudo-mc (%d) failed", board);
2748 		return (-1);
2749 	}
2750 
2751 	board_cfg->cfg_pseudo_mc = NULL;
2752 
2753 	return (0);
2754 }
2755 
2756 /*
2757  * Destroy the "cmp" nodes for a board. This also destroys the "core"
2758  * and "cpu" nodes below the "cmp" nodes.
2759  */
2760 static int
2761 opl_unprobe_processors(int board)
2762 {
2763 	int		i;
2764 	dev_info_t	**cfg_cpu_chips;
2765 
2766 	cfg_cpu_chips = opl_boards[board].cfg_cpu_chips;
2767 
2768 	for (i = 0; i < HWD_CPU_CHIPS_PER_CMU; i++) {
2769 
2770 		if (cfg_cpu_chips[i] == NULL)
2771 			continue;
2772 
2773 		if (opl_destroy_node(cfg_cpu_chips[i]) != 0) {
2774 
2775 			cmn_err(CE_WARN,
2776 				"IKP: destroy chip (%d-%d) failed", board, i);
2777 			return (-1);
2778 		}
2779 
2780 		cfg_cpu_chips[i] = NULL;
2781 	}
2782 
2783 	return (0);
2784 }
2785 
2786 /*
2787  * Perform the unprobe in the following order:
2788  *
2789  *	IO
2790  *	memory
2791  *	processors
2792  */
2793 int
2794 opl_unprobe_sb(int board)
2795 {
2796 	if ((board < 0) || (board >= HWD_SBS_PER_DOMAIN))
2797 		return (-1);
2798 
2799 	ASSERT(opl_cfg_inited != 0);
2800 
2801 	if ((opl_unprobe_io(board) != 0) ||
2802 
2803 	    (opl_unprobe_memory(board) != 0) ||
2804 
2805 	    (opl_unprobe_processors(board) != 0))
2806 
2807 		return (-1);
2808 
2809 	if (opl_boards[board].cfg_hwd != NULL) {
2810 #ifdef UCTEST
2811 		size_t			size = 0xA000;
2812 #endif
2813 		/* Release the memory for the HWD */
2814 		void *hwdp = opl_boards[board].cfg_hwd;
2815 		opl_boards[board].cfg_hwd = NULL;
2816 #ifdef UCTEST
2817 		hwdp = (void *)((char *)hwdp - 0x1000);
2818 		hat_unload(kas.a_hat, hwdp, size, HAT_UNLOAD_UNLOCK);
2819 		vmem_free(heap_arena, hwdp, size);
2820 #else
2821 		kmem_free(hwdp, HWD_DATA_SIZE);
2822 #endif
2823 	}
2824 	return (0);
2825 }
2826 
2827 /*
2828  * For MAC patrol support, we need to update the PA-related properties
2829  * when there is a copy-rename event.  This should be called after the
2830  * physical copy and rename has been done by DR, and before the MAC
2831  * patrol is restarted.
2832  */
2833 int
2834 oplcfg_pa_swap(int from, int to)
2835 {
2836 	dev_info_t *from_node = opl_boards[from].cfg_pseudo_mc;
2837 	dev_info_t *to_node = opl_boards[to].cfg_pseudo_mc;
2838 	opl_range_t *rangef, *ranget;
2839 	int elems;
2840 	int ret;
2841 
2842 	if ((OPL_GET_PROP_ARRAY(int, from_node, "sb-mem-ranges", rangef,
2843 	    elems) != DDI_SUCCESS) || (elems != 4)) {
2844 		/* XXX -- bad news */
2845 		return (-1);
2846 	}
2847 	if ((OPL_GET_PROP_ARRAY(int, to_node, "sb-mem-ranges", ranget,
2848 	    elems) != DDI_SUCCESS) || (elems != 4)) {
2849 		/* XXX -- bad news */
2850 		return (-1);
2851 	}
2852 	OPL_UPDATE_PROP_ARRAY(int, from_node, "sb-mem-ranges", (int *)ranget,
2853 	    4);
2854 	OPL_UPDATE_PROP_ARRAY(int, to_node, "sb-mem-ranges", (int *)rangef,
2855 	    4);
2856 
2857 	OPL_FREE_PROP(ranget);
2858 	OPL_FREE_PROP(rangef);
2859 
2860 	return (0);
2861 }
2862