xref: /titanic_52/usr/src/uts/sun4u/io/i2c/clients/adm1026.c (revision 88294e09b5c27cbb12b6735e2fb247a86b76666d)
1d58fda43Sjbeloro /*
2d58fda43Sjbeloro  * CDDL HEADER START
3d58fda43Sjbeloro  *
4d58fda43Sjbeloro  * The contents of this file are subject to the terms of the
519397407SSherry Moore  * Common Development and Distribution License (the "License").
619397407SSherry Moore  * You may not use this file except in compliance with the License.
7d58fda43Sjbeloro  *
8d58fda43Sjbeloro  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9d58fda43Sjbeloro  * or http://www.opensolaris.org/os/licensing.
10d58fda43Sjbeloro  * See the License for the specific language governing permissions
11d58fda43Sjbeloro  * and limitations under the License.
12d58fda43Sjbeloro  *
13d58fda43Sjbeloro  * When distributing Covered Code, include this CDDL HEADER in each
14d58fda43Sjbeloro  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15d58fda43Sjbeloro  * If applicable, add the following below this CDDL HEADER, with the
16d58fda43Sjbeloro  * fields enclosed by brackets "[]" replaced with your own identifying
17d58fda43Sjbeloro  * information: Portions Copyright [yyyy] [name of copyright owner]
18d58fda43Sjbeloro  *
19d58fda43Sjbeloro  * CDDL HEADER END
20d58fda43Sjbeloro  */
21d58fda43Sjbeloro /*
2219397407SSherry Moore  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23d58fda43Sjbeloro  * Use is subject to license terms.
24d58fda43Sjbeloro  */
25d58fda43Sjbeloro 
26d58fda43Sjbeloro #include <sys/stat.h>		/* ddi_create_minor_node S_IFCHR */
27d58fda43Sjbeloro #include <sys/modctl.h>		/* for modldrv */
28d58fda43Sjbeloro #include <sys/open.h>		/* for open params.	 */
29d58fda43Sjbeloro #include <sys/types.h>
30d58fda43Sjbeloro #include <sys/kmem.h>
31d58fda43Sjbeloro #include <sys/sunddi.h>
32d58fda43Sjbeloro #include <sys/conf.h>		/* req. by dev_ops flags MTSAFE etc. */
33d58fda43Sjbeloro #include <sys/ddi.h>
34d58fda43Sjbeloro #include <sys/file.h>
35d58fda43Sjbeloro #include <sys/note.h>
36d58fda43Sjbeloro #include <sys/i2c/clients/i2c_gpio.h>
37d58fda43Sjbeloro #include <sys/i2c/clients/adm1026_impl.h>
38d58fda43Sjbeloro 
39d58fda43Sjbeloro /*
40d58fda43Sjbeloro  * This driver supports the GPIO subset of the full ADM1026 register set.
41d58fda43Sjbeloro  * The driver is designed to allow modifying and reading the Polarity and
42d58fda43Sjbeloro  * Direction bits of the ADM1026's 16 GPIO pins via the 4 GPIO Config
43d58fda43Sjbeloro  * registers.  In addition, the driver supports modifying and reading
44d58fda43Sjbeloro  * the 16 GPIO pins via the 2 GPIO input/output registers.
45d58fda43Sjbeloro  *
46d58fda43Sjbeloro  * The 4 GPIO Config registers configure the direction and polarity of
47d58fda43Sjbeloro  * the 16 GPIO pins.  When a Polarity bit is set to 0, the GPIO pin is
48d58fda43Sjbeloro  * active low, otherwise, it is active high.  When a Direction bit is set
49d58fda43Sjbeloro  * to 0, the GPIO pin configured as an input; otherwise, it is an output.
50d58fda43Sjbeloro  *
51d58fda43Sjbeloro  * The 2 GPIO input/output registers (Status Register 5 & 6 ) behave as follows.
52d58fda43Sjbeloro  * When a GPIO pin is configured as an input, the bit is set when its GPIO
53d58fda43Sjbeloro  * pin is asserted.  When a GPIO pin is configured as an output, the bit
54d58fda43Sjbeloro  * asserts the GPIO pin.
55d58fda43Sjbeloro  *
56d58fda43Sjbeloro  * The commands supported in the ioctl routine are:
57d58fda43Sjbeloro  * GPIO_GET_OUTPUT   -- Read GPIO0-GPIO15 bits in Status Register 5 & 6
58d58fda43Sjbeloro  * GPIO_SET_OUTPUT   -- Modify GPIO0-GPIO15 bits in Status Register 5 & 6
59d58fda43Sjbeloro  * GPIO_GET_POLARITY -- Read GPIO0-GPIO15 Polarity bits in GPIO Config 1-4
60d58fda43Sjbeloro  * GPIO_SET_POLARITY -- Modify GPIO0-GPIO15 Polarity bits in GPIO Config 1-4
61d58fda43Sjbeloro  * GPIO_GET_CONFIG   -- Read GPIO0-GPIO15 Direction bits in GPIO Config 1-4
62d58fda43Sjbeloro  * GPIO_SET_CONFIG   -- Modify GPIO0-GPIO15 Direction bits in GPIO Config 1-4
63d58fda43Sjbeloro  *
64d58fda43Sjbeloro  * A pointer to the i2c_gpio_t data structure is sent as the third argument
65d58fda43Sjbeloro  * in the ioctl call.  The reg_mask and reg_val members of i2c_gpio_t are
66d58fda43Sjbeloro  * used to logically represent the 16 GPIO pins, thus only the lower 16 bits
67d58fda43Sjbeloro  * of each member is used.  The reg_mask member identifies the GPIO pin(s)
68d58fda43Sjbeloro  * that the user wants to read or modify and reg_val has the actual value of
69d58fda43Sjbeloro  * what the corresponding GPIO pin should be set to.
70d58fda43Sjbeloro  *
71d58fda43Sjbeloro  * For example, a reg_mask of 0x8001 indicates that the ioctl should only
72d58fda43Sjbeloro  * access GPIO15 and GPIO0.
73d58fda43Sjbeloro  */
74d58fda43Sjbeloro 
75d58fda43Sjbeloro static void *adm1026soft_statep;
76d58fda43Sjbeloro 
77d58fda43Sjbeloro static int adm1026_do_attach(dev_info_t *);
78d58fda43Sjbeloro static int adm1026_do_detach(dev_info_t *);
79d58fda43Sjbeloro static int adm1026_do_resume(void);
80d58fda43Sjbeloro static int adm1026_do_suspend(void);
81d58fda43Sjbeloro static int adm1026_get8(adm1026_unit_t *unitp, uint8_t reg, uint8_t *val);
82d58fda43Sjbeloro static int adm1026_put8(adm1026_unit_t *unitp, uint8_t reg, uint8_t val);
83d58fda43Sjbeloro 
84d58fda43Sjbeloro /*
85d58fda43Sjbeloro  * cb ops (only need ioctl)
86d58fda43Sjbeloro  */
87d58fda43Sjbeloro static int adm1026_open(dev_t *, int, int, cred_t *);
88d58fda43Sjbeloro static int adm1026_close(dev_t, int, int, cred_t *);
89d58fda43Sjbeloro static int adm1026_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
90d58fda43Sjbeloro 
91d58fda43Sjbeloro static struct cb_ops adm1026_cbops = {
92d58fda43Sjbeloro 	adm1026_open,			/* open  */
93d58fda43Sjbeloro 	adm1026_close,			/* close */
94d58fda43Sjbeloro 	nodev,				/* strategy */
95d58fda43Sjbeloro 	nodev,				/* print */
96d58fda43Sjbeloro 	nodev,				/* dump */
97d58fda43Sjbeloro 	nodev,				/* read */
98d58fda43Sjbeloro 	nodev,				/* write */
99d58fda43Sjbeloro 	adm1026_ioctl,			/* ioctl */
100d58fda43Sjbeloro 	nodev,				/* devmap */
101d58fda43Sjbeloro 	nodev,				/* mmap */
102d58fda43Sjbeloro 	nodev,				/* segmap */
103d58fda43Sjbeloro 	nochpoll,			/* poll */
104d58fda43Sjbeloro 	ddi_prop_op,			/* cb_prop_op */
105d58fda43Sjbeloro 	NULL,				/* streamtab */
106d58fda43Sjbeloro 	D_NEW | D_MP | D_HOTPLUG,	/* Driver compatibility flag */
107d58fda43Sjbeloro 	CB_REV,				/* rev */
108d58fda43Sjbeloro 	nodev,				/* int (*cb_aread)() */
109d58fda43Sjbeloro 	nodev				/* int (*cb_awrite)() */
110d58fda43Sjbeloro };
111d58fda43Sjbeloro 
112d58fda43Sjbeloro /*
113d58fda43Sjbeloro  * dev ops
114d58fda43Sjbeloro  */
115d58fda43Sjbeloro static int adm1026_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
116d58fda43Sjbeloro static int adm1026_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
117d58fda43Sjbeloro 
118d58fda43Sjbeloro static struct dev_ops adm1026_ops = {
119d58fda43Sjbeloro 	DEVO_REV,
120d58fda43Sjbeloro 	0,
121d58fda43Sjbeloro 	ddi_getinfo_1to1,
122d58fda43Sjbeloro 	nulldev,
123d58fda43Sjbeloro 	nulldev,
124d58fda43Sjbeloro 	adm1026_attach,
125d58fda43Sjbeloro 	adm1026_detach,
126d58fda43Sjbeloro 	nodev,
127d58fda43Sjbeloro 	&adm1026_cbops,
12819397407SSherry Moore 	NULL,
12919397407SSherry Moore 	NULL,
13019397407SSherry Moore 	ddi_quiesce_not_needed,		/* quiesce */
131d58fda43Sjbeloro };
132d58fda43Sjbeloro 
133d58fda43Sjbeloro extern struct mod_ops mod_driverops;
134d58fda43Sjbeloro 
135d58fda43Sjbeloro static struct modldrv adm1026_modldrv = {
136d58fda43Sjbeloro 	&mod_driverops,			/* type of module - driver */
137*88294e09SRichard Bean 	"ADM1026 i2c device driver",
138d58fda43Sjbeloro 	&adm1026_ops
139d58fda43Sjbeloro };
140d58fda43Sjbeloro 
141d58fda43Sjbeloro static struct modlinkage adm1026_modlinkage = {
142d58fda43Sjbeloro 	MODREV_1,
143d58fda43Sjbeloro 	&adm1026_modldrv,
144d58fda43Sjbeloro 	0
145d58fda43Sjbeloro };
146d58fda43Sjbeloro 
147d58fda43Sjbeloro 
148d58fda43Sjbeloro int
149d58fda43Sjbeloro _init(void)
150d58fda43Sjbeloro {
151d58fda43Sjbeloro 	int error;
152d58fda43Sjbeloro 
153d58fda43Sjbeloro 	error = mod_install(&adm1026_modlinkage);
154d58fda43Sjbeloro 
155d58fda43Sjbeloro 	if (!error)
156d58fda43Sjbeloro 		(void) ddi_soft_state_init(&adm1026soft_statep,
157d58fda43Sjbeloro 		    sizeof (struct adm1026_unit), 1);
158d58fda43Sjbeloro 	return (error);
159d58fda43Sjbeloro }
160d58fda43Sjbeloro 
161d58fda43Sjbeloro int
162d58fda43Sjbeloro _fini(void)
163d58fda43Sjbeloro {
164d58fda43Sjbeloro 	int error;
165d58fda43Sjbeloro 
166d58fda43Sjbeloro 	error = mod_remove(&adm1026_modlinkage);
167d58fda43Sjbeloro 	if (!error)
168d58fda43Sjbeloro 		ddi_soft_state_fini(&adm1026soft_statep);
169d58fda43Sjbeloro 
170d58fda43Sjbeloro 	return (error);
171d58fda43Sjbeloro }
172d58fda43Sjbeloro 
173d58fda43Sjbeloro int
174d58fda43Sjbeloro _info(struct modinfo *modinfop)
175d58fda43Sjbeloro {
176d58fda43Sjbeloro 	return (mod_info(&adm1026_modlinkage, modinfop));
177d58fda43Sjbeloro }
178d58fda43Sjbeloro 
179d58fda43Sjbeloro static int
180d58fda43Sjbeloro adm1026_open(dev_t *devp, int flags, int otyp, cred_t *credp)
181d58fda43Sjbeloro {
182d58fda43Sjbeloro 	_NOTE(ARGUNUSED(credp))
183d58fda43Sjbeloro 
184d58fda43Sjbeloro 	adm1026_unit_t *unitp;
185d58fda43Sjbeloro 	int instance;
186d58fda43Sjbeloro 	int error = 0;
187d58fda43Sjbeloro 
188d58fda43Sjbeloro 	instance = getminor(*devp);
189d58fda43Sjbeloro 
190d58fda43Sjbeloro 	D2CMN_ERR((CE_WARN, "adm1026_open: instance=%d\n", instance));
191d58fda43Sjbeloro 
192d58fda43Sjbeloro 	if (instance < 0) {
193d58fda43Sjbeloro 		return (ENXIO);
194d58fda43Sjbeloro 	}
195d58fda43Sjbeloro 
196d58fda43Sjbeloro 	unitp = (struct adm1026_unit *)
197d58fda43Sjbeloro 	    ddi_get_soft_state(adm1026soft_statep, instance);
198d58fda43Sjbeloro 
199d58fda43Sjbeloro 	if (unitp == NULL) {
200d58fda43Sjbeloro 		return (ENXIO);
201d58fda43Sjbeloro 	}
202d58fda43Sjbeloro 
203d58fda43Sjbeloro 	if (otyp != OTYP_CHR) {
204d58fda43Sjbeloro 		return (EINVAL);
205d58fda43Sjbeloro 	}
206d58fda43Sjbeloro 
207d58fda43Sjbeloro 	mutex_enter(&unitp->adm1026_mutex);
208d58fda43Sjbeloro 
209d58fda43Sjbeloro 	if (flags & FEXCL) {
210d58fda43Sjbeloro 		if (unitp->adm1026_oflag != 0) {
211d58fda43Sjbeloro 			error = EBUSY;
212d58fda43Sjbeloro 		} else {
213d58fda43Sjbeloro 			unitp->adm1026_oflag = FEXCL;
214d58fda43Sjbeloro 		}
215d58fda43Sjbeloro 	} else {
216d58fda43Sjbeloro 		if (unitp->adm1026_oflag == FEXCL) {
217d58fda43Sjbeloro 			error = EBUSY;
218d58fda43Sjbeloro 		} else {
219d58fda43Sjbeloro 			unitp->adm1026_oflag = FOPEN;
220d58fda43Sjbeloro 		}
221d58fda43Sjbeloro 	}
222d58fda43Sjbeloro 
223d58fda43Sjbeloro 	mutex_exit(&unitp->adm1026_mutex);
224d58fda43Sjbeloro 
225d58fda43Sjbeloro 	return (error);
226d58fda43Sjbeloro }
227d58fda43Sjbeloro 
228d58fda43Sjbeloro static int
229d58fda43Sjbeloro adm1026_close(dev_t dev, int flags, int otyp, cred_t *credp)
230d58fda43Sjbeloro {
231d58fda43Sjbeloro 	_NOTE(ARGUNUSED(flags, otyp, credp))
232d58fda43Sjbeloro 
233d58fda43Sjbeloro 	adm1026_unit_t *unitp;
234d58fda43Sjbeloro 	int instance;
235d58fda43Sjbeloro 
236d58fda43Sjbeloro 	instance = getminor(dev);
237d58fda43Sjbeloro 
238d58fda43Sjbeloro 	D2CMN_ERR((CE_WARN, "adm1026_close: instance=%d\n", instance));
239d58fda43Sjbeloro 
240d58fda43Sjbeloro 	if (instance < 0) {
241d58fda43Sjbeloro 		return (ENXIO);
242d58fda43Sjbeloro 	}
243d58fda43Sjbeloro 
244d58fda43Sjbeloro 	unitp = (struct adm1026_unit *)
245d58fda43Sjbeloro 	    ddi_get_soft_state(adm1026soft_statep, instance);
246d58fda43Sjbeloro 
247d58fda43Sjbeloro 	if (unitp == NULL) {
248d58fda43Sjbeloro 		return (ENXIO);
249d58fda43Sjbeloro 	}
250d58fda43Sjbeloro 
251d58fda43Sjbeloro 	mutex_enter(&unitp->adm1026_mutex);
252d58fda43Sjbeloro 
253d58fda43Sjbeloro 	unitp->adm1026_oflag = 0;
254d58fda43Sjbeloro 
255d58fda43Sjbeloro 	mutex_exit(&unitp->adm1026_mutex);
256d58fda43Sjbeloro 	return (DDI_SUCCESS);
257d58fda43Sjbeloro }
258d58fda43Sjbeloro 
259d58fda43Sjbeloro static int
260d58fda43Sjbeloro adm1026_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
261d58fda43Sjbeloro {
262d58fda43Sjbeloro 	D2CMN_ERR((CE_WARN, "adm1026_attach: cmd=%x\n", cmd));
263d58fda43Sjbeloro 
264d58fda43Sjbeloro 	switch (cmd) {
265d58fda43Sjbeloro 	case DDI_ATTACH:
266d58fda43Sjbeloro 		return (adm1026_do_attach(dip));
267d58fda43Sjbeloro 	case DDI_RESUME:
268d58fda43Sjbeloro 		return (adm1026_do_resume());
269d58fda43Sjbeloro 	default:
270d58fda43Sjbeloro 		return (DDI_FAILURE);
271d58fda43Sjbeloro 	}
272d58fda43Sjbeloro }
273d58fda43Sjbeloro 
274d58fda43Sjbeloro static int
275d58fda43Sjbeloro adm1026_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
276d58fda43Sjbeloro {
277d58fda43Sjbeloro 	D2CMN_ERR((CE_WARN, "adm1026_detach: cmd=%x\n", cmd));
278d58fda43Sjbeloro 	switch (cmd) {
279d58fda43Sjbeloro 	case DDI_DETACH:
280d58fda43Sjbeloro 		return (adm1026_do_detach(dip));
281d58fda43Sjbeloro 	case DDI_SUSPEND:
282d58fda43Sjbeloro 		return (adm1026_do_suspend());
283d58fda43Sjbeloro 	default:
284d58fda43Sjbeloro 		return (DDI_FAILURE);
285d58fda43Sjbeloro 	}
286d58fda43Sjbeloro }
287d58fda43Sjbeloro 
288d58fda43Sjbeloro static int
289d58fda43Sjbeloro adm1026_do_attach(dev_info_t *dip)
290d58fda43Sjbeloro {
291d58fda43Sjbeloro 	adm1026_unit_t *unitp;
292d58fda43Sjbeloro 	int instance;
293d58fda43Sjbeloro 
294d58fda43Sjbeloro 	instance = ddi_get_instance(dip);
295d58fda43Sjbeloro 
296d58fda43Sjbeloro 	D2CMN_ERR((CE_WARN, "adm1026_do_attach: instance=%d, dip=%p",
297d58fda43Sjbeloro 	    instance, (void *)dip));
298d58fda43Sjbeloro 
299d58fda43Sjbeloro 	if (ddi_soft_state_zalloc(adm1026soft_statep, instance) != 0) {
300d58fda43Sjbeloro 		cmn_err(CE_WARN, "%s%d: ddi_soft_state_zalloc() failed",
301d58fda43Sjbeloro 		    ddi_get_name(dip), instance);
302d58fda43Sjbeloro 		return (DDI_FAILURE);
303d58fda43Sjbeloro 	}
304d58fda43Sjbeloro 
305d58fda43Sjbeloro 	unitp = ddi_get_soft_state(adm1026soft_statep, instance);
306d58fda43Sjbeloro 
307d58fda43Sjbeloro 	if (unitp == NULL) {
308d58fda43Sjbeloro 		cmn_err(CE_WARN, "%s%d: ddi_get_soft_state(), no memory",
309d58fda43Sjbeloro 		    ddi_get_name(dip), instance);
310d58fda43Sjbeloro 		return (ENOMEM);
311d58fda43Sjbeloro 	}
312d58fda43Sjbeloro 
313d58fda43Sjbeloro 	D2CMN_ERR((CE_WARN, "adm1026_do_attach: ddi_create_minor_node"));
314d58fda43Sjbeloro 	if (ddi_create_minor_node(dip, "adm1026", S_IFCHR, instance,
315d58fda43Sjbeloro 	"ddi_i2c:led_control", NULL) == DDI_FAILURE) {
316d58fda43Sjbeloro 		cmn_err(CE_WARN,
317d58fda43Sjbeloro 		    "adm1026_do_attach: ddi_create_minor_node failed");
318d58fda43Sjbeloro 		ddi_soft_state_free(adm1026soft_statep, instance);
319d58fda43Sjbeloro 
320d58fda43Sjbeloro 		return (DDI_FAILURE);
321d58fda43Sjbeloro 	}
322d58fda43Sjbeloro 
323d58fda43Sjbeloro 	D2CMN_ERR((CE_WARN, "adm1026_do_attach: i2c_client_register"));
324d58fda43Sjbeloro 	if (i2c_client_register(dip, &unitp->adm1026_hdl) != I2C_SUCCESS) {
325d58fda43Sjbeloro 		ddi_remove_minor_node(dip, NULL);
326d58fda43Sjbeloro 		ddi_soft_state_free(adm1026soft_statep, instance);
327d58fda43Sjbeloro 		cmn_err(CE_WARN,
328d58fda43Sjbeloro 		    "adm1026_do_attach: i2c_client_register failed");
329d58fda43Sjbeloro 
330d58fda43Sjbeloro 		return (DDI_FAILURE);
331d58fda43Sjbeloro 	}
332d58fda43Sjbeloro 
333d58fda43Sjbeloro 	mutex_init(&unitp->adm1026_mutex, NULL, MUTEX_DRIVER, NULL);
334d58fda43Sjbeloro 
335d58fda43Sjbeloro 	D2CMN_ERR((CE_WARN, "adm1026_do_attach: DDI_SUCCESS"));
336d58fda43Sjbeloro 	return (DDI_SUCCESS);
337d58fda43Sjbeloro }
338d58fda43Sjbeloro 
339d58fda43Sjbeloro static int
340d58fda43Sjbeloro adm1026_do_resume(void)
341d58fda43Sjbeloro {
342d58fda43Sjbeloro 	int ret = DDI_SUCCESS;
343d58fda43Sjbeloro 
344d58fda43Sjbeloro 	return (ret);
345d58fda43Sjbeloro }
346d58fda43Sjbeloro 
347d58fda43Sjbeloro static int
348d58fda43Sjbeloro adm1026_do_suspend()
349d58fda43Sjbeloro {
350d58fda43Sjbeloro 	int ret = DDI_SUCCESS;
351d58fda43Sjbeloro 
352d58fda43Sjbeloro 	return (ret);
353d58fda43Sjbeloro }
354d58fda43Sjbeloro 
355d58fda43Sjbeloro static int
356d58fda43Sjbeloro adm1026_do_detach(dev_info_t *dip)
357d58fda43Sjbeloro {
358d58fda43Sjbeloro 	adm1026_unit_t *unitp;
359d58fda43Sjbeloro 	int instance;
360d58fda43Sjbeloro 
361d58fda43Sjbeloro 	instance = ddi_get_instance(dip);
362d58fda43Sjbeloro 
363d58fda43Sjbeloro 	unitp = ddi_get_soft_state(adm1026soft_statep, instance);
364d58fda43Sjbeloro 
365d58fda43Sjbeloro 	if (unitp == NULL) {
366d58fda43Sjbeloro 		cmn_err(CE_WARN,
367d58fda43Sjbeloro 		    "adm1026_do_detach: ddi_get_soft_state failed");
368d58fda43Sjbeloro 		return (ENOMEM);
369d58fda43Sjbeloro 	}
370d58fda43Sjbeloro 
371d58fda43Sjbeloro 	i2c_client_unregister(unitp->adm1026_hdl);
372d58fda43Sjbeloro 
373d58fda43Sjbeloro 	ddi_remove_minor_node(dip, NULL);
374d58fda43Sjbeloro 
375d58fda43Sjbeloro 	mutex_destroy(&unitp->adm1026_mutex);
376d58fda43Sjbeloro 	ddi_soft_state_free(adm1026soft_statep, instance);
377d58fda43Sjbeloro 
378d58fda43Sjbeloro 	return (DDI_SUCCESS);
379d58fda43Sjbeloro }
380d58fda43Sjbeloro 
381d58fda43Sjbeloro static int
382d58fda43Sjbeloro adm1026_get8(adm1026_unit_t *unitp, uint8_t reg, uint8_t *val)
383d58fda43Sjbeloro {
384d58fda43Sjbeloro 	i2c_transfer_t		*i2c_tran_pointer = NULL;
385d58fda43Sjbeloro 	int			err = DDI_SUCCESS;
386d58fda43Sjbeloro 
387d58fda43Sjbeloro 	(void) i2c_transfer_alloc(unitp->adm1026_hdl, &i2c_tran_pointer,
388d58fda43Sjbeloro 	    1, 1, I2C_SLEEP);
389d58fda43Sjbeloro 	if (i2c_tran_pointer == NULL)
390d58fda43Sjbeloro 		return (ENOMEM);
391d58fda43Sjbeloro 
392d58fda43Sjbeloro 	i2c_tran_pointer->i2c_flags = I2C_WR_RD;
393d58fda43Sjbeloro 	i2c_tran_pointer->i2c_wbuf[0] = (uchar_t)reg;
394d58fda43Sjbeloro 	err = i2c_transfer(unitp->adm1026_hdl, i2c_tran_pointer);
395d58fda43Sjbeloro 	if (err) {
396d58fda43Sjbeloro 		D1CMN_ERR((CE_WARN,
397d58fda43Sjbeloro 		    "adm1026_get8: I2C_WR_RD reg=0x%x failed", reg));
398d58fda43Sjbeloro 	} else {
399d58fda43Sjbeloro 		*val = i2c_tran_pointer->i2c_rbuf[0];
400d58fda43Sjbeloro 		D1CMN_ERR((CE_WARN, "adm1026_get8: reg=%02x, val=%02x",
401d58fda43Sjbeloro 		    reg, *val));
402d58fda43Sjbeloro 	}
403d58fda43Sjbeloro 	i2c_transfer_free(unitp->adm1026_hdl, i2c_tran_pointer);
404d58fda43Sjbeloro 
405d58fda43Sjbeloro 	return (err);
406d58fda43Sjbeloro }
407d58fda43Sjbeloro 
408d58fda43Sjbeloro static int
409d58fda43Sjbeloro adm1026_put8(adm1026_unit_t *unitp, uint8_t reg, uint8_t val)
410d58fda43Sjbeloro {
411d58fda43Sjbeloro 	i2c_transfer_t		*i2c_tran_pointer = NULL;
412d58fda43Sjbeloro 	int			err = DDI_SUCCESS;
413d58fda43Sjbeloro 
414d58fda43Sjbeloro 	D1CMN_ERR((CE_WARN, "adm1026_put8: reg=%02x, val=%02x\n", reg, val));
415d58fda43Sjbeloro 
416d58fda43Sjbeloro 	(void) i2c_transfer_alloc(unitp->adm1026_hdl, &i2c_tran_pointer,
417d58fda43Sjbeloro 	    2, 0, I2C_SLEEP);
418d58fda43Sjbeloro 	if (i2c_tran_pointer == NULL)
419d58fda43Sjbeloro 		return (ENOMEM);
420d58fda43Sjbeloro 
421d58fda43Sjbeloro 	i2c_tran_pointer->i2c_flags = I2C_WR;
422d58fda43Sjbeloro 	i2c_tran_pointer->i2c_wbuf[0] = reg;
423d58fda43Sjbeloro 	i2c_tran_pointer->i2c_wbuf[1] = val;
424d58fda43Sjbeloro 
425d58fda43Sjbeloro 	err = i2c_transfer(unitp->adm1026_hdl, i2c_tran_pointer);
426d58fda43Sjbeloro 	if (err)
427d58fda43Sjbeloro 		D2CMN_ERR((CE_WARN, "adm1026_put8: return=%x", err));
428d58fda43Sjbeloro 
429d58fda43Sjbeloro 	i2c_transfer_free(unitp->adm1026_hdl, i2c_tran_pointer);
430d58fda43Sjbeloro 
431d58fda43Sjbeloro 	return (err);
432d58fda43Sjbeloro }
433d58fda43Sjbeloro 
434d58fda43Sjbeloro /*
435d58fda43Sjbeloro  * adm1026_send8:
436d58fda43Sjbeloro  * Read the i2c register, apply the mask to contents so that only
437d58fda43Sjbeloro  * bits in mask affected. Or in value and write it back to the i2c register.
438d58fda43Sjbeloro  */
439d58fda43Sjbeloro static int
440d58fda43Sjbeloro adm1026_send8(adm1026_unit_t *unitp, uint8_t reg, uint8_t reg_val,
441d58fda43Sjbeloro 			uint8_t reg_mask)
442d58fda43Sjbeloro {
443d58fda43Sjbeloro 	uint8_t val = 0;
444d58fda43Sjbeloro 	int err;
445d58fda43Sjbeloro 
446d58fda43Sjbeloro 	if ((err = adm1026_get8(unitp, reg, &val)) != I2C_SUCCESS)
447d58fda43Sjbeloro 		return (err);
448d58fda43Sjbeloro 	val &= ~reg_mask;
449d58fda43Sjbeloro 	val |= (reg_val & reg_mask);
450d58fda43Sjbeloro 
451d58fda43Sjbeloro 	return (adm1026_put8(unitp, reg, val));
452d58fda43Sjbeloro }
453d58fda43Sjbeloro 
454d58fda43Sjbeloro /*
455d58fda43Sjbeloro  * adm1026_set_output:
456d58fda43Sjbeloro  * The low 16 bits of the mask is a 1:1 mask indicating which of the
457d58fda43Sjbeloro  * 16 GPIO pin(s) to set.
458d58fda43Sjbeloro  */
459d58fda43Sjbeloro static int
460d58fda43Sjbeloro adm1026_set_output(adm1026_unit_t *unitp, uint32_t val, uint32_t mask)
461d58fda43Sjbeloro {
462d58fda43Sjbeloro 	int err = I2C_SUCCESS;
463d58fda43Sjbeloro 
464d58fda43Sjbeloro 	if (mask & 0xff)
465d58fda43Sjbeloro 		err = adm1026_send8(unitp, ADM1026_STS_REG5, (uint8_t)val,
466d58fda43Sjbeloro 		    (uint8_t)mask);
467d58fda43Sjbeloro 
468d58fda43Sjbeloro 	if ((err == I2C_SUCCESS) && (mask & 0xff00))
469d58fda43Sjbeloro 		err = adm1026_send8(unitp, ADM1026_STS_REG6,
470d58fda43Sjbeloro 		    (uint8_t)(val >> OUTPUT_SHIFT),
471d58fda43Sjbeloro 		    (uint8_t)(mask >> OUTPUT_SHIFT));
472d58fda43Sjbeloro 
473d58fda43Sjbeloro 	return (err);
474d58fda43Sjbeloro }
475d58fda43Sjbeloro 
476d58fda43Sjbeloro /*
477d58fda43Sjbeloro  * adm1026_get_output:
478d58fda43Sjbeloro  * The low 16 bits of the mask is a 1:1 mask indicating which of the
479d58fda43Sjbeloro  * 16 GPIO pin(s) to get.
480d58fda43Sjbeloro  */
481d58fda43Sjbeloro static int
482d58fda43Sjbeloro adm1026_get_output(adm1026_unit_t *unitp, uint32_t mask, uint32_t *val)
483d58fda43Sjbeloro {
484d58fda43Sjbeloro 	uint8_t reg_val = 0;
485d58fda43Sjbeloro 	int err = I2C_SUCCESS;
486d58fda43Sjbeloro 
487d58fda43Sjbeloro 	if (mask & 0xff) {
488d58fda43Sjbeloro 		err = adm1026_get8(unitp, ADM1026_STS_REG5, &reg_val);
489d58fda43Sjbeloro 		if (err != I2C_SUCCESS)
490d58fda43Sjbeloro 			return (err);
491d58fda43Sjbeloro 
492d58fda43Sjbeloro 		*val = reg_val;
493d58fda43Sjbeloro 	}
494d58fda43Sjbeloro 
495d58fda43Sjbeloro 	if (mask & 0xff00) {
496d58fda43Sjbeloro 		err = adm1026_get8(unitp, ADM1026_STS_REG6, &reg_val);
497d58fda43Sjbeloro 		if (err != I2C_SUCCESS)
498d58fda43Sjbeloro 			return (err);
499d58fda43Sjbeloro 
500d58fda43Sjbeloro 		*val |= ((reg_val << OUTPUT_SHIFT) & (mask & 0xff00));
501d58fda43Sjbeloro 	}
502d58fda43Sjbeloro 
503d58fda43Sjbeloro 	return (err);
504d58fda43Sjbeloro }
505d58fda43Sjbeloro 
506d58fda43Sjbeloro /*
507d58fda43Sjbeloro  * adm1026_set_config:
508d58fda43Sjbeloro  * The low 16 bits of the mask is a 1:1 mask indicating which of the
509d58fda43Sjbeloro  * 16 GPIO pin(s) to set the polarity or direction configuration for.
510d58fda43Sjbeloro  * Each GPIO pin has 2 bits of configuration - 1 polarity bit and 1
511d58fda43Sjbeloro  * direction bit.  Traverse the mask 4 bits at a time to determine
512d58fda43Sjbeloro  * which of the 4 GPIO Config registers to access and apply the value
513d58fda43Sjbeloro  * based on whether cmd is GPIO_SET_CONFIG (set Direction) or
514d58fda43Sjbeloro  * GPIO_SET_POLARITY.
515d58fda43Sjbeloro  */
516d58fda43Sjbeloro static int
517d58fda43Sjbeloro adm1026_set_config(adm1026_unit_t *unitp, int cmd, uint32_t val, uint32_t mask)
518d58fda43Sjbeloro {
519d58fda43Sjbeloro 	int i;
520d58fda43Sjbeloro 	uint8_t r;
521d58fda43Sjbeloro 	uint32_t m = mask, v = val;
522d58fda43Sjbeloro 	int err = I2C_SUCCESS;
523d58fda43Sjbeloro 
524d58fda43Sjbeloro 	for (i = 0, r = ADM1026_GPIO_CFG1; i < BYTES_PER_CONFIG; i++, r++) {
525d58fda43Sjbeloro 		if (m & GPIO_CFG_MASK) {
526d58fda43Sjbeloro 			int j;
527d58fda43Sjbeloro 			uint8_t mm = 0, vv = 0;
528d58fda43Sjbeloro 			uint8_t bit = (cmd == GPIO_SET_CONFIG) ?
529d58fda43Sjbeloro 			    DIR_BIT : POLARITY_BIT;
530d58fda43Sjbeloro 
531d58fda43Sjbeloro 			for (j = 0; j < GPIOS_PER_CFG_BYTE; j++) {
532d58fda43Sjbeloro 				if (m & (1 << j)) {
533d58fda43Sjbeloro 					mm |= (bit << (j * BITSPERCFG));
534d58fda43Sjbeloro 				}
535d58fda43Sjbeloro 				if (v & (1 << j)) {
536d58fda43Sjbeloro 					vv |= (bit << (j * BITSPERCFG));
537d58fda43Sjbeloro 				}
538d58fda43Sjbeloro 			}
539d58fda43Sjbeloro 			D2CMN_ERR((CE_WARN, "adm1026_set_config: r=%02x, "
540d58fda43Sjbeloro 			    "vv=%02x, mm=%02x, m=%02x", r, vv, mm, m));
541d58fda43Sjbeloro 			err = adm1026_send8(unitp, r, vv, mm);
542d58fda43Sjbeloro 			if (err != I2C_SUCCESS)
543d58fda43Sjbeloro 				return (err);
544d58fda43Sjbeloro 		}
545d58fda43Sjbeloro 		m >>= GPIOS_PER_CFG_BYTE;
546d58fda43Sjbeloro 		v >>= GPIOS_PER_CFG_BYTE;
547d58fda43Sjbeloro 	}
548d58fda43Sjbeloro 	return (err);
549d58fda43Sjbeloro }
550d58fda43Sjbeloro 
551d58fda43Sjbeloro /*
552d58fda43Sjbeloro  * adm1026_get_config:
553d58fda43Sjbeloro  * The low 16 bits of the mask is a 1:1 mask indicating which of the
554d58fda43Sjbeloro  * 16 GPIO pin(s) to get the polarity or direction configuration for.
555d58fda43Sjbeloro  * Each GPIO pin has 2 bits of configuration - 1 polarity bit and 1
556d58fda43Sjbeloro  * direction bit.  Traverse the mask 4 bits at a time to determine
557d58fda43Sjbeloro  * which of the 4 GPIO Config registers to access and build the return
558d58fda43Sjbeloro  * value based on whether cmd is GPIO_GET_CONFIG (get Direction) or
559d58fda43Sjbeloro  * GPIO_GET_POLARITY.
560d58fda43Sjbeloro  */
561d58fda43Sjbeloro static int
562d58fda43Sjbeloro adm1026_get_config(adm1026_unit_t *unitp, int cmd, uint32_t mask, uint32_t *val)
563d58fda43Sjbeloro {
564d58fda43Sjbeloro 	int i, j;
565d58fda43Sjbeloro 	uint8_t r;
566d58fda43Sjbeloro 	int err = I2C_SUCCESS;
567d58fda43Sjbeloro 
568d58fda43Sjbeloro 	*val = 0;
569d58fda43Sjbeloro 
570d58fda43Sjbeloro 	for (i = 0, r = ADM1026_GPIO_CFG1; i < BYTES_PER_CONFIG; i++, r++) {
571d58fda43Sjbeloro 		if (mask & GPIO_CFG_MASK) {
572d58fda43Sjbeloro 			uint8_t newval = 0, x;
573d58fda43Sjbeloro 			uint8_t bit = (cmd == GPIO_GET_CONFIG) ?
574d58fda43Sjbeloro 			    DIR_BIT : POLARITY_BIT;
575d58fda43Sjbeloro 
576d58fda43Sjbeloro 			err = adm1026_get8(unitp, r, &x);
577d58fda43Sjbeloro 			if (err != I2C_SUCCESS)
578d58fda43Sjbeloro 				return (err);
579d58fda43Sjbeloro 			for (j = 0; j < GPIOS_PER_CFG_BYTE; j++) {
580d58fda43Sjbeloro 				if (mask & (1 << j)) {
581d58fda43Sjbeloro 					if (x & (bit << (j * BITSPERCFG)))
582d58fda43Sjbeloro 						newval |= (1 << j);
583d58fda43Sjbeloro 				}
584d58fda43Sjbeloro 			}
585d58fda43Sjbeloro 			*val |= (newval << (i * GPIOS_PER_CFG_BYTE));
586d58fda43Sjbeloro 		} else
587d58fda43Sjbeloro 			*val <<= GPIOS_PER_CFG_BYTE;
588d58fda43Sjbeloro 
589d58fda43Sjbeloro 		mask >>= GPIOS_PER_CFG_BYTE;
590d58fda43Sjbeloro 	}
591d58fda43Sjbeloro 	return (err);
592d58fda43Sjbeloro }
593d58fda43Sjbeloro 
594d58fda43Sjbeloro static int
595d58fda43Sjbeloro adm1026_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
596d58fda43Sjbeloro 		int *rvalp)
597d58fda43Sjbeloro {
598d58fda43Sjbeloro 	_NOTE(ARGUNUSED(credp, rvalp))
599d58fda43Sjbeloro 
600d58fda43Sjbeloro 	adm1026_unit_t		*unitp;
601d58fda43Sjbeloro 	int			instance;
602d58fda43Sjbeloro 	int			err = DDI_SUCCESS;
603d58fda43Sjbeloro 	i2c_gpio_t		g_buf;
604d58fda43Sjbeloro 
605d58fda43Sjbeloro 	instance = getminor(dev);
606d58fda43Sjbeloro 
607d58fda43Sjbeloro 	D2CMN_ERR((CE_WARN, "adm1026_ioctl: instance=%d, cmd=%x\n",
608d58fda43Sjbeloro 	    instance, cmd));
609d58fda43Sjbeloro 
610d58fda43Sjbeloro 	unitp = (struct adm1026_unit *)
611d58fda43Sjbeloro 	    ddi_get_soft_state(adm1026soft_statep, instance);
612d58fda43Sjbeloro 
613d58fda43Sjbeloro 	if (unitp == NULL) {
614d58fda43Sjbeloro 		cmn_err(CE_WARN, "adm1026_ioctl: ddi_get_soft_state failed");
615d58fda43Sjbeloro 		err = ENOMEM;
616d58fda43Sjbeloro 		return (err);
617d58fda43Sjbeloro 	}
618d58fda43Sjbeloro 
619d58fda43Sjbeloro 	mutex_enter(&unitp->adm1026_mutex);
620d58fda43Sjbeloro 
621d58fda43Sjbeloro 	if (ddi_copyin((caddr_t)arg, &g_buf,
622d58fda43Sjbeloro 	    sizeof (i2c_gpio_t), mode) != DDI_SUCCESS) {
623d58fda43Sjbeloro 
624d58fda43Sjbeloro 		mutex_exit(&unitp->adm1026_mutex);
625d58fda43Sjbeloro 		return (EFAULT);
626d58fda43Sjbeloro 	}
627d58fda43Sjbeloro 	if (g_buf.reg_mask & 0xffff0000) {
628d58fda43Sjbeloro 		cmn_err(CE_WARN,
629d58fda43Sjbeloro 		    "adm1026_ioctl: reg_mask too large. "
630d58fda43Sjbeloro 		    "Only bits 15-0 supported");
631d58fda43Sjbeloro 		mutex_exit(&unitp->adm1026_mutex);
632d58fda43Sjbeloro 		return (EINVAL);
633d58fda43Sjbeloro 	}
634d58fda43Sjbeloro 	switch (cmd) {
635d58fda43Sjbeloro 	case GPIO_SET_OUTPUT:
636d58fda43Sjbeloro 		err = adm1026_set_output(unitp, g_buf.reg_val, g_buf.reg_mask);
637d58fda43Sjbeloro 		break;
638d58fda43Sjbeloro 
639d58fda43Sjbeloro 	case GPIO_GET_OUTPUT:
640d58fda43Sjbeloro 		err = adm1026_get_output(unitp, g_buf.reg_mask, &g_buf.reg_val);
641d58fda43Sjbeloro 		if (err == DDI_SUCCESS)
642d58fda43Sjbeloro 			err = ddi_copyout(&g_buf, (caddr_t)arg,
643d58fda43Sjbeloro 			    sizeof (i2c_gpio_t), mode);
644d58fda43Sjbeloro 		break;
645d58fda43Sjbeloro 
646d58fda43Sjbeloro 	case GPIO_SET_CONFIG:
647d58fda43Sjbeloro 	case GPIO_SET_POLARITY:
648d58fda43Sjbeloro 		err = adm1026_set_config(unitp, cmd, g_buf.reg_val,
649d58fda43Sjbeloro 		    g_buf.reg_mask);
650d58fda43Sjbeloro 		break;
651d58fda43Sjbeloro 
652d58fda43Sjbeloro 	case GPIO_GET_CONFIG:
653d58fda43Sjbeloro 	case GPIO_GET_POLARITY:
654d58fda43Sjbeloro 		err = adm1026_get_config(unitp, cmd, g_buf.reg_mask,
655d58fda43Sjbeloro 		    &g_buf.reg_val);
656d58fda43Sjbeloro 		if (err == DDI_SUCCESS)
657d58fda43Sjbeloro 			err = ddi_copyout(&g_buf, (caddr_t)arg,
658d58fda43Sjbeloro 			    sizeof (i2c_gpio_t), mode);
659d58fda43Sjbeloro 		break;
660d58fda43Sjbeloro 	default:
661d58fda43Sjbeloro 		D2CMN_ERR((CE_WARN,
662d58fda43Sjbeloro 		    "adm1026_ioctl: Invalid ioctl cmd %x\n", cmd));
663d58fda43Sjbeloro 		err = EINVAL;
664d58fda43Sjbeloro 	}
665d58fda43Sjbeloro 	mutex_exit(&unitp->adm1026_mutex);
666d58fda43Sjbeloro 
667d58fda43Sjbeloro 	if (err) {
668d58fda43Sjbeloro 		D2CMN_ERR((CE_WARN,
669d58fda43Sjbeloro 		    "adm1026_ioctl: failed, err=%x\n", err));
670d58fda43Sjbeloro 		if (err == DDI_FAILURE)
671d58fda43Sjbeloro 			err = EIO;
672d58fda43Sjbeloro 	}
673d58fda43Sjbeloro 
674d58fda43Sjbeloro 	return (err);
675d58fda43Sjbeloro }
676