1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/systm.h> 31 #include <sys/ddi.h> 32 #include <sys/sysmacros.h> 33 #include <sys/archsystm.h> 34 #include <sys/vmsystm.h> 35 #include <sys/machparam.h> 36 #include <sys/machsystm.h> 37 #include <sys/machthread.h> 38 #include <sys/cpu.h> 39 #include <sys/cmp.h> 40 #include <sys/elf_SPARC.h> 41 #include <vm/hat_sfmmu.h> 42 #include <vm/seg_kmem.h> 43 #include <sys/cpuvar.h> 44 #include <sys/cheetahregs.h> 45 #include <sys/us3_module.h> 46 #include <sys/async.h> 47 #include <sys/cmn_err.h> 48 #include <sys/debug.h> 49 #include <sys/dditypes.h> 50 #include <sys/prom_debug.h> 51 #include <sys/prom_plat.h> 52 #include <sys/cpu_module.h> 53 #include <sys/sysmacros.h> 54 #include <sys/intreg.h> 55 #include <sys/clock.h> 56 #include <sys/platform_module.h> 57 #include <sys/machtrap.h> 58 #include <sys/ontrap.h> 59 #include <sys/panic.h> 60 #include <sys/memlist.h> 61 #include <sys/bootconf.h> 62 #include <sys/ivintr.h> 63 #include <sys/atomic.h> 64 #include <sys/fm/protocol.h> 65 #include <sys/fm/cpu/UltraSPARC-III.h> 66 #include <sys/fm/util.h> 67 68 #ifdef CHEETAHPLUS_ERRATUM_25 69 #include <sys/cyclic.h> 70 #endif /* CHEETAHPLUS_ERRATUM_25 */ 71 72 /* 73 * See comment above cpu_scrub_cpu_setup() for description 74 */ 75 #define SCRUBBER_NEITHER_CORE_ONLINE 0x0 76 #define SCRUBBER_CORE_0_ONLINE 0x1 77 #define SCRUBBER_CORE_1_ONLINE 0x2 78 #define SCRUBBER_BOTH_CORES_ONLINE (SCRUBBER_CORE_0_ONLINE | \ 79 SCRUBBER_CORE_1_ONLINE) 80 81 static int pn_matching_valid_l2_line(uint64_t faddr, ch_ec_data_t *clo_l2_data); 82 static void cpu_async_log_tlb_parity_err(void *flt); 83 static cpu_t *cpu_get_sibling_core(cpu_t *cpup); 84 85 86 /* 87 * Setup trap handlers. 88 */ 89 void 90 cpu_init_trap(void) 91 { 92 CH_SET_TRAP(tt_pil15, ch_pil15_interrupt_instr); 93 94 CH_SET_TRAP(tt0_fecc, fecc_err_instr); 95 CH_SET_TRAP(tt1_fecc, fecc_err_tl1_instr); 96 CH_SET_TRAP(tt1_swtrap0, fecc_err_tl1_cont_instr); 97 98 CH_SET_TRAP(tt0_dperr, dcache_parity_instr); 99 CH_SET_TRAP(tt1_dperr, dcache_parity_tl1_instr); 100 CH_SET_TRAP(tt1_swtrap1, dcache_parity_tl1_cont_instr); 101 102 CH_SET_TRAP(tt0_iperr, icache_parity_instr); 103 CH_SET_TRAP(tt1_iperr, icache_parity_tl1_instr); 104 CH_SET_TRAP(tt1_swtrap2, icache_parity_tl1_cont_instr); 105 } 106 107 /* 108 * Set the magic constants of the implementation. 109 */ 110 /*ARGSUSED*/ 111 void 112 cpu_fiximp(dnode_t dnode) 113 { 114 int i, a; 115 extern int vac_size, vac_shift; 116 extern uint_t vac_mask; 117 118 dcache_size = CH_DCACHE_SIZE; 119 dcache_linesize = CH_DCACHE_LSIZE; 120 121 icache_size = CHP_ICACHE_MAX_SIZE; 122 icache_linesize = CHP_ICACHE_MIN_LSIZE; 123 124 ecache_size = CH_ECACHE_MAX_SIZE; 125 ecache_alignsize = CH_ECACHE_MAX_LSIZE; 126 ecache_associativity = CHP_ECACHE_MIN_NWAY; 127 128 /* 129 * ecache_setsize needs to maximum of all cpu ecache setsizes 130 */ 131 ecache_setsize = CHP_ECACHE_MAX_SETSIZE; 132 ASSERT(ecache_setsize >= (ecache_size / ecache_associativity)); 133 134 vac_size = CH_VAC_SIZE; 135 vac_mask = MMU_PAGEMASK & (vac_size - 1); 136 i = 0; a = vac_size; 137 while (a >>= 1) 138 ++i; 139 vac_shift = i; 140 shm_alignment = vac_size; 141 vac = 1; 142 } 143 144 /* 145 * Use Panther values for Panther-only domains. 146 * See Panther PRM, 1.5.4 Cache Hierarchy 147 */ 148 void 149 cpu_fix_allpanther(void) 150 { 151 /* dcache same as Ch+ */ 152 icache_size = PN_ICACHE_SIZE; 153 icache_linesize = PN_ICACHE_LSIZE; 154 ecache_size = PN_L3_SIZE; 155 ecache_alignsize = PN_L3_LINESIZE; 156 ecache_associativity = PN_L3_NWAYS; 157 ecache_setsize = PN_L3_SET_SIZE; 158 ASSERT(ecache_setsize >= (ecache_size / ecache_associativity)); 159 /* vac same as Ch+ */ 160 } 161 162 void 163 send_mondo_set(cpuset_t set) 164 { 165 int lo, busy, nack, shipped = 0; 166 uint16_t i, cpuids[IDSR_BN_SETS]; 167 uint64_t idsr, nackmask = 0, busymask, curnack, curbusy; 168 uint64_t starttick, endtick, tick, lasttick; 169 #if (NCPU > IDSR_BN_SETS) 170 int index = 0; 171 int ncpuids = 0; 172 #endif 173 #ifdef CHEETAHPLUS_ERRATUM_25 174 int recovered = 0; 175 int cpuid; 176 #endif 177 178 ASSERT(!CPUSET_ISNULL(set)); 179 starttick = lasttick = gettick(); 180 181 #if (NCPU <= IDSR_BN_SETS) 182 for (i = 0; i < NCPU; i++) 183 if (CPU_IN_SET(set, i)) { 184 shipit(i, shipped); 185 nackmask |= IDSR_NACK_BIT(shipped); 186 cpuids[shipped++] = i; 187 CPUSET_DEL(set, i); 188 if (CPUSET_ISNULL(set)) 189 break; 190 } 191 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped); 192 #else 193 for (i = 0; i < NCPU; i++) 194 if (CPU_IN_SET(set, i)) { 195 ncpuids++; 196 197 /* 198 * Ship only to the first (IDSR_BN_SETS) CPUs. If we 199 * find we have shipped to more than (IDSR_BN_SETS) 200 * CPUs, set "index" to the highest numbered CPU in 201 * the set so we can ship to other CPUs a bit later on. 202 */ 203 if (shipped < IDSR_BN_SETS) { 204 shipit(i, shipped); 205 nackmask |= IDSR_NACK_BIT(shipped); 206 cpuids[shipped++] = i; 207 CPUSET_DEL(set, i); 208 if (CPUSET_ISNULL(set)) 209 break; 210 } else 211 index = (int)i; 212 } 213 214 CPU_STATS_ADDQ(CPU, sys, xcalls, ncpuids); 215 #endif 216 217 busymask = IDSR_NACK_TO_BUSY(nackmask); 218 busy = nack = 0; 219 endtick = starttick + xc_tick_limit; 220 for (;;) { 221 idsr = getidsr(); 222 #if (NCPU <= IDSR_BN_SETS) 223 if (idsr == 0) 224 break; 225 #else 226 if (idsr == 0 && shipped == ncpuids) 227 break; 228 #endif 229 tick = gettick(); 230 /* 231 * If there is a big jump between the current tick 232 * count and lasttick, we have probably hit a break 233 * point. Adjust endtick accordingly to avoid panic. 234 */ 235 if (tick > (lasttick + xc_tick_jump_limit)) 236 endtick += (tick - lasttick); 237 lasttick = tick; 238 if (tick > endtick) { 239 if (panic_quiesce) 240 return; 241 #ifdef CHEETAHPLUS_ERRATUM_25 242 cpuid = -1; 243 for (i = 0; i < IDSR_BN_SETS; i++) { 244 if (idsr & (IDSR_NACK_BIT(i) | 245 IDSR_BUSY_BIT(i))) { 246 cpuid = cpuids[i]; 247 break; 248 } 249 } 250 if (cheetah_sendmondo_recover && cpuid != -1 && 251 recovered == 0) { 252 if (mondo_recover(cpuid, i)) { 253 /* 254 * We claimed the whole memory or 255 * full scan is disabled. 256 */ 257 recovered++; 258 } 259 tick = gettick(); 260 endtick = tick + xc_tick_limit; 261 lasttick = tick; 262 /* 263 * Recheck idsr 264 */ 265 continue; 266 } else 267 #endif /* CHEETAHPLUS_ERRATUM_25 */ 268 { 269 cmn_err(CE_CONT, "send mondo timeout " 270 "[%d NACK %d BUSY]\nIDSR 0x%" 271 "" PRIx64 " cpuids:", nack, busy, idsr); 272 for (i = 0; i < IDSR_BN_SETS; i++) { 273 if (idsr & (IDSR_NACK_BIT(i) | 274 IDSR_BUSY_BIT(i))) { 275 cmn_err(CE_CONT, " 0x%x", 276 cpuids[i]); 277 } 278 } 279 cmn_err(CE_CONT, "\n"); 280 cmn_err(CE_PANIC, "send_mondo_set: timeout"); 281 } 282 } 283 curnack = idsr & nackmask; 284 curbusy = idsr & busymask; 285 #if (NCPU > IDSR_BN_SETS) 286 if (shipped < ncpuids) { 287 uint64_t cpus_left; 288 uint16_t next = (uint16_t)index; 289 290 cpus_left = ~(IDSR_NACK_TO_BUSY(curnack) | curbusy) & 291 busymask; 292 293 if (cpus_left) { 294 do { 295 /* 296 * Sequence through and ship to the 297 * remainder of the CPUs in the system 298 * (e.g. other than the first 299 * (IDSR_BN_SETS)) in reverse order. 300 */ 301 lo = lowbit(cpus_left) - 1; 302 i = IDSR_BUSY_IDX(lo); 303 shipit(next, i); 304 shipped++; 305 cpuids[i] = next; 306 307 /* 308 * If we've processed all the CPUs, 309 * exit the loop now and save 310 * instructions. 311 */ 312 if (shipped == ncpuids) 313 break; 314 315 for ((index = ((int)next - 1)); 316 index >= 0; index--) 317 if (CPU_IN_SET(set, index)) { 318 next = (uint16_t)index; 319 break; 320 } 321 322 cpus_left &= ~(1ull << lo); 323 } while (cpus_left); 324 #ifdef CHEETAHPLUS_ERRATUM_25 325 /* 326 * Clear recovered because we are sending to 327 * a new set of targets. 328 */ 329 recovered = 0; 330 #endif 331 continue; 332 } 333 } 334 #endif 335 if (curbusy) { 336 busy++; 337 continue; 338 } 339 340 #ifdef SEND_MONDO_STATS 341 { 342 int n = gettick() - starttick; 343 if (n < 8192) 344 x_nack_stimes[n >> 7]++; 345 } 346 #endif 347 while (gettick() < (tick + sys_clock_mhz)) 348 ; 349 do { 350 lo = lowbit(curnack) - 1; 351 i = IDSR_NACK_IDX(lo); 352 shipit(cpuids[i], i); 353 curnack &= ~(1ull << lo); 354 } while (curnack); 355 nack++; 356 busy = 0; 357 } 358 #ifdef SEND_MONDO_STATS 359 { 360 int n = gettick() - starttick; 361 if (n < 8192) 362 x_set_stimes[n >> 7]++; 363 else 364 x_set_ltimes[(n >> 13) & 0xf]++; 365 } 366 x_set_cpus[shipped]++; 367 #endif 368 } 369 370 /* 371 * Handles error logging for implementation specific error types 372 */ 373 /*ARGSUSED1*/ 374 int 375 cpu_impl_async_log_err(void *flt, errorq_elem_t *eqep) 376 { 377 ch_async_flt_t *ch_flt = (ch_async_flt_t *)flt; 378 struct async_flt *aflt = (struct async_flt *)flt; 379 380 switch (ch_flt->flt_type) { 381 382 case CPU_IC_PARITY: 383 cpu_async_log_ic_parity_err(flt); 384 return (CH_ASYNC_LOG_DONE); 385 386 case CPU_DC_PARITY: 387 cpu_async_log_dc_parity_err(flt); 388 return (CH_ASYNC_LOG_DONE); 389 390 case CPU_DUE: 391 cpu_log_err(aflt); 392 cpu_page_retire(ch_flt); 393 return (CH_ASYNC_LOG_DONE); 394 395 case CPU_ITLB_PARITY: 396 case CPU_DTLB_PARITY: 397 cpu_async_log_tlb_parity_err(flt); 398 return (CH_ASYNC_LOG_DONE); 399 400 default: 401 return (CH_ASYNC_LOG_UNKNOWN); 402 } 403 } 404 405 /* 406 * Figure out if Ecache is direct-mapped (Cheetah or Cheetah+ with Ecache 407 * control ECCR_ASSOC bit off or 2-way (Cheetah+ with ECCR_ASSOC on). 408 * We need to do this on the fly because we may have mixed Cheetah+'s with 409 * both direct and 2-way Ecaches. Panther only supports 4-way L3$. 410 */ 411 int 412 cpu_ecache_nway(void) 413 { 414 if (IS_PANTHER(cpunodes[CPU->cpu_id].implementation)) 415 return (PN_L3_NWAYS); 416 return ((get_ecache_ctrl() & ECCR_ASSOC) ? 2 : 1); 417 } 418 419 /* 420 * Note that these are entered into the table: Fatal Errors (PERR, IERR, ISAP, 421 * EMU, IMU) first, orphaned UCU/UCC, AFAR Overwrite policy, finally IVU, IVC. 422 * Afar overwrite policy is: 423 * Class 4: 424 * AFSR -- UCC, UCU, TUE, TSCE, TUE_SH 425 * AFSR_EXT -- L3_UCC, L3_UCU, L3_TUE, L3_TUE_SH 426 * Class 3: 427 * AFSR -- UE, DUE, EDU, WDU, CPU 428 * AFSR_EXT -- L3_EDU, L3_WDU, L3_CPU 429 * Class 2: 430 * AFSR -- CE, EDC, EMC, WDC, CPC, THCE 431 * AFSR_EXT -- L3_EDC, L3_WDC, L3_CPC, L3_THCE 432 * Class 1: 433 * AFSR -- TO, DTO, BERR, DBERR 434 */ 435 ecc_type_to_info_t ecc_type_to_info[] = { 436 437 /* Fatal Errors */ 438 C_AFSR_PERR, "PERR ", ECC_ALL_TRAPS, 439 CPU_FATAL, "PERR Fatal", 440 FM_EREPORT_PAYLOAD_SYSTEM2, 441 FM_EREPORT_CPU_USIII_PERR, 442 C_AFSR_IERR, "IERR ", ECC_ALL_TRAPS, 443 CPU_FATAL, "IERR Fatal", 444 FM_EREPORT_PAYLOAD_SYSTEM2, 445 FM_EREPORT_CPU_USIII_IERR, 446 C_AFSR_ISAP, "ISAP ", ECC_ALL_TRAPS, 447 CPU_FATAL, "ISAP Fatal", 448 FM_EREPORT_PAYLOAD_SYSTEM1, 449 FM_EREPORT_CPU_USIII_ISAP, 450 C_AFSR_L3_TUE_SH, "L3_TUE_SH ", ECC_C_TRAP, 451 CPU_FATAL, "L3_TUE_SH Fatal", 452 FM_EREPORT_PAYLOAD_L3_TAG_ECC, 453 FM_EREPORT_CPU_USIII_L3_TUE_SH, 454 C_AFSR_L3_TUE, "L3_TUE ", ECC_C_TRAP, 455 CPU_FATAL, "L3_TUE Fatal", 456 FM_EREPORT_PAYLOAD_L3_TAG_ECC, 457 FM_EREPORT_CPU_USIII_L3_TUE, 458 C_AFSR_TUE_SH, "TUE_SH ", ECC_C_TRAP, 459 CPU_FATAL, "TUE_SH Fatal", 460 FM_EREPORT_PAYLOAD_L2_TAG_ECC, 461 FM_EREPORT_CPU_USIII_TUE_SH, 462 C_AFSR_TUE, "TUE ", ECC_ALL_TRAPS, 463 CPU_FATAL, "TUE Fatal", 464 FM_EREPORT_PAYLOAD_L2_TAG_ECC, 465 FM_EREPORT_CPU_USIII_TUE, 466 C_AFSR_EMU, "EMU ", ECC_ASYNC_TRAPS, 467 CPU_FATAL, "EMU Fatal", 468 FM_EREPORT_PAYLOAD_MEMORY, 469 FM_EREPORT_CPU_USIII_EMU, 470 C_AFSR_IMU, "IMU ", ECC_C_TRAP, 471 CPU_FATAL, "IMU Fatal", 472 FM_EREPORT_PAYLOAD_SYSTEM1, 473 FM_EREPORT_CPU_USIII_IMU, 474 475 /* L3$ Address parity errors are reported via the MECC bit */ 476 C_AFSR_L3_MECC, "L3_MECC ", ECC_MECC_TRAPS, 477 CPU_L3_ADDR_PE, "L3 Address Parity", 478 FM_EREPORT_PAYLOAD_L3_DATA, 479 FM_EREPORT_CPU_USIII_L3_MECC, 480 481 /* Orphaned UCC/UCU Errors */ 482 C_AFSR_L3_UCU, "L3_OUCU ", ECC_ORPH_TRAPS, 483 CPU_ORPH, "Orphaned L3_UCU", 484 FM_EREPORT_PAYLOAD_L3_DATA, 485 FM_EREPORT_CPU_USIII_L3_UCU, 486 C_AFSR_L3_UCC, "L3_OUCC ", ECC_ORPH_TRAPS, 487 CPU_ORPH, "Orphaned L3_UCC", 488 FM_EREPORT_PAYLOAD_L3_DATA, 489 FM_EREPORT_CPU_USIII_L3_UCC, 490 C_AFSR_UCU, "OUCU ", ECC_ORPH_TRAPS, 491 CPU_ORPH, "Orphaned UCU", 492 FM_EREPORT_PAYLOAD_L2_DATA, 493 FM_EREPORT_CPU_USIII_UCU, 494 C_AFSR_UCC, "OUCC ", ECC_ORPH_TRAPS, 495 CPU_ORPH, "Orphaned UCC", 496 FM_EREPORT_PAYLOAD_L2_DATA, 497 FM_EREPORT_CPU_USIII_UCC, 498 499 /* UCU, UCC */ 500 C_AFSR_L3_UCU, "L3_UCU ", ECC_F_TRAP, 501 CPU_UE_ECACHE, "L3_UCU", 502 FM_EREPORT_PAYLOAD_L3_DATA, 503 FM_EREPORT_CPU_USIII_L3_UCU, 504 C_AFSR_L3_UCC, "L3_UCC ", ECC_F_TRAP, 505 CPU_CE_ECACHE, "L3_UCC", 506 FM_EREPORT_PAYLOAD_L3_DATA, 507 FM_EREPORT_CPU_USIII_L3_UCC, 508 C_AFSR_UCU, "UCU ", ECC_F_TRAP, 509 CPU_UE_ECACHE, "UCU", 510 FM_EREPORT_PAYLOAD_L2_DATA, 511 FM_EREPORT_CPU_USIII_UCU, 512 C_AFSR_UCC, "UCC ", ECC_F_TRAP, 513 CPU_CE_ECACHE, "UCC", 514 FM_EREPORT_PAYLOAD_L2_DATA, 515 FM_EREPORT_CPU_USIII_UCC, 516 C_AFSR_TSCE, "TSCE ", ECC_F_TRAP, 517 CPU_CE_ECACHE, "TSCE", 518 FM_EREPORT_PAYLOAD_L2_TAG_ECC, 519 FM_EREPORT_CPU_USIII_TSCE, 520 521 /* UE, EDU:ST, EDU:BLD, WDU, CPU */ 522 C_AFSR_UE, "UE ", ECC_ASYNC_TRAPS, 523 CPU_UE, "Uncorrectable system bus (UE)", 524 FM_EREPORT_PAYLOAD_MEMORY, 525 FM_EREPORT_CPU_USIII_UE, 526 C_AFSR_L3_EDU, "L3_EDU ", ECC_C_TRAP, 527 CPU_UE_ECACHE_RETIRE, "L3_EDU:ST", 528 FM_EREPORT_PAYLOAD_L3_DATA, 529 FM_EREPORT_CPU_USIII_L3_EDUST, 530 C_AFSR_L3_EDU, "L3_EDU ", ECC_D_TRAP, 531 CPU_UE_ECACHE_RETIRE, "L3_EDU:BLD", 532 FM_EREPORT_PAYLOAD_L3_DATA, 533 FM_EREPORT_CPU_USIII_L3_EDUBL, 534 C_AFSR_L3_WDU, "L3_WDU ", ECC_C_TRAP, 535 CPU_UE_ECACHE_RETIRE, "L3_WDU", 536 FM_EREPORT_PAYLOAD_L3_DATA, 537 FM_EREPORT_CPU_USIII_L3_WDU, 538 C_AFSR_L3_CPU, "L3_CPU ", ECC_C_TRAP, 539 CPU_UE_ECACHE, "L3_CPU", 540 FM_EREPORT_PAYLOAD_L3_DATA, 541 FM_EREPORT_CPU_USIII_L3_CPU, 542 C_AFSR_EDU, "EDU ", ECC_C_TRAP, 543 CPU_UE_ECACHE_RETIRE, "EDU:ST", 544 FM_EREPORT_PAYLOAD_L2_DATA, 545 FM_EREPORT_CPU_USIII_EDUST, 546 C_AFSR_EDU, "EDU ", ECC_D_TRAP, 547 CPU_UE_ECACHE_RETIRE, "EDU:BLD", 548 FM_EREPORT_PAYLOAD_L2_DATA, 549 FM_EREPORT_CPU_USIII_EDUBL, 550 C_AFSR_WDU, "WDU ", ECC_C_TRAP, 551 CPU_UE_ECACHE_RETIRE, "WDU", 552 FM_EREPORT_PAYLOAD_L2_DATA, 553 FM_EREPORT_CPU_USIII_WDU, 554 C_AFSR_CPU, "CPU ", ECC_C_TRAP, 555 CPU_UE_ECACHE, "CPU", 556 FM_EREPORT_PAYLOAD_L2_DATA, 557 FM_EREPORT_CPU_USIII_CPU, 558 C_AFSR_DUE, "DUE ", ECC_C_TRAP, 559 CPU_DUE, "DUE", 560 FM_EREPORT_PAYLOAD_MEMORY, 561 FM_EREPORT_CPU_USIII_DUE, 562 563 /* CE, EDC, EMC, WDC, CPC */ 564 C_AFSR_CE, "CE ", ECC_C_TRAP, 565 CPU_CE, "Corrected system bus (CE)", 566 FM_EREPORT_PAYLOAD_MEMORY, 567 FM_EREPORT_CPU_USIII_CE, 568 C_AFSR_L3_EDC, "L3_EDC ", ECC_C_TRAP, 569 CPU_CE_ECACHE, "L3_EDC", 570 FM_EREPORT_PAYLOAD_L3_DATA, 571 FM_EREPORT_CPU_USIII_L3_EDC, 572 C_AFSR_EDC, "EDC ", ECC_C_TRAP, 573 CPU_CE_ECACHE, "EDC", 574 FM_EREPORT_PAYLOAD_L2_DATA, 575 FM_EREPORT_CPU_USIII_EDC, 576 C_AFSR_EMC, "EMC ", ECC_C_TRAP, 577 CPU_EMC, "EMC", 578 FM_EREPORT_PAYLOAD_MEMORY, 579 FM_EREPORT_CPU_USIII_EMC, 580 C_AFSR_L3_WDC, "L3_WDC ", ECC_C_TRAP, 581 CPU_CE_ECACHE, "L3_WDC", 582 FM_EREPORT_PAYLOAD_L3_DATA, 583 FM_EREPORT_CPU_USIII_L3_WDC, 584 C_AFSR_L3_CPC, "L3_CPC ", ECC_C_TRAP, 585 CPU_CE_ECACHE, "L3_CPC", 586 FM_EREPORT_PAYLOAD_L3_DATA, 587 FM_EREPORT_CPU_USIII_L3_CPC, 588 C_AFSR_L3_THCE, "L3_THCE ", ECC_C_TRAP, 589 CPU_CE_ECACHE, "L3_THCE", 590 FM_EREPORT_PAYLOAD_L3_TAG_ECC, 591 FM_EREPORT_CPU_USIII_L3_THCE, 592 C_AFSR_WDC, "WDC ", ECC_C_TRAP, 593 CPU_CE_ECACHE, "WDC", 594 FM_EREPORT_PAYLOAD_L2_DATA, 595 FM_EREPORT_CPU_USIII_WDC, 596 C_AFSR_CPC, "CPC ", ECC_C_TRAP, 597 CPU_CE_ECACHE, "CPC", 598 FM_EREPORT_PAYLOAD_L2_DATA, 599 FM_EREPORT_CPU_USIII_CPC, 600 C_AFSR_THCE, "THCE ", ECC_C_TRAP, 601 CPU_CE_ECACHE, "THCE", 602 FM_EREPORT_PAYLOAD_L2_TAG_ECC, 603 FM_EREPORT_CPU_USIII_THCE, 604 605 /* TO, BERR */ 606 C_AFSR_TO, "TO ", ECC_ASYNC_TRAPS, 607 CPU_TO, "Timeout (TO)", 608 FM_EREPORT_PAYLOAD_IO, 609 FM_EREPORT_CPU_USIII_TO, 610 C_AFSR_BERR, "BERR ", ECC_ASYNC_TRAPS, 611 CPU_BERR, "Bus Error (BERR)", 612 FM_EREPORT_PAYLOAD_IO, 613 FM_EREPORT_CPU_USIII_BERR, 614 C_AFSR_DTO, "DTO ", ECC_C_TRAP, 615 CPU_TO, "Disrupting Timeout (DTO)", 616 FM_EREPORT_PAYLOAD_IO, 617 FM_EREPORT_CPU_USIII_DTO, 618 C_AFSR_DBERR, "DBERR ", ECC_C_TRAP, 619 CPU_BERR, "Disrupting Bus Error (DBERR)", 620 FM_EREPORT_PAYLOAD_IO, 621 FM_EREPORT_CPU_USIII_DBERR, 622 623 /* IVU, IVC, IMC */ 624 C_AFSR_IVU, "IVU ", ECC_C_TRAP, 625 CPU_IV, "IVU", 626 FM_EREPORT_PAYLOAD_SYSTEM1, 627 FM_EREPORT_CPU_USIII_IVU, 628 C_AFSR_IVC, "IVC ", ECC_C_TRAP, 629 CPU_IV, "IVC", 630 FM_EREPORT_PAYLOAD_SYSTEM1, 631 FM_EREPORT_CPU_USIII_IVC, 632 C_AFSR_IMC, "IMC ", ECC_C_TRAP, 633 CPU_IV, "IMC", 634 FM_EREPORT_PAYLOAD_SYSTEM1, 635 FM_EREPORT_CPU_USIII_IMC, 636 637 0, NULL, 0, 638 0, NULL, 639 FM_EREPORT_PAYLOAD_UNKNOWN, 640 FM_EREPORT_CPU_USIII_UNKNOWN, 641 }; 642 643 /* 644 * See Cheetah+ Delta PRM 10.9 and section P.6.1 of the Panther PRM 645 * Class 4: 646 * AFSR -- UCC, UCU, TUE, TSCE, TUE_SH 647 * AFSR_EXT -- L3_UCC, L3_UCU, L3_TUE, L3_TUE_SH 648 * Class 3: 649 * AFSR -- UE, DUE, EDU, EMU, WDU, CPU 650 * AFSR_EXT -- L3_EDU, L3_WDU, L3_CPU 651 * Class 2: 652 * AFSR -- CE, EDC, EMC, WDC, CPC, THCE 653 * AFSR_EXT -- L3_EDC, L3_WDC, L3_CPC, L3_THCE 654 * Class 1: 655 * AFSR -- TO, DTO, BERR, DBERR 656 * AFSR_EXT -- 657 */ 658 uint64_t afar_overwrite[] = { 659 /* class 4: */ 660 C_AFSR_UCC | C_AFSR_UCU | C_AFSR_TUE | C_AFSR_TSCE | C_AFSR_TUE_SH | 661 C_AFSR_L3_UCC | C_AFSR_L3_UCU | C_AFSR_L3_TUE | C_AFSR_L3_TUE_SH, 662 /* class 3: */ 663 C_AFSR_UE | C_AFSR_DUE | C_AFSR_EDU | C_AFSR_EMU | C_AFSR_WDU | 664 C_AFSR_CPU | C_AFSR_L3_EDU | C_AFSR_L3_WDU | C_AFSR_L3_CPU, 665 /* class 2: */ 666 C_AFSR_CE | C_AFSR_EDC | C_AFSR_EMC | C_AFSR_WDC | C_AFSR_CPC | 667 C_AFSR_THCE | C_AFSR_L3_EDC | C_AFSR_L3_WDC | C_AFSR_L3_CPC | 668 C_AFSR_L3_THCE, 669 /* class 1: */ 670 C_AFSR_TO | C_AFSR_DTO | C_AFSR_BERR | C_AFSR_DBERR, 671 672 0 673 }; 674 675 /* 676 * See Cheetah+ Delta PRM 10.9. 677 * Class 2: UE, DUE, IVU, EDU, WDU, UCU, CPU 678 * Class 1: CE, IVC, EDC, WDC, UCC, CPC 679 */ 680 uint64_t esynd_overwrite[] = { 681 /* class 2: */ 682 C_AFSR_UE | C_AFSR_DUE | C_AFSR_IVU | C_AFSR_EDU | C_AFSR_WDU | 683 C_AFSR_UCU | C_AFSR_CPU, 684 /* class 1: */ 685 C_AFSR_CE | C_AFSR_IVC | C_AFSR_EDC | C_AFSR_WDC | C_AFSR_UCC | 686 C_AFSR_CPC, 687 0 688 }; 689 690 /* 691 * In panther, the E_SYND overwrite policy changed a little bit 692 * by adding one more level. 693 * class 3: 694 * AFSR -- UCU, UCC 695 * AFSR_EXT -- L3_UCU, L3_UCC 696 * Class 2: 697 * AFSR -- UE, DUE, IVU, EDU, WDU, CPU 698 * AFSR_EXT -- L3_EDU, L3_WDU, L3_CPU 699 * Class 1: 700 * AFSR -- CE, IVC, EDC, WDC, CPC 701 * AFSR_EXT -- L3_EDC, L3_WDC, L3_CPC 702 */ 703 uint64_t pn_esynd_overwrite[] = { 704 /* class 3: */ 705 C_AFSR_UCU | C_AFSR_UCC | 706 C_AFSR_L3_UCU | C_AFSR_L3_UCC, 707 /* class 2: */ 708 C_AFSR_UE | C_AFSR_DUE | C_AFSR_IVU | C_AFSR_EDU | C_AFSR_WDU | 709 C_AFSR_CPU | 710 C_AFSR_L3_EDU | C_AFSR_L3_WDU | C_AFSR_L3_CPU, 711 /* class 1: */ 712 C_AFSR_CE | C_AFSR_IVC | C_AFSR_EDC | C_AFSR_WDC | C_AFSR_CPC | 713 C_AFSR_L3_EDC | C_AFSR_L3_WDC | C_AFSR_L3_CPC, 714 715 0 716 }; 717 718 int 719 afsr_to_pn_esynd_status(uint64_t afsr, uint64_t afsr_bit) 720 { 721 return (afsr_to_overw_status(afsr, afsr_bit, pn_esynd_overwrite)); 722 } 723 724 /* 725 * Prioritized list of Error bits for MSYND overwrite. 726 * See Cheetah PRM P.6.3 727 * Class 2: EMU 728 * Class 1: EMC 729 * 730 * Panther adds IMU and IMC. 731 */ 732 uint64_t msynd_overwrite[] = { 733 /* class 2: */ 734 C_AFSR_EMU | C_AFSR_IMU, 735 /* class 1: */ 736 C_AFSR_EMC | C_AFSR_IMC, 737 738 0 739 }; 740 741 /* 742 * change cpu speed bits -- new speed will be normal-speed/divisor. 743 * 744 * The Jalapeno memory controllers are required to drain outstanding 745 * memory transactions within 32 JBus clocks in order to be ready 746 * to enter Estar mode. In some corner cases however, that time 747 * fell short. 748 * 749 * A safe software solution is to force MCU to act like in Estar mode, 750 * then delay 1us (in ppm code) prior to assert J_CHNG_L signal. 751 * To reverse the effect, upon exiting Estar, software restores the 752 * MCU to its original state. 753 */ 754 /* ARGSUSED1 */ 755 void 756 cpu_change_speed(uint64_t divisor, uint64_t arg2) 757 { 758 bus_config_eclk_t *bceclk; 759 uint64_t reg; 760 761 for (bceclk = bus_config_eclk; bceclk->divisor; bceclk++) { 762 if (bceclk->divisor != divisor) 763 continue; 764 reg = get_safari_config(); 765 reg &= ~SAFARI_CONFIG_ECLK_MASK; 766 reg |= bceclk->mask; 767 set_safari_config(reg); 768 CPU->cpu_m.divisor = (uchar_t)divisor; 769 return; 770 } 771 /* 772 * We will reach here only if OBP and kernel don't agree on 773 * the speeds supported by the CPU. 774 */ 775 cmn_err(CE_WARN, "cpu_change_speed: bad divisor %" PRIu64, divisor); 776 } 777 778 /* 779 * Cpu private initialization. This includes allocating the cpu_private 780 * data structure, initializing it, and initializing the scrubber for this 781 * cpu. This function calls cpu_init_ecache_scrub_dr to init the scrubber. 782 * We use kmem_cache_create for the cheetah private data structure because 783 * it needs to be allocated on a PAGESIZE (8192) byte boundary. 784 */ 785 void 786 cpu_init_private(struct cpu *cp) 787 { 788 cheetah_private_t *chprp; 789 int i; 790 791 ASSERT(CPU_PRIVATE(cp) == NULL); 792 793 /* LINTED: E_TRUE_LOGICAL_EXPR */ 794 ASSERT((offsetof(cheetah_private_t, chpr_tl1_err_data) + 795 sizeof (ch_err_tl1_data_t) * CH_ERR_TL1_TLMAX) <= PAGESIZE); 796 797 /* 798 * Running with Cheetah CPUs in a Cheetah+, Jaguar, Panther or 799 * mixed Cheetah+/Jaguar/Panther machine is not a supported 800 * configuration. Attempting to do so may result in unpredictable 801 * failures (e.g. running Cheetah+ CPUs with Cheetah E$ disp flush) 802 * so don't allow it. 803 * 804 * This is just defensive code since this configuration mismatch 805 * should have been caught prior to OS execution. 806 */ 807 if (!(IS_CHEETAH_PLUS(cpunodes[cp->cpu_id].implementation) || 808 IS_JAGUAR(cpunodes[cp->cpu_id].implementation) || 809 IS_PANTHER(cpunodes[cp->cpu_id].implementation))) { 810 cmn_err(CE_PANIC, "CPU%d: UltraSPARC-III not supported" 811 " on UltraSPARC-III+/IV/IV+ code\n", cp->cpu_id); 812 } 813 814 /* 815 * If the ch_private_cache has not been created, create it. 816 */ 817 if (ch_private_cache == NULL) { 818 ch_private_cache = kmem_cache_create("ch_private_cache", 819 sizeof (cheetah_private_t), PAGESIZE, NULL, NULL, 820 NULL, NULL, static_arena, 0); 821 } 822 823 chprp = CPU_PRIVATE(cp) = kmem_cache_alloc(ch_private_cache, KM_SLEEP); 824 825 bzero(chprp, sizeof (cheetah_private_t)); 826 chprp->chpr_fecctl0_logout.clo_data.chd_afar = LOGOUT_INVALID; 827 chprp->chpr_cecc_logout.clo_data.chd_afar = LOGOUT_INVALID; 828 chprp->chpr_async_logout.clo_data.chd_afar = LOGOUT_INVALID; 829 chprp->chpr_tlb_logout.tlo_addr = LOGOUT_INVALID; 830 for (i = 0; i < CH_ERR_TL1_TLMAX; i++) 831 chprp->chpr_tl1_err_data[i].ch_err_tl1_logout.clo_data.chd_afar 832 = LOGOUT_INVALID; 833 834 /* Panther has a larger Icache compared to cheetahplus or Jaguar */ 835 if (IS_PANTHER(cpunodes[cp->cpu_id].implementation)) { 836 chprp->chpr_icache_size = PN_ICACHE_SIZE; 837 chprp->chpr_icache_linesize = PN_ICACHE_LSIZE; 838 } else { 839 chprp->chpr_icache_size = CH_ICACHE_SIZE; 840 chprp->chpr_icache_linesize = CH_ICACHE_LSIZE; 841 } 842 843 cpu_init_ecache_scrub_dr(cp); 844 845 /* 846 * Panther's L2$ and E$ are shared between cores, so the scrubber is 847 * only needed on one of the cores. At this point, we assume all cores 848 * are online, and we only enable the scrubber on core 0. 849 */ 850 if (IS_PANTHER(cpunodes[cp->cpu_id].implementation)) { 851 chprp->chpr_scrub_misc.chsm_core_state = 852 SCRUBBER_BOTH_CORES_ONLINE; 853 if (cp->cpu_id != (processorid_t)cmp_cpu_to_chip(cp->cpu_id)) { 854 chprp->chpr_scrub_misc.chsm_enable[ 855 CACHE_SCRUBBER_INFO_E] = 0; 856 } 857 } 858 859 chprp->chpr_ec_set_size = cpunodes[cp->cpu_id].ecache_size / 860 cpu_ecache_nway(); 861 862 adjust_hw_copy_limits(cpunodes[cp->cpu_id].ecache_size); 863 ch_err_tl1_paddrs[cp->cpu_id] = va_to_pa(chprp); 864 ASSERT(ch_err_tl1_paddrs[cp->cpu_id] != -1); 865 } 866 867 /* 868 * Clear the error state registers for this CPU. 869 * For Cheetah+/Jaguar, just clear the AFSR but 870 * for Panther we also have to clear the AFSR_EXT. 871 */ 872 void 873 set_cpu_error_state(ch_cpu_errors_t *cpu_error_regs) 874 { 875 set_asyncflt(cpu_error_regs->afsr & ~C_AFSR_FATAL_ERRS); 876 if (IS_PANTHER(cpunodes[CPU->cpu_id].implementation)) { 877 set_afsr_ext(cpu_error_regs->afsr_ext & ~C_AFSR_EXT_FATAL_ERRS); 878 } 879 } 880 881 void 882 pn_cpu_log_diag_l2_info(ch_async_flt_t *ch_flt) { 883 struct async_flt *aflt = (struct async_flt *)ch_flt; 884 ch_ec_data_t *l2_data = &ch_flt->flt_diag_data.chd_l2_data[0]; 885 uint64_t faddr = aflt->flt_addr; 886 uint8_t log_way_mask = 0; 887 int i; 888 889 /* 890 * Only Panther CPUs have the additional L2$ data that needs 891 * to be logged here 892 */ 893 if (!IS_PANTHER(cpunodes[aflt->flt_inst].implementation)) 894 return; 895 896 /* 897 * We'll use a simple bit mask to keep track of which way(s) 898 * of the stored cache line we want to log. The idea is to 899 * log the entry if it is a valid line and it matches our 900 * fault AFAR. If no match is found, we will simply log all 901 * the ways. 902 */ 903 for (i = 0; i < PN_L2_NWAYS; i++) 904 if (pn_matching_valid_l2_line(faddr, &l2_data[i])) 905 log_way_mask |= (1 << i); 906 907 /* If no matching valid lines were found, we log all ways */ 908 if (log_way_mask == 0) 909 log_way_mask = (1 << PN_L2_NWAYS) - 1; 910 911 /* Log the cache lines */ 912 for (i = 0; i < PN_L2_NWAYS; i++) 913 if (log_way_mask & (1 << i)) 914 l2_data[i].ec_logflag = EC_LOGFLAG_MAGIC; 915 } 916 917 /* 918 * For this routine to return true, the L2 tag in question must be valid 919 * and the tag PA must match the fault address (faddr) assuming the correct 920 * index is being used. 921 */ 922 static int 923 pn_matching_valid_l2_line(uint64_t faddr, ch_ec_data_t *clo_l2_data) { 924 if ((!PN_L2_LINE_INVALID(clo_l2_data->ec_tag)) && 925 ((faddr & P2ALIGN(C_AFAR_PA, PN_L2_SET_SIZE)) == 926 PN_L2TAG_TO_PA(clo_l2_data->ec_tag))) 927 return (1); 928 return (0); 929 } 930 931 /* 932 * This array is used to convert the 3 digit PgSz encoding (as used in 933 * various MMU registers such as MMU_TAG_ACCESS_EXT) into the corresponding 934 * page size. 935 */ 936 static uint64_t tlb_pgsz_to_size[] = { 937 /* 000 = 8KB: */ 938 0x2000, 939 /* 001 = 64KB: */ 940 0x10000, 941 /* 010 = 512KB: */ 942 0x80000, 943 /* 011 = 4MB: */ 944 0x400000, 945 /* 100 = 32MB: */ 946 0x2000000, 947 /* 101 = 256MB: */ 948 0x10000000, 949 /* undefined for encodings 110 and 111: */ 950 0, 0 951 }; 952 953 /* 954 * The itlb_parity_trap and dtlb_parity_trap handlers transfer control here 955 * after collecting logout information related to the TLB parity error and 956 * flushing the offending TTE entries from the ITLB or DTLB. 957 * 958 * DTLB traps which occur at TL>0 are not recoverable because we will most 959 * likely be corrupting some other trap handler's alternate globals. As 960 * such, we simply panic here when that happens. ITLB parity errors are 961 * not expected to happen at TL>0. 962 */ 963 void 964 cpu_tlb_parity_error(struct regs *rp, ulong_t trap_va, ulong_t tlb_info) { 965 ch_async_flt_t ch_flt; 966 struct async_flt *aflt; 967 pn_tlb_logout_t *tlop = NULL; 968 int immu_parity = (tlb_info & PN_TLO_INFO_IMMU) != 0; 969 int tl1_trap = (tlb_info & PN_TLO_INFO_TL1) != 0; 970 char *error_class; 971 972 bzero(&ch_flt, sizeof (ch_async_flt_t)); 973 974 /* 975 * Get the CPU log out info. If we can't find our CPU private 976 * pointer, or if the logout information does not correspond to 977 * this error, then we will have to make due without detailed 978 * logout information. 979 */ 980 if (CPU_PRIVATE(CPU)) { 981 tlop = CPU_PRIVATE_PTR(CPU, chpr_tlb_logout); 982 if ((tlop->tlo_addr != trap_va) || 983 (tlop->tlo_info != tlb_info)) 984 tlop = NULL; 985 } 986 987 if (tlop) { 988 ch_flt.tlb_diag_data = *tlop; 989 990 /* Zero out + invalidate TLB logout. */ 991 bzero(tlop, sizeof (pn_tlb_logout_t)); 992 tlop->tlo_addr = LOGOUT_INVALID; 993 } else { 994 /* 995 * Copy what logout information we have and mark 996 * it incomplete. 997 */ 998 ch_flt.flt_data_incomplete = 1; 999 ch_flt.tlb_diag_data.tlo_info = tlb_info; 1000 ch_flt.tlb_diag_data.tlo_addr = trap_va; 1001 } 1002 1003 /* 1004 * Log the error. 1005 */ 1006 aflt = (struct async_flt *)&ch_flt; 1007 aflt->flt_id = gethrtime_waitfree(); 1008 aflt->flt_bus_id = getprocessorid(); 1009 aflt->flt_inst = CPU->cpu_id; 1010 aflt->flt_pc = (caddr_t)rp->r_pc; 1011 aflt->flt_addr = trap_va; 1012 aflt->flt_prot = AFLT_PROT_NONE; 1013 aflt->flt_class = CPU_FAULT; 1014 aflt->flt_priv = (rp->r_tstate & TSTATE_PRIV) ? 1 : 0; 1015 aflt->flt_tl = tl1_trap ? 1 : 0; 1016 aflt->flt_panic = tl1_trap ? 1 : 0; 1017 1018 if (immu_parity) { 1019 aflt->flt_status = ECC_ITLB_TRAP; 1020 ch_flt.flt_type = CPU_ITLB_PARITY; 1021 error_class = FM_EREPORT_CPU_USIII_ITLBPE; 1022 aflt->flt_payload = FM_EREPORT_PAYLOAD_ITLB_PE; 1023 } else { 1024 aflt->flt_status = ECC_DTLB_TRAP; 1025 ch_flt.flt_type = CPU_DTLB_PARITY; 1026 error_class = FM_EREPORT_CPU_USIII_DTLBPE; 1027 aflt->flt_payload = FM_EREPORT_PAYLOAD_DTLB_PE; 1028 } 1029 1030 /* 1031 * The TLB entries have already been flushed by the TL1 trap 1032 * handler so at this point the only thing left to do is log 1033 * the error message. 1034 */ 1035 if (aflt->flt_panic) { 1036 cpu_errorq_dispatch(error_class, (void *)&ch_flt, 1037 sizeof (ch_async_flt_t), ue_queue, aflt->flt_panic); 1038 /* 1039 * Panic here if aflt->flt_panic has been set. Enqueued 1040 * errors will be logged as part of the panic flow. 1041 */ 1042 fm_panic("%sError(s)", immu_parity ? "ITLBPE " : "DTLBPE "); 1043 } else { 1044 cpu_errorq_dispatch(error_class, (void *)&ch_flt, 1045 sizeof (ch_async_flt_t), ce_queue, aflt->flt_panic); 1046 } 1047 } 1048 1049 /* 1050 * This routine is called when a TLB parity error event is 'ue_drain'ed 1051 * or 'ce_drain'ed from the errorq. 1052 */ 1053 void 1054 cpu_async_log_tlb_parity_err(void *flt) { 1055 ch_async_flt_t *ch_flt = (ch_async_flt_t *)flt; 1056 struct async_flt *aflt = (struct async_flt *)flt; 1057 #ifdef lint 1058 aflt = aflt; 1059 #endif 1060 1061 /* 1062 * We only capture TLB information if we encountered 1063 * a TLB parity error and Panther is the only CPU which 1064 * can detect a TLB parity error. 1065 */ 1066 ASSERT(IS_PANTHER(cpunodes[aflt->flt_inst].implementation)); 1067 ASSERT((ch_flt->flt_type == CPU_ITLB_PARITY) || 1068 (ch_flt->flt_type == CPU_DTLB_PARITY)); 1069 1070 if (ch_flt->flt_data_incomplete == 0) { 1071 if (ch_flt->flt_type == CPU_ITLB_PARITY) 1072 ch_flt->tlb_diag_data.tlo_logflag = IT_LOGFLAG_MAGIC; 1073 else /* parity error is in DTLB */ 1074 ch_flt->tlb_diag_data.tlo_logflag = DT_LOGFLAG_MAGIC; 1075 } 1076 } 1077 1078 /* 1079 * Add L1 Prefetch cache data to the ereport payload. 1080 */ 1081 void 1082 cpu_payload_add_pcache(struct async_flt *aflt, nvlist_t *nvl) 1083 { 1084 ch_async_flt_t *ch_flt = (ch_async_flt_t *)aflt; 1085 ch_pc_data_t *pcp; 1086 ch_pc_data_t pcdata[CH_PCACHE_NWAY]; 1087 uint_t nelem; 1088 int i, ways_logged = 0; 1089 1090 /* 1091 * We only capture P$ information if we encountered 1092 * a P$ parity error and Panther is the only CPU which 1093 * can detect a P$ parity error. 1094 */ 1095 ASSERT(IS_PANTHER(cpunodes[aflt->flt_inst].implementation)); 1096 for (i = 0; i < CH_PCACHE_NWAY; i++) { 1097 pcp = &ch_flt->parity_data.dpe.cpl_pc[i]; 1098 if (pcp->pc_logflag == PC_LOGFLAG_MAGIC) { 1099 bcopy(pcp, &pcdata[ways_logged], 1100 sizeof (ch_pc_data_t)); 1101 ways_logged++; 1102 } 1103 } 1104 1105 /* 1106 * Add the pcache data to the payload. 1107 */ 1108 fm_payload_set(nvl, FM_EREPORT_PAYLOAD_NAME_L1P_WAYS, 1109 DATA_TYPE_UINT8, (uint8_t)ways_logged, NULL); 1110 if (ways_logged != 0) { 1111 nelem = sizeof (ch_pc_data_t) / sizeof (uint64_t) * ways_logged; 1112 fm_payload_set(nvl, FM_EREPORT_PAYLOAD_NAME_L1P_DATA, 1113 DATA_TYPE_UINT64_ARRAY, nelem, (uint64_t *)pcdata, NULL); 1114 } 1115 } 1116 1117 /* 1118 * Add TLB diagnostic data to the ereport payload. 1119 */ 1120 void 1121 cpu_payload_add_tlb(struct async_flt *aflt, nvlist_t *nvl) 1122 { 1123 ch_async_flt_t *ch_flt = (ch_async_flt_t *)aflt; 1124 uint8_t num_entries, tlb_data_words; 1125 1126 /* 1127 * We only capture TLB information if we encountered 1128 * a TLB parity error and Panther is the only CPU which 1129 * can detect a TLB parity error. 1130 */ 1131 ASSERT(IS_PANTHER(cpunodes[aflt->flt_inst].implementation)); 1132 ASSERT((ch_flt->flt_type == CPU_ITLB_PARITY) || 1133 (ch_flt->flt_type == CPU_DTLB_PARITY)); 1134 1135 if (ch_flt->flt_type == CPU_ITLB_PARITY) { 1136 num_entries = (uint8_t)(PN_ITLB_NWAYS * PN_NUM_512_ITLBS); 1137 tlb_data_words = sizeof (ch_tte_entry_t) / sizeof (uint64_t) * 1138 num_entries; 1139 1140 /* 1141 * Add the TLB diagnostic data to the payload 1142 * if it was collected. 1143 */ 1144 if (ch_flt->tlb_diag_data.tlo_logflag == IT_LOGFLAG_MAGIC) { 1145 fm_payload_set(nvl, 1146 FM_EREPORT_PAYLOAD_NAME_ITLB_ENTRIES, 1147 DATA_TYPE_UINT8, num_entries, NULL); 1148 fm_payload_set(nvl, FM_EREPORT_PAYLOAD_NAME_ITLB_DATA, 1149 DATA_TYPE_UINT64_ARRAY, tlb_data_words, 1150 (uint64_t *)ch_flt->tlb_diag_data.tlo_itlb_tte, 1151 NULL); 1152 } 1153 } else { 1154 num_entries = (uint8_t)(PN_DTLB_NWAYS * PN_NUM_512_DTLBS); 1155 tlb_data_words = sizeof (ch_tte_entry_t) / sizeof (uint64_t) * 1156 num_entries; 1157 1158 fm_payload_set(nvl, FM_EREPORT_PAYLOAD_NAME_VA, 1159 DATA_TYPE_UINT64, ch_flt->tlb_diag_data.tlo_addr, NULL); 1160 1161 /* 1162 * Add the TLB diagnostic data to the payload 1163 * if it was collected. 1164 */ 1165 if (ch_flt->tlb_diag_data.tlo_logflag == DT_LOGFLAG_MAGIC) { 1166 fm_payload_set(nvl, 1167 FM_EREPORT_PAYLOAD_NAME_DTLB_ENTRIES, 1168 DATA_TYPE_UINT8, num_entries, NULL); 1169 fm_payload_set(nvl, FM_EREPORT_PAYLOAD_NAME_DTLB_DATA, 1170 DATA_TYPE_UINT64_ARRAY, tlb_data_words, 1171 (uint64_t *)ch_flt->tlb_diag_data.tlo_dtlb_tte, 1172 NULL); 1173 } 1174 } 1175 } 1176 1177 /* 1178 * Panther Cache Scrubbing: 1179 * 1180 * In Jaguar, the E$ was split between cores, so the scrubber must run on both 1181 * cores. For Panther, however, the L2$ and L3$ are shared across cores. 1182 * Therefore, the E$ scrubber only needs to run on one of the two cores. 1183 * 1184 * There are four possible states for the E$ scrubber: 1185 * 1186 * 0. If both cores are offline, add core 0 to cpu_offline_set so that 1187 * the offline scrubber will run on it. 1188 * 1. If core 0 is online and core 1 off, we run the scrubber on core 0. 1189 * 2. If core 1 is online and core 0 off, we move the scrubber to run 1190 * on core 1. 1191 * 3. If both cores are online, only run the scrubber on core 0. 1192 * 1193 * These states are enumerated by the SCRUBBER_[BOTH|CORE|NEITHER]_* defines 1194 * above. One of those values is stored in 1195 * chpr_scrub_misc->chsm_core_state on each core. 1196 * 1197 * Also note that, for Panther, ecache_flush_line() will flush out the L2$ 1198 * before the E$, so the L2$ will be scrubbed by the E$ scrubber. No 1199 * additional code is necessary to scrub the L2$. 1200 * 1201 * For all cpu types, whenever a cpu or core is offlined, add it to 1202 * cpu_offline_set so the necessary scrubbers can still run. This is still 1203 * necessary on Panther so the D$ scrubber can still run. 1204 */ 1205 /*ARGSUSED*/ 1206 int 1207 cpu_scrub_cpu_setup(cpu_setup_t what, int cpuid, void *arg) 1208 { 1209 processorid_t core_0_id; 1210 cpu_t *core_cpus[2]; 1211 ch_scrub_misc_t *core_scrub[2]; 1212 int old_state, i; 1213 int new_state = SCRUBBER_NEITHER_CORE_ONLINE; 1214 1215 switch (what) { 1216 case CPU_ON: 1217 case CPU_INIT: 1218 CPUSET_DEL(cpu_offline_set, cpuid); 1219 break; 1220 case CPU_OFF: 1221 CPUSET_ADD(cpu_offline_set, cpuid); 1222 break; 1223 default: 1224 return (0); 1225 } 1226 1227 if (!IS_PANTHER(cpunodes[cpuid].implementation)) { 1228 return (0); 1229 } 1230 1231 /* 1232 * Update the chsm_enable[CACHE_SCRUBBER_INFO_E] value 1233 * if necessary 1234 */ 1235 core_0_id = cmp_cpu_to_chip(cpuid); 1236 core_cpus[0] = cpu_get(core_0_id); 1237 core_cpus[1] = cpu_get_sibling_core(core_cpus[0]); 1238 1239 for (i = 0; i < 2; i++) { 1240 if (core_cpus[i] == NULL) { 1241 /* 1242 * This may happen during DR - one core is offlined 1243 * and completely unconfigured before the second 1244 * core is offlined. Give up and return quietly, 1245 * since the second core should quickly be removed 1246 * anyways. 1247 */ 1248 return (0); 1249 } 1250 core_scrub[i] = CPU_PRIVATE_PTR(core_cpus[i], chpr_scrub_misc); 1251 } 1252 1253 if (cpuid == (processorid_t)cmp_cpu_to_chip(cpuid)) { 1254 /* cpuid is core 0 */ 1255 if (cpu_is_active(core_cpus[1])) { 1256 new_state |= SCRUBBER_CORE_1_ONLINE; 1257 } 1258 if (what != CPU_OFF) { 1259 new_state |= SCRUBBER_CORE_0_ONLINE; 1260 } 1261 } else { 1262 /* cpuid is core 1 */ 1263 if (cpu_is_active(core_cpus[0])) { 1264 new_state |= SCRUBBER_CORE_0_ONLINE; 1265 } 1266 if (what != CPU_OFF) { 1267 new_state |= SCRUBBER_CORE_1_ONLINE; 1268 } 1269 } 1270 1271 old_state = core_scrub[0]->chsm_core_state; 1272 1273 if (old_state == new_state) { 1274 return (0); 1275 } 1276 1277 if (old_state == SCRUBBER_CORE_1_ONLINE) { 1278 /* 1279 * We need to move the scrubber state from core 1 1280 * back to core 0. This data is not protected by 1281 * locks, but the worst that can happen is some 1282 * lines are scrubbed multiple times. chsm_oustanding is 1283 * set to 0 to make sure an interrupt is scheduled the 1284 * first time through do_scrub(). 1285 */ 1286 core_scrub[0]->chsm_flush_index[CACHE_SCRUBBER_INFO_E] = 1287 core_scrub[1]->chsm_flush_index[CACHE_SCRUBBER_INFO_E]; 1288 core_scrub[0]->chsm_outstanding[CACHE_SCRUBBER_INFO_E] = 0; 1289 } 1290 1291 switch (new_state) { 1292 case SCRUBBER_NEITHER_CORE_ONLINE: 1293 case SCRUBBER_BOTH_CORES_ONLINE: 1294 case SCRUBBER_CORE_0_ONLINE: 1295 core_scrub[1]->chsm_enable[CACHE_SCRUBBER_INFO_E] = 0; 1296 core_scrub[0]->chsm_enable[CACHE_SCRUBBER_INFO_E] = 1; 1297 break; 1298 1299 case SCRUBBER_CORE_1_ONLINE: 1300 default: 1301 /* 1302 * We need to move the scrubber state from core 0 1303 * to core 1. 1304 */ 1305 core_scrub[1]->chsm_flush_index[CACHE_SCRUBBER_INFO_E] = 1306 core_scrub[0]->chsm_flush_index[CACHE_SCRUBBER_INFO_E]; 1307 core_scrub[1]->chsm_outstanding[CACHE_SCRUBBER_INFO_E] = 0; 1308 1309 core_scrub[0]->chsm_enable[CACHE_SCRUBBER_INFO_E] = 0; 1310 core_scrub[1]->chsm_enable[CACHE_SCRUBBER_INFO_E] = 1; 1311 break; 1312 } 1313 1314 core_scrub[0]->chsm_core_state = new_state; 1315 core_scrub[1]->chsm_core_state = new_state; 1316 return (0); 1317 } 1318 1319 /* 1320 * Returns a pointer to the cpu structure of the argument's sibling core. 1321 * If no sibling core can be found, return NULL. 1322 */ 1323 static cpu_t * 1324 cpu_get_sibling_core(cpu_t *cpup) 1325 { 1326 cpu_t *nextp; 1327 1328 if ((cpup == NULL) || (!cmp_cpu_is_cmp(cpup->cpu_id))) 1329 return (NULL); 1330 1331 nextp = cpup->cpu_next_chip; 1332 if ((nextp == NULL) || (nextp == cpup)) 1333 return (NULL); 1334 1335 return (nextp); 1336 } 1337