1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_INTREG_H 28 #define _SYS_INTREG_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #include <sys/machintreg.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #define INO_SIZE 6 /* Interrupt Number Offset bit size */ 39 #define INR_SIZE (IGN_SIZE + INO_SIZE) /* Interrupt Number bit size */ 40 #define MAX_IGN (1 << IGN_SIZE) /* max Interrupt Group Number size */ 41 #define MAX_INO (1 << INO_SIZE) /* max Interrupt Number per group */ 42 43 /* 44 * MAX_SOFT_INO: Need two softints per cpu for cyclics plus some for 45 * miscellaneous system use. 46 */ 47 #define MAX_SOFT_INO ((NCPU * 2) + 192) 48 49 #define SOFTIVNUM (MAX_IGN * MAX_INO) 50 #define MAXIVNUM (MAX_IGN * MAX_INO + MAX_SOFT_INO) 51 52 /* 53 * Interrupt State Machine 54 * Each interrupt source has a 2-bit state machine which ensures that 55 * software sees exactly one interrupt packet per assertion of the 56 * interrupt signal. 57 */ 58 #define ISM_IDLE 0x0 /* not asserted or pending */ 59 #define ISM_TRANSMIT 0x1 /* asserted but is not dispatched */ 60 #define ISM_PENDING 0x2 /* dispatched to a processor or is in transit */ 61 62 /* 63 * Per-Processor Soft Interrupt Register 64 * XXX use %asr when the new assembler supports them 65 */ 66 #define SET_SOFTINT %asr20 /* ASR 0x14 */ 67 #define CLEAR_SOFTINT %asr21 /* ASR 0x15 */ 68 #define SOFTINT %asr22 /* ASR 0x16 */ 69 #define SOFTINT_MASK 0xFFFE /* <15:1> */ 70 #define TICK_INT_MASK 0x1 /* <0> */ 71 #define STICK_INT_MASK 0x10000 /* <0> */ 72 73 /* 74 * Per-Processor TICK Register and TICK_Compare registers 75 * 76 */ 77 #define TICK_COMPARE %asr23 /* ASR 0x17 */ 78 #define STICK %asr24 /* ASR 0x18 */ 79 #define STICK_COMPARE %asr25 /* ASR 0x19 */ 80 #define TICKINT_DIS_SHFT 0x3f 81 82 #ifndef _ASM 83 84 /* 85 * Interrupt Packet (mondo) 86 */ 87 struct intr_packet { 88 uint64_t intr_data0; /* can be an interrupt number or a pc */ 89 uint64_t intr_data1; 90 uint64_t intr_data2; 91 }; 92 93 /* 94 * Leftover bogus stuff; removed them later 95 */ 96 struct cpu_intreg { 97 uint_t pend; 98 uint_t clr_pend; 99 uint_t set_pend; 100 uchar_t filler[0x1000 - 0xc]; 101 }; 102 103 struct sys_intreg { 104 uint_t sys_pend; 105 uint_t sys_m; 106 uint_t sys_mclear; 107 uint_t sys_mset; 108 uint_t itr; 109 }; 110 111 #endif /* _ASM */ 112 113 #ifdef __cplusplus 114 } 115 #endif 116 117 #endif /* _SYS_INTREG_H */ 118