1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PX_VAR_H 28 #define _SYS_PX_VAR_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * offsets of PCI address spaces from base address: 38 */ 39 #define PX_CONFIG 0x001000000ull 40 #define PX_A_IO 0x002000000ull 41 #define PX_B_IO 0x002010000ull 42 #define PX_A_MEMORY 0x100000000ull 43 #define PX_B_MEMORY 0x180000000ull 44 #define PX_IO_SIZE 0x000010000ull 45 #define PX_MEM_SIZE 0x080000000ull 46 47 /* 48 * The following typedef is used to represent a 49 * 1275 "bus-range" property of a PCI Bus node. 50 */ 51 typedef struct px_bus_range { 52 uint32_t lo; 53 uint32_t hi; 54 } px_bus_range_t; 55 56 /* 57 * The following typedef is used to represent an entry in the "ranges" 58 * property of a device node. 59 */ 60 typedef struct px_ranges { 61 uint32_t child_high; 62 uint32_t child_mid; 63 uint32_t child_low; 64 uint32_t parent_high; 65 uint32_t parent_low; 66 uint32_t size_high; 67 uint32_t size_low; 68 } px_ranges_t; 69 70 /* 71 * The following typedef is used to represent a 72 * 1275 "reg" property of a PCI nexus. 73 */ 74 typedef struct px_nexus_regspec { 75 uint64_t phys_addr; 76 uint64_t size; 77 } px_nexus_regspec_t; 78 79 typedef enum { PX_NEW, PX_ATTACHED, PX_DETACHED, PX_SUSPENDED } px_state_t; 80 enum { PX_INTR_XBC, PX_INTR_PEC }; 81 82 #define PX_ATTACH_RETCODE(obj, op, err) \ 83 ((err) ? (obj) << 8 | (op) << 4 | (err) & 0xf : DDI_SUCCESS) 84 85 /* 86 * px soft state structure: 87 * 88 * Each px node has a px soft state structure. 89 */ 90 struct px { 91 /* 92 * State flags and mutex: 93 */ 94 px_state_t px_state; 95 uint_t px_soft_state; 96 uint_t px_open_count; 97 kmutex_t px_mutex; 98 99 /* 100 * Links to other state structures: 101 */ 102 dev_info_t *px_dip; /* devinfo structure */ 103 devhandle_t px_dev_hdl; /* device handle */ 104 px_cb_t *px_cb_p; /* XBC block */ 105 px_ib_t *px_ib_p; /* interrupt block */ 106 px_pec_t *px_pec_p; /* PEC block */ 107 px_mmu_t *px_mmu_p; /* IOMMU block */ 108 109 /* 110 * px device node properties: 111 */ 112 px_bus_range_t px_bus_range; /* "bus-range" */ 113 px_ranges_t *px_ranges_p; /* "ranges" data & length */ 114 int px_ranges_length; 115 devino_t *px_inos; /* inos from "interrupts" prop */ 116 int px_inos_len; /* "interrupts" length */ 117 int pci_numproxy; /* upa interrupt proxies */ 118 int px_thermal_interrupt; /* node has thermal interrupt */ 119 120 /* Interrupt support */ 121 int intr_map_size; 122 struct intr_map *intr_map; 123 struct intr_map_mask *intr_map_mask; 124 125 /* Error handling */ 126 px_fault_t px_fault; 127 px_fault_t px_cb_fault; 128 129 /* FMA */ 130 int px_fm_cap; 131 ddi_iblock_cookie_t px_fm_ibc; 132 133 /* Platform specific information */ 134 void *px_plat_p; 135 136 /* Power Management fields */ 137 kmutex_t px_l23ready_lock; /* used in PME_To_ACK interrupt */ 138 kcondvar_t px_l23ready_cv; /* used in PME_TO_ACK timeout */ 139 140 /* Fields below deal with link up interrupt */ 141 kmutex_t px_lup_lock; 142 kcondvar_t px_lup_cv; /* used in LUP event timeout */ 143 kmutex_t px_lupsoft_lock; 144 ddi_softintr_t px_lupsoft_id; 145 int px_lupsoft_pending; 146 int px_pm_flags; 147 msiqid_t px_pm_msiq_id; /* EQ id for PCIE_PME_ACK_MSG Message */ 148 uint32_t px_pmetoack_ignored; /* count of PME_To_ACKs ignored */ 149 uint32_t px_pme_ignored; /* count of PME ignored */ 150 uint32_t px_lup_ignored; /* count of link up events ignored */ 151 152 }; 153 154 /* px soft state flag */ 155 #define PX_SOFT_STATE_OPEN 0x01 156 #define PX_SOFT_STATE_OPEN_EXCL 0x02 157 #define PX_SOFT_STATE_CLOSED 0x04 158 #define PX_BYPASS_DMA_ALLOWED 0x10 159 160 /* px_pm_flags definitions used with interrupts and FMA code */ 161 #define PX_PMETOACK_RECVD 0x01 /* With PME_To_ACK interrupt */ 162 #define PX_PME_TURNOFF_PENDING 0x02 /* With PME_To_ACK interrupt */ 163 #define PX_LINKUP_RECVD 0x04 /* With link up soft interrupt */ 164 #define PX_LINKUP_PENDING 0x08 /* With link up soft interrupt */ 165 #define PX_LUP_EXPECTED 0x10 /* With FMA code */ 166 #define PX_LDN_EXPECTED 0x20 /* With FMA code */ 167 168 #define DIP_TO_INST(dip) ddi_get_instance(dip) 169 #define INST_TO_STATE(inst) ddi_get_soft_state(px_state_p, inst) 170 #define DIP_TO_STATE(dip) INST_TO_STATE(DIP_TO_INST(dip)) 171 172 #define DEV_TO_SOFTSTATE(dev) ((px_t *)ddi_get_soft_state( \ 173 px_state_p, PCIHP_AP_MINOR_NUM_TO_INSTANCE(getminor(dev)))) 174 175 extern void *px_state_p; 176 177 /* 178 * function prototypes for bus ops routines: 179 */ 180 extern int 181 px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 182 off_t offset, off_t len, caddr_t *addrp); 183 extern int 184 px_dma_setup(dev_info_t *dip, dev_info_t *rdip, 185 ddi_dma_req_t *dmareq, ddi_dma_handle_t *handlep); 186 extern int 187 px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 188 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep); 189 extern int 190 px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 191 ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 192 ddi_dma_cookie_t *cookiep, uint_t *ccountp); 193 extern int 194 px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 195 ddi_dma_handle_t handle); 196 extern int 197 px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 198 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 199 uint_t cache_flags); 200 extern int 201 px_ctlops(dev_info_t *dip, dev_info_t *rdip, 202 ddi_ctl_enum_t op, void *arg, void *result); 203 extern int 204 px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 205 ddi_intr_handle_impl_t *handle, void *result); 206 207 #ifdef __cplusplus 208 } 209 #endif 210 211 #endif /* _SYS_PX_VAR_H */ 212