1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PX mmu initialization and configuration 31 */ 32 #include <sys/types.h> 33 #include <sys/kmem.h> 34 #include <sys/async.h> 35 #include <sys/sysmacros.h> 36 #include <sys/sunddi.h> 37 #include <sys/ddi_impldefs.h> 38 #include <sys/vmem.h> 39 #include <sys/machsystm.h> /* lddphys() */ 40 #include <sys/iommutsb.h> 41 #include "px_obj.h" 42 43 int 44 px_mmu_attach(px_t *px_p) 45 { 46 dev_info_t *dip = px_p->px_dip; 47 px_mmu_t *mmu_p; 48 uint32_t base_pg_index, i = 0; 49 char map_name[32]; 50 px_dvma_range_prop_t *dvma_prop; 51 int dvma_prop_len; 52 uint32_t cache_size, tsb_entries; 53 54 /* 55 * Allocate mmu state structure and link it to the 56 * px state structure. 57 */ 58 mmu_p = kmem_zalloc(sizeof (px_mmu_t), KM_SLEEP); 59 if (mmu_p == NULL) 60 return (DDI_FAILURE); 61 62 px_p->px_mmu_p = mmu_p; 63 mmu_p->mmu_px_p = px_p; 64 mmu_p->mmu_inst = ddi_get_instance(dip); 65 66 /* 67 * Check for "virtual-dma" property that specifies 68 * the DVMA range. 69 */ 70 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 71 "virtual-dma", (caddr_t)&dvma_prop, &dvma_prop_len) != 72 DDI_PROP_SUCCESS) { 73 74 DBG(DBG_ATTACH, dip, "Getting virtual-dma failed\n"); 75 76 kmem_free(mmu_p, sizeof (px_mmu_t)); 77 px_p->px_mmu_p = NULL; 78 79 return (DDI_FAILURE); 80 } 81 82 mmu_p->mmu_dvma_base = dvma_prop->dvma_base; 83 mmu_p->mmu_dvma_end = dvma_prop->dvma_base + 84 (dvma_prop->dvma_len - 1); 85 tsb_entries = MMU_BTOP(dvma_prop->dvma_len); 86 87 kmem_free(dvma_prop, dvma_prop_len); 88 89 /* 90 * Setup base and bounds for DVMA and bypass mappings. 91 */ 92 mmu_p->mmu_dvma_cache_locks = 93 kmem_zalloc(px_dvma_page_cache_entries, KM_SLEEP); 94 95 mmu_p->dvma_base_pg = MMU_BTOP(mmu_p->mmu_dvma_base); 96 mmu_p->mmu_dvma_reserve = tsb_entries >> 1; 97 mmu_p->dvma_end_pg = MMU_BTOP(mmu_p->mmu_dvma_end); 98 99 /* 100 * Create a virtual memory map for dvma address space. 101 * Reserve 'size' bytes of low dvma space for fast track cache. 102 */ 103 (void) snprintf(map_name, sizeof (map_name), "%s%d_dvma", 104 ddi_driver_name(dip), ddi_get_instance(dip)); 105 106 cache_size = MMU_PTOB(px_dvma_page_cache_entries * 107 px_dvma_page_cache_clustsz); 108 mmu_p->mmu_dvma_fast_end = mmu_p->mmu_dvma_base + 109 cache_size - 1; 110 111 mmu_p->mmu_dvma_map = vmem_create(map_name, 112 (void *)(mmu_p->mmu_dvma_fast_end + 1), 113 MMU_PTOB(tsb_entries) - cache_size, MMU_PAGE_SIZE, 114 NULL, NULL, NULL, MMU_PAGE_SIZE, VM_SLEEP); 115 116 mutex_init(&mmu_p->dvma_debug_lock, NULL, MUTEX_DRIVER, NULL); 117 118 base_pg_index = MMU_BTOP(mmu_p->mmu_dvma_end) - tsb_entries + 1; 119 120 for (i = 0; i < tsb_entries; i++) { 121 r_addr_t ra = 0; 122 io_attributes_t attr; 123 caddr_t va; 124 125 if (px_lib_iommu_getmap(px_p->px_dip, PCI_TSBID(0, i), 126 &attr, &ra) == DDI_SUCCESS) { 127 va = (caddr_t)(MMU_PTOB(base_pg_index + i)); 128 (void) vmem_xalloc(mmu_p->mmu_dvma_map, MMU_PAGE_SIZE, 129 MMU_PAGE_SIZE, 0, 0, va, va + MMU_PAGE_SIZE, 130 VM_NOSLEEP | VM_BESTFIT | VM_PANIC); 131 } 132 } 133 134 return (DDI_SUCCESS); 135 } 136 137 void 138 px_mmu_detach(px_t *px_p) 139 { 140 px_mmu_t *mmu_p = px_p->px_mmu_p; 141 142 /* 143 * Free the dvma resource map. 144 */ 145 vmem_destroy(mmu_p->mmu_dvma_map); 146 147 kmem_free(mmu_p->mmu_dvma_cache_locks, 148 px_dvma_page_cache_entries); 149 150 if (PX_DVMA_DBG_ON(mmu_p)) 151 px_dvma_debug_fini(mmu_p); 152 153 mutex_destroy(&mmu_p->dvma_debug_lock); 154 155 /* 156 * Free the mmu state structure. 157 */ 158 kmem_free(mmu_p, sizeof (px_mmu_t)); 159 px_p->px_mmu_p = NULL; 160 } 161 162 int 163 px_mmu_map_pages(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, px_dvma_addr_t dvma_pg, 164 size_t npages, size_t pfn_index) 165 { 166 dev_info_t *dip = mmu_p->mmu_px_p->px_dip; 167 px_dvma_addr_t pg_index = MMU_PAGE_INDEX(mmu_p, dvma_pg); 168 io_attributes_t attr = PX_GET_MP_TTE(mp->dmai_tte); 169 int ret; 170 171 ASSERT(npages <= mp->dmai_ndvmapages); 172 DBG(DBG_MAP_WIN, mmu_p->mmu_px_p->px_dip, 173 "px_mmu_map_pages:%x+%x=%x npages=0x%x pfn_index=0x%x\n", 174 (uint_t)mmu_p->dvma_base_pg, (uint_t)pg_index, dvma_pg, 175 (uint_t)npages, (uint_t)pfn_index); 176 177 if ((ret = px_lib_iommu_map(dip, PCI_TSBID(0, pg_index), npages, 178 attr, (void *)mp, pfn_index, MMU_MAP_MP)) != DDI_SUCCESS) { 179 DBG(DBG_MAP_WIN, mmu_p->mmu_px_p->px_dip, 180 "px_mmu_map_pages: px_iommu_map failed, ret %x\n", ret); 181 182 return (ret); 183 } 184 185 if (PX_DVMA_DBG_ON(mmu_p)) 186 px_dvma_alloc_debug(mmu_p, (char *)mp->dmai_mapping, 187 mp->dmai_size, mp); 188 189 return (ret); 190 } 191 192 void 193 px_mmu_unmap_pages(px_mmu_t *mmu_p, px_dvma_addr_t dvma_pg, uint_t npages) 194 { 195 px_dvma_addr_t pg_index = MMU_PAGE_INDEX(mmu_p, dvma_pg); 196 197 DBG(DBG_UNMAP_WIN, mmu_p->mmu_px_p->px_dip, 198 "px_mmu_unmap_pages:%x+%x=%x npages=0x%x\n", 199 (uint_t)mmu_p->dvma_base_pg, (uint_t)pg_index, dvma_pg, 200 (uint_t)npages); 201 202 (void) px_lib_iommu_demap(mmu_p->mmu_px_p->px_dip, 203 PCI_TSBID(0, pg_index), npages); 204 } 205 206 /* 207 * px_mmu_map_window - map a dvma window into the mmu 208 * used by: px_dma_win(), px_dma_ctlops() - DDI_DMA_MOVWIN, DDI_DMA_NEXTWIN 209 * return value: none 210 */ 211 /*ARGSUSED*/ 212 int 213 px_mmu_map_window(px_mmu_t *mmu_p, ddi_dma_impl_t *mp, px_window_t win_no) 214 { 215 uint32_t obj_pg0_off = mp->dmai_roffset; 216 uint32_t win_pg0_off = win_no ? 0 : obj_pg0_off; 217 size_t win_size = mp->dmai_winsize; 218 size_t pfn_index = win_size * win_no; /* temp value */ 219 size_t obj_off = win_no ? pfn_index - obj_pg0_off : 0; /* xferred sz */ 220 px_dvma_addr_t dvma_pg = MMU_BTOP(mp->dmai_mapping); 221 size_t res_size = mp->dmai_object.dmao_size - obj_off + win_pg0_off; 222 int ret = DDI_SUCCESS; 223 224 ASSERT(!(win_size & MMU_PAGE_OFFSET)); 225 if (win_no >= mp->dmai_nwin) 226 return (ret); 227 if (res_size < win_size) /* last window */ 228 win_size = res_size; /* mp->dmai_winsize unchanged */ 229 230 mp->dmai_mapping = MMU_PTOB(dvma_pg) | win_pg0_off; 231 mp->dmai_size = win_size - win_pg0_off; /* cur win xferrable size */ 232 mp->dmai_offset = obj_off; /* win offset into object */ 233 pfn_index = MMU_BTOP(pfn_index); /* index into pfnlist */ 234 ret = px_mmu_map_pages(mmu_p, mp, dvma_pg, MMU_BTOPR(win_size), 235 pfn_index); 236 237 return (ret); 238 } 239 240 /* 241 * px_mmu_unmap_window 242 * This routine is called to break down the mmu mappings to a dvma window. 243 * Non partial mappings are viewed as single window mapping. 244 * used by: px_dma_unbindhdl(), px_dma_window(), 245 * and px_dma_ctlops() - DDI_DMA_FREE, DDI_DMA_MOVWIN, DDI_DMA_NEXTWIN 246 * return value: none 247 */ 248 /*ARGSUSED*/ 249 void 250 px_mmu_unmap_window(px_mmu_t *mmu_p, ddi_dma_impl_t *mp) 251 { 252 px_dvma_addr_t dvma_pg = MMU_BTOP(mp->dmai_mapping); 253 uint_t npages = MMU_BTOP(mp->dmai_winsize); 254 255 px_mmu_unmap_pages(mmu_p, dvma_pg, npages); 256 257 if (PX_DVMA_DBG_ON(mmu_p)) 258 px_dvma_free_debug(mmu_p, (char *)mp->dmai_mapping, 259 mp->dmai_size, mp); 260 } 261 262 263 #if 0 264 /* 265 * The following table is for reference only. It denotes the 266 * the TSB table size measured in number of 8 byte entries. 267 * It is represented by bits 3:0 in the MMU TSB CTRL REG. 268 */ 269 static int px_mmu_tsb_sizes[] = { 270 0x0, /* 1K */ 271 0x1, /* 2K */ 272 0x2, /* 4K */ 273 0x3, /* 8K */ 274 0x4, /* 16K */ 275 0x5, /* 32K */ 276 0x6, /* 64K */ 277 0x7, /* 128K */ 278 0x8 /* 256K */ 279 }; 280 #endif 281 282 static char *px_mmu_errsts[] = { 283 "Protection Error", "Invalid Error", "Timeout", "ECC Error(UE)" 284 }; 285 286 /*ARGSUSED*/ 287 static int 288 px_log_mmu_err(px_t *px_p) 289 { 290 /* 291 * Place holder, the correct eror bits need tobe logged. 292 */ 293 return (0); 294 } 295