1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PX_IB_H 28 #define _SYS_PX_IB_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/ddi_subrdefs.h> 37 38 typedef struct px_ib_ino_info px_ib_ino_info_t; 39 40 /* 41 * interrupt block soft state structure: 42 * 43 * Each px node may share an interrupt block structure with its peer 44 * node or have its own private interrupt block structure. 45 */ 46 typedef struct px_ib px_ib_t; 47 struct px_ib { 48 px_t *ib_px_p; /* link back to px soft state */ 49 px_ib_ino_info_t *ib_ino_lst; /* ino link list */ 50 kmutex_t ib_ino_lst_mutex; /* mutex for ino link list */ 51 kmutex_t ib_intr_lock; /* lock for internal intr */ 52 53 px_msiq_state_t ib_msiq_state; /* MSIQ soft state */ 54 px_msi_state_t ib_msi_state; /* MSI soft state */ 55 }; 56 57 /* 58 * The following structure represents an interrupt entry for an INO. 59 */ 60 typedef struct px_ih { 61 dev_info_t *ih_dip; /* devinfo structure */ 62 uint32_t ih_inum; /* interrupt number for this device */ 63 uint_t (*ih_handler)(); /* interrupt handler */ 64 caddr_t ih_handler_arg1; /* interrupt handler argument #1 */ 65 caddr_t ih_handler_arg2; /* interrupt handler argument #2 */ 66 ddi_acc_handle_t ih_config_handle; /* config space reg map handle */ 67 uint_t ih_intr_state; /* Only used for fixed interrupts */ 68 msiq_rec_type_t ih_rec_type; /* MSI or PCIe record type */ 69 msgcode_t ih_msg_code; /* MSI number or PCIe message code */ 70 struct px_ih *ih_next; /* next entry in list */ 71 uint64_t ih_ticks; /* ticks spent in this handler */ 72 uint64_t ih_nsec; /* nsec spent in this handler */ 73 kstat_t *ih_ksp; 74 struct px_ib_ino_info *ih_ino_p; /* only for use by kstat */ 75 } px_ih_t; 76 77 /* Only used for fixed or legacy interrupts */ 78 #define PX_INTR_STATE_DISABLE 0 /* disabled */ 79 #define PX_INTR_STATE_ENABLE 1 /* enabled */ 80 81 /* 82 * ino structure : one per each ino with interrupt registered 83 */ 84 struct px_ib_ino_info { 85 devino_t ino_ino; /* INO number - 8 bit */ 86 sysino_t ino_sysino; /* Virtual inumber */ 87 uint16_t ino_ih_size; /* size of the px intrspec list */ 88 px_ih_t *ino_ih_head; /* intr spec (part of ppd) list head */ 89 px_ih_t *ino_ih_tail; /* intr spec (part of ppd) list tail */ 90 px_ih_t *ino_ih_start; /* starting point in intr spec list */ 91 px_ib_t *ino_ib_p; /* link back to interrupt block state */ 92 uint32_t ino_pil; /* PIL for this ino */ 93 uint_t ino_unclaimed; /* number of unclaimed interrupts */ 94 clock_t ino_spurintr_begin; /* begin time of spurious intr */ 95 cpuid_t ino_cpuid; /* cpu that ino is targeting */ 96 int32_t ino_intr_weight; /* intr wt of devices sharing ino */ 97 px_msiq_t *ino_msiq_p; /* Pointer to MSIQ used */ 98 struct px_ib_ino_info *ino_next; 99 }; 100 101 #define IB_INTR_WAIT 1 /* wait for interrupt completion */ 102 #define IB_INTR_NOWAIT 0 /* already handling intr, no wait */ 103 104 #define PX_INTR_ENABLE(dip, sysino, cpuid) \ 105 px_lib_intr_settarget(dip, sysino, cpuid); \ 106 px_lib_intr_setstate(dip, sysino, INTR_IDLE_STATE); \ 107 px_lib_intr_setvalid(dip, sysino, INTR_VALID); 108 109 #define PX_INTR_DISABLE(dip, sysino) \ 110 px_lib_intr_setvalid(dip, sysino, INTR_NOTVALID); 111 112 extern int px_ib_attach(px_t *px_p); 113 extern void px_ib_detach(px_t *px_p); 114 extern void px_ib_intr_enable(px_t *px_p, cpuid_t cpuid, devino_t ino); 115 extern void px_ib_intr_disable(px_ib_t *ib_p, devino_t ino, int wait); 116 117 extern px_ib_ino_info_t *px_ib_locate_ino(px_ib_t *ib_p, devino_t ino_num); 118 extern px_ib_ino_info_t *px_ib_new_ino(px_ib_t *ib_p, devino_t ino_num, 119 px_ih_t *ih_p); 120 extern void px_ib_delete_ino(px_ib_t *ib_p, px_ib_ino_info_t *ino_p); 121 extern void px_ib_free_ino_all(px_ib_t *ib_p); 122 extern int px_ib_ino_add_intr(px_t *px_p, px_ib_ino_info_t *ino_p, 123 px_ih_t *ih_p); 124 extern int px_ib_ino_rem_intr(px_t *px_p, px_ib_ino_info_t *ino_p, 125 px_ih_t *ih_p); 126 extern px_ih_t *px_ib_ino_locate_intr(px_ib_ino_info_t *ino_p, dev_info_t *dip, 127 uint32_t inum, msiq_rec_type_t rec_type, msgcode_t msg_code); 128 extern px_ih_t *px_ib_alloc_ih(dev_info_t *rdip, uint32_t inum, 129 uint_t (*int_handler)(caddr_t int_handler_arg1, 130 caddr_t int_handler_arg2), caddr_t int_handler_arg1, 131 caddr_t int_handler_arg2, msiq_rec_type_t rec_type, msgcode_t msg_code); 132 extern void px_ib_free_ih(px_ih_t *ih_p); 133 extern int px_ib_update_intr_state(px_t *px_p, dev_info_t *rdip, uint_t inum, 134 devino_t ino, uint_t new_intr_state); 135 136 #ifdef __cplusplus 137 } 138 #endif 139 140 #endif /* _SYS_PX_IB_H */ 141