1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PX Fault Management Architecture 30 */ 31 #include <sys/types.h> 32 #include <sys/sunndi.h> 33 #include <sys/sunddi.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/fm/util.h> 36 #include <sys/fm/io/pci.h> 37 #include <sys/membar.h> 38 #include "px_obj.h" 39 40 #define PX_PCIE_PANIC_BITS \ 41 (PCIE_AER_UCE_DLP | PCIE_AER_UCE_FCP | PCIE_AER_UCE_TO | \ 42 PCIE_AER_UCE_RO | PCIE_AER_UCE_MTLP | PCIE_AER_UCE_ECRC) 43 #define PX_PCIE_NO_PANIC_BITS \ 44 (PCIE_AER_UCE_TRAINING | PCIE_AER_UCE_SD | PCIE_AER_UCE_CA | \ 45 PCIE_AER_UCE_UC | PCIE_AER_UCE_UR) 46 47 /* 48 * Global panicing state variabled used to control if further error handling 49 * should occur. If the system is already panic'ing or if PX itself has 50 * recommended panic'ing the system, no further error handling should occur to 51 * prevent the system from hanging. 52 */ 53 boolean_t px_panicing = B_FALSE; 54 55 static pf_data_t *px_get_pfd(px_t *px_p); 56 57 static int px_pcie_ptlp(dev_info_t *dip, ddi_fm_error_t *derr, 58 px_err_pcie_t *regs); 59 60 #if defined(DEBUG) 61 static void px_pcie_log(dev_info_t *dip, px_err_pcie_t *regs); 62 #else /* DEBUG */ 63 #define px_pcie_log 0 && 64 #endif /* DEBUG */ 65 66 /* 67 * Initialize px FMA support 68 */ 69 int 70 px_fm_attach(px_t *px_p) 71 { 72 int i; 73 dev_info_t *dip = px_p->px_dip; 74 pcie_bus_t *bus_p; 75 76 px_p->px_fm_cap = DDI_FM_EREPORT_CAPABLE | DDI_FM_ERRCB_CAPABLE | 77 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE; 78 79 /* 80 * Initialize pci_target_queue for FMA handling of 81 * pci errors. 82 */ 83 pci_targetq_init(); 84 85 /* 86 * check parents' capability 87 */ 88 ddi_fm_init(dip, &px_p->px_fm_cap, &px_p->px_fm_ibc); 89 90 /* 91 * parents need to be ereport and error handling capable 92 */ 93 ASSERT(px_p->px_fm_cap && 94 (DDI_FM_ERRCB_CAPABLE | DDI_FM_EREPORT_CAPABLE)); 95 96 /* 97 * Initialize lock to synchronize fabric error handling 98 */ 99 mutex_init(&px_p->px_fm_mutex, NULL, MUTEX_DRIVER, 100 (void *)px_p->px_fm_ibc); 101 102 103 pcie_rc_init_bus(dip); 104 105 px_p->px_pfd_idx = 0; 106 for (i = 0; i < 5; i++) 107 pcie_rc_init_pfd(dip, &px_p->px_pfd_arr[i]); 108 PCIE_DIP2PFD(dip) = px_p->px_pfd_arr; 109 110 bus_p = PCIE_DIP2BUS(dip); 111 bus_p->bus_rp_bdf = px_p->px_bdf; 112 bus_p->bus_rp_dip = dip; 113 114 /* 115 * register error callback in parent 116 */ 117 ddi_fm_handler_register(dip, px_fm_callback, px_p); 118 119 return (DDI_SUCCESS); 120 } 121 122 /* 123 * Deregister FMA 124 */ 125 void 126 px_fm_detach(px_t *px_p) 127 { 128 int i; 129 130 ddi_fm_handler_unregister(px_p->px_dip); 131 mutex_destroy(&px_p->px_fm_mutex); 132 ddi_fm_fini(px_p->px_dip); 133 for (i = 0; i < 5; i++) 134 pcie_rc_fini_pfd(&px_p->px_pfd_arr[i]); 135 pcie_rc_fini_bus(px_p->px_dip); 136 } 137 138 /* 139 * Function used to setup access functions depending on level of desired 140 * protection. 141 */ 142 void 143 px_fm_acc_setup(ddi_map_req_t *mp, dev_info_t *rdip, pci_regspec_t *rp) 144 { 145 uchar_t fflag; 146 ndi_err_t *errp; 147 ddi_acc_hdl_t *hp; 148 ddi_acc_impl_t *ap; 149 150 hp = mp->map_handlep; 151 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 152 fflag = ap->ahi_common.ah_acc.devacc_attr_access; 153 154 if (mp->map_op == DDI_MO_MAP_LOCKED) { 155 ndi_fmc_insert(rdip, ACC_HANDLE, (void *)hp, NULL); 156 switch (fflag) { 157 case DDI_FLAGERR_ACC: 158 ap->ahi_get8 = i_ddi_prot_get8; 159 ap->ahi_get16 = i_ddi_prot_get16; 160 ap->ahi_get32 = i_ddi_prot_get32; 161 ap->ahi_get64 = i_ddi_prot_get64; 162 ap->ahi_put8 = i_ddi_prot_put8; 163 ap->ahi_put16 = i_ddi_prot_put16; 164 ap->ahi_put32 = i_ddi_prot_put32; 165 ap->ahi_put64 = i_ddi_prot_put64; 166 ap->ahi_rep_get8 = i_ddi_prot_rep_get8; 167 ap->ahi_rep_get16 = i_ddi_prot_rep_get16; 168 ap->ahi_rep_get32 = i_ddi_prot_rep_get32; 169 ap->ahi_rep_get64 = i_ddi_prot_rep_get64; 170 ap->ahi_rep_put8 = i_ddi_prot_rep_put8; 171 ap->ahi_rep_put16 = i_ddi_prot_rep_put16; 172 ap->ahi_rep_put32 = i_ddi_prot_rep_put32; 173 ap->ahi_rep_put64 = i_ddi_prot_rep_put64; 174 impl_acc_err_init(hp); 175 errp = ((ddi_acc_impl_t *)hp)->ahi_err; 176 if ((rp->pci_phys_hi & PCI_REG_ADDR_M) == 177 PCI_ADDR_CONFIG) 178 errp->err_cf = px_err_cfg_hdl_check; 179 else 180 errp->err_cf = px_err_pio_hdl_check; 181 break; 182 case DDI_CAUTIOUS_ACC : 183 ap->ahi_get8 = i_ddi_caut_get8; 184 ap->ahi_get16 = i_ddi_caut_get16; 185 ap->ahi_get32 = i_ddi_caut_get32; 186 ap->ahi_get64 = i_ddi_caut_get64; 187 ap->ahi_put8 = i_ddi_caut_put8; 188 ap->ahi_put16 = i_ddi_caut_put16; 189 ap->ahi_put32 = i_ddi_caut_put32; 190 ap->ahi_put64 = i_ddi_caut_put64; 191 ap->ahi_rep_get8 = i_ddi_caut_rep_get8; 192 ap->ahi_rep_get16 = i_ddi_caut_rep_get16; 193 ap->ahi_rep_get32 = i_ddi_caut_rep_get32; 194 ap->ahi_rep_get64 = i_ddi_caut_rep_get64; 195 ap->ahi_rep_put8 = i_ddi_caut_rep_put8; 196 ap->ahi_rep_put16 = i_ddi_caut_rep_put16; 197 ap->ahi_rep_put32 = i_ddi_caut_rep_put32; 198 ap->ahi_rep_put64 = i_ddi_caut_rep_put64; 199 impl_acc_err_init(hp); 200 errp = ((ddi_acc_impl_t *)hp)->ahi_err; 201 if ((rp->pci_phys_hi & PCI_REG_ADDR_M) == 202 PCI_ADDR_CONFIG) 203 errp->err_cf = px_err_cfg_hdl_check; 204 else 205 errp->err_cf = px_err_pio_hdl_check; 206 break; 207 default: 208 break; 209 } 210 } else if (mp->map_op == DDI_MO_UNMAP) { 211 ndi_fmc_remove(rdip, ACC_HANDLE, (void *)hp); 212 } 213 } 214 215 /* 216 * Function used to initialize FMA for our children nodes. Called 217 * through pci busops when child node calls ddi_fm_init. 218 */ 219 /*ARGSUSED*/ 220 int 221 px_fm_init_child(dev_info_t *dip, dev_info_t *cdip, int cap, 222 ddi_iblock_cookie_t *ibc_p) 223 { 224 px_t *px_p = DIP_TO_STATE(dip); 225 226 ASSERT(ibc_p != NULL); 227 *ibc_p = px_p->px_fm_ibc; 228 229 return (px_p->px_fm_cap); 230 } 231 232 /* 233 * lock access for exclusive PCIe access 234 */ 235 void 236 px_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle) 237 { 238 px_pec_t *pec_p = ((px_t *)DIP_TO_STATE(dip))->px_pec_p; 239 240 /* 241 * Exclusive access has been used for cautious put/get, 242 * Both utilize i_ddi_ontrap which, on sparcv9, implements 243 * similar protection as what on_trap() does, and which calls 244 * membar #Sync to flush out all cpu deferred errors 245 * prior to get/put operation, so here we're not calling 246 * membar #Sync - a difference from what's in pci_bus_enter(). 247 */ 248 mutex_enter(&pec_p->pec_pokefault_mutex); 249 pec_p->pec_acc_hdl = handle; 250 } 251 252 /* 253 * unlock access for exclusive PCIe access 254 */ 255 /* ARGSUSED */ 256 void 257 px_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle) 258 { 259 px_t *px_p = DIP_TO_STATE(dip); 260 px_pec_t *pec_p = px_p->px_pec_p; 261 262 pec_p->pec_acc_hdl = NULL; 263 mutex_exit(&pec_p->pec_pokefault_mutex); 264 } 265 266 static uint64_t 267 px_in_addr_range(dev_info_t *dip, px_ranges_t *ranges_p, uint64_t addr) 268 { 269 uint64_t addr_low, addr_high; 270 271 addr_low = ((uint64_t)ranges_p->parent_high << 32) | 272 (uint64_t)ranges_p->parent_low; 273 addr_high = addr_low + ((uint64_t)ranges_p->size_high << 32) + 274 (uint64_t)ranges_p->size_low; 275 276 DBG(DBG_ERR_INTR, dip, "Addr: 0x%llx high: 0x%llx low: 0x%llx\n", 277 addr, addr_high, addr_low); 278 279 if ((addr < addr_high) && (addr >= addr_low)) 280 return (addr_low); 281 282 return (0); 283 } 284 285 /* 286 * PCI error callback which is registered with our parent to call 287 * for PCIe logging when the CPU traps due to PCIe Uncorrectable Errors 288 * and PCI BERR/TO/UE on IO Loads. 289 */ 290 /*ARGSUSED*/ 291 int 292 px_fm_callback(dev_info_t *dip, ddi_fm_error_t *derr, const void *impl_data) 293 { 294 dev_info_t *pdip = ddi_get_parent(dip); 295 px_t *px_p = (px_t *)impl_data; 296 int i, acc_type = 0; 297 int lookup, rc_err, fab_err; 298 uint64_t addr, base_addr; 299 uint64_t fault_addr = (uint64_t)derr->fme_bus_specific; 300 pcie_req_id_t bdf; 301 px_ranges_t *ranges_p; 302 int range_len; 303 304 /* 305 * If the current thread already owns the px_fm_mutex, then we 306 * have encountered an error while processing a previous 307 * error. Attempting to take the mutex again will cause the 308 * system to deadlock. 309 */ 310 if (px_p->px_fm_mutex_owner == curthread) 311 return (DDI_FM_FATAL); 312 313 i_ddi_fm_handler_exit(pdip); 314 if (px_fm_enter(px_p) != DDI_SUCCESS) { 315 i_ddi_fm_handler_enter(pdip); 316 return (DDI_FM_FATAL); 317 } 318 319 /* 320 * Make sure this failed load came from this PCIe port. Check by 321 * matching the upper 32 bits of the address with the ranges property. 322 */ 323 range_len = px_p->px_ranges_length / sizeof (px_ranges_t); 324 i = 0; 325 for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) { 326 base_addr = px_in_addr_range(dip, ranges_p, fault_addr); 327 if (base_addr) { 328 switch (ranges_p->child_high & PCI_ADDR_MASK) { 329 case PCI_ADDR_CONFIG: 330 acc_type = PF_ADDR_CFG; 331 addr = NULL; 332 bdf = (pcie_req_id_t)((fault_addr >> 12) & 333 0xFFFF); 334 break; 335 case PCI_ADDR_IO: 336 case PCI_ADDR_MEM64: 337 case PCI_ADDR_MEM32: 338 acc_type = PF_ADDR_PIO; 339 addr = fault_addr - base_addr; 340 bdf = NULL; 341 break; 342 } 343 break; 344 } 345 } 346 347 /* This address doesn't belong to this leaf, just return with OK */ 348 if (!acc_type) { 349 px_fm_exit(px_p); 350 i_ddi_fm_handler_enter(pdip); 351 return (DDI_FM_OK); 352 } 353 354 rc_err = px_err_cmn_intr(px_p, derr, PX_TRAP_CALL, PX_FM_BLOCK_ALL); 355 lookup = pf_hdl_lookup(dip, derr->fme_ena, acc_type, (uint64_t)addr, 356 bdf); 357 358 px_rp_en_q(px_p, bdf, addr, 359 (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)); 360 361 fab_err = px_scan_fabric(px_p, dip, derr); 362 363 px_fm_exit(px_p); 364 i_ddi_fm_handler_enter(pdip); 365 366 if (!px_die) 367 return (DDI_FM_OK); 368 369 if ((rc_err & (PX_PANIC | PX_PROTECTED)) || 370 (fab_err & PF_ERR_FATAL_FLAGS) || 371 (lookup == PF_HDL_NOTFOUND)) 372 return (DDI_FM_FATAL); 373 else if ((rc_err == PX_NO_ERROR) && (fab_err == PF_ERR_NO_ERROR)) 374 return (DDI_FM_OK); 375 376 return (DDI_FM_NONFATAL); 377 } 378 379 /* 380 * px_err_fabric_intr: 381 * Interrupt handler for PCIE fabric block. 382 * o lock 383 * o create derr 384 * o px_err_cmn_intr(leaf, with jbc) 385 * o send ereport(fire fmri, derr, payload = BDF) 386 * o dispatch (leaf) 387 * o unlock 388 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 389 */ 390 /* ARGSUSED */ 391 uint_t 392 px_err_fabric_intr(px_t *px_p, msgcode_t msg_code, pcie_req_id_t rid) 393 { 394 dev_info_t *rpdip = px_p->px_dip; 395 int rc_err, fab_err; 396 ddi_fm_error_t derr; 397 uint32_t rp_status; 398 uint16_t ce_source, ue_source; 399 400 if (px_fm_enter(px_p) != DDI_SUCCESS) 401 goto done; 402 403 /* Create the derr */ 404 bzero(&derr, sizeof (ddi_fm_error_t)); 405 derr.fme_version = DDI_FME_VERSION; 406 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 407 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 408 409 px_err_safeacc_check(px_p, &derr); 410 411 if (msg_code == PCIE_MSG_CODE_ERR_COR) { 412 rp_status = PCIE_AER_RE_STS_CE_RCVD; 413 ce_source = rid; 414 ue_source = 0; 415 } else { 416 rp_status = PCIE_AER_RE_STS_FE_NFE_RCVD; 417 ce_source = 0; 418 ue_source = rid; 419 if (msg_code == PCIE_MSG_CODE_ERR_NONFATAL) 420 rp_status |= PCIE_AER_RE_STS_NFE_MSGS_RCVD; 421 else { 422 rp_status |= PCIE_AER_RE_STS_FE_MSGS_RCVD; 423 rp_status |= PCIE_AER_RE_STS_FIRST_UC_FATAL; 424 } 425 } 426 427 if (derr.fme_flag == DDI_FM_ERR_UNEXPECTED) { 428 ddi_fm_ereport_post(rpdip, PCI_ERROR_SUBCLASS "." PCIEX_FABRIC, 429 derr.fme_ena, 430 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 431 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 432 "pcie_adv_rp_status", DATA_TYPE_UINT32, rp_status, 433 "pcie_adv_rp_command", DATA_TYPE_UINT32, 0, 434 "pcie_adv_rp_ce_src_id", DATA_TYPE_UINT16, ce_source, 435 "pcie_adv_rp_ue_src_id", DATA_TYPE_UINT16, ue_source, 436 NULL); 437 } 438 439 /* Ensure that the rid of the fabric message will get scanned. */ 440 px_rp_en_q(px_p, rid, NULL, NULL); 441 442 rc_err = px_err_cmn_intr(px_p, &derr, PX_INTR_CALL, PX_FM_BLOCK_PCIE); 443 444 /* call rootport dispatch */ 445 fab_err = px_scan_fabric(px_p, rpdip, &derr); 446 447 px_err_panic(rc_err, PX_RC, fab_err, B_TRUE); 448 px_fm_exit(px_p); 449 px_err_panic(rc_err, PX_RC, fab_err, B_FALSE); 450 451 done: 452 return (DDI_INTR_CLAIMED); 453 } 454 455 /* 456 * px_scan_fabric: 457 * 458 * Check for drain state and if there is anything to scan. 459 */ 460 int 461 px_scan_fabric(px_t *px_p, dev_info_t *rpdip, ddi_fm_error_t *derr) { 462 int fab_err = 0; 463 464 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 465 466 if (!px_lib_is_in_drain_state(px_p) && px_p->px_pfd_idx) { 467 fab_err = pf_scan_fabric(rpdip, derr, px_p->px_pfd_arr); 468 px_p->px_pfd_idx = 0; 469 } 470 471 return (fab_err); 472 } 473 474 /* 475 * px_err_safeacc_check: 476 * Check to see if a peek/poke and cautious access is currently being 477 * done on a particular leaf. 478 * 479 * Safe access reads induced fire errors will be handled by cpu trap handler 480 * which will call px_fm_callback() which calls this function. In that 481 * case, the derr fields will be set by trap handler with the correct values. 482 * 483 * Safe access writes induced errors will be handled by px interrupt 484 * handlers, this function will fill in the derr fields. 485 * 486 * If a cpu trap does occur, it will quiesce all other interrupts allowing 487 * the cpu trap error handling to finish before Fire receives an interrupt. 488 * 489 * If fire does indeed have an error when a cpu trap occurs as a result of 490 * a safe access, a trap followed by a Mondo/Fabric interrupt will occur. 491 * In which case derr will be initialized as "UNEXPECTED" by the interrupt 492 * handler and this function will need to find if this error occured in the 493 * middle of a safe access operation. 494 * 495 * @param px_p leaf in which to check access 496 * @param derr fm err data structure to be updated 497 */ 498 void 499 px_err_safeacc_check(px_t *px_p, ddi_fm_error_t *derr) 500 { 501 px_pec_t *pec_p = px_p->px_pec_p; 502 int acctype = pec_p->pec_safeacc_type; 503 504 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 505 506 if (derr->fme_flag != DDI_FM_ERR_UNEXPECTED) { 507 return; 508 } 509 510 /* safe access checking */ 511 switch (acctype) { 512 case DDI_FM_ERR_EXPECTED: 513 /* 514 * cautious access protection, protected from all err. 515 */ 516 ddi_fm_acc_err_get(pec_p->pec_acc_hdl, derr, 517 DDI_FME_VERSION); 518 derr->fme_flag = acctype; 519 derr->fme_acc_handle = pec_p->pec_acc_hdl; 520 break; 521 case DDI_FM_ERR_POKE: 522 /* 523 * ddi_poke protection, check nexus and children for 524 * expected errors. 525 */ 526 membar_sync(); 527 derr->fme_flag = acctype; 528 break; 529 case DDI_FM_ERR_PEEK: 530 derr->fme_flag = acctype; 531 break; 532 } 533 } 534 535 /* 536 * Suggest panic if any EQ (except CE q) has overflown. 537 */ 538 int 539 px_err_check_eq(dev_info_t *dip) 540 { 541 px_t *px_p = DIP_TO_STATE(dip); 542 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 543 px_pec_t *pec_p = px_p->px_pec_p; 544 msiqid_t eq_no = msiq_state_p->msiq_1st_msiq_id; 545 pci_msiq_state_t msiq_state; 546 int i; 547 548 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 549 if (i + eq_no == pec_p->pec_corr_msg_msiq_id) /* skip CE q */ 550 continue; 551 if ((px_lib_msiq_getstate(dip, i + eq_no, &msiq_state) != 552 DDI_SUCCESS) || msiq_state == PCI_MSIQ_STATE_ERROR) 553 return (PX_PANIC); 554 } 555 return (PX_NO_PANIC); 556 } 557 558 /* ARGSUSED */ 559 int 560 px_err_check_pcie(dev_info_t *dip, ddi_fm_error_t *derr, px_err_pcie_t *regs) 561 { 562 px_t *px_p = DIP_TO_STATE(dip); 563 pf_data_t *pfd_p = px_get_pfd(px_p); 564 int i; 565 pf_pcie_adv_err_regs_t *adv_reg = PCIE_ADV_REG(pfd_p); 566 567 /* 568 * set RC s_status in PCI term to coordinate with downstream fabric 569 * errors ananlysis. 570 */ 571 if (regs->primary_ue & PCIE_AER_UCE_UR) 572 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat = PCI_STAT_R_MAST_AB; 573 if (regs->primary_ue & PCIE_AER_UCE_CA) 574 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat = PCI_STAT_R_TARG_AB; 575 if (regs->primary_ue & (PCIE_AER_UCE_PTLP | PCIE_AER_UCE_ECRC)) 576 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat = PCI_STAT_PERROR; 577 578 if (!regs->primary_ue) 579 goto done; 580 581 adv_reg->pcie_ce_status = regs->ce_reg; 582 adv_reg->pcie_ue_status = regs->ue_reg | regs->primary_ue; 583 PCIE_ADV_HDR(pfd_p, 0) = regs->rx_hdr1; 584 PCIE_ADV_HDR(pfd_p, 1) = regs->rx_hdr2; 585 PCIE_ADV_HDR(pfd_p, 2) = regs->rx_hdr3; 586 PCIE_ADV_HDR(pfd_p, 3) = regs->rx_hdr4; 587 for (i = regs->primary_ue; i != 1; i = i >> 1) 588 adv_reg->pcie_adv_ctl++; 589 590 if (regs->primary_ue & (PCIE_AER_UCE_UR | PCIE_AER_UCE_CA)) { 591 if (pf_tlp_decode(PCIE_DIP2BUS(dip), adv_reg) == DDI_SUCCESS) 592 PCIE_ROOT_FAULT(pfd_p)->fault_bdf = 593 adv_reg->pcie_ue_tgt_bdf; 594 } else if (regs->primary_ue & PCIE_AER_UCE_PTLP) { 595 if (pf_tlp_decode(PCIE_DIP2BUS(dip), adv_reg) == DDI_SUCCESS) { 596 PCIE_ROOT_FAULT(pfd_p)->fault_bdf = 597 adv_reg->pcie_ue_tgt_bdf; 598 if (adv_reg->pcie_ue_tgt_trans == 599 PF_ADDR_PIO) 600 PCIE_ROOT_FAULT(pfd_p)->fault_addr = 601 adv_reg->pcie_ue_tgt_addr; 602 } 603 604 /* 605 * Normally for Poisoned Completion TLPs we can look at the 606 * transmit log header for the original request and the original 607 * address, however this doesn't seem to be working. HW BUG. 608 */ 609 } 610 611 done: 612 px_pcie_log(dip, regs); 613 614 /* Return No Error here and let the pcie misc module analyse it */ 615 return (PX_NO_ERROR); 616 } 617 618 #if defined(DEBUG) 619 static void 620 px_pcie_log(dev_info_t *dip, px_err_pcie_t *regs) 621 { 622 DBG(DBG_ERR_INTR, dip, 623 "A PCIe RC error has occured\n" 624 "\tCE: 0x%x UE: 0x%x Primary UE: 0x%x\n" 625 "\tTX Hdr: 0x%x 0x%x 0x%x 0x%x\n\tRX Hdr: 0x%x 0x%x 0x%x 0x%x\n", 626 regs->ce_reg, regs->ue_reg, regs->primary_ue, 627 regs->tx_hdr1, regs->tx_hdr2, regs->tx_hdr3, regs->tx_hdr4, 628 regs->rx_hdr1, regs->rx_hdr2, regs->rx_hdr3, regs->rx_hdr4); 629 } 630 #endif 631 632 /* 633 * look through poisoned TLP cases and suggest panic/no panic depend on 634 * handle lookup. 635 */ 636 static int 637 px_pcie_ptlp(dev_info_t *dip, ddi_fm_error_t *derr, px_err_pcie_t *regs) 638 { 639 pf_pcie_adv_err_regs_t adv_reg; 640 pcie_req_id_t bdf; 641 uint64_t addr; 642 uint32_t trans_type; 643 int tlp_sts, tlp_cmd; 644 int lookup = PF_HDL_NOTFOUND; 645 646 if (regs->primary_ue != PCIE_AER_UCE_PTLP) 647 return (PX_PANIC); 648 649 if (!regs->rx_hdr1) 650 goto done; 651 652 adv_reg.pcie_ue_hdr[0] = regs->rx_hdr1; 653 adv_reg.pcie_ue_hdr[1] = regs->rx_hdr2; 654 adv_reg.pcie_ue_hdr[2] = regs->rx_hdr3; 655 adv_reg.pcie_ue_hdr[3] = regs->rx_hdr4; 656 657 tlp_sts = pf_tlp_decode(PCIE_DIP2BUS(dip), &adv_reg); 658 tlp_cmd = ((pcie_tlp_hdr_t *)(adv_reg.pcie_ue_hdr))->type; 659 660 if (tlp_sts == DDI_FAILURE) 661 goto done; 662 663 bdf = adv_reg.pcie_ue_tgt_bdf; 664 addr = adv_reg.pcie_ue_tgt_addr; 665 trans_type = adv_reg.pcie_ue_tgt_trans; 666 667 switch (tlp_cmd) { 668 case PCIE_TLP_TYPE_CPL: 669 case PCIE_TLP_TYPE_CPLLK: 670 /* 671 * Usually a PTLP is a CPL with data. Grab the completer BDF 672 * from the RX TLP, and the original address from the TX TLP. 673 */ 674 if (regs->tx_hdr1) { 675 adv_reg.pcie_ue_hdr[0] = regs->tx_hdr1; 676 adv_reg.pcie_ue_hdr[1] = regs->tx_hdr2; 677 adv_reg.pcie_ue_hdr[2] = regs->tx_hdr3; 678 adv_reg.pcie_ue_hdr[3] = regs->tx_hdr4; 679 680 lookup = pf_tlp_decode(PCIE_DIP2BUS(dip), &adv_reg); 681 if (lookup != DDI_SUCCESS) 682 break; 683 addr = adv_reg.pcie_ue_tgt_addr; 684 trans_type = adv_reg.pcie_ue_tgt_trans; 685 } /* FALLTHRU */ 686 case PCIE_TLP_TYPE_IO: 687 case PCIE_TLP_TYPE_MEM: 688 case PCIE_TLP_TYPE_MEMLK: 689 lookup = pf_hdl_lookup(dip, derr->fme_ena, trans_type, addr, 690 bdf); 691 break; 692 default: 693 lookup = PF_HDL_NOTFOUND; 694 } 695 done: 696 return (lookup == PF_HDL_FOUND ? PX_NO_PANIC : PX_PANIC); 697 } 698 699 /* 700 * px_get_pdf automatically allocates a RC pf_data_t and returns a pointer to 701 * it. This function should be used when an error requires a fabric scan. 702 */ 703 static pf_data_t * 704 px_get_pfd(px_t *px_p) { 705 int idx = px_p->px_pfd_idx++; 706 pf_data_t *pfd_p = &px_p->px_pfd_arr[idx]; 707 708 /* Clear Old Data */ 709 PCIE_ROOT_FAULT(pfd_p)->fault_bdf = 0; 710 PCIE_ROOT_FAULT(pfd_p)->fault_addr = 0; 711 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat = 0; 712 PCIE_ADV_REG(pfd_p)->pcie_ce_status = 0; 713 PCIE_ADV_REG(pfd_p)->pcie_ue_status = 0; 714 715 pfd_p->pe_next = NULL; 716 717 if (idx > 0) { 718 px_p->px_pfd_arr[idx - 1].pe_next = pfd_p; 719 pfd_p->pe_prev = &px_p->px_pfd_arr[idx - 1]; 720 } else { 721 pfd_p->pe_prev = NULL; 722 } 723 724 pfd_p->pe_valid = B_TRUE; 725 726 return (pfd_p); 727 } 728 729 /* 730 * This function appends a pf_data structure to the error q which is used later 731 * during PCIe fabric scan. It signifies: 732 * o errs rcvd in RC, that may have been propagated to/from the fabric 733 * o the fabric scan code should scan the device path of fault bdf/addr 734 * 735 * fault_bdf: The bdf that caused the fault, which may have error bits set. 736 * fault_addr: The PIO addr that caused the fault, such as failed PIO, but not 737 * failed DMAs. 738 * s_status: Secondary Status equivalent to why the fault occured. 739 * (ie S-TA/MA, R-TA) 740 * Either the fault bdf or addr may be NULL, but not both. 741 */ 742 void 743 px_rp_en_q(px_t *px_p, pcie_req_id_t fault_bdf, uint32_t fault_addr, 744 uint16_t s_status) 745 { 746 pf_data_t *pfd_p; 747 748 if (!fault_bdf && !fault_addr) 749 return; 750 751 pfd_p = px_get_pfd(px_p); 752 753 PCIE_ROOT_FAULT(pfd_p)->fault_bdf = fault_bdf; 754 PCIE_ROOT_FAULT(pfd_p)->fault_addr = (uint64_t)fault_addr; 755 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat = s_status; 756 } 757 758 759 /* 760 * Find and Mark CFG Handles as failed associated with the given BDF. We should 761 * always know the BDF for CFG accesses, since it is encoded in the address of 762 * the TLP. Since there can be multiple cfg handles, mark them all as failed. 763 */ 764 /* ARGSUSED */ 765 int 766 px_err_cfg_hdl_check(dev_info_t *dip, const void *handle, const void *arg1, 767 const void *arg2) 768 { 769 int status = DDI_FM_FATAL; 770 uint32_t addr = *(uint32_t *)arg1; 771 uint16_t bdf = *(uint16_t *)arg2; 772 pcie_bus_t *bus_p; 773 774 DBG(DBG_ERR_INTR, dip, "Check CFG Hdl: dip 0x%p addr 0x%x bdf=0x%x\n", 775 dip, addr, bdf); 776 777 bus_p = PCIE_DIP2BUS(dip); 778 779 /* 780 * Because CFG and IO Acc Handlers are on the same cache list and both 781 * types of hdls gets called for both types of errors. For this checker 782 * only mark the device as "Non-Fatal" if the addr == NULL and bdf != 783 * NULL. 784 */ 785 status = (!addr && (bus_p->bus_bdf == bdf)) ? DDI_FM_NONFATAL : 786 DDI_FM_FATAL; 787 788 return (status); 789 } 790 791 /* 792 * Find and Mark all ACC Handles associated with a give address and BDF as 793 * failed. If the BDF != NULL, then check to see if the device has a ACC Handle 794 * associated with ADDR. If the handle is not found, mark all the handles as 795 * failed. If the BDF == NULL, mark the handle as failed if it is associated 796 * with ADDR. 797 */ 798 int 799 px_err_pio_hdl_check(dev_info_t *dip, const void *handle, const void *arg1, 800 const void *arg2) 801 { 802 dev_info_t *px_dip = PCIE_DIP2BUS(dip)->bus_rp_dip; 803 px_t *px_p = INST_TO_STATE(ddi_get_instance(px_dip)); 804 px_ranges_t *ranges_p; 805 int range_len; 806 ddi_acc_handle_t ap = (ddi_acc_handle_t)handle; 807 ddi_acc_hdl_t *hp = impl_acc_hdl_get(ap); 808 int i, status = DDI_FM_FATAL; 809 uint64_t fault_addr = *(uint64_t *)arg1; 810 uint16_t bdf = *(uint16_t *)arg2; 811 uint64_t base_addr, range_addr; 812 uint_t size; 813 814 DBG(DBG_ERR_INTR, dip, "Check PIO Hdl: dip 0x%x addr 0x%x bdf=0x%x\n", 815 dip, fault_addr, bdf); 816 817 /* Normalize the base addr to the addr and strip off the HB info. */ 818 base_addr = (hp->ah_pfn << MMU_PAGESHIFT) + hp->ah_offset; 819 range_len = px_p->px_ranges_length / sizeof (px_ranges_t); 820 i = 0; 821 for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) { 822 range_addr = px_in_addr_range(dip, ranges_p, base_addr); 823 if (range_addr) { 824 switch (ranges_p->child_high & PCI_ADDR_MASK) { 825 case PCI_ADDR_IO: 826 case PCI_ADDR_MEM64: 827 case PCI_ADDR_MEM32: 828 base_addr = base_addr - range_addr; 829 break; 830 } 831 break; 832 } 833 } 834 835 /* 836 * Mark the handle as failed if the ADDR is mapped, or if we 837 * know the BDF and ADDR == 0. 838 */ 839 size = hp->ah_len; 840 if (((fault_addr >= base_addr) && (fault_addr < (base_addr + size))) || 841 ((fault_addr == NULL) && (bdf == PCIE_DIP2BUS(dip)->bus_bdf))) 842 status = DDI_FM_NONFATAL; 843 844 return (status); 845 } 846 847 /* 848 * Find and Mark all DNA Handles associated with a give address and BDF as 849 * failed. If the BDF != NULL, then check to see if the device has a DMA Handle 850 * associated with ADDR. If the handle is not found, mark all the handles as 851 * failed. If the BDF == NULL, mark the handle as failed if it is associated 852 * with ADDR. 853 */ 854 int 855 px_err_dma_hdl_check(dev_info_t *dip, const void *handle, const void *arg1, 856 const void *arg2) 857 { 858 ddi_dma_impl_t *pcie_dp; 859 int status = DDI_FM_FATAL; 860 uint32_t addr = *(uint32_t *)arg1; 861 uint16_t bdf = *(uint16_t *)arg2; 862 uint32_t base_addr; 863 uint_t size; 864 865 DBG(DBG_ERR_INTR, dip, "Check PIO Hdl: dip 0x%x addr 0x%x bdf=0x%x\n", 866 dip, addr, bdf); 867 868 pcie_dp = (ddi_dma_impl_t *)handle; 869 base_addr = (uint32_t)pcie_dp->dmai_mapping; 870 size = pcie_dp->dmai_size; 871 872 /* 873 * Mark the handle as failed if the ADDR is mapped, or if we 874 * know the BDF and ADDR == 0. 875 */ 876 if (((addr >= base_addr) && (addr < (base_addr + size))) || 877 ((addr == NULL) && (bdf != NULL))) 878 status = DDI_FM_NONFATAL; 879 880 return (status); 881 } 882 883 int 884 px_fm_enter(px_t *px_p) { 885 if (px_panicing || (px_p->px_fm_mutex_owner == curthread)) 886 return (DDI_FAILURE); 887 888 mutex_enter(&px_p->px_fm_mutex); 889 /* 890 * In rare cases when trap occurs and in the middle of scanning the 891 * fabric, a PIO will fail in the scan fabric. The CPU error handling 892 * code will correctly panic the system, while a mondo for the failed 893 * PIO may also show up. Normally the mondo will try to grab the mutex 894 * and wait until the callback finishes. But in this rare case, 895 * mutex_enter actually suceeds also continues to scan the fabric. 896 * 897 * This code below is designed specifically to check for this case. If 898 * we successfully grab the px_fm_mutex, the px_fm_mutex_owner better be 899 * NULL. If it isn't that means we are in the rare corner case. Return 900 * DDI_FAILURE, this should prevent PX from doing anymore error 901 * handling. 902 */ 903 if (px_p->px_fm_mutex_owner) { 904 return (DDI_FAILURE); 905 } 906 907 px_p->px_fm_mutex_owner = curthread; 908 909 if (px_panicing) { 910 px_fm_exit(px_p); 911 return (DDI_FAILURE); 912 } 913 return (DDI_SUCCESS); 914 } 915 916 void 917 px_fm_exit(px_t *px_p) { 918 px_p->px_fm_mutex_owner = NULL; 919 mutex_exit(&px_p->px_fm_mutex); 920 } 921 922 /* 923 * Panic if the err tunable is set and that we are not already in the middle 924 * of panic'ing. 925 * 926 * rc_err = Error severity of PX specific errors 927 * msg = Where the error was detected 928 * fabric_err = Error severity of PCIe Fabric errors 929 * isTest = Test if error severity causes panic 930 */ 931 #define MSZ (sizeof (fm_msg) -strlen(fm_msg) - 1) 932 void 933 px_err_panic(int rc_err, int msg, int fabric_err, boolean_t isTest) 934 { 935 char fm_msg[96] = ""; 936 int ferr = PX_NO_ERROR; 937 938 if (panicstr) { 939 px_panicing = B_TRUE; 940 return; 941 } 942 943 if (!(rc_err & px_die)) 944 goto fabric; 945 if (msg & PX_RC) 946 (void) strncat(fm_msg, px_panic_rc_msg, MSZ); 947 if (msg & PX_RP) 948 (void) strncat(fm_msg, px_panic_rp_msg, MSZ); 949 if (msg & PX_HB) 950 (void) strncat(fm_msg, px_panic_hb_msg, MSZ); 951 952 fabric: 953 if (fabric_err & PF_ERR_FATAL_FLAGS) 954 ferr = PX_PANIC; 955 else if (fabric_err & ~(PF_ERR_FATAL_FLAGS | PF_ERR_NO_ERROR)) 956 ferr = PX_NO_PANIC; 957 958 if (ferr & px_die) { 959 if (strlen(fm_msg)) { 960 (void) strncat(fm_msg, " and", MSZ); 961 } 962 (void) strncat(fm_msg, px_panic_fab_msg, MSZ); 963 } 964 965 if (strlen(fm_msg)) { 966 px_panicing = B_TRUE; 967 if (!isTest) 968 fm_panic("Fatal error has occured in:%s.(0x%x)(0x%x)", 969 fm_msg, rc_err, fabric_err); 970 } 971 } 972