1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCI Express nexus driver interface 31 */ 32 33 #include <sys/types.h> 34 #include <sys/conf.h> /* nulldev */ 35 #include <sys/stat.h> /* devctl */ 36 #include <sys/kmem.h> 37 #include <sys/sunddi.h> 38 #include <sys/sunndi.h> 39 #include <sys/hotplug/pci/pcihp.h> 40 #include <sys/ddi_impldefs.h> 41 #include <sys/ddi_subrdefs.h> 42 #include <sys/spl.h> 43 #include <sys/epm.h> 44 #include <sys/iommutsb.h> 45 #include "px_obj.h" 46 #include <sys/pci_tools.h> 47 #include "px_tools.h" 48 #include "pcie_pwr.h" 49 50 /*LINTLIBRARY*/ 51 52 /* 53 * function prototypes for dev ops routines: 54 */ 55 static int px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 56 static int px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 57 static int px_info(dev_info_t *dip, ddi_info_cmd_t infocmd, 58 void *arg, void **result); 59 static int px_pwr_setup(dev_info_t *dip); 60 static void px_pwr_teardown(dev_info_t *dip); 61 62 /* 63 * bus ops and dev ops structures: 64 */ 65 static struct bus_ops px_bus_ops = { 66 BUSO_REV, 67 px_map, 68 0, 69 0, 70 0, 71 i_ddi_map_fault, 72 px_dma_setup, 73 px_dma_allochdl, 74 px_dma_freehdl, 75 px_dma_bindhdl, 76 px_dma_unbindhdl, 77 px_lib_dma_sync, 78 px_dma_win, 79 px_dma_ctlops, 80 px_ctlops, 81 ddi_bus_prop_op, 82 ndi_busop_get_eventcookie, 83 ndi_busop_add_eventcall, 84 ndi_busop_remove_eventcall, 85 ndi_post_event, 86 NULL, 87 NULL, /* (*bus_config)(); */ 88 NULL, /* (*bus_unconfig)(); */ 89 px_fm_init_child, /* (*bus_fm_init)(); */ 90 NULL, /* (*bus_fm_fini)(); */ 91 px_bus_enter, /* (*bus_fm_access_enter)(); */ 92 px_bus_exit, /* (*bus_fm_access_fini)(); */ 93 pcie_bus_power, /* (*bus_power)(); */ 94 px_intr_ops /* (*bus_intr_op)(); */ 95 }; 96 97 extern struct cb_ops px_cb_ops; 98 99 static struct dev_ops px_ops = { 100 DEVO_REV, 101 0, 102 px_info, 103 nulldev, 104 0, 105 px_attach, 106 px_detach, 107 nodev, 108 &px_cb_ops, 109 &px_bus_ops, 110 nulldev 111 }; 112 113 /* 114 * module definitions: 115 */ 116 #include <sys/modctl.h> 117 extern struct mod_ops mod_driverops; 118 119 static struct modldrv modldrv = { 120 &mod_driverops, /* Type of module - driver */ 121 "PCI Express nexus driver %I%", /* Name of module. */ 122 &px_ops, /* driver ops */ 123 }; 124 125 static struct modlinkage modlinkage = { 126 MODREV_1, (void *)&modldrv, NULL 127 }; 128 129 /* driver soft state */ 130 void *px_state_p; 131 132 int 133 _init(void) 134 { 135 int e; 136 137 /* 138 * Initialize per-px bus soft state pointer. 139 */ 140 e = ddi_soft_state_init(&px_state_p, sizeof (px_t), 1); 141 if (e != DDI_SUCCESS) 142 return (e); 143 144 /* 145 * Install the module. 146 */ 147 e = mod_install(&modlinkage); 148 if (e != DDI_SUCCESS) 149 ddi_soft_state_fini(&px_state_p); 150 return (e); 151 } 152 153 int 154 _fini(void) 155 { 156 int e; 157 158 /* 159 * Remove the module. 160 */ 161 e = mod_remove(&modlinkage); 162 if (e != DDI_SUCCESS) 163 return (e); 164 165 /* Free px soft state */ 166 ddi_soft_state_fini(&px_state_p); 167 168 return (e); 169 } 170 171 int 172 _info(struct modinfo *modinfop) 173 { 174 return (mod_info(&modlinkage, modinfop)); 175 } 176 177 /* ARGSUSED */ 178 static int 179 px_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 180 { 181 int instance = getminor((dev_t)arg); 182 px_t *px_p = INST_TO_STATE(instance); 183 184 #ifdef HOTPLUG 185 /* 186 * Allow hotplug to deal with ones it manages 187 * Hot Plug will be done later. 188 */ 189 if (px_p && (px_p->hotplug_capable == B_TRUE)) 190 return (pcihp_info(dip, infocmd, arg, result)); 191 #endif /* HOTPLUG */ 192 193 /* non-hotplug or not attached */ 194 switch (infocmd) { 195 case DDI_INFO_DEVT2INSTANCE: 196 *result = (void *)(intptr_t)instance; 197 return (DDI_SUCCESS); 198 199 case DDI_INFO_DEVT2DEVINFO: 200 if (px_p == NULL) 201 return (DDI_FAILURE); 202 *result = (void *)px_p->px_dip; 203 return (DDI_SUCCESS); 204 205 default: 206 return (DDI_FAILURE); 207 } 208 } 209 210 /* device driver entry points */ 211 /* 212 * attach entry point: 213 */ 214 /*ARGSUSED*/ 215 static int 216 px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 217 { 218 px_t *px_p; /* per bus state pointer */ 219 int instance = DIP_TO_INST(dip); 220 int ret = DDI_SUCCESS; 221 devhandle_t dev_hdl = NULL; 222 223 switch (cmd) { 224 case DDI_ATTACH: 225 DBG(DBG_ATTACH, dip, "DDI_ATTACH\n"); 226 227 /* 228 * Allocate and get the per-px soft state structure. 229 */ 230 if (ddi_soft_state_zalloc(px_state_p, instance) 231 != DDI_SUCCESS) { 232 cmn_err(CE_WARN, "%s%d: can't allocate px state", 233 ddi_driver_name(dip), instance); 234 goto err_bad_px_softstate; 235 } 236 px_p = INST_TO_STATE(instance); 237 px_p->px_dip = dip; 238 mutex_init(&px_p->px_mutex, NULL, MUTEX_DRIVER, NULL); 239 px_p->px_soft_state = PX_SOFT_STATE_CLOSED; 240 px_p->px_open_count = 0; 241 242 /* 243 * Get key properties of the pci bridge node and 244 * determine it's type (psycho, schizo, etc ...). 245 */ 246 if (px_get_props(px_p, dip) == DDI_FAILURE) 247 goto err_bad_px_prop; 248 249 if ((px_fm_attach(px_p)) != DDI_SUCCESS) 250 goto err_bad_fm; 251 252 if (px_lib_dev_init(dip, &dev_hdl) != DDI_SUCCESS) 253 goto err_bad_dev_init; 254 255 /* Initilize device handle */ 256 px_p->px_dev_hdl = dev_hdl; 257 258 /* 259 * Initialize interrupt block. Note that this 260 * initialize error handling for the PEC as well. 261 */ 262 if ((ret = px_ib_attach(px_p)) != DDI_SUCCESS) 263 goto err_bad_ib; 264 265 if (px_cb_attach(px_p) != DDI_SUCCESS) 266 goto err_bad_cb; 267 268 /* 269 * Start creating the modules. 270 * Note that attach() routines should 271 * register and enable their own interrupts. 272 */ 273 274 if ((px_mmu_attach(px_p)) != DDI_SUCCESS) 275 goto err_bad_mmu; 276 277 if ((px_msiq_attach(px_p)) != DDI_SUCCESS) 278 goto err_bad_msiq; 279 280 if ((px_msi_attach(px_p)) != DDI_SUCCESS) 281 goto err_bad_msi; 282 283 if ((px_pec_attach(px_p)) != DDI_SUCCESS) 284 goto err_bad_pec; 285 286 if ((px_dma_attach(px_p)) != DDI_SUCCESS) 287 goto err_bad_pec; /* nothing to uninitialize on DMA */ 288 289 /* 290 * All of the error handlers have been registered 291 * by now so it's time to activate the interrupt. 292 */ 293 if ((ret = px_err_add_intr(&px_p->px_fault)) != DDI_SUCCESS) 294 goto err_bad_pec_add_intr; 295 296 /* 297 * Create the "devctl" node for hotplug and pcitool support. 298 * For non-hotplug bus, we still need ":devctl" to 299 * support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls. 300 */ 301 if (ddi_create_minor_node(dip, "devctl", S_IFCHR, 302 PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR), 303 DDI_NT_NEXUS, 0) != DDI_SUCCESS) { 304 goto err_bad_devctl_node; 305 } 306 307 if (pxtool_init(dip) != DDI_SUCCESS) 308 goto err_bad_pcitool_node; 309 310 /* 311 * power management setup. Even if it fails, attach will 312 * succeed as this is a optional feature. Since we are 313 * always at full power, this is not critical. 314 */ 315 if (pwr_common_setup(dip) != DDI_SUCCESS) { 316 DBG(DBG_PWR, dip, "pwr_common_setup failed\n"); 317 } else if (px_pwr_setup(dip) != DDI_SUCCESS) { 318 DBG(DBG_PWR, dip, "px_pwr_setup failed \n"); 319 pwr_common_teardown(dip); 320 } 321 322 /* 323 * add cpr callback 324 */ 325 px_cpr_add_callb(px_p); 326 327 ddi_report_dev(dip); 328 329 px_p->px_state = PX_ATTACHED; 330 DBG(DBG_ATTACH, dip, "attach success\n"); 331 break; 332 333 err_bad_pcitool_node: 334 ddi_remove_minor_node(dip, "devctl"); 335 err_bad_devctl_node: 336 px_err_rem_intr(&px_p->px_fault); 337 err_bad_pec_add_intr: 338 px_pec_detach(px_p); 339 err_bad_pec: 340 px_msi_detach(px_p); 341 err_bad_msi: 342 px_msiq_detach(px_p); 343 err_bad_msiq: 344 px_mmu_detach(px_p); 345 err_bad_mmu: 346 px_cb_detach(px_p); 347 err_bad_cb: 348 px_ib_detach(px_p); 349 err_bad_ib: 350 (void) px_lib_dev_fini(dip); 351 err_bad_dev_init: 352 px_fm_detach(px_p); 353 err_bad_fm: 354 px_free_props(px_p); 355 err_bad_px_prop: 356 mutex_destroy(&px_p->px_mutex); 357 ddi_soft_state_free(px_state_p, instance); 358 err_bad_px_softstate: 359 ret = DDI_FAILURE; 360 break; 361 362 case DDI_RESUME: 363 DBG(DBG_ATTACH, dip, "DDI_RESUME\n"); 364 365 px_p = INST_TO_STATE(instance); 366 367 mutex_enter(&px_p->px_mutex); 368 369 /* suspend might have not succeeded */ 370 if (px_p->px_state != PX_SUSPENDED) { 371 DBG(DBG_ATTACH, px_p->px_dip, 372 "instance NOT suspended\n"); 373 ret = DDI_FAILURE; 374 break; 375 } 376 377 px_lib_resume(dip); 378 (void) pcie_pwr_resume(dip); 379 px_p->px_state = PX_ATTACHED; 380 381 mutex_exit(&px_p->px_mutex); 382 383 break; 384 default: 385 DBG(DBG_ATTACH, dip, "unsupported attach op\n"); 386 ret = DDI_FAILURE; 387 break; 388 } 389 390 return (ret); 391 } 392 393 /* 394 * detach entry point: 395 */ 396 /*ARGSUSED*/ 397 static int 398 px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 399 { 400 int instance = ddi_get_instance(dip); 401 px_t *px_p = INST_TO_STATE(instance); 402 int ret; 403 404 /* 405 * Make sure we are currently attached 406 */ 407 if (px_p->px_state != PX_ATTACHED) { 408 DBG(DBG_DETACH, dip, "failed - instance not attached\n"); 409 return (DDI_FAILURE); 410 } 411 412 mutex_enter(&px_p->px_mutex); 413 414 switch (cmd) { 415 case DDI_DETACH: 416 DBG(DBG_DETACH, dip, "DDI_DETACH\n"); 417 418 /* 419 * remove cpr callback 420 */ 421 px_cpr_rem_callb(px_p); 422 423 #ifdef HOTPLUG 424 /* 425 * Hot plug will be done later. 426 */ 427 if (px_p->hotplug_capable == B_TRUE) { 428 if (pxhp_uninit(dip) == DDI_FAILURE) { 429 mutex_exit(&px_p->px_mutex); 430 return (DDI_FAILURE); 431 } 432 } 433 #endif /* HOTPLUG */ 434 435 /* 436 * things which used to be done in obj_destroy 437 * are now in-lined here. 438 */ 439 440 px_p->px_state = PX_DETACHED; 441 442 pxtool_uninit(dip); 443 444 ddi_remove_minor_node(dip, "devctl"); 445 px_err_rem_intr(&px_p->px_fault); 446 px_pec_detach(px_p); 447 px_msi_detach(px_p); 448 px_msiq_detach(px_p); 449 px_mmu_detach(px_p); 450 px_cb_detach(px_p); 451 px_ib_detach(px_p); 452 (void) px_lib_dev_fini(dip); 453 px_fm_detach(px_p); 454 455 /* 456 * Free the px soft state structure and the rest of the 457 * resources it's using. 458 */ 459 px_free_props(px_p); 460 px_pwr_teardown(dip); 461 pwr_common_teardown(dip); 462 mutex_exit(&px_p->px_mutex); 463 mutex_destroy(&px_p->px_mutex); 464 ddi_soft_state_free(px_state_p, instance); 465 466 /* Free the interrupt-priorities prop if we created it. */ { 467 int len; 468 469 if (ddi_getproplen(DDI_DEV_T_ANY, dip, 470 DDI_PROP_NOTPROM | DDI_PROP_DONTPASS, 471 "interrupt-priorities", &len) == DDI_PROP_SUCCESS) 472 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 473 "interrupt-priorities"); 474 } 475 476 px_p->px_dev_hdl = NULL; 477 478 return (DDI_SUCCESS); 479 480 case DDI_SUSPEND: 481 if (pcie_pwr_suspend(dip) != DDI_SUCCESS) { 482 mutex_exit(&px_p->px_mutex); 483 return (DDI_FAILURE); 484 } 485 if ((ret = px_lib_suspend(dip)) == DDI_SUCCESS) 486 px_p->px_state = PX_SUSPENDED; 487 mutex_exit(&px_p->px_mutex); 488 489 return (ret); 490 491 default: 492 DBG(DBG_DETACH, dip, "unsupported detach op\n"); 493 mutex_exit(&px_p->px_mutex); 494 return (DDI_FAILURE); 495 } 496 } 497 498 /* 499 * power management related initialization specific to px 500 * called by px_attach() 501 */ 502 static int 503 px_pwr_setup(dev_info_t *dip) 504 { 505 pcie_pwr_t *pwr_p; 506 int instance = ddi_get_instance(dip); 507 px_t *px_p = INST_TO_STATE(instance); 508 ddi_intr_handle_impl_t hdl; 509 ddi_iblock_cookie_t iblk_cookie; 510 511 ASSERT(PCIE_PMINFO(dip)); 512 pwr_p = PCIE_NEXUS_PMINFO(dip); 513 ASSERT(pwr_p); 514 515 /* 516 * indicate support LDI (Layered Driver Interface) 517 * Create the property, if it is not already there 518 */ 519 if (!ddi_prop_exists(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 520 DDI_KERNEL_IOCTL)) { 521 if (ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP, 522 DDI_KERNEL_IOCTL, NULL, 0) != DDI_PROP_SUCCESS) { 523 DBG(DBG_PWR, dip, "can't create kernel ioctl prop\n"); 524 return (DDI_FAILURE); 525 } 526 } 527 /* No support for device PM. We are always at full power */ 528 pwr_p->pwr_func_lvl = PM_LEVEL_D0; 529 530 mutex_init(&px_p->px_l23ready_lock, NULL, MUTEX_DRIVER, 531 (void *)(uintptr_t)px_pwr_pil); 532 cv_init(&px_p->px_l23ready_cv, NULL, CV_DRIVER, NULL); 533 534 mutex_init(&px_p->px_lup_lock, NULL, MUTEX_DRIVER, 535 (void *)PX_ERR_PIL); 536 cv_init(&px_p->px_lup_cv, NULL, CV_DRIVER, NULL); 537 538 if (ddi_get_soft_iblock_cookie(dip, DDI_SOFTINT_HIGH, 539 &iblk_cookie) != DDI_SUCCESS) { 540 DBG(DBG_PWR, dip, "px_pwr_setup: couldn't get iblock cookie\n"); 541 goto pwr_setup_err1; 542 } 543 mutex_init(&px_p->px_lupsoft_lock, NULL, MUTEX_DRIVER, 544 (void *)iblk_cookie); 545 if (ddi_add_softintr(dip, DDI_SOFTINT_HIGH, &px_p->px_lupsoft_id, 546 NULL, NULL, px_lup_softintr, (caddr_t)px_p) != DDI_SUCCESS) { 547 DBG(DBG_PWR, dip, "px_pwr_setup: couldn't add soft intr \n"); 548 goto pwr_setup_err2; 549 } 550 551 /* Initilize handle */ 552 hdl.ih_cb_arg1 = px_p; 553 hdl.ih_cb_arg2 = NULL; 554 hdl.ih_ver = DDI_INTR_VERSION; 555 hdl.ih_state = DDI_IHDL_STATE_ALLOC; 556 hdl.ih_dip = dip; 557 hdl.ih_inum = 0; 558 hdl.ih_pri = px_pwr_pil; 559 560 /* Add PME_TO_ACK message handler */ 561 hdl.ih_cb_func = (ddi_intr_handler_t *)px_pmeq_intr; 562 if (px_add_msiq_intr(dip, dip, &hdl, MSG_REC, 563 (msgcode_t)PCIE_PME_ACK_MSG, &px_p->px_pm_msiq_id) != DDI_SUCCESS) { 564 DBG(DBG_PWR, dip, "px_pwr_setup: couldn't add " 565 " PME_TO_ACK intr\n"); 566 goto px_pwrsetup_err; 567 } 568 px_lib_msg_setmsiq(dip, PCIE_PME_ACK_MSG, px_p->px_pm_msiq_id); 569 px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_VALID); 570 571 return (DDI_SUCCESS); 572 573 px_pwrsetup_err: 574 ddi_remove_softintr(px_p->px_lupsoft_id); 575 pwr_setup_err2: 576 mutex_destroy(&px_p->px_lupsoft_lock); 577 pwr_setup_err1: 578 mutex_destroy(&px_p->px_lup_lock); 579 cv_destroy(&px_p->px_lup_cv); 580 mutex_destroy(&px_p->px_l23ready_lock); 581 cv_destroy(&px_p->px_l23ready_cv); 582 583 return (DDI_FAILURE); 584 } 585 586 /* 587 * undo whatever is done in px_pwr_setup. called by px_detach() 588 */ 589 static void 590 px_pwr_teardown(dev_info_t *dip) 591 { 592 int instance = ddi_get_instance(dip); 593 px_t *px_p = INST_TO_STATE(instance); 594 ddi_intr_handle_impl_t hdl; 595 596 if (!PCIE_PMINFO(dip) || !PCIE_NEXUS_PMINFO(dip)) 597 return; 598 599 /* Initilize handle */ 600 hdl.ih_ver = DDI_INTR_VERSION; 601 hdl.ih_state = DDI_IHDL_STATE_ALLOC; 602 hdl.ih_dip = dip; 603 hdl.ih_inum = 0; 604 605 px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID); 606 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG, 607 px_p->px_pm_msiq_id); 608 609 px_p->px_pm_msiq_id = -1; 610 611 cv_destroy(&px_p->px_l23ready_cv); 612 ddi_remove_softintr(px_p->px_lupsoft_id); 613 mutex_destroy(&px_p->px_lupsoft_lock); 614 mutex_destroy(&px_p->px_lup_lock); 615 mutex_destroy(&px_p->px_l23ready_lock); 616 } 617 618 /* bus driver entry points */ 619 620 /* 621 * bus map entry point: 622 * 623 * if map request is for an rnumber 624 * get the corresponding regspec from device node 625 * build a new regspec in our parent's format 626 * build a new map_req with the new regspec 627 * call up the tree to complete the mapping 628 */ 629 int 630 px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 631 off_t off, off_t len, caddr_t *addrp) 632 { 633 px_t *px_p = DIP_TO_STATE(dip); 634 struct regspec p_regspec; 635 ddi_map_req_t p_mapreq; 636 int reglen, rval, r_no; 637 pci_regspec_t reloc_reg, *rp = &reloc_reg; 638 639 DBG(DBG_MAP, dip, "rdip=%s%d:", 640 ddi_driver_name(rdip), ddi_get_instance(rdip)); 641 642 if (mp->map_flags & DDI_MF_USER_MAPPING) 643 return (DDI_ME_UNIMPLEMENTED); 644 645 switch (mp->map_type) { 646 case DDI_MT_REGSPEC: 647 reloc_reg = *(pci_regspec_t *)mp->map_obj.rp; /* dup whole */ 648 break; 649 650 case DDI_MT_RNUMBER: 651 r_no = mp->map_obj.rnumber; 652 DBG(DBG_MAP | DBG_CONT, dip, " r#=%x", r_no); 653 654 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 655 "reg", (caddr_t)&rp, ®len) != DDI_SUCCESS) 656 return (DDI_ME_RNUMBER_RANGE); 657 658 if (r_no < 0 || r_no >= reglen / sizeof (pci_regspec_t)) { 659 kmem_free(rp, reglen); 660 return (DDI_ME_RNUMBER_RANGE); 661 } 662 rp += r_no; 663 break; 664 665 default: 666 return (DDI_ME_INVAL); 667 } 668 DBG(DBG_MAP | DBG_CONT, dip, "\n"); 669 670 if ((rp->pci_phys_hi & PCI_REG_ADDR_M) == PCI_ADDR_CONFIG) { 671 /* 672 * There may be a need to differentiate between PCI 673 * and PCI-Ex devices so the following range check is 674 * done correctly, depending on the implementation of 675 * px_pci bridge nexus driver. 676 */ 677 if ((off >= PCIE_CONF_HDR_SIZE) || 678 (len > PCIE_CONF_HDR_SIZE) || 679 (off + len > PCIE_CONF_HDR_SIZE)) 680 return (DDI_ME_INVAL); 681 /* 682 * the following function returning a DDI_FAILURE assumes 683 * that there are no virtual config space access services 684 * defined in this layer. Otherwise it is availed right 685 * here and we return. 686 */ 687 rval = px_lib_map_vconfig(dip, mp, off, rp, addrp); 688 if (rval == DDI_SUCCESS) 689 goto done; 690 } 691 692 /* 693 * No virtual config space services or we are mapping 694 * a region of memory mapped config/IO/memory space, so proceed 695 * to the parent. 696 */ 697 698 /* relocate within 64-bit pci space through "assigned-addresses" */ 699 if (rval = px_reloc_reg(dip, rdip, px_p, rp)) 700 goto done; 701 702 if (len) /* adjust regspec according to mapping request */ 703 rp->pci_size_low = len; /* MIN ? */ 704 rp->pci_phys_low += off; 705 706 /* translate relocated pci regspec into parent space through "ranges" */ 707 if (rval = px_xlate_reg(px_p, rp, &p_regspec)) 708 goto done; 709 710 p_mapreq = *mp; /* dup the whole structure */ 711 p_mapreq.map_type = DDI_MT_REGSPEC; 712 p_mapreq.map_obj.rp = &p_regspec; 713 px_lib_map_attr_check(&p_mapreq); 714 rval = ddi_map(dip, &p_mapreq, 0, 0, addrp); 715 716 if (rval == DDI_SUCCESS) { 717 /* 718 * Set-up access functions for FM access error capable drivers. 719 */ 720 if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(rdip)) && 721 mp->map_handlep->ah_acc.devacc_attr_access != 722 DDI_DEFAULT_ACC) 723 px_fm_acc_setup(mp, rdip); 724 } 725 726 done: 727 if (mp->map_type == DDI_MT_RNUMBER) 728 kmem_free(rp - r_no, reglen); 729 730 return (rval); 731 } 732 733 /* 734 * bus dma map entry point 735 * return value: 736 * DDI_DMA_PARTIAL_MAP 1 737 * DDI_DMA_MAPOK 0 738 * DDI_DMA_MAPPED 0 739 * DDI_DMA_NORESOURCES -1 740 * DDI_DMA_NOMAPPING -2 741 * DDI_DMA_TOOBIG -3 742 */ 743 int 744 px_dma_setup(dev_info_t *dip, dev_info_t *rdip, ddi_dma_req_t *dmareq, 745 ddi_dma_handle_t *handlep) 746 { 747 px_t *px_p = DIP_TO_STATE(dip); 748 px_mmu_t *mmu_p = px_p->px_mmu_p; 749 ddi_dma_impl_t *mp; 750 int ret; 751 752 DBG(DBG_DMA_MAP, dip, "mapping - rdip=%s%d type=%s\n", 753 ddi_driver_name(rdip), ddi_get_instance(rdip), 754 handlep ? "alloc" : "advisory"); 755 756 if (!(mp = px_dma_lmts2hdl(dip, rdip, mmu_p, dmareq))) 757 return (DDI_DMA_NORESOURCES); 758 if (mp == (ddi_dma_impl_t *)DDI_DMA_NOMAPPING) 759 return (DDI_DMA_NOMAPPING); 760 if (ret = px_dma_type(px_p, dmareq, mp)) 761 goto freehandle; 762 if (ret = px_dma_pfn(px_p, dmareq, mp)) 763 goto freehandle; 764 765 switch (PX_DMA_TYPE(mp)) { 766 case DMAI_FLAGS_DVMA: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */ 767 if ((ret = px_dvma_win(px_p, dmareq, mp)) || !handlep) 768 goto freehandle; 769 if (!PX_DMA_CANCACHE(mp)) { /* try fast track */ 770 if (PX_DMA_CANFAST(mp)) { 771 if (!px_dvma_map_fast(mmu_p, mp)) 772 break; 773 /* LINTED E_NOP_ELSE_STMT */ 774 } else { 775 PX_DVMA_FASTTRAK_PROF(mp); 776 } 777 } 778 if (ret = px_dvma_map(mp, dmareq, mmu_p)) 779 goto freehandle; 780 break; 781 case DMAI_FLAGS_PTP: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */ 782 if ((ret = px_dma_physwin(px_p, dmareq, mp)) || !handlep) 783 goto freehandle; 784 break; 785 case DMAI_FLAGS_BYPASS: 786 default: 787 cmn_err(CE_PANIC, "%s%d: px_dma_setup: bad dma type 0x%x", 788 ddi_driver_name(rdip), ddi_get_instance(rdip), 789 PX_DMA_TYPE(mp)); 790 /*NOTREACHED*/ 791 } 792 *handlep = (ddi_dma_handle_t)mp; 793 mp->dmai_flags |= DMAI_FLAGS_INUSE; 794 px_dump_dma_handle(DBG_DMA_MAP, dip, mp); 795 796 return ((mp->dmai_nwin == 1) ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP); 797 freehandle: 798 if (ret == DDI_DMA_NORESOURCES) 799 px_dma_freemp(mp); /* don't run_callback() */ 800 else 801 (void) px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp); 802 return (ret); 803 } 804 805 806 /* 807 * bus dma alloc handle entry point: 808 */ 809 int 810 px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 811 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep) 812 { 813 px_t *px_p = DIP_TO_STATE(dip); 814 ddi_dma_impl_t *mp; 815 int rval; 816 817 DBG(DBG_DMA_ALLOCH, dip, "rdip=%s%d\n", 818 ddi_driver_name(rdip), ddi_get_instance(rdip)); 819 820 if (attrp->dma_attr_version != DMA_ATTR_V0) 821 return (DDI_DMA_BADATTR); 822 823 if (!(mp = px_dma_allocmp(dip, rdip, waitfp, arg))) 824 return (DDI_DMA_NORESOURCES); 825 826 /* 827 * Save requestor's information 828 */ 829 mp->dmai_attr = *attrp; /* whole object - augmented later */ 830 *DEV_ATTR(mp) = *attrp; /* whole object - device orig attr */ 831 DBG(DBG_DMA_ALLOCH, dip, "mp=%p\n", mp); 832 833 /* check and convert dma attributes to handle parameters */ 834 if (rval = px_dma_attr2hdl(px_p, mp)) { 835 px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp); 836 *handlep = NULL; 837 return (rval); 838 } 839 *handlep = (ddi_dma_handle_t)mp; 840 return (DDI_SUCCESS); 841 } 842 843 844 /* 845 * bus dma free handle entry point: 846 */ 847 /*ARGSUSED*/ 848 int 849 px_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 850 { 851 DBG(DBG_DMA_FREEH, dip, "rdip=%s%d mp=%p\n", 852 ddi_driver_name(rdip), ddi_get_instance(rdip), handle); 853 px_dma_freemp((ddi_dma_impl_t *)handle); 854 855 if (px_kmem_clid) { 856 DBG(DBG_DMA_FREEH, dip, "run handle callback\n"); 857 ddi_run_callback(&px_kmem_clid); 858 } 859 return (DDI_SUCCESS); 860 } 861 862 863 /* 864 * bus dma bind handle entry point: 865 */ 866 int 867 px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 868 ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 869 ddi_dma_cookie_t *cookiep, uint_t *ccountp) 870 { 871 px_t *px_p = DIP_TO_STATE(dip); 872 px_mmu_t *mmu_p = px_p->px_mmu_p; 873 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 874 int ret; 875 876 DBG(DBG_DMA_BINDH, dip, "rdip=%s%d mp=%p dmareq=%p\n", 877 ddi_driver_name(rdip), ddi_get_instance(rdip), mp, dmareq); 878 879 if (mp->dmai_flags & DMAI_FLAGS_INUSE) 880 return (DDI_DMA_INUSE); 881 882 ASSERT((mp->dmai_flags & ~DMAI_FLAGS_PRESERVE) == 0); 883 mp->dmai_flags |= DMAI_FLAGS_INUSE; 884 885 if (ret = px_dma_type(px_p, dmareq, mp)) 886 goto err; 887 if (ret = px_dma_pfn(px_p, dmareq, mp)) 888 goto err; 889 890 switch (PX_DMA_TYPE(mp)) { 891 case DMAI_FLAGS_DVMA: 892 if (ret = px_dvma_win(px_p, dmareq, mp)) 893 goto map_err; 894 if (!PX_DMA_CANCACHE(mp)) { /* try fast track */ 895 if (PX_DMA_CANFAST(mp)) { 896 if (!px_dvma_map_fast(mmu_p, mp)) 897 goto mapped; /*LINTED E_NOP_ELSE_STMT*/ 898 } else { 899 PX_DVMA_FASTTRAK_PROF(mp); 900 } 901 } 902 if (ret = px_dvma_map(mp, dmareq, mmu_p)) 903 goto map_err; 904 mapped: 905 *ccountp = 1; 906 MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, mp->dmai_size); 907 break; 908 case DMAI_FLAGS_BYPASS: 909 case DMAI_FLAGS_PTP: 910 if (ret = px_dma_physwin(px_p, dmareq, mp)) 911 goto map_err; 912 *ccountp = WINLST(mp)->win_ncookies; 913 *cookiep = *(ddi_dma_cookie_t *)(WINLST(mp) + 1); /* wholeobj */ 914 break; 915 default: 916 cmn_err(CE_PANIC, "%s%d: px_dma_bindhdl(%p): bad dma type", 917 ddi_driver_name(rdip), ddi_get_instance(rdip), mp); 918 /*NOTREACHED*/ 919 } 920 DBG(DBG_DMA_BINDH, dip, "cookie %" PRIx64 "+%x\n", 921 cookiep->dmac_address, cookiep->dmac_size); 922 px_dump_dma_handle(DBG_DMA_MAP, dip, mp); 923 924 /* insert dma handle into FMA cache */ 925 if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR) 926 (void) ndi_fmc_insert(rdip, DMA_HANDLE, mp, NULL); 927 928 return (mp->dmai_nwin == 1 ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP); 929 map_err: 930 px_dma_freepfn(mp); 931 err: 932 mp->dmai_flags &= DMAI_FLAGS_PRESERVE; 933 return (ret); 934 } 935 936 937 /* 938 * bus dma unbind handle entry point: 939 */ 940 /*ARGSUSED*/ 941 int 942 px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 943 { 944 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 945 px_t *px_p = DIP_TO_STATE(dip); 946 px_mmu_t *mmu_p = px_p->px_mmu_p; 947 948 DBG(DBG_DMA_UNBINDH, dip, "rdip=%s%d, mp=%p\n", 949 ddi_driver_name(rdip), ddi_get_instance(rdip), handle); 950 if ((mp->dmai_flags & DMAI_FLAGS_INUSE) == 0) { 951 DBG(DBG_DMA_UNBINDH, dip, "handle not inuse\n"); 952 return (DDI_FAILURE); 953 } 954 955 /* remove dma handle from FMA cache */ 956 if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR) { 957 if (DEVI(rdip)->devi_fmhdl != NULL && 958 DDI_FM_DMA_ERR_CAP(DEVI(rdip)->devi_fmhdl->fh_cap)) { 959 (void) ndi_fmc_remove(rdip, DMA_HANDLE, mp); 960 } 961 } 962 963 /* 964 * Here if the handle is using the iommu. Unload all the iommu 965 * translations. 966 */ 967 switch (PX_DMA_TYPE(mp)) { 968 case DMAI_FLAGS_DVMA: 969 px_mmu_unmap_window(mmu_p, mp); 970 px_dvma_unmap(mmu_p, mp); 971 px_dma_freepfn(mp); 972 break; 973 case DMAI_FLAGS_BYPASS: 974 case DMAI_FLAGS_PTP: 975 px_dma_freewin(mp); 976 break; 977 default: 978 cmn_err(CE_PANIC, "%s%d: px_dma_unbindhdl:bad dma type %p", 979 ddi_driver_name(rdip), ddi_get_instance(rdip), mp); 980 /*NOTREACHED*/ 981 } 982 if (mmu_p->mmu_dvma_clid != 0) { 983 DBG(DBG_DMA_UNBINDH, dip, "run dvma callback\n"); 984 ddi_run_callback(&mmu_p->mmu_dvma_clid); 985 } 986 if (px_kmem_clid) { 987 DBG(DBG_DMA_UNBINDH, dip, "run handle callback\n"); 988 ddi_run_callback(&px_kmem_clid); 989 } 990 mp->dmai_flags &= DMAI_FLAGS_PRESERVE; 991 992 return (DDI_SUCCESS); 993 } 994 995 /* 996 * bus dma win entry point: 997 */ 998 int 999 px_dma_win(dev_info_t *dip, dev_info_t *rdip, 1000 ddi_dma_handle_t handle, uint_t win, off_t *offp, 1001 size_t *lenp, ddi_dma_cookie_t *cookiep, uint_t *ccountp) 1002 { 1003 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 1004 int ret; 1005 1006 DBG(DBG_DMA_WIN, dip, "rdip=%s%d\n", 1007 ddi_driver_name(rdip), ddi_get_instance(rdip)); 1008 1009 px_dump_dma_handle(DBG_DMA_WIN, dip, mp); 1010 if (win >= mp->dmai_nwin) { 1011 DBG(DBG_DMA_WIN, dip, "%x out of range\n", win); 1012 return (DDI_FAILURE); 1013 } 1014 1015 switch (PX_DMA_TYPE(mp)) { 1016 case DMAI_FLAGS_DVMA: 1017 if (win != PX_DMA_CURWIN(mp)) { 1018 px_t *px_p = DIP_TO_STATE(dip); 1019 px_mmu_t *mmu_p = px_p->px_mmu_p; 1020 px_mmu_unmap_window(mmu_p, mp); 1021 1022 /* map_window sets dmai_mapping/size/offset */ 1023 px_mmu_map_window(mmu_p, mp, win); 1024 if ((ret = px_mmu_map_window(mmu_p, 1025 mp, win)) != DDI_SUCCESS) 1026 return (ret); 1027 } 1028 if (cookiep) 1029 MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, 1030 mp->dmai_size); 1031 if (ccountp) 1032 *ccountp = 1; 1033 break; 1034 case DMAI_FLAGS_PTP: 1035 case DMAI_FLAGS_BYPASS: { 1036 int i; 1037 ddi_dma_cookie_t *ck_p; 1038 px_dma_win_t *win_p = mp->dmai_winlst; 1039 1040 for (i = 0; i < win; win_p = win_p->win_next, i++); 1041 ck_p = (ddi_dma_cookie_t *)(win_p + 1); 1042 *cookiep = *ck_p; 1043 mp->dmai_offset = win_p->win_offset; 1044 mp->dmai_size = win_p->win_size; 1045 mp->dmai_mapping = ck_p->dmac_laddress; 1046 mp->dmai_cookie = ck_p + 1; 1047 win_p->win_curseg = 0; 1048 if (ccountp) 1049 *ccountp = win_p->win_ncookies; 1050 } 1051 break; 1052 default: 1053 cmn_err(CE_WARN, "%s%d: px_dma_win:bad dma type 0x%x", 1054 ddi_driver_name(rdip), ddi_get_instance(rdip), 1055 PX_DMA_TYPE(mp)); 1056 return (DDI_FAILURE); 1057 } 1058 if (cookiep) 1059 DBG(DBG_DMA_WIN, dip, 1060 "cookie - dmac_address=%x dmac_size=%x\n", 1061 cookiep->dmac_address, cookiep->dmac_size); 1062 if (offp) 1063 *offp = (off_t)mp->dmai_offset; 1064 if (lenp) 1065 *lenp = mp->dmai_size; 1066 return (DDI_SUCCESS); 1067 } 1068 1069 #ifdef DEBUG 1070 static char *px_dmactl_str[] = { 1071 "DDI_DMA_FREE", 1072 "DDI_DMA_SYNC", 1073 "DDI_DMA_HTOC", 1074 "DDI_DMA_KVADDR", 1075 "DDI_DMA_MOVWIN", 1076 "DDI_DMA_REPWIN", 1077 "DDI_DMA_GETERR", 1078 "DDI_DMA_COFF", 1079 "DDI_DMA_NEXTWIN", 1080 "DDI_DMA_NEXTSEG", 1081 "DDI_DMA_SEGTOC", 1082 "DDI_DMA_RESERVE", 1083 "DDI_DMA_RELEASE", 1084 "DDI_DMA_RESETH", 1085 "DDI_DMA_CKSYNC", 1086 "DDI_DMA_IOPB_ALLOC", 1087 "DDI_DMA_IOPB_FREE", 1088 "DDI_DMA_SMEM_ALLOC", 1089 "DDI_DMA_SMEM_FREE", 1090 "DDI_DMA_SET_SBUS64" 1091 }; 1092 #endif /* DEBUG */ 1093 1094 /* 1095 * bus dma control entry point: 1096 */ 1097 /*ARGSUSED*/ 1098 int 1099 px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 1100 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 1101 uint_t cache_flags) 1102 { 1103 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 1104 1105 #ifdef DEBUG 1106 DBG(DBG_DMA_CTL, dip, "%s: rdip=%s%d\n", px_dmactl_str[cmd], 1107 ddi_driver_name(rdip), ddi_get_instance(rdip)); 1108 #endif /* DEBUG */ 1109 1110 switch (cmd) { 1111 case DDI_DMA_FREE: 1112 (void) px_dma_unbindhdl(dip, rdip, handle); 1113 (void) px_dma_freehdl(dip, rdip, handle); 1114 return (DDI_SUCCESS); 1115 case DDI_DMA_RESERVE: { 1116 px_t *px_p = DIP_TO_STATE(dip); 1117 return (px_fdvma_reserve(dip, rdip, px_p, 1118 (ddi_dma_req_t *)offp, (ddi_dma_handle_t *)objp)); 1119 } 1120 case DDI_DMA_RELEASE: { 1121 px_t *px_p = DIP_TO_STATE(dip); 1122 return (px_fdvma_release(dip, px_p, mp)); 1123 } 1124 default: 1125 break; 1126 } 1127 1128 switch (PX_DMA_TYPE(mp)) { 1129 case DMAI_FLAGS_DVMA: 1130 return (px_dvma_ctl(dip, rdip, mp, cmd, offp, lenp, objp, 1131 cache_flags)); 1132 case DMAI_FLAGS_PTP: 1133 case DMAI_FLAGS_BYPASS: 1134 return (px_dma_ctl(dip, rdip, mp, cmd, offp, lenp, objp, 1135 cache_flags)); 1136 default: 1137 cmn_err(CE_PANIC, "%s%d: px_dma_ctlops(%x):bad dma type %x", 1138 ddi_driver_name(rdip), ddi_get_instance(rdip), cmd, 1139 mp->dmai_flags); 1140 /*NOTREACHED*/ 1141 } 1142 return (0); 1143 } 1144 1145 /* 1146 * control ops entry point: 1147 * 1148 * Requests handled completely: 1149 * DDI_CTLOPS_INITCHILD see init_child() for details 1150 * DDI_CTLOPS_UNINITCHILD 1151 * DDI_CTLOPS_REPORTDEV see report_dev() for details 1152 * DDI_CTLOPS_XLATE_INTRS nothing to do 1153 * DDI_CTLOPS_IOMIN cache line size if streaming otherwise 1 1154 * DDI_CTLOPS_REGSIZE 1155 * DDI_CTLOPS_NREGS 1156 * DDI_CTLOPS_NINTRS 1157 * DDI_CTLOPS_DVMAPAGESIZE 1158 * DDI_CTLOPS_POKE 1159 * DDI_CTLOPS_PEEK 1160 * 1161 * All others passed to parent. 1162 */ 1163 int 1164 px_ctlops(dev_info_t *dip, dev_info_t *rdip, 1165 ddi_ctl_enum_t op, void *arg, void *result) 1166 { 1167 px_t *px_p = DIP_TO_STATE(dip); 1168 struct detachspec *ds; 1169 struct attachspec *as; 1170 1171 switch (op) { 1172 case DDI_CTLOPS_INITCHILD: 1173 return (px_init_child(px_p, (dev_info_t *)arg)); 1174 1175 case DDI_CTLOPS_UNINITCHILD: 1176 return (px_uninit_child(px_p, (dev_info_t *)arg)); 1177 1178 case DDI_CTLOPS_ATTACH: 1179 as = (struct attachspec *)arg; 1180 switch (as->when) { 1181 case DDI_PRE: 1182 if (as->cmd == DDI_ATTACH) { 1183 DBG(DBG_PWR, dip, "PRE_ATTACH for %s@%d\n", 1184 ddi_driver_name(rdip), 1185 ddi_get_instance(rdip)); 1186 return (pcie_pm_hold(dip)); 1187 } 1188 if (as->cmd == DDI_RESUME) { 1189 ddi_acc_handle_t config_handle; 1190 DBG(DBG_PWR, dip, "PRE_RESUME for %s@%d\n", 1191 ddi_driver_name(rdip), 1192 ddi_get_instance(rdip)); 1193 1194 if (pci_config_setup(rdip, &config_handle) == 1195 DDI_SUCCESS) { 1196 pcie_clear_errors(rdip, config_handle); 1197 pci_config_teardown(&config_handle); 1198 } 1199 } 1200 return (DDI_SUCCESS); 1201 1202 case DDI_POST: 1203 DBG(DBG_PWR, dip, "POST_ATTACH for %s@%d\n", 1204 ddi_driver_name(rdip), ddi_get_instance(rdip)); 1205 if (as->cmd == DDI_ATTACH && as->result != DDI_SUCCESS) 1206 pcie_pm_release(dip); 1207 return (DDI_SUCCESS); 1208 default: 1209 break; 1210 } 1211 break; 1212 1213 case DDI_CTLOPS_DETACH: 1214 ds = (struct detachspec *)arg; 1215 switch (ds->when) { 1216 case DDI_POST: 1217 if (ds->cmd == DDI_DETACH && 1218 ds->result == DDI_SUCCESS) { 1219 DBG(DBG_PWR, dip, "POST_DETACH for %s@%d\n", 1220 ddi_driver_name(rdip), 1221 ddi_get_instance(rdip)); 1222 return (pcie_pm_remove_child(dip, rdip)); 1223 } 1224 return (DDI_SUCCESS); 1225 default: 1226 break; 1227 } 1228 break; 1229 1230 case DDI_CTLOPS_REPORTDEV: 1231 return (px_report_dev(rdip)); 1232 1233 case DDI_CTLOPS_IOMIN: 1234 return (DDI_SUCCESS); 1235 1236 case DDI_CTLOPS_REGSIZE: 1237 *((off_t *)result) = px_get_reg_set_size(rdip, *((int *)arg)); 1238 return (*((off_t *)result) == 0 ? DDI_FAILURE : DDI_SUCCESS); 1239 1240 case DDI_CTLOPS_NREGS: 1241 *((uint_t *)result) = px_get_nreg_set(rdip); 1242 return (DDI_SUCCESS); 1243 1244 case DDI_CTLOPS_DVMAPAGESIZE: 1245 *((ulong_t *)result) = MMU_PAGE_SIZE; 1246 return (DDI_SUCCESS); 1247 1248 case DDI_CTLOPS_POKE: /* platform dependent implementation. */ 1249 return (px_lib_ctlops_poke(dip, rdip, 1250 (peekpoke_ctlops_t *)arg)); 1251 1252 case DDI_CTLOPS_PEEK: /* platform dependent implementation. */ 1253 return (px_lib_ctlops_peek(dip, rdip, 1254 (peekpoke_ctlops_t *)arg, result)); 1255 1256 case DDI_CTLOPS_POWER: 1257 default: 1258 break; 1259 } 1260 1261 /* 1262 * Now pass the request up to our parent. 1263 */ 1264 DBG(DBG_CTLOPS, dip, "passing request to parent: rdip=%s%d\n", 1265 ddi_driver_name(rdip), ddi_get_instance(rdip)); 1266 return (ddi_ctlops(dip, rdip, op, arg, result)); 1267 } 1268 1269 /* ARGSUSED */ 1270 int 1271 px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 1272 ddi_intr_handle_impl_t *hdlp, void *result) 1273 { 1274 int intr_types, ret = DDI_SUCCESS; 1275 1276 DBG(DBG_INTROPS, dip, "px_intr_ops: rdip=%s%d\n", 1277 ddi_driver_name(rdip), ddi_get_instance(rdip)); 1278 1279 /* Process DDI_INTROP_SUPPORTED_TYPES request here */ 1280 if (intr_op == DDI_INTROP_SUPPORTED_TYPES) { 1281 px_t *px_p = DIP_TO_STATE(dip); 1282 px_msi_state_t *msi_state_p = &px_p->px_ib_p->ib_msi_state; 1283 1284 *(int *)result = i_ddi_get_nintrs(rdip) ? 1285 DDI_INTR_TYPE_FIXED : 0; 1286 1287 if ((pci_msi_get_supported_type(rdip, 1288 &intr_types)) == DDI_SUCCESS) { 1289 /* 1290 * Double check supported interrupt types vs. 1291 * what the host bridge supports. 1292 */ 1293 *(int *)result |= (intr_types & msi_state_p->msi_type); 1294 } 1295 1296 return (ret); 1297 } 1298 1299 /* 1300 * PCI-E nexus driver supports fixed, MSI and MSI-X interrupts. 1301 * Return failure if interrupt type is not supported. 1302 */ 1303 switch (hdlp->ih_type) { 1304 case DDI_INTR_TYPE_FIXED: 1305 ret = px_intx_ops(dip, rdip, intr_op, hdlp, result); 1306 break; 1307 case DDI_INTR_TYPE_MSI: 1308 case DDI_INTR_TYPE_MSIX: 1309 ret = px_msix_ops(dip, rdip, intr_op, hdlp, result); 1310 break; 1311 default: 1312 ret = DDI_ENOTSUP; 1313 break; 1314 } 1315 1316 return (ret); 1317 } 1318