1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * Intel 82077 Floppy Disk Driver 31 */ 32 33 /* 34 * Notes 35 * 36 * 0. The driver supports two flavors of hardware design: 37 * "SUNW,fdtwo" - sun4m - 82077 with sun4m style Auxio 38 * "fdthree" - sun4u - 82077 with DMA 39 * In addition it supports an apparent bug in some versions of 40 * the 82077 controller. 41 * 42 * 1. The driver is mostly set up for multiple controllers, multiple 43 * drives. However- we *do* assume the use of the AUXIO register, and 44 * if we ever have > 1 fdc, we'll have to see what that means. This 45 * is all intrinsically machine specific, but there isn't much we 46 * can do about it. 47 * 48 * 2. The driver also is structured to deal with one drive active at 49 * a time. This is because the 82072 chip (no longer supported) was 50 * known to be buggy with respect to overlapped seeks. 51 * 52 * 3. The high level interrupt code is in assembler, and runs in a 53 * sparc trap window. It acts as a pseudo-dma engine as well as 54 * handles a couple of other interrupts. When it gets its job done, 55 * it schedules a second stage interrupt (soft interrupt) which 56 * is then fielded here in fd_lointr. When DMA is used, the fdintr_dma 57 * interrupt handler is used. 58 * 59 * 4. Nearly all locking is done on a lower level MUTEX_DRIVER 60 * mutex. The locking is quite conservative, and is generally 61 * established very close to any of the entries into the driver. 62 * There is nearly no locking done of the high level MUTEX_DRIVER 63 * mutex (which generally is a SPIN mutex because the floppy usually 64 * interrupts above LOCK_LEVEL). The assembler high level interrupt 65 * handler grabs the high level mutex, but the code in the driver 66 * here is especially structured to not need to do this. 67 * 68 * 5. Fdrawioctl commands that pass data are not optimized for 69 * speed. If they need to be faster, the driver structure will 70 * have to be redone such that fdrawioctl calls physio after 71 * cons'ing up a uio structure and that fdstart will be able 72 * to detect that a particular buffer is a 'special' buffer. 73 * 74 * 6. Removable media support is not complete. 75 * 76 */ 77 78 #include <sys/param.h> 79 #include <sys/buf.h> 80 #include <sys/ioctl.h> 81 #include <sys/uio.h> 82 #include <sys/open.h> 83 #include <sys/conf.h> 84 #include <sys/file.h> 85 #include <sys/cmn_err.h> 86 #include <sys/debug.h> 87 #include <sys/kmem.h> 88 #include <sys/stat.h> 89 #include <sys/autoconf.h> 90 91 #include <sys/dklabel.h> 92 93 #include <sys/vtoc.h> 94 #include <sys/dkio.h> 95 #include <sys/fdio.h> 96 97 #include <sys/ddi.h> 98 #include <sys/sunddi.h> 99 #include <sys/kstat.h> 100 101 /* 102 * included to check for ELC or SLC which report floppy controller that 103 */ 104 #include <sys/cpu.h> 105 106 #include "sys/fdvar.h" 107 #include "sys/fdreg.h" 108 #include "sys/dma_i8237A.h" 109 110 /* 111 * Defines 112 */ 113 #define KIOSP KSTAT_IO_PTR(un->un_iostat) 114 #define KIOIP KSTAT_INTR_PTR(fdc->c_intrstat) 115 #define MEDIUM_DENSITY 0x40 116 #define SEC_SIZE_CODE (fdctlr.c_csb->csb_unit]->un_chars->medium ? 3 : 2) 117 #define CMD_READ (MT + SK + FDRAW_RDCMD + MFM) 118 #define CMD_WRITE (MT + FDRAW_WRCMD + MFM) 119 #define C CE_CONT 120 #define FD_POLLABLE_PROP "pollable" /* prom property */ 121 #define FD_MANUAL_EJECT "manual" /* prom property */ 122 #define FD_UNIT "unit" /* prom property */ 123 124 /* 125 * Sony MP-F17W-50D Drive Parameters 126 * High Capacity 127 * Capacity unformatted 2Mb 128 * Capacity formatted 1.47Mb 129 * Encoding method MFM 130 * Recording density 17434 bpi 131 * Track density 135 tpi 132 * Cylinders 80 133 * Heads 2 134 * Tracks 160 135 * Rotational speed 300 rpm 136 * Transfer rate 250/500 kbps 137 * Latency (average) 100 ms 138 * Access time 139 * Average 95 ms 140 * Track to track 3 ms 141 * Head settling time 15 ms 142 * Motor start time 500 ms 143 * Head load time ? ms 144 */ 145 146 /* 147 * The max_fd_dma_len is used only when southbridge is present. 148 * It has been observed that when IFB tests are run the floppy dma could get 149 * starved and result in underrun errors. After experimenting it was found that 150 * doing dma in chunks of 2048 works OK. 151 * The reason for making this a global variable is that there could be 152 * situations under which the customer would like to get full performance 153 * from floppy. He may not be having IFB boards that cause underrun errors. 154 * Under those conditions we could set this value to a much higher value 155 * by editing /etc/system file. 156 */ 157 int max_fd_dma_len = 2048; 158 159 static void quiesce_fd_interrupt(struct fdctlr *); 160 161 /* 162 * Character/block entry points function prototypes 163 */ 164 static int fd_open(dev_t *, int, int, cred_t *); 165 static int fd_close(dev_t, int, int, cred_t *); 166 static int fd_strategy(struct buf *); 167 static int fd_read(dev_t, struct uio *, cred_t *); 168 static int fd_write(dev_t, struct uio *, cred_t *); 169 static int fd_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 170 static int 171 fd_prop_op(dev_t, dev_info_t *, ddi_prop_op_t, int, char *, caddr_t, int *); 172 173 /* 174 * Device operations (dev_ops) entries function prototypes 175 */ 176 static int fd_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, 177 void **result); 178 static int fd_attach(dev_info_t *, ddi_attach_cmd_t); 179 static int fd_detach(dev_info_t *, ddi_detach_cmd_t); 180 static int fd_power(dev_info_t *dip, int component, int level); 181 182 /* 183 * Internal functions 184 */ 185 static int fd_attach_check_drive(struct fdctlr *fdc); 186 static int fd_attach_det_ctlr(dev_info_t *dip, struct fdctlr *fdc); 187 static int fd_attach_map_regs(dev_info_t *dip, struct fdctlr *fdc); 188 static int fd_attach_register_interrupts(dev_info_t *dip, struct fdctlr *fdc, 189 int *hard); 190 static int fd_build_label_vtoc(struct fdunit *, struct vtoc *); 191 static void fd_build_user_vtoc(struct fdunit *, struct vtoc *); 192 static int fdcheckdisk(struct fdctlr *fdc, int unit); 193 static int fd_check_media(dev_t dev, enum dkio_state state); 194 static void fd_cleanup(dev_info_t *dip, struct fdctlr *fdc, int hard, 195 int locks); 196 static void fdeject(struct fdctlr *, int unit); 197 static int fdexec(struct fdctlr *fdc, int flags); 198 static void fdexec_turn_on_motor(struct fdctlr *fdc, int flags, uint_t unit); 199 static int fdformat(struct fdctlr *fdc, int unit, int cyl, int hd); 200 static caddr_t fd_getauxiova(); 201 static struct fdctlr *fd_getctlr(dev_t); 202 static void fdgetcsb(struct fdctlr *); 203 static int fdgetlabel(struct fdctlr *fdc, int unit); 204 enum dkio_state fd_get_media_state(struct fdctlr *, int); 205 static uint_t fdintr_dma(); 206 static int fd_isauxiodip(dev_info_t *); 207 static uint_t fd_lointr(caddr_t arg); 208 static void fd_media_watch(void *); 209 static void fdmotoff(void *); 210 static int fd_part_is_open(struct fdunit *un, int part); 211 static int fdrawioctl(struct fdctlr *, int, intptr_t, int); 212 static int fdrecalseek(struct fdctlr *fdc, int unit, int arg, int execflg); 213 static int fdrecover(struct fdctlr *); 214 static void fdretcsb(struct fdctlr *); 215 static int fdreset(struct fdctlr *); 216 static int fdrw(struct fdctlr *fdc, int, int, int, int, int, caddr_t, uint_t); 217 static void fdselect(struct fdctlr *fdc, int unit, int onoff); 218 static int fdsensedrv(struct fdctlr *fdc, int unit); 219 static int fdsense_chng(struct fdctlr *, int unit); 220 static void fdstart(struct fdctlr *); 221 static int fdstart_dma(register struct fdctlr *fdc, caddr_t addr, uint_t len); 222 static int fd_unit_is_open(struct fdunit *); 223 static void fdunpacklabel(struct packed_label *, struct dk_label *); 224 static int fd_unbind_handle(struct fdctlr *); 225 static void fdwatch(void *); 226 static void set_rotational_speed(struct fdctlr *, int); 227 static int fd_get_media_info(struct fdunit *un, caddr_t buf, int flag); 228 static int fd_pm_lower_power(struct fdctlr *fdc); 229 static int fd_pm_raise_power(struct fdctlr *fdc); 230 static void create_pm_components(dev_info_t *dip); 231 static void set_data_count_register(struct fdctlr *fdc, uint32_t count); 232 static uint32_t get_data_count_register(struct fdctlr *fdc); 233 static void reset_dma_controller(struct fdctlr *fdc); 234 static void set_data_address_register(struct fdctlr *fdc, uint32_t address); 235 static uint32_t get_dma_control_register(struct fdctlr *fdc); 236 static void set_dma_mode(struct fdctlr *fdc, int val); 237 static void set_dma_control_register(struct fdctlr *fdc, uint32_t val); 238 static void release_sb_dma(struct fdctlr *fdc); 239 240 /* 241 * External functions 242 */ 243 extern uint_t fd_intr(caddr_t); /* defined in fd_asm.s */ 244 extern void set_auxioreg(); 245 extern void call_debug(); 246 247 248 249 /* 250 * The following macro checks whether the device in a SUSPENDED state. 251 * As per WDD guide lines the I/O requests to a suspended device should 252 * be blocked until the device is resumed. 253 * Here we cv_wait on c_suspend_cv, and there is a cv_broadcast() in 254 * DDI_RESUME to wake up this thread. 255 * 256 * NOTE: This code is not tested because the kernel threads are suspended 257 * before the device is suspended. So there can not be any I/O requests on 258 * a suspended device until the cpr implementation changes.. 259 */ 260 261 #define CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc) \ 262 {\ 263 while (fdc->c_un->un_state == FD_STATE_SUSPENDED) {\ 264 cv_wait(&fdc->c_suspend_cv, \ 265 &fdc->c_lolock);\ 266 }\ 267 } 268 269 /* 270 * bss (uninitialized data) 271 */ 272 struct fdctlr *fdctlrs; /* linked list of controllers */ 273 274 /* 275 * initialized data 276 */ 277 278 static int fd_check_media_time = 5000000; /* 5 second state check */ 279 static int fd_pollable = 0; 280 static uchar_t rwretry = 10; 281 static uchar_t skretry = 5; 282 /* This variable allows the dynamic change of the burst size */ 283 static int fd_burstsize = DCSR_BURST_0 | DCSR_BURST_1; 284 285 static struct driver_minor_data { 286 char *name; 287 int minor; 288 int type; 289 } fd_minor [] = { 290 { "a", 0, S_IFBLK}, 291 { "b", 1, S_IFBLK}, 292 { "c", 2, S_IFBLK}, 293 { "a,raw", 0, S_IFCHR}, 294 { "b,raw", 1, S_IFCHR}, 295 { "c,raw", 2, S_IFCHR}, 296 {0} 297 }; 298 299 /* 300 * If the interrupt handler is invoked and no controllers expect an 301 * interrupt, the kernel panics. The following message is printed out. 302 */ 303 char *panic_msg = "fd_intr: unexpected interrupt\n"; 304 305 /* 306 * Specify/Configure cmd parameters 307 */ 308 static uchar_t fdspec[2] = { 0xc2, 0x33 }; /* "specify" parameters */ 309 static uchar_t fdconf[3] = { 0x64, 0x58, 0x00 }; /* "configure" parameters */ 310 311 /* When DMA is used, set the ND bit to 0 */ 312 #define SPEC_DMA_MODE 0x32 313 314 /* 315 * default characteristics 316 */ 317 static struct fd_char fdtypes[] = { 318 { /* struct fd_char fdchar_1.7MB density */ 319 0, /* medium */ 320 500, /* transfer rate */ 321 80, /* number of cylinders */ 322 2, /* number of heads */ 323 512, /* sector size */ 324 21, /* sectors per track */ 325 -1, /* (NA) # steps per data track */ 326 }, 327 { /* struct fd_char fdchar_highdens */ 328 0, /* medium */ 329 500, /* transfer rate */ 330 80, /* number of cylinders */ 331 2, /* number of heads */ 332 512, /* sector size */ 333 18, /* sectors per track */ 334 -1, /* (NA) # steps per data track */ 335 }, 336 { /* struct fd_char fdchar_meddens */ 337 1, /* medium */ 338 500, /* transfer rate */ 339 77, /* number of cylinders */ 340 2, /* number of heads */ 341 1024, /* sector size */ 342 8, /* sectors per track */ 343 -1, /* (NA) # steps per data track */ 344 }, 345 { /* struct fd_char fdchar_lowdens */ 346 0, /* medium */ 347 250, /* transfer rate */ 348 80, /* number of cylinders */ 349 2, /* number of heads */ 350 512, /* sector size */ 351 9, /* sectors per track */ 352 -1, /* (NA) # steps per data track */ 353 } 354 }; 355 356 357 static int nfdtypes = sizeof (fdtypes) / sizeof (fdtypes[0]); 358 359 360 /* 361 * Default Label & partition maps 362 */ 363 364 static struct packed_label fdlbl_high_21 = { 365 { "3.5\" floppy cyl 80 alt 0 hd 2 sec 21" }, 366 300, /* rotations per minute */ 367 80, /* # physical cylinders */ 368 0, /* alternates per cylinder */ 369 1, /* interleave factor */ 370 80, /* # of data cylinders */ 371 0, /* # of alternate cylinders */ 372 2, /* # of heads in this partition */ 373 21, /* # of 512 byte sectors per track */ 374 { 375 { 0, 79 * 2 * 21 }, /* part 0 - all but last cyl */ 376 { 79, 1 * 2 * 21 }, /* part 1 - just the last cyl */ 377 { 0, 80 * 2 * 21 }, /* part 2 - "the whole thing" */ 378 }, 379 { 0, /* version */ 380 "", /* volume label */ 381 3, /* no. of partitions */ 382 { 0 }, /* partition hdrs, sec 2 */ 383 { 0 }, /* mboot info. unsupported */ 384 VTOC_SANE, /* verify vtoc sanity */ 385 { 0 }, /* reserved space */ 386 0, /* timestamp */ 387 }, 388 }; 389 390 static struct packed_label fdlbl_high_80 = { 391 { "3.5\" floppy cyl 80 alt 0 hd 2 sec 18" }, 392 300, /* rotations per minute */ 393 80, /* # physical cylinders */ 394 0, /* alternates per cylinder */ 395 1, /* interleave factor */ 396 80, /* # of data cylinders */ 397 0, /* # of alternate cylinders */ 398 2, /* # of heads in this partition */ 399 18, /* # of 512 byte sectors per track */ 400 { 401 { 0, 79 * 2 * 18 }, /* part 0 - all but last cyl */ 402 { 79, 1 * 2 * 18 }, /* part 1 - just the last cyl */ 403 { 0, 80 * 2 * 18 }, /* part 2 - "the whole thing" */ 404 }, 405 { 0, /* version */ 406 "", /* volume label */ 407 3, /* no. of partitions */ 408 { 0 }, /* partition hdrs, sec 2 */ 409 { 0 }, /* mboot info. unsupported */ 410 VTOC_SANE, /* verify vtoc sanity */ 411 { 0 }, /* reserved space */ 412 0, /* timestamp */ 413 }, 414 }; 415 416 /* 417 * A medium density diskette has 1024 byte sectors. The dk_label structure 418 * assumes a sector is DEVBSIZE (512) bytes. 419 */ 420 static struct packed_label fdlbl_medium_80 = { 421 { "3.5\" floppy cyl 77 alt 0 hd 2 sec 8" }, 422 360, /* rotations per minute */ 423 77, /* # physical cylinders */ 424 0, /* alternates per cylinder */ 425 1, /* interleave factor */ 426 77, /* # of data cylinders */ 427 0, /* # of alternate cylinders */ 428 2, /* # of heads in this partition */ 429 16, /* # of 512 byte sectors per track */ 430 { 431 { 0, 76 * 2 * 8 * 2 }, /* part 0 - all but last cyl */ 432 { 76, 1 * 2 * 8 * 2 }, /* part 1 - just the last cyl */ 433 { 0, 77 * 2 * 8 * 2 }, /* part 2 - "the whole thing" */ 434 }, 435 { 0, /* version */ 436 "", /* volume label */ 437 3, /* no. of partitions */ 438 { 0 }, /* partition hdrs, sec 2 */ 439 { 0 }, /* mboot info. unsupported */ 440 VTOC_SANE, /* verify vtoc sanity */ 441 { 0 }, /* reserved space */ 442 0, /* timestamp */ 443 }, 444 }; 445 446 static struct packed_label fdlbl_low_80 = { 447 { "3.5\" floppy cyl 80 alt 0 hd 2 sec 9" }, 448 300, /* rotations per minute */ 449 80, /* # physical cylinders */ 450 0, /* alternates per cylinder */ 451 1, /* interleave factor */ 452 80, /* # of data cylinders */ 453 0, /* # of alternate cylinders */ 454 2, /* # of heads in this partition */ 455 9, /* # of 512 byte sectors per track */ 456 { 457 { 0, 79 * 2 * 9 }, /* part 0 - all but last cyl */ 458 { 79, 1 * 2 * 9 }, /* part 1 - just the last cyl */ 459 { 0, 80 * 2 * 9 }, /* part 2 - "the whole thing" */ 460 }, 461 { 0, /* version */ 462 "", /* volume label */ 463 3, /* no. of partitions */ 464 { 0 }, /* partition hdrs, sec 2 */ 465 { 0 }, /* mboot info. unsupported */ 466 VTOC_SANE, /* verify vtoc sanity */ 467 { 0 }, /* reserved space */ 468 0, /* timestamp */ 469 }, 470 }; 471 472 static struct fdcmdinfo { 473 char *cmdname; /* command name */ 474 uchar_t ncmdbytes; /* number of bytes of command */ 475 uchar_t nrsltbytes; /* number of bytes in result */ 476 uchar_t cmdtype; /* characteristics */ 477 } fdcmds[] = { 478 "", 0, 0, 0, /* - */ 479 "", 0, 0, 0, /* - */ 480 "read_track", 9, 7, 1, /* 2 */ 481 "specify", 3, 0, 3, /* 3 */ 482 "sense_drv_status", 2, 1, 3, /* 4 */ 483 "write", 9, 7, 1, /* 5 */ 484 "read", 9, 7, 1, /* 6 */ 485 "recalibrate", 2, 0, 2, /* 7 */ 486 "sense_int_status", 1, 2, 3, /* 8 */ 487 "write_del", 9, 7, 1, /* 9 */ 488 "read_id", 2, 7, 2, /* A */ 489 "motor_on/off", 1, 0, 4, /* B */ 490 "read_del", 9, 7, 1, /* C */ 491 "format_track", 10, 7, 1, /* D */ 492 "dump_reg", 1, 10, 4, /* E */ 493 "seek", 3, 0, 2, /* F */ 494 "", 0, 0, 0, /* - */ 495 "", 0, 0, 0, /* - */ 496 "", 0, 0, 0, /* - */ 497 "configure", 4, 0, 4, /* 13 */ 498 /* relative seek */ 499 }; 500 501 static struct cb_ops fd_cb_ops = { 502 fd_open, /* open */ 503 fd_close, /* close */ 504 fd_strategy, /* strategy */ 505 nodev, /* print */ 506 nodev, /* dump */ 507 fd_read, /* read */ 508 fd_write, /* write */ 509 fd_ioctl, /* ioctl */ 510 nodev, /* devmap */ 511 nodev, /* mmap */ 512 nodev, /* segmap */ 513 nochpoll, /* poll */ 514 fd_prop_op, /* cb_prop_op */ 515 0, /* streamtab */ 516 D_NEW | D_MP /* Driver compatibility flag */ 517 }; 518 519 static struct dev_ops fd_ops = { 520 DEVO_REV, /* devo_rev, */ 521 0, /* refcnt */ 522 fd_info, /* info */ 523 nulldev, /* identify */ 524 nulldev, /* probe */ 525 fd_attach, /* attach */ 526 fd_detach, /* detach */ 527 nodev, /* reset */ 528 &fd_cb_ops, /* driver operations */ 529 (struct bus_ops *)0, /* bus operations */ 530 fd_power /* power */ 531 }; 532 533 534 /* 535 * error handling 536 * 537 * for debugging, set rwretry and skretry = 1 538 * set fderrlevel to 1 539 * set fderrmask to 224 or 100644 540 * 541 * after debug set rwretry to 10, skretry to 5, and fderrlevel to 3 542 * set fderrmask to FDEM_ALL 543 * remove the define FD_DEBUG 544 * 545 */ 546 547 static unsigned int fderrmask = (unsigned int)FDEM_ALL; 548 static int fderrlevel = 3; 549 550 static int tosec = 16; /* long timeouts for sundiag for now */ 551 552 /* 553 * loadable module support 554 */ 555 556 #include <sys/modctl.h> 557 558 extern struct mod_ops mod_driverops; 559 static struct modldrv modldrv = { 560 &mod_driverops, /* Type of module. driver here */ 561 "Floppy Driver v%I%", /* Name of the module. */ 562 &fd_ops, /* Driver ops vector */ 563 }; 564 565 static struct modlinkage modlinkage = { 566 MODREV_1, 567 &modldrv, 568 NULL 569 }; 570 571 int 572 _init(void) 573 { 574 return (mod_install(&modlinkage)); 575 } 576 577 int 578 _info(struct modinfo *modinfop) 579 { 580 return (mod_info(&modlinkage, modinfop)); 581 } 582 583 int 584 _fini(void) 585 { 586 int e; 587 588 if ((e = mod_remove(&modlinkage)) != 0) 589 return (e); 590 591 /* ddi_soft_state_fini() */ 592 return (0); 593 } 594 595 /* ARGSUSED */ 596 static int 597 fd_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 598 { 599 struct fdctlr *fdc; 600 struct driver_minor_data *dmdp; 601 int instance = ddi_get_instance(dip); 602 int hard_intr_set = 0; 603 604 FDERRPRINT(FDEP_L1, FDEM_ATTA, (C, "fd_attach: start\n")); 605 606 switch (cmd) { 607 case DDI_ATTACH: 608 break; 609 case DDI_RESUME: 610 611 if (!(fdc = fd_getctlr(instance << FDINSTSHIFT))) { 612 return (DDI_FAILURE); 613 } 614 quiesce_fd_interrupt(fdc); 615 if (fdc->c_fdtype & FDCTYPE_SB) 616 if (ddi_add_intr(dip, 0, &fdc->c_block, 0, 617 fdintr_dma, (caddr_t)0) != DDI_SUCCESS) { 618 return (DDI_FAILURE); 619 } 620 621 (void) pm_raise_power(dip, 0, PM_LEVEL_ON); 622 mutex_enter(&fdc->c_lolock); 623 /* 624 * Wake up any thread blocked due to I/O requests 625 * while the device was suspended. 626 */ 627 cv_broadcast(&fdc->c_suspend_cv); 628 mutex_exit(&fdc->c_lolock); 629 return (DDI_SUCCESS); 630 631 default: 632 return (DDI_FAILURE); 633 } 634 635 636 /* 637 * Check for the pollable property 638 * A pollable floppy drive currently only exists on the 639 * Sparcstation Voyager. This drive does not need to 640 * be turned on in order to sense whether or not a diskette 641 * is present. 642 */ 643 if (ddi_getprop(DDI_DEV_T_ANY, dip, 644 DDI_PROP_DONTPASS, FD_POLLABLE_PROP, 0)) 645 fd_pollable = 1; 646 647 fdc = kmem_zalloc(sizeof (*fdc), KM_SLEEP); 648 fdc->c_dip = dip; 649 650 651 fdc->c_next = fdctlrs; 652 fdctlrs = fdc; 653 654 /* Determine which type of controller is present and initialize it */ 655 if (fd_attach_det_ctlr(dip, fdc) == DDI_FAILURE) { 656 fd_cleanup(dip, fdc, hard_intr_set, 0); 657 return (DDI_FAILURE); 658 } 659 /* Finish mapping the device registers & setting up structures */ 660 if (fd_attach_map_regs(dip, fdc) == DDI_FAILURE) { 661 fd_cleanup(dip, fdc, hard_intr_set, 0); 662 return (DDI_FAILURE); 663 } 664 665 /* 666 * Initialize the DMA limit structures if it's being used. 667 */ 668 if (fdc->c_fdtype & FDCTYPE_DMA) { 669 fdc->c_fd_dma_lim.dma_attr_version = DMA_ATTR_V0; 670 fdc->c_fd_dma_lim.dma_attr_addr_lo = 0x00000000ull; 671 fdc->c_fd_dma_lim.dma_attr_addr_hi = 0xfffffffeull; 672 fdc->c_fd_dma_lim.dma_attr_count_max = 0xffffff; 673 if (fdc->c_fdtype & FDCTYPE_SB) { 674 fdc->c_fd_dma_lim.dma_attr_align = FD_SB_DMA_ALIGN; 675 } else { 676 fdc->c_fd_dma_lim.dma_attr_align = 1; 677 } 678 fdc->c_fd_dma_lim.dma_attr_burstsizes = 0x0; 679 fdc->c_fd_dma_lim.dma_attr_minxfer = 1; 680 fdc->c_fd_dma_lim.dma_attr_maxxfer = 0xffff; 681 fdc->c_fd_dma_lim.dma_attr_seg = 0xffff; 682 fdc->c_fd_dma_lim.dma_attr_sgllen = 1; 683 fdc->c_fd_dma_lim.dma_attr_granular = 512; 684 685 if (ddi_dma_alloc_handle(dip, &fdc->c_fd_dma_lim, 686 DDI_DMA_DONTWAIT, 0, &fdc->c_dmahandle) != DDI_SUCCESS) { 687 fd_cleanup(dip, fdc, hard_intr_set, 0); 688 return (DDI_FAILURE); 689 } 690 691 if (fdc->c_fdtype & FDCTYPE_SB) { 692 ddi_device_acc_attr_t dev_attr; 693 size_t rlen; 694 695 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 696 dev_attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 697 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 698 699 if (ddi_dma_mem_alloc(fdc->c_dmahandle, 700 (size_t)(32*1024), &dev_attr, DDI_DMA_CONSISTENT, 701 DDI_DMA_SLEEP, NULL, (caddr_t *)&fdc->dma_buf, 702 &rlen, &fdc->c_dma_buf_handle) != DDI_SUCCESS) { 703 fd_cleanup(dip, fdc, hard_intr_set, 0); 704 return (DDI_FAILURE); 705 } 706 707 } 708 } 709 710 711 /* Register the interrupts */ 712 if (fd_attach_register_interrupts(dip, fdc, 713 &hard_intr_set) == DDI_FAILURE) { 714 fd_cleanup(dip, fdc, hard_intr_set, 0); 715 FDERRPRINT(FDEP_L1, FDEM_ATTA, 716 (C, "fd_attach: registering interrupts failed\n")); 717 return (DDI_FAILURE); 718 } 719 720 721 /* 722 * set initial controller/drive/disk "characteristics/geometry" 723 * 724 * NOTE: The driver only supports one floppy drive. The hardware 725 * only supports one drive because there is only one auxio register 726 * for one drive. 727 */ 728 fdc->c_un = kmem_zalloc(sizeof (struct fdunit), KM_SLEEP); 729 fdc->c_un->un_chars = kmem_alloc(sizeof (struct fd_char), KM_SLEEP); 730 fdc->c_un->un_iostat = kstat_create("fd", 0, "fd0", "disk", 731 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT); 732 if (fdc->c_un->un_iostat) { 733 fdc->c_un->un_iostat->ks_lock = &fdc->c_lolock; 734 kstat_install(fdc->c_un->un_iostat); 735 } 736 737 fdc->c_un->un_drive = kmem_zalloc(sizeof (struct fd_drive), KM_SLEEP); 738 739 /* check for the manual eject property */ 740 if (ddi_getprop(DDI_DEV_T_ANY, dip, 741 DDI_PROP_DONTPASS, FD_MANUAL_EJECT, 0)) { 742 fdc->c_un->un_drive->fdd_ejectable = 0; 743 } else { 744 /* an absence of the property indicates auto eject */ 745 fdc->c_un->un_drive->fdd_ejectable = -1; 746 } 747 748 FDERRPRINT(FDEP_L1, FDEM_ATTA, (C, "fd_attach: ejectable? %d\n", 749 fdc->c_un->un_drive->fdd_ejectable)); 750 751 /* 752 * Check for the drive id. If the drive id property doesn't exist 753 * then the drive id is set to 0 754 */ 755 fdc->c_un->un_unit_no = ddi_getprop(DDI_DEV_T_ANY, dip, 756 DDI_PROP_DONTPASS, FD_UNIT, 0); 757 758 759 if (fdc->c_fdtype & FDCTYPE_SB) { 760 fdc->sb_dma_channel = ddi_getprop(DDI_DEV_T_ANY, dip, 761 DDI_PROP_DONTPASS, "dma-channel", 0); 762 } 763 764 765 FDERRPRINT(FDEP_L1, FDEM_ATTA, (C, "fd_attach: unit %d\n", 766 fdc->c_un->un_unit_no)); 767 768 /* Initially set the characteristics to high density */ 769 fdc->c_un->un_curfdtype = 1; 770 *fdc->c_un->un_chars = fdtypes[fdc->c_un->un_curfdtype]; 771 fdunpacklabel(&fdlbl_high_80, &fdc->c_un->un_label); 772 773 /* Make sure drive is present */ 774 if (fd_attach_check_drive(fdc) == DDI_FAILURE) { 775 fd_cleanup(dip, fdc, hard_intr_set, 1); 776 return (DDI_FAILURE); 777 } 778 779 for (dmdp = fd_minor; dmdp->name != NULL; dmdp++) { 780 if (ddi_create_minor_node(dip, dmdp->name, dmdp->type, 781 (instance << FDINSTSHIFT) | dmdp->minor, 782 DDI_NT_FD, 0) == DDI_FAILURE) { 783 fd_cleanup(dip, fdc, hard_intr_set, 1); 784 return (DDI_FAILURE); 785 } 786 } 787 788 create_pm_components(dip); 789 790 /* 791 * Add a zero-length attribute to tell the world we support 792 * kernel ioctls (for layered drivers) 793 */ 794 (void) ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP, 795 DDI_KERNEL_IOCTL, NULL, 0); 796 797 ddi_report_dev(dip); 798 799 FDERRPRINT(FDEP_L1, FDEM_ATTA, 800 (C, "attached 0x%x\n", ddi_get_instance(dip))); 801 802 return (DDI_SUCCESS); 803 } 804 805 /* 806 * Finish mapping the registers and initializing structures 807 */ 808 static int 809 fd_attach_map_regs(dev_info_t *dip, struct fdctlr *fdc) 810 { 811 ddi_device_acc_attr_t attr; 812 813 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 814 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 815 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 816 817 /* Map the DMA registers of the platform supports DMA */ 818 if (fdc->c_fdtype & FDCTYPE_SB) { 819 if (ddi_regs_map_setup(dip, 1, (caddr_t *)&fdc->c_dma_regs, 820 0, sizeof (struct sb_dma_reg), &attr, 821 &fdc->c_handlep_dma)) { 822 return (DDI_FAILURE); 823 } 824 825 826 } else if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 827 if (ddi_regs_map_setup(dip, 1, (caddr_t *)&fdc->c_dma_regs, 828 0, sizeof (struct cheerio_dma_reg), &attr, 829 &fdc->c_handlep_dma)) { 830 return (DDI_FAILURE); 831 } 832 } 833 834 /* Reset the DMA engine and enable floppy interrupts */ 835 reset_dma_controller(fdc); 836 set_dma_control_register(fdc, DCSR_INIT_BITS); 837 838 /* Finish initializing structures associated with the device regs */ 839 switch (fdc->c_fdtype & FDCTYPE_CTRLMASK) { 840 case FDCTYPE_82077: 841 FDERRPRINT(FDEP_L1, FDEM_ATTA, (C, "type is 82077\n")); 842 /* 843 * Initialize addrs of key registers 844 */ 845 fdc->c_control = 846 (uchar_t *)&fdc->c_reg->fdc_82077_reg.fdc_control; 847 fdc->c_fifo = (uchar_t *)&fdc->c_reg->fdc_82077_reg.fdc_fifo; 848 fdc->c_dor = (uchar_t *)&fdc->c_reg->fdc_82077_reg.fdc_dor; 849 fdc->c_dir = (uchar_t *)&fdc->c_reg->fdc_82077_reg.fdc_dir; 850 851 852 FDERRPRINT(FDEP_L1, FDEM_ATTA, ((int)C, 853 (char *)"fdattach: msr/dsr at %p\n", 854 (void *)fdc->c_control)); 855 856 /* 857 * The 82077 doesn't use the first configuration parameter 858 * so let's adjust that while we know we're an 82077. 859 */ 860 fdconf[0] = 0; 861 862 quiesce_fd_interrupt(fdc); 863 break; 864 default: 865 break; 866 } 867 868 return (0); 869 } 870 871 /* 872 * Determine which type of floppy controller is present and 873 * initialize the registers accordingly 874 */ 875 static int 876 fd_attach_det_ctlr(dev_info_t *dip, struct fdctlr *fdc) 877 { 878 ddi_device_acc_attr_t attr; 879 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 880 /* DDI_NEVERSWAP_ACC since the controller has a byte interface. */ 881 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 882 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 883 884 FDERRPRINT(FDEP_L1, FDEM_ATTA, 885 (C, "fdattach_det_cltr: start \n")); 886 887 /* 888 * First, map in the controller's registers 889 * The controller has an 8-bit interface, so byte 890 * swapping isn't needed 891 */ 892 893 if (ddi_regs_map_setup(dip, 0, (caddr_t *)&fdc->c_reg, 894 0, sizeof (union fdcreg), 895 &attr, 896 &fdc->c_handlep_cont)) { 897 return (DDI_FAILURE); 898 } 899 900 FDERRPRINT(FDEP_L1, FDEM_ATTA, 901 (C, "fdattach_det_cltr: mapped floppy regs\n")); 902 903 904 /* 905 * Set platform specific characteristics based on the device-tree 906 * node name. 907 */ 908 909 910 if (strcmp(ddi_get_name(dip), "SUNW,fdtwo") == 0) { 911 fdc->c_fdtype |= FDCTYPE_SLAVIO; 912 fdc->c_fdtype |= FDCTYPE_82077; 913 fdc->c_auxiova = fd_getauxiova(dip); 914 fdc->c_auxiodata = (uchar_t)(AUX_MBO4M|AUX_TC4M); 915 fdc->c_auxiodata2 = (uchar_t)AUX_TC4M; 916 FDERRPRINT(FDEP_L1, FDEM_ATTA, 917 (C, "fdattach: slavio will be used!\n")); 918 919 920 /* 921 * Check the binding name to identify whether it is a South bridge based 922 * system or not. 923 */ 924 } else if (strcmp(ddi_get_name(dip), "pnpALI,1533,0") == 0) { 925 926 fdc->c_fdtype |= FDCTYPE_SB; 927 fdc->c_fdtype |= FDCTYPE_82077; 928 fdc->c_fdtype |= FDCTYPE_DMA; 929 930 FDERRPRINT(FDEP_L1, FDEM_ATTA, 931 (C, "fdattach: southbridge will be used!\n")); 932 933 /* 934 * The driver assumes high density characteristics until 935 * the diskette is looked at. 936 */ 937 938 fdc->c_fdtype |= FDCTYPE_DMA8237; 939 FDERRPRINT(FDEP_L1, FDEM_ATTA, (C, "fd_attach: DMA used\n")); 940 941 942 } else if (strcmp(ddi_get_name(dip), "fdthree") == 0) { 943 944 fdc->c_fdtype |= FDCTYPE_CHEERIO; 945 fdc->c_fdtype |= FDCTYPE_82077; 946 947 FDERRPRINT(FDEP_L1, FDEM_ATTA, 948 (C, "fdattach: cheerio will be used!\n")); 949 /* 950 * The cheerio auxio register should be memory mapped. The 951 * auxio register on other platforms is shared and mapped 952 * elsewhere in the kernel 953 */ 954 if (ddi_regs_map_setup(dip, 2, (caddr_t *)&fdc->c_auxio_reg, 955 0, sizeof (uint_t), &attr, &fdc->c_handlep_aux)) { 956 return (DDI_FAILURE); 957 } 958 959 /* 960 * The driver assumes high density characteristics until 961 * the diskette is looked at. 962 */ 963 Set_auxio(fdc, AUX_HIGH_DENSITY); 964 FDERRPRINT(FDEP_L1, FDEM_ATTA, 965 (C, "fdattach: auxio register 0x%x\n", 966 *fdc->c_auxio_reg)); 967 968 fdc->c_fdtype |= FDCTYPE_DMA; 969 FDERRPRINT(FDEP_L1, FDEM_ATTA, (C, "fd_attach: DMA used\n")); 970 971 } 972 973 if (fdc->c_fdtype == 0) { 974 FDERRPRINT(FDEP_L1, FDEM_ATTA, 975 (C, "fdattach: no controller!\n")); 976 return (DDI_FAILURE); 977 } else { 978 return (0); 979 } 980 } 981 982 983 /* 984 * Register the floppy interrupts 985 */ 986 static int 987 fd_attach_register_interrupts(dev_info_t *dip, struct fdctlr *fdc, int *hard) 988 { 989 ddi_iblock_cookie_t iblock_cookie_soft; 990 int status; 991 992 /* 993 * First call ddi_get_iblock_cookie() to retrieve the 994 * the interrupt block cookie so that the mutexes may 995 * be initialized before adding the interrupt. If the 996 * mutexes are initialized after adding the interrupt, there 997 * could be a race condition. 998 */ 999 if (ddi_get_iblock_cookie(dip, 0, &fdc->c_block) != DDI_SUCCESS) { 1000 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1001 (C, "fdattach: ddi_get_iblock_cookie failed\n")); 1002 return (DDI_FAILURE); 1003 1004 } 1005 1006 /* Initialize high level mutex */ 1007 mutex_init(&fdc->c_hilock, NULL, MUTEX_DRIVER, fdc->c_block); 1008 1009 /* 1010 * Try to register fast trap handler, if unable try standard 1011 * interrupt handler, else bad 1012 */ 1013 1014 if (fdc->c_fdtype & FDCTYPE_DMA) { 1015 if (ddi_add_intr(dip, 0, &fdc->c_block, 0, 1016 fdintr_dma, (caddr_t)0) == DDI_SUCCESS) { 1017 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1018 (C, "fdattach: standard intr\n")); 1019 1020 /* 1021 * When DMA is used, the low level lock 1022 * is used in the hard interrupt handler. 1023 */ 1024 mutex_init(&fdc->c_lolock, NULL, 1025 MUTEX_DRIVER, fdc->c_block); 1026 1027 *hard = 1; 1028 } else { 1029 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1030 (C, "fdattach: can't add dma intr\n")); 1031 1032 mutex_destroy(&fdc->c_hilock); 1033 1034 return (DDI_FAILURE); 1035 } 1036 } else { 1037 /* 1038 * Platforms that don't support DMA have both hard 1039 * and soft interrupts. 1040 */ 1041 if (ddi_add_intr(dip, 0, &fdc->c_block, 0, 1042 fd_intr, (caddr_t)0) == DDI_SUCCESS) { 1043 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1044 (C, "fdattach: standard intr\n")); 1045 *hard = 1; 1046 1047 /* fast traps are not enabled */ 1048 fdc->c_fasttrap = 0; 1049 1050 } else { 1051 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1052 (C, "fdattach: can't add intr\n")); 1053 1054 mutex_destroy(&fdc->c_hilock); 1055 1056 return (DDI_FAILURE); 1057 } 1058 1059 1060 /* 1061 * Initialize the soft interrupt handler. First call 1062 * ddi_get_soft_iblock_cookie() so that the mutex may 1063 * be initialized before the handler is added. 1064 */ 1065 status = ddi_get_soft_iblock_cookie(dip, DDI_SOFTINT_LOW, 1066 &iblock_cookie_soft); 1067 1068 1069 if (status != DDI_SUCCESS) { 1070 mutex_destroy(&fdc->c_hilock); 1071 return (DDI_FAILURE); 1072 } 1073 1074 /* 1075 * Initialize low level mutex which is used in the soft 1076 * interrupt handler 1077 */ 1078 mutex_init(&fdc->c_lolock, NULL, MUTEX_DRIVER, 1079 iblock_cookie_soft); 1080 1081 if (ddi_add_softintr(dip, DDI_SOFTINT_LOW, &fdc->c_softid, 1082 NULL, NULL, 1083 fd_lointr, 1084 (caddr_t)fdc) != DDI_SUCCESS) { 1085 1086 mutex_destroy(&fdc->c_hilock); 1087 mutex_destroy(&fdc->c_lolock); 1088 1089 return (DDI_FAILURE); 1090 } 1091 } 1092 1093 fdc->c_intrstat = kstat_create("fd", 0, "fdc0", "controller", 1094 KSTAT_TYPE_INTR, 1, KSTAT_FLAG_PERSISTENT); 1095 if (fdc->c_intrstat) { 1096 fdc->c_hiintct = &KIOIP->intrs[KSTAT_INTR_HARD]; 1097 kstat_install(fdc->c_intrstat); 1098 } 1099 1100 /* condition variable to wait on while an io transaction occurs */ 1101 cv_init(&fdc->c_iocv, NULL, CV_DRIVER, NULL); 1102 1103 /* condition variable for the csb */ 1104 cv_init(&fdc->c_csbcv, NULL, CV_DRIVER, NULL); 1105 1106 /* condition variable for motor on waiting period */ 1107 cv_init(&fdc->c_motoncv, NULL, CV_DRIVER, NULL); 1108 1109 /* semaphore to serialize opens and closes */ 1110 sema_init(&fdc->c_ocsem, 1, NULL, SEMA_DRIVER, NULL); 1111 1112 /* condition variable to wait on suspended floppy controller. */ 1113 cv_init(&fdc->c_suspend_cv, NULL, CV_DRIVER, NULL); 1114 1115 return (0); 1116 } 1117 1118 /* 1119 * Make sure the drive is present 1120 * - acquires the low level lock 1121 */ 1122 static int 1123 fd_attach_check_drive(struct fdctlr *fdc) 1124 { 1125 int tmp_fderrlevel; 1126 int unit = fdc->c_un->un_unit_no; 1127 1128 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1129 (C, "fd_attach_check_drive\n")); 1130 1131 1132 mutex_enter(&fdc->c_lolock); 1133 switch (fdc->c_fdtype & FDCTYPE_CTRLMASK) { 1134 1135 /* insure that the eject line is reset */ 1136 case FDCTYPE_82077: 1137 1138 /* 1139 * Everything but the motor enable, drive select, 1140 * and reset bits are turned off. These three 1141 * bits remain as they are. 1142 */ 1143 /* LINTED */ 1144 Set_dor(fdc, ~((MOTEN(unit))|DRVSEL|RESET), 0); 1145 1146 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1147 (C, "fdattach: Dor 0x%x\n", Dor(fdc))); 1148 1149 drv_usecwait(5); 1150 if (unit == 0) { 1151 /* LINTED */ 1152 Set_dor(fdc, RESET|DRVSEL, 1); 1153 } else { 1154 1155 /* LINTED */ 1156 Set_dor(fdc, DRVSEL, 0); 1157 /* LINTED */ 1158 Set_dor(fdc, RESET, 1); 1159 } 1160 1161 drv_usecwait(5); 1162 1163 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1164 (C, "fdattach: Dor 0x%x\n", Dor(fdc))); 1165 1166 if (!((fdc->c_fdtype & FDCTYPE_CHEERIO) || 1167 (fdc->c_fdtype & FDCTYPE_SB))) { 1168 set_auxioreg(AUX_TC4M, 0); 1169 } 1170 break; 1171 default: 1172 break; 1173 } 1174 1175 1176 fdgetcsb(fdc); 1177 if (fdreset(fdc) != 0) { 1178 mutex_exit(&fdc->c_lolock); 1179 return (DDI_FAILURE); 1180 } 1181 1182 1183 /* check for drive present */ 1184 1185 tmp_fderrlevel = fderrlevel; 1186 1187 1188 fderrlevel = FDEP_LMAX; 1189 1190 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1191 (C, "fdattach: call fdrecalseek\n")); 1192 1193 /* Make sure the drive is present */ 1194 if (fdrecalseek(fdc, unit, -1, 0) != 0) { 1195 timeout_id_t timeid = fdc->c_mtimeid; 1196 fderrlevel = tmp_fderrlevel; 1197 fdc->c_mtimeid = 0; 1198 mutex_exit(&fdc->c_lolock); 1199 1200 1201 /* Do not hold the mutex over the call to untimeout */ 1202 if (timeid) { 1203 (void) untimeout(timeid); 1204 } 1205 1206 FDERRPRINT(FDEP_L2, FDEM_ATTA, 1207 (C, "fd_attach: no drive?\n")); 1208 1209 return (DDI_FAILURE); 1210 } 1211 1212 fderrlevel = tmp_fderrlevel; 1213 1214 fdselect(fdc, unit, 0); /* deselect drive zero (used in fdreset) */ 1215 fdretcsb(fdc); 1216 mutex_exit(&fdc->c_lolock); 1217 1218 return (0); 1219 } 1220 1221 /* 1222 * Clean up routine used by fd_detach and fd_attach 1223 * 1224 * Note: if the soft id is non-zero, then ddi_add_softintr() completed 1225 * successfully. I can not make the same assumption about the iblock_cookie 1226 * for the high level interrupt handler. So, the hard parameter indicates 1227 * whether or not a high level interrupt handler has been added. 1228 * 1229 * If the locks parameter is nonzero, then all mutexes, semaphores and 1230 * condition variables will be destroyed. 1231 * 1232 * Does not assume the low level mutex is held. 1233 * 1234 */ 1235 static void 1236 fd_cleanup(dev_info_t *dip, struct fdctlr *fdc, int hard, int locks) 1237 { 1238 1239 1240 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1241 (C, "fd_cleanup instance: %d ctlr: 0x%x\n", 1242 ddi_get_instance(dip), (int)fdc)); 1243 1244 1245 if (fdc == NULL) { 1246 return; 1247 } 1248 1249 /* 1250 * Remove interrupt handlers first before anything else 1251 * is deallocated. 1252 */ 1253 1254 /* Remove hard interrupt if one is registered */ 1255 if (hard) { 1256 ddi_remove_intr(dip, (uint_t)0, fdc->c_block); 1257 } 1258 1259 /* Remove soft interrupt if one is registered */ 1260 if (fdc->c_softid != NULL) 1261 ddi_remove_softintr(fdc->c_softid); 1262 1263 1264 /* Remove timers */ 1265 if (fdc->c_fdtype & FDCTYPE_82077) { 1266 if (fdc->c_mtimeid) 1267 (void) untimeout(fdc->c_mtimeid); 1268 /* 1269 * Need to turn off motor (includes select/LED for South Bridge 1270 * chipset) just in case it was on when timer was removed 1271 */ 1272 fdmotoff(fdc); 1273 } 1274 if (fdc->c_timeid) 1275 (void) untimeout(fdc->c_timeid); 1276 1277 1278 /* Remove memory handles */ 1279 if (fdc->c_handlep_cont) 1280 ddi_regs_map_free(&fdc->c_handlep_cont); 1281 1282 if (fdc->c_handlep_aux) 1283 ddi_regs_map_free(&fdc->c_handlep_aux); 1284 1285 if (fdc->c_handlep_dma) 1286 ddi_regs_map_free(&fdc->c_handlep_dma); 1287 1288 if (fdc->c_dma_buf_handle != NULL) 1289 ddi_dma_mem_free(&fdc->c_dma_buf_handle); 1290 1291 if (fdc->c_dmahandle != NULL) 1292 ddi_dma_free_handle(&fdc->c_dmahandle); 1293 1294 1295 /* Remove all minor nodes */ 1296 ddi_remove_minor_node(dip, NULL); 1297 1298 1299 1300 /* Remove unit structure if one exists */ 1301 if (fdc->c_un != (struct fdunit *)NULL) { 1302 1303 ASSERT(!mutex_owned(&fdc->c_lolock)); 1304 1305 if (fdc->c_un->un_iostat) 1306 kstat_delete(fdc->c_un->un_iostat); 1307 fdc->c_un->un_iostat = NULL; 1308 1309 if (fdc->c_un->un_chars) 1310 kmem_free(fdc->c_un->un_chars, sizeof (struct fd_char)); 1311 1312 if (fdc->c_un->un_drive) 1313 kmem_free(fdc->c_un->un_drive, 1314 sizeof (struct fd_drive)); 1315 1316 kmem_free((caddr_t)fdc->c_un, sizeof (struct fdunit)); 1317 } 1318 1319 if (fdc->c_intrstat) { 1320 FDERRPRINT(FDEP_L1, FDEM_ATTA, 1321 (C, "fd_cleanup: delete intrstat\n")); 1322 1323 kstat_delete(fdc->c_intrstat); 1324 } 1325 1326 fdc->c_intrstat = NULL; 1327 1328 if (locks) { 1329 cv_destroy(&fdc->c_iocv); 1330 cv_destroy(&fdc->c_csbcv); 1331 cv_destroy(&fdc->c_motoncv); 1332 cv_destroy(&fdc->c_suspend_cv); 1333 sema_destroy(&fdc->c_ocsem); 1334 mutex_destroy(&fdc->c_hilock); 1335 mutex_destroy(&fdc->c_lolock); 1336 } 1337 1338 1339 fdctlrs = fdc->c_next; 1340 kmem_free(fdc, sizeof (*fdc)); 1341 1342 1343 } 1344 1345 1346 static int 1347 fd_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1348 { 1349 int instance = ddi_get_instance(dip); 1350 struct fdctlr *fdc = fd_getctlr(instance << FDINSTSHIFT); 1351 timeout_id_t c_mtimeid; 1352 1353 FDERRPRINT(FDEP_L1, FDEM_ATTA, (C, "fd_detach\n")); 1354 1355 switch (cmd) { 1356 1357 case DDI_DETACH: 1358 /* 1359 * The hard parameter is set to 1. If detach is called, then 1360 * attach must have passed meaning that the high level 1361 * interrupt handler was successfully added. 1362 * Similarly, the locks parameter is also set to 1. 1363 */ 1364 fd_cleanup(dip, fdc, 1, 1); 1365 1366 ddi_prop_remove_all(dip); 1367 1368 return (DDI_SUCCESS); 1369 1370 case DDI_SUSPEND: 1371 if (!fdc) 1372 return (DDI_FAILURE); 1373 1374 1375 mutex_enter(&fdc->c_lolock); 1376 fdgetcsb(fdc); /* Wait for I/O to finish */ 1377 c_mtimeid = fdc->c_mtimeid; 1378 fdretcsb(fdc); 1379 mutex_exit(&fdc->c_lolock); 1380 1381 (void) untimeout(c_mtimeid); 1382 /* 1383 * After suspend, the system could be powered off. 1384 * When it is later powered on the southbridge floppy 1385 * controller will tristate the interrupt line causing 1386 * continuous dma interrupts. 1387 * To avoid getting continuous fd interrupts we will remove the 1388 * dma interrupt handler installed. We will re-install the 1389 * handler when we RESUME. 1390 */ 1391 if (fdc->c_fdtype & FDCTYPE_SB) 1392 ddi_remove_intr(dip, 0, fdc->c_block); 1393 1394 fdc->c_un->un_state = FD_STATE_SUSPENDED; 1395 1396 return (DDI_SUCCESS); 1397 1398 default: 1399 return (DDI_FAILURE); 1400 } 1401 } 1402 1403 /* ARGSUSED */ 1404 static int 1405 fd_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 1406 { 1407 register struct fdctlr *fdc; 1408 register int error; 1409 1410 switch (infocmd) { 1411 1412 case DDI_INFO_DEVT2DEVINFO: 1413 if ((fdc = fd_getctlr((dev_t)arg)) == NULL) { 1414 error = DDI_FAILURE; 1415 } else { 1416 *result = fdc->c_dip; 1417 error = DDI_SUCCESS; 1418 } 1419 break; 1420 1421 case DDI_INFO_DEVT2INSTANCE: 1422 *result = 0; 1423 error = DDI_SUCCESS; 1424 break; 1425 1426 default: 1427 error = DDI_FAILURE; 1428 } 1429 return (error); 1430 } 1431 1432 /* 1433 * property operation routine. return the number of blocks for the partition 1434 * in question or forward the request to the property facilities. 1435 */ 1436 static int 1437 fd_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, int mod_flags, 1438 char *name, caddr_t valuep, int *lengthp) 1439 { 1440 struct fdunit *un; 1441 struct fdctlr *fdc; 1442 uint64_t nblocks64; 1443 1444 /* 1445 * Our dynamic properties are all device specific and size oriented. 1446 * Requests issued under conditions where size is valid are passed 1447 * to ddi_prop_op_nblocks with the size information, otherwise the 1448 * request is passed to ddi_prop_op. 1449 */ 1450 if (dev == DDI_DEV_T_ANY) { 1451 pass: return (ddi_prop_op(dev, dip, prop_op, mod_flags, 1452 name, valuep, lengthp)); 1453 } else { 1454 fdc = fd_getctlr(dev); 1455 if (fdc == NULL) 1456 goto pass; 1457 1458 /* we have size if diskette opened and label read */ 1459 un = fdc->c_un; 1460 if ((un == NULL) || !fd_unit_is_open(fdc->c_un)) 1461 goto pass; 1462 1463 /* get nblocks value */ 1464 nblocks64 = (ulong_t) 1465 un->un_label.dkl_map[FDPARTITION(dev)].dkl_nblk; 1466 1467 return (ddi_prop_op_nblocks(dev, dip, prop_op, mod_flags, 1468 name, valuep, lengthp, nblocks64)); 1469 } 1470 } 1471 1472 /* ARGSUSED3 */ 1473 static int 1474 fd_open(dev_t *devp, int flag, int otyp, cred_t *cred_p) 1475 { 1476 dev_t dev; 1477 int part; 1478 struct fdctlr *fdc; 1479 struct fdunit *un; 1480 struct dk_map32 *dkm; 1481 uchar_t pbit; 1482 int err, part_is_open; 1483 int unit; 1484 1485 dev = *devp; 1486 fdc = fd_getctlr(dev); 1487 if ((fdc == NULL) || ((un = fdc->c_un) == NULL)) { 1488 return (ENXIO); 1489 } 1490 1491 unit = fdc->c_un->un_unit_no; 1492 1493 /* 1494 * Serialize opens/closes 1495 */ 1496 1497 sema_p(&fdc->c_ocsem); 1498 1499 /* check partition */ 1500 part = FDPARTITION(dev); 1501 pbit = 1 << part; 1502 dkm = &un->un_label.dkl_map[part]; 1503 if (dkm->dkl_nblk == 0) { 1504 sema_v(&fdc->c_ocsem); 1505 return (ENXIO); 1506 } 1507 1508 FDERRPRINT(FDEP_L1, FDEM_OPEN, 1509 (C, "fdopen: ctlr %d unit %d part %d\n", 1510 ddi_get_instance(fdc->c_dip), unit, part)); 1511 1512 FDERRPRINT(FDEP_L1, FDEM_OPEN, 1513 (C, "fdopen: flag 0x%x", flag)); 1514 1515 1516 /* 1517 * Insure that drive is present with a recalibrate on first open. 1518 */ 1519 (void) pm_busy_component(fdc->c_dip, 0); 1520 1521 mutex_enter(&fdc->c_lolock); 1522 1523 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 1524 1525 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 1526 mutex_exit(&fdc->c_lolock); 1527 if ((pm_raise_power(fdc->c_dip, 0, PM_LEVEL_ON)) 1528 != DDI_SUCCESS) { 1529 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "Power change \ 1530 failed. \n")); 1531 1532 sema_v(&fdc->c_ocsem); 1533 (void) pm_idle_component(fdc->c_dip, 0); 1534 return (EIO); 1535 } 1536 mutex_enter(&fdc->c_lolock); 1537 } 1538 if (fd_unit_is_open(un) == 0) { 1539 fdgetcsb(fdc); 1540 /* 1541 * no check changed! 1542 */ 1543 err = fdrecalseek(fdc, unit, -1, 0); 1544 fdretcsb(fdc); 1545 if (err) { 1546 FDERRPRINT(FDEP_L3, FDEM_OPEN, 1547 (C, "fd%d: drive not ready\n", 0)); 1548 /* deselect drv on last close */ 1549 fdselect(fdc, unit, 0); 1550 mutex_exit(&fdc->c_lolock); 1551 sema_v(&fdc->c_ocsem); 1552 (void) pm_idle_component(fdc->c_dip, 0); 1553 return (EIO); 1554 } 1555 } 1556 1557 /* 1558 * Check for previous exclusive open, or trying to exclusive open 1559 */ 1560 if (otyp == OTYP_LYR) { 1561 part_is_open = (un->un_lyropen[part] != 0); 1562 } else { 1563 part_is_open = fd_part_is_open(un, part); 1564 } 1565 if ((un->un_exclmask & pbit) || ((flag & FEXCL) && part_is_open)) { 1566 mutex_exit(&fdc->c_lolock); 1567 sema_v(&fdc->c_ocsem); 1568 FDERRPRINT(FDEP_L2, FDEM_OPEN, (C, "fd:just return\n")); 1569 (void) pm_idle_component(fdc->c_dip, 0); 1570 return (EBUSY); 1571 } 1572 1573 /* don't attempt access, just return successfully */ 1574 if (flag & (FNDELAY | FNONBLOCK)) { 1575 FDERRPRINT(FDEP_L2, FDEM_OPEN, 1576 (C, "fd: return busy..\n")); 1577 goto out; 1578 } 1579 1580 fdc->c_csb.csb_unit = (uchar_t)unit; 1581 if (fdgetlabel(fdc, unit)) { 1582 /* didn't find label (couldn't read anything) */ 1583 FDERRPRINT(FDEP_L3, FDEM_OPEN, 1584 (C, 1585 "fd%d: unformatted diskette or no diskette in the drive\n", 1586 0)); 1587 if (fd_unit_is_open(un) == 0) { 1588 /* deselect drv on last close */ 1589 fdselect(fdc, unit, 0); 1590 } 1591 1592 mutex_exit(&fdc->c_lolock); 1593 sema_v(&fdc->c_ocsem); 1594 (void) pm_idle_component(fdc->c_dip, 0); 1595 return (EIO); 1596 } 1597 1598 /* 1599 * if opening for writing, check write protect on diskette 1600 */ 1601 if (flag & FWRITE) { 1602 fdgetcsb(fdc); 1603 err = fdsensedrv(fdc, unit) & WP_SR3; 1604 fdretcsb(fdc); 1605 if (err) { 1606 if (fd_unit_is_open(un) == 0) 1607 fdselect(fdc, unit, 0); 1608 mutex_exit(&fdc->c_lolock); 1609 sema_v(&fdc->c_ocsem); 1610 (void) pm_idle_component(fdc->c_dip, 0); 1611 return (EROFS); 1612 } 1613 } 1614 1615 out: 1616 /* 1617 * mark open as having succeeded 1618 */ 1619 if (flag & FEXCL) { 1620 un->un_exclmask |= pbit; 1621 } 1622 if (otyp == OTYP_LYR) { 1623 un->un_lyropen[part]++; 1624 } else { 1625 un->un_regopen[otyp] |= pbit; 1626 } 1627 mutex_exit(&fdc->c_lolock); 1628 sema_v(&fdc->c_ocsem); 1629 (void) pm_idle_component(fdc->c_dip, 0); 1630 return (0); 1631 } 1632 /* 1633 * fd_part_is_open 1634 * return 1 if the partition is open 1635 * return 0 otherwise 1636 */ 1637 static int 1638 fd_part_is_open(struct fdunit *un, int part) 1639 { 1640 int i; 1641 for (i = 0; i < OTYPCNT - 1; i++) 1642 if (un->un_regopen[i] & (1 << part)) 1643 return (1); 1644 return (0); 1645 } 1646 1647 1648 /* ARGSUSED */ 1649 static int 1650 fd_close(dev_t dev, int flag, int otyp, cred_t *cred_p) 1651 { 1652 int unit, part_is_closed, part; 1653 register struct fdctlr *fdc; 1654 register struct fdunit *un; 1655 1656 fdc = fd_getctlr(dev); 1657 if (!fdc || !(un = fdc->c_un)) 1658 return (ENXIO); 1659 1660 1661 unit = fdc->c_un->un_unit_no; 1662 FDERRPRINT(FDEP_L1, FDEM_CLOS, (C, "fd_close\n")); 1663 part = FDPARTITION(dev); 1664 1665 sema_p(&fdc->c_ocsem); 1666 mutex_enter(&fdc->c_lolock); 1667 1668 if (otyp == OTYP_LYR) { 1669 un->un_lyropen[part]--; 1670 part_is_closed = (un->un_lyropen[part] == 0); 1671 } else { 1672 un->un_regopen[otyp] &= ~(1<<part); 1673 part_is_closed = 1; 1674 } 1675 if (part_is_closed) 1676 un->un_exclmask &= ~(1<<part); 1677 1678 if (fd_unit_is_open(un) == 0) { 1679 /* deselect drive on last close */ 1680 fdselect(fdc, unit, 0); 1681 un->un_flags &= ~FDUNIT_CHANGED; 1682 } 1683 mutex_exit(&fdc->c_lolock); 1684 sema_v(&fdc->c_ocsem); 1685 1686 return (0); 1687 } 1688 1689 /* 1690 * fd_strategy 1691 * checks operation, hangs buf struct off fdctlr, calls fdstart 1692 * if not already busy. Note that if we call start, then the operation 1693 * will already be done on return (start sleeps). 1694 */ 1695 static int 1696 fd_strategy(register struct buf *bp) 1697 { 1698 struct fdctlr *fdc; 1699 struct fdunit *un; 1700 uint_t phys_blkno; 1701 struct dk_map32 *dkm; 1702 1703 FDERRPRINT(FDEP_L1, FDEM_STRA, 1704 (C, "fd_strategy: bp = 0x%p, dev = 0x%lx\n", 1705 (void *)bp, bp->b_edev)); 1706 FDERRPRINT(FDEP_L1, FDEM_STRA, 1707 (C, "b_blkno=%x b_flags=%x b_count=%x\n", 1708 (int)bp->b_blkno, bp->b_flags, (int)bp->b_bcount)); 1709 fdc = fd_getctlr(bp->b_edev); 1710 un = fdc->c_un; 1711 dkm = &un->un_label.dkl_map[FDPARTITION(bp->b_edev)]; 1712 1713 /* 1714 * If it's medium density and the block no. isn't a multiple 1715 * of 1K, then return an error. 1716 */ 1717 if (un->un_chars->fdc_medium) { 1718 phys_blkno = (uint_t)bp->b_blkno >> 1; 1719 if (bp->b_blkno & 1) { 1720 FDERRPRINT(FDEP_L3, FDEM_STRA, 1721 (C, "b_blkno=0x%lx is not 1k aligned\n", 1722 (long)bp->b_blkno)); 1723 bp->b_error = EINVAL; 1724 bp->b_resid = bp->b_bcount; 1725 bp->b_flags |= B_ERROR; 1726 biodone(bp); 1727 return (0); 1728 } 1729 } else { 1730 phys_blkno = (uint_t)bp->b_blkno; 1731 } 1732 1733 1734 /* If the block number is past the end, return an error */ 1735 if ((phys_blkno > dkm->dkl_nblk)) { 1736 FDERRPRINT(FDEP_L3, FDEM_STRA, 1737 (C, "fd%d: block %ld is past the end! (nblk=%d)\n", 1738 0, (long)bp->b_blkno, dkm->dkl_nblk)); 1739 bp->b_error = ENOSPC; 1740 bp->b_resid = bp->b_bcount; 1741 bp->b_flags |= B_ERROR; 1742 biodone(bp); 1743 return (0); 1744 } 1745 1746 /* if at end of file, skip out now */ 1747 if (phys_blkno == dkm->dkl_nblk) { 1748 FDERRPRINT(FDEP_L1, FDEM_STRA, 1749 (C, "b_blkno is at the end!\n")); 1750 1751 if ((bp->b_flags & B_READ) == 0) { 1752 /* a write needs to get an error! */ 1753 bp->b_error = ENOSPC; 1754 bp->b_flags |= B_ERROR; 1755 1756 FDERRPRINT(FDEP_L1, FDEM_STRA, 1757 (C, "block is at end and this is a write\n")); 1758 1759 } 1760 1761 bp->b_resid = bp->b_bcount; 1762 biodone(bp); 1763 return (0); 1764 } 1765 1766 /* if operation not a multiple of sector size, is error! */ 1767 if (bp->b_bcount % un->un_chars->fdc_sec_size) { 1768 FDERRPRINT(FDEP_L3, FDEM_STRA, 1769 (C, "fd%d: requested transfer size(0x%lx) is not" 1770 " multiple of sector size(0x%x)\n", 0, 1771 bp->b_bcount, un->un_chars->fdc_sec_size)); 1772 FDERRPRINT(FDEP_L3, FDEM_STRA, 1773 (C, " b_blkno=0x%lx b_flags=0x%x\n", 1774 (long)bp->b_blkno, bp->b_flags)); 1775 bp->b_error = EINVAL; 1776 bp->b_resid = bp->b_bcount; 1777 bp->b_flags |= B_ERROR; 1778 biodone(bp); 1779 return (0); 1780 1781 } 1782 1783 /* 1784 * Put the buf request in the controller's queue, FIFO. 1785 */ 1786 bp->av_forw = 0; 1787 sema_p(&fdc->c_ocsem); 1788 1789 (void) pm_busy_component(fdc->c_dip, 0); 1790 1791 mutex_enter(&fdc->c_lolock); 1792 1793 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 1794 1795 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 1796 mutex_exit(&fdc->c_lolock); 1797 if ((pm_raise_power(fdc->c_dip, 0, PM_LEVEL_ON)) 1798 != DDI_SUCCESS) { 1799 sema_v(&fdc->c_ocsem); 1800 (void) pm_idle_component(fdc->c_dip, 0); 1801 bp->b_error = EIO; 1802 bp->b_resid = bp->b_bcount; 1803 bp->b_flags |= B_ERROR; 1804 biodone(bp); 1805 return (0); 1806 } else { 1807 mutex_enter(&fdc->c_lolock); 1808 } 1809 } 1810 if (un->un_iostat) { 1811 kstat_waitq_enter(KIOSP); 1812 } 1813 if (fdc->c_actf) 1814 fdc->c_actl->av_forw = bp; 1815 else 1816 fdc->c_actf = bp; 1817 fdc->c_actl = bp; 1818 1819 1820 /* call fdstart to start the transfer */ 1821 fdstart(fdc); 1822 1823 mutex_exit(&fdc->c_lolock); 1824 sema_v(&fdc->c_ocsem); 1825 (void) pm_idle_component(fdc->c_dip, 0); 1826 return (0); 1827 } 1828 1829 /* ARGSUSED2 */ 1830 static int 1831 fd_read(dev_t dev, struct uio *uio, cred_t *cred_p) 1832 { 1833 FDERRPRINT(FDEP_L1, FDEM_RDWR, (C, "fd_read\n")); 1834 return (physio(fd_strategy, NULL, dev, B_READ, minphys, uio)); 1835 } 1836 1837 /* ARGSUSED2 */ 1838 static int 1839 fd_write(dev_t dev, struct uio *uio, cred_t *cred_p) 1840 { 1841 FDERRPRINT(FDEP_L1, FDEM_RDWR, (C, "fd_write\n")); 1842 return (physio(fd_strategy, NULL, dev, B_WRITE, minphys, uio)); 1843 } 1844 1845 static void 1846 fdmotoff(void *arg) 1847 { 1848 struct fdctlr *fdc = arg; 1849 int unit = fdc->c_un->un_unit_no; 1850 1851 mutex_enter(&fdc->c_lolock); 1852 1853 /* Just return if we're about to call untimeout */ 1854 if (fdc->c_mtimeid == 0) { 1855 mutex_exit(&fdc->c_lolock); 1856 return; 1857 } 1858 1859 FDERRPRINT(FDEP_L1, FDEM_MOFF, (C, "fdmotoff\n")); 1860 1861 fdc->c_mtimeid = 0; 1862 1863 if (!(Msr(fdc) & CB) && (Dor(fdc) & (MOTEN(unit)))) { 1864 /* LINTED */ 1865 Set_dor(fdc, MOTEN(unit), 0); 1866 } 1867 1868 mutex_exit(&fdc->c_lolock); 1869 } 1870 1871 /* ARGSUSED */ 1872 static int 1873 fd_ioctl(dev_t dev, int cmd, intptr_t arg, int flag, 1874 cred_t *cred_p, int *rval_p) 1875 { 1876 union { 1877 struct dk_cinfo dki; 1878 struct dk_geom dkg; 1879 struct dk_allmap32 dka; 1880 struct fd_char fdchar; 1881 struct fd_drive drvchar; 1882 int temp; 1883 } cpy; 1884 1885 struct vtoc vtoc; 1886 struct fdunit *un; 1887 struct fdctlr *fdc; 1888 int unit, dkunit; 1889 int err = 0; 1890 uint_t sec_size; 1891 enum dkio_state state; 1892 int transfer_rate; 1893 1894 FDERRPRINT(FDEP_L1, FDEM_IOCT, 1895 (C, "fd_ioctl: cmd 0x%x, arg 0x%lx\n", cmd, (long)arg)); 1896 1897 /* The minor number should always be 0 */ 1898 if (FDUNIT(dev) != 0) 1899 return (ENXIO); 1900 1901 fdc = fd_getctlr(dev); 1902 unit = fdc->c_un->un_unit_no; 1903 un = fdc->c_un; 1904 sec_size = un->un_chars->fdc_sec_size; 1905 bzero(&cpy, sizeof (cpy)); 1906 1907 switch (cmd) { 1908 case DKIOCINFO: 1909 cpy.dki.dki_addr = 0; 1910 1911 /* 1912 * The meaning of the dki_slave and dki_unit fields 1913 * is unclear. The sparc floppy driver follows the same 1914 * convention as sd.c in that the instance number is 1915 * returned in the dki_cnum field. The dki_slave field is 1916 * ignored. 1917 * 1918 * The dki_cnum contains the controller instance 1919 * and its value can be any positive number. Even 1920 * though currently Sparc platforms only support 1921 * one controller, the controller instance number 1922 * can be any number since it is assigned by the 1923 * system depending on the device properties. 1924 */ 1925 1926 cpy.dki.dki_cnum = FDCTLR(dev); 1927 1928 /* 1929 * Sparc platforms support only one floppy drive. 1930 * The device node for the controller is the same as 1931 * the device node for the drive. The x86 driver is 1932 * different in that it has a node for the controller 1933 * and a child node for each drive. Since Sparc supports 1934 * only one drive, the unit number will always be zero. 1935 */ 1936 1937 cpy.dki.dki_unit = FDUNIT(dev); 1938 1939 /* 1940 * The meaning of the dki_slave field is unclear. 1941 * So, I will leave it set to 0. 1942 */ 1943 1944 cpy.dki.dki_slave = 0; 1945 1946 cpy.dki.dki_ctype = (ushort_t)-1; 1947 if (fdc->c_fdtype & FDCTYPE_82077) 1948 cpy.dki.dki_ctype = DKC_INTEL82077; 1949 cpy.dki.dki_flags = DKI_FMTTRK; 1950 cpy.dki.dki_partition = FDPARTITION(dev); 1951 cpy.dki.dki_maxtransfer = maxphys / DEV_BSIZE; 1952 if (ddi_copyout((caddr_t)&cpy.dki, (caddr_t)arg, 1953 sizeof (cpy.dki), flag)) 1954 err = EFAULT; 1955 break; 1956 case DKIOCGGEOM: 1957 cpy.dkg.dkg_ncyl = un->un_chars->fdc_ncyl; 1958 cpy.dkg.dkg_nhead = un->un_chars->fdc_nhead; 1959 cpy.dkg.dkg_nsect = un->un_chars->fdc_secptrack; 1960 cpy.dkg.dkg_intrlv = un->un_label.dkl_intrlv; 1961 cpy.dkg.dkg_rpm = un->un_label.dkl_rpm; 1962 cpy.dkg.dkg_pcyl = un->un_chars->fdc_ncyl; 1963 cpy.dkg.dkg_read_reinstruct = 1964 (int)(cpy.dkg.dkg_nsect * cpy.dkg.dkg_rpm * 4) / 60000; 1965 cpy.dkg.dkg_write_reinstruct = cpy.dkg.dkg_read_reinstruct; 1966 if (ddi_copyout((caddr_t)&cpy.dkg, (caddr_t)arg, 1967 sizeof (cpy.dkg), flag)) 1968 err = EFAULT; 1969 break; 1970 case DKIOCSGEOM: 1971 FDERRPRINT(FDEP_L3, FDEM_IOCT, 1972 (C, "fd_ioctl: DKIOCSGEOM not supported\n")); 1973 err = ENOTTY; 1974 break; 1975 1976 /* 1977 * return the map of all logical partitions 1978 */ 1979 case DKIOCGAPART: 1980 /* 1981 * We don't have anything to do if the application is ILP32 1982 * because the label map has a 32-bit format. Otherwise 1983 * convert. 1984 */ 1985 if ((flag & DATAMODEL_MASK) == DATAMODEL_ILP32) { 1986 if (ddi_copyout(&un->un_label.dkl_map, 1987 (void *)arg, sizeof (struct dk_allmap32), flag)) 1988 err = EFAULT; 1989 } 1990 #ifdef _MULTI_DATAMODEL 1991 else { 1992 struct dk_allmap dk_allmap; 1993 1994 ASSERT((flag & DATAMODEL_MASK) == DATAMODEL_LP64); 1995 for (dkunit = 0; dkunit < NDKMAP; dkunit++) { 1996 dk_allmap.dka_map[dkunit].dkl_cylno = 1997 un->un_label.dkl_map[dkunit].dkl_cylno; 1998 dk_allmap.dka_map[dkunit].dkl_nblk = 1999 un->un_label.dkl_map[dkunit].dkl_nblk; 2000 } 2001 if (ddi_copyout(&dk_allmap, (void *)arg, 2002 sizeof (struct dk_allmap), flag)) 2003 err = EFAULT; 2004 } 2005 #endif /* _MULTI_DATAMODEL */ 2006 break; 2007 2008 /* 2009 * Set the map of all logical partitions 2010 */ 2011 case DKIOCSAPART: 2012 if ((flag & DATAMODEL_MASK) == DATAMODEL_ILP32) { 2013 if (ddi_copyin((const void *)arg, &cpy.dka, 2014 sizeof (cpy.dka), flag)) 2015 return (EFAULT); 2016 else { 2017 mutex_enter(&fdc->c_lolock); 2018 for (dkunit = 0; dkunit < NDKMAP; dkunit++) { 2019 un->un_label.dkl_map[dkunit] = 2020 cpy.dka.dka_map[dkunit]; 2021 } 2022 mutex_exit(&fdc->c_lolock); 2023 } 2024 } 2025 #ifdef _MULTI_DATAMODEL 2026 else { 2027 struct dk_allmap dk_allmap; 2028 2029 ASSERT((flag & DATAMODEL_MASK) == DATAMODEL_LP64); 2030 if (ddi_copyin((const void *)arg, &dk_allmap, 2031 sizeof (dk_allmap), flag)) 2032 return (EFAULT); 2033 else { 2034 mutex_enter(&fdc->c_lolock); 2035 for (dkunit = 0; dkunit < NDKMAP; dkunit++) { 2036 un->un_label.dkl_map[dkunit].dkl_cylno = 2037 dk_allmap.dka_map[dkunit].dkl_cylno; 2038 un->un_label.dkl_map[dkunit].dkl_nblk = 2039 dk_allmap.dka_map[dkunit].dkl_nblk; 2040 } 2041 mutex_exit(&fdc->c_lolock); 2042 } 2043 } 2044 #endif /* _MULTI_DATAMODEL */ 2045 break; 2046 2047 case DKIOCGVTOC: 2048 mutex_enter(&fdc->c_lolock); 2049 2050 /* 2051 * Exit if the diskette has no label. 2052 * Also, get the label to make sure the 2053 * correct one is being used since the diskette 2054 * may have changed 2055 */ 2056 if (fdgetlabel(fdc, unit)) { 2057 mutex_exit(&fdc->c_lolock); 2058 err = EINVAL; 2059 break; 2060 } 2061 2062 /* Build a vtoc from the diskette's label */ 2063 fd_build_user_vtoc(un, &vtoc); 2064 mutex_exit(&fdc->c_lolock); 2065 2066 #ifdef _MULTI_DATAMODEL 2067 switch (ddi_model_convert_from(flag & FMODELS)) { 2068 case DDI_MODEL_ILP32: { 2069 struct vtoc32 vtoc32; 2070 2071 vtoctovtoc32(vtoc, vtoc32); 2072 if (ddi_copyout(&vtoc32, (void *)arg, 2073 sizeof (struct vtoc32), flag)) 2074 return (EFAULT); 2075 break; 2076 } 2077 2078 case DDI_MODEL_NONE: 2079 if (ddi_copyout(&vtoc, (void *)arg, 2080 sizeof (vtoc), flag)) 2081 return (EFAULT); 2082 break; 2083 } 2084 #else /* ! _MULTI_DATAMODEL */ 2085 if (ddi_copyout(&vtoc, (void *)arg, sizeof (vtoc), flag)) 2086 return (EFAULT); 2087 #endif /* _MULTI_DATAMODEL */ 2088 break; 2089 2090 case DKIOCSVTOC: 2091 2092 #ifdef _MULTI_DATAMODEL 2093 switch (ddi_model_convert_from(flag & FMODELS)) { 2094 case DDI_MODEL_ILP32: { 2095 struct vtoc32 vtoc32; 2096 2097 if (ddi_copyin((const void *)arg, &vtoc32, 2098 sizeof (struct vtoc32), flag)) { 2099 return (EFAULT); 2100 } 2101 vtoc32tovtoc(vtoc32, vtoc); 2102 break; 2103 } 2104 2105 case DDI_MODEL_NONE: 2106 if (ddi_copyin((const void *)arg, &vtoc, 2107 sizeof (vtoc), flag)) { 2108 return (EFAULT); 2109 } 2110 break; 2111 } 2112 #else /* ! _MULTI_DATAMODEL */ 2113 if (ddi_copyin((const void *)arg, &vtoc, sizeof (vtoc), flag)) 2114 return (EFAULT); 2115 #endif /* _MULTI_DATAMODEL */ 2116 2117 mutex_enter(&fdc->c_lolock); 2118 2119 /* 2120 * The characteristics structure must be filled in because 2121 * it helps build the vtoc. 2122 */ 2123 if ((un->un_chars->fdc_ncyl == 0) || 2124 (un->un_chars->fdc_nhead == 0) || 2125 (un->un_chars->fdc_secptrack == 0)) { 2126 mutex_exit(&fdc->c_lolock); 2127 err = EINVAL; 2128 break; 2129 } 2130 2131 if ((err = fd_build_label_vtoc(un, &vtoc)) != 0) { 2132 mutex_exit(&fdc->c_lolock); 2133 break; 2134 } 2135 2136 (void) pm_busy_component(fdc->c_dip, 0); 2137 2138 err = fdrw(fdc, unit, FDWRITE, 0, 0, 1, 2139 (caddr_t)&un->un_label, sizeof (struct dk_label)); 2140 mutex_exit(&fdc->c_lolock); 2141 (void) pm_idle_component(fdc->c_dip, 0); 2142 break; 2143 2144 case DKIOCSTATE: 2145 if (ddi_copyin((caddr_t)arg, (caddr_t)&state, 2146 sizeof (int), flag)) { 2147 err = EFAULT; 2148 break; 2149 } 2150 (void) pm_busy_component(fdc->c_dip, 0); 2151 2152 err = fd_check_media(dev, state); 2153 (void) pm_idle_component(fdc->c_dip, 0); 2154 2155 if (ddi_copyout((caddr_t)&un->un_media_state, 2156 (caddr_t)arg, sizeof (int), flag)) 2157 err = EFAULT; 2158 break; 2159 2160 case FDIOGCHAR: 2161 if (ddi_copyout((caddr_t)un->un_chars, (caddr_t)arg, 2162 sizeof (struct fd_char), flag)) 2163 err = EFAULT; 2164 break; 2165 2166 case FDIOSCHAR: 2167 if (ddi_copyin((caddr_t)arg, (caddr_t)&cpy.fdchar, 2168 sizeof (struct fd_char), flag)) { 2169 err = EFAULT; 2170 break; 2171 } 2172 2173 /* 2174 * Check the fields in the fdchar structure that are either 2175 * driver or controller dependent. 2176 */ 2177 2178 transfer_rate = cpy.fdchar.fdc_transfer_rate; 2179 if ((transfer_rate != 500) && (transfer_rate != 300) && 2180 (transfer_rate != 250) && (transfer_rate != 1000)) { 2181 FDERRPRINT(FDEP_L3, FDEM_IOCT, 2182 (C, "fd_ioctl: FDIOSCHAR odd transfer rate %d\n", 2183 cpy.fdchar.fdc_transfer_rate)); 2184 err = EINVAL; 2185 break; 2186 } 2187 2188 if ((cpy.fdchar.fdc_nhead < 1) || 2189 (cpy.fdchar.fdc_nhead > 2)) { 2190 FDERRPRINT(FDEP_L3, FDEM_IOCT, 2191 (C, "fd_ioctl: FDIOSCHAR bad no. of heads %d\n", 2192 cpy.fdchar.fdc_nhead)); 2193 err = EINVAL; 2194 break; 2195 } 2196 2197 /* 2198 * The number of cylinders must be between 0 and 255 2199 */ 2200 if ((cpy.fdchar.fdc_ncyl < 0) || (cpy.fdchar.fdc_ncyl > 255)) { 2201 FDERRPRINT(FDEP_L3, FDEM_IOCT, 2202 (C, "fd_ioctl: FDIOSCHAR bad cyl no %d\n", 2203 cpy.fdchar.fdc_ncyl)); 2204 err = EINVAL; 2205 break; 2206 } 2207 2208 /* Copy the fdchar structure */ 2209 2210 mutex_enter(&fdc->c_lolock); 2211 *(un->un_chars) = cpy.fdchar; 2212 2213 un->un_curfdtype = -1; 2214 2215 mutex_exit(&fdc->c_lolock); 2216 2217 break; 2218 case FDEJECT: /* eject disk */ 2219 case DKIOCEJECT: 2220 2221 /* 2222 * Fail the ioctl if auto-eject isn't supported 2223 */ 2224 if (fdc->c_un->un_drive->fdd_ejectable == 0) { 2225 2226 err = ENOSYS; 2227 2228 } else { 2229 (void) pm_busy_component(fdc->c_dip, 0); 2230 2231 mutex_enter(&fdc->c_lolock); 2232 2233 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 2234 2235 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 2236 mutex_exit(&fdc->c_lolock); 2237 if ((pm_raise_power(fdc->c_dip, 0, 2238 PM_LEVEL_ON)) != DDI_SUCCESS) { 2239 (void) pm_idle_component(fdc->c_dip, 0); 2240 err = EIO; 2241 } 2242 mutex_enter(&fdc->c_lolock); 2243 } 2244 } 2245 if (err == 0) { 2246 fdselect(fdc, unit, 1); 2247 fdeject(fdc, unit); 2248 mutex_exit(&fdc->c_lolock); 2249 } 2250 2251 (void) pm_idle_component(fdc->c_dip, 0); 2252 2253 /* 2254 * Make sure the drive is turned off 2255 */ 2256 if (fdc->c_fdtype & FDCTYPE_82077) { 2257 if (fdc->c_mtimeid == 0) { 2258 fdc->c_mtimeid = timeout(fdmotoff, fdc, 2259 Motoff_delay); 2260 } 2261 } 2262 2263 break; 2264 case FDGETCHANGE: /* disk changed */ 2265 2266 if (ddi_copyin((caddr_t)arg, (caddr_t)&cpy.temp, 2267 sizeof (int), flag)) { 2268 err = EFAULT; 2269 break; 2270 } 2271 2272 /* zero out the user's parameter */ 2273 cpy.temp = 0; 2274 2275 (void) pm_busy_component(fdc->c_dip, 0); 2276 2277 mutex_enter(&fdc->c_lolock); 2278 2279 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 2280 2281 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 2282 mutex_exit(&fdc->c_lolock); 2283 if ((pm_raise_power(fdc->c_dip, 0, PM_LEVEL_ON)) 2284 != DDI_SUCCESS) { 2285 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "Power \ 2286 change failed. \n")); 2287 (void) pm_idle_component(fdc->c_dip, 0); 2288 return (EIO); 2289 } 2290 2291 mutex_enter(&fdc->c_lolock); 2292 } 2293 if (un->un_flags & FDUNIT_CHANGED) 2294 cpy.temp |= FDGC_HISTORY; 2295 else 2296 cpy.temp &= ~FDGC_HISTORY; 2297 un->un_flags &= ~FDUNIT_CHANGED; 2298 2299 if (fd_pollable) { 2300 /* 2301 * If it's a "pollable" floppy, then we don't 2302 * have to do all the fdcheckdisk nastyness to 2303 * figure out if the thing is still there. 2304 */ 2305 if (fdsense_chng(fdc, unit)) { 2306 cpy.temp |= FDGC_CURRENT; 2307 } else { 2308 cpy.temp &= ~FDGC_CURRENT; 2309 } 2310 } else { 2311 2312 if (fdsense_chng(fdc, unit)) { 2313 /* 2314 * check disk change signal is asserted. 2315 * Now find out if the floppy is 2316 * inserted 2317 */ 2318 if (fdcheckdisk(fdc, unit)) { 2319 cpy.temp |= FDGC_CURRENT; 2320 } else { 2321 /* 2322 * Yes, the floppy was 2323 * reinserted. Implies 2324 * floppy change. 2325 */ 2326 cpy.temp &= ~FDGC_CURRENT; 2327 cpy.temp |= FDGC_HISTORY; 2328 } 2329 } else { 2330 cpy.temp &= ~FDGC_CURRENT; 2331 } 2332 } 2333 2334 /* 2335 * For a pollable floppy, the floppy_change signal 2336 * reflects whether the floppy is in there or not. 2337 * We can not detect a floppy change if we don't poll 2338 * this signal when the floppy is being changed. 2339 * Because as soon as the floppy is put back, the 2340 * signal is reset. 2341 * BUT the pollable floppies are available only on 2342 * Sparcstation Voyager Voyagers (Gypsy) only and 2343 * those are motorized floppies. For motorized floppies, 2344 * the floppy can only (assuming the user doesn't use a 2345 * pin to take out the floppy) be taken out by 2346 * issuing 'eject' command which sets the 2347 * un->un_ejected flag. So, if the following 2348 * condition is true, we can assume there 2349 * was a floppy change. 2350 */ 2351 if (un->un_ejected && !(cpy.temp & FDGC_CURRENT)) { 2352 cpy.temp |= FDGC_HISTORY; 2353 } 2354 un->un_ejected = 0; 2355 2356 2357 /* return the write-protection status */ 2358 fdgetcsb(fdc); 2359 if (fdsensedrv(fdc, unit) & WP_SR3) { 2360 cpy.temp |= FDGC_CURWPROT; 2361 } 2362 fdretcsb(fdc); 2363 mutex_exit(&fdc->c_lolock); 2364 2365 if (ddi_copyout((caddr_t)&cpy.temp, (caddr_t)arg, 2366 sizeof (int), flag)) 2367 err = EFAULT; 2368 (void) pm_idle_component(fdc->c_dip, 0); 2369 break; 2370 2371 case FDGETDRIVECHAR: 2372 2373 if (ddi_copyin((caddr_t)arg, (caddr_t)&cpy.drvchar, 2374 sizeof (struct fd_drive), flag)) { 2375 err = EFAULT; 2376 break; 2377 } 2378 2379 /* 2380 * Return the ejectable value based on the FD_MANUAL_EJECT 2381 * property 2382 */ 2383 cpy.drvchar.fdd_ejectable = fdc->c_un->un_drive->fdd_ejectable; 2384 cpy.drvchar.fdd_maxsearch = nfdtypes; /* 3 - hi m lo density */ 2385 if (fd_pollable) /* pollable device */ 2386 cpy.drvchar.fdd_flags |= FDD_POLLABLE; 2387 2388 /* the rest of the fd_drive struct is meaningless to us */ 2389 2390 if (ddi_copyout((caddr_t)&cpy.drvchar, (caddr_t)arg, 2391 sizeof (struct fd_drive), flag)) 2392 err = EFAULT; 2393 break; 2394 2395 case FDSETDRIVECHAR: 2396 FDERRPRINT(FDEP_L3, FDEM_IOCT, 2397 (C, "fd_ioctl: FDSETDRIVECHAR not supportedn\n")); 2398 err = ENOTTY; 2399 break; 2400 2401 case DKIOCREMOVABLE: { 2402 int i = 1; 2403 2404 /* no brainer: floppies are always removable */ 2405 if (ddi_copyout((caddr_t)&i, (caddr_t)arg, sizeof (int), 2406 flag)) { 2407 err = EFAULT; 2408 } 2409 break; 2410 } 2411 case DKIOCGMEDIAINFO: 2412 err = fd_get_media_info(un, (caddr_t)arg, flag); 2413 break; 2414 2415 2416 case FDIOCMD: 2417 { 2418 struct fd_cmd fc; 2419 int cyl, hd, spc, spt; 2420 int nblks; /* total no. of blocks */ 2421 2422 #ifdef _MULTI_DATAMODEL 2423 switch (ddi_model_convert_from(flag & FMODELS)) { 2424 case DDI_MODEL_ILP32: { 2425 struct fd_cmd32 fc32; 2426 2427 if (ddi_copyin((const void *)arg, &fc32, 2428 sizeof (fc32), flag)) { 2429 return (EFAULT); 2430 } 2431 fc.fdc_cmd = fc32.fdc_cmd; 2432 fc.fdc_flags = fc32.fdc_flags; 2433 fc.fdc_blkno = (daddr_t)fc32.fdc_blkno; 2434 fc.fdc_secnt = fc32.fdc_secnt; 2435 fc.fdc_bufaddr = (caddr_t)fc32.fdc_bufaddr; 2436 fc.fdc_buflen = fc32.fdc_buflen; 2437 fc.fdc_cmd = fc32.fdc_cmd; 2438 2439 break; 2440 } 2441 2442 case DDI_MODEL_NONE: 2443 if (ddi_copyin((const void *)arg, &fc, 2444 sizeof (fc), flag)) { 2445 return (EFAULT); 2446 } 2447 break; 2448 } 2449 #else /* ! _MULTI_DATAMODEL */ 2450 if (ddi_copyin((const void *)arg, &fc, sizeof (fc), flag)) { 2451 return (EFAULT); 2452 } 2453 #endif /* _MULTI_DATAMODEL */ 2454 2455 if (fc.fdc_cmd == FDCMD_READ || fc.fdc_cmd == FDCMD_WRITE) { 2456 auto struct iovec aiov; 2457 auto struct uio auio; 2458 struct uio *uio = &auio; 2459 2460 spc = (fc.fdc_cmd == FDCMD_READ)? B_READ: B_WRITE; 2461 2462 bzero(&auio, sizeof (struct uio)); 2463 bzero(&aiov, sizeof (struct iovec)); 2464 aiov.iov_base = fc.fdc_bufaddr; 2465 aiov.iov_len = (uint_t)fc.fdc_secnt * sec_size; 2466 uio->uio_iov = &aiov; 2467 2468 uio->uio_iovcnt = 1; 2469 uio->uio_resid = aiov.iov_len; 2470 uio->uio_segflg = UIO_USERSPACE; 2471 FDERRPRINT(FDEP_L2, FDEM_IOCT, 2472 (C, "fd_ioctl: call physio\n")); 2473 err = physio(fd_strategy, NULL, dev, 2474 spc, minphys, uio); 2475 break; 2476 } else if (fc.fdc_cmd != FDCMD_FORMAT_TRACK) { 2477 2478 /* 2479 * The manpage states that only the FDCMD_WRITE, 2480 * FDCMD_READ, and the FDCMD_FORMAT_TR are available. 2481 */ 2482 FDERRPRINT(FDEP_L1, FDEM_IOCT, 2483 (C, "fd_ioctl: FDIOCMD invalid command\n")); 2484 err = EINVAL; 2485 break; 2486 } 2487 2488 /* The command is FDCMD_FORMAT_TRACK */ 2489 2490 spt = un->un_chars->fdc_secptrack; /* sec/trk */ 2491 spc = un->un_chars->fdc_nhead * spt; /* sec/cyl */ 2492 cyl = fc.fdc_blkno / spc; 2493 hd = (fc.fdc_blkno % spc) / spt; 2494 2495 /* 2496 * Make sure the specified block number is in the correct 2497 * range. (block numbers start at 0) 2498 */ 2499 nblks = spc * un->un_chars->fdc_ncyl; 2500 2501 if (fc.fdc_blkno < 0 || fc.fdc_blkno > (nblks - 1)) { 2502 err = EINVAL; 2503 break; 2504 } 2505 2506 (void) pm_busy_component(fdc->c_dip, 0); 2507 2508 mutex_enter(&fdc->c_lolock); 2509 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 2510 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 2511 mutex_exit(&fdc->c_lolock); 2512 if ((pm_raise_power(fdc->c_dip, 0, PM_LEVEL_ON)) 2513 != DDI_SUCCESS) { 2514 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "Power \ 2515 change failed. \n")); 2516 (void) pm_idle_component(fdc->c_dip, 0); 2517 return (EIO); 2518 } 2519 2520 mutex_enter(&fdc->c_lolock); 2521 } 2522 2523 if (fdformat(fdc, unit, cyl, hd)) 2524 err = EIO; 2525 2526 mutex_exit(&fdc->c_lolock); 2527 (void) pm_idle_component(fdc->c_dip, 0); 2528 2529 break; 2530 } 2531 2532 case FDRAW: 2533 2534 (void) pm_busy_component(fdc->c_dip, 0); 2535 err = fdrawioctl(fdc, unit, arg, flag); 2536 2537 (void) pm_idle_component(fdc->c_dip, 0); 2538 2539 break; 2540 #ifdef FD_DEBUG 2541 case IOCTL_DEBUG: 2542 fderrlevel--; 2543 if (fderrlevel < 0) 2544 fderrlevel = 3; 2545 cmn_err(C, "fdioctl: CHANGING debug to %d", fderrlevel); 2546 return (0); 2547 #endif /* FD_DEBUG */ 2548 default: 2549 FDERRPRINT(FDEP_L2, FDEM_IOCT, 2550 (C, "fd_ioctl: invalid ioctl 0x%x\n", cmd)); 2551 err = ENOTTY; 2552 break; 2553 } 2554 2555 return (err); 2556 } 2557 2558 /* 2559 * fdrawioctl 2560 * 2561 * - acquires the low level lock 2562 */ 2563 2564 static int 2565 fdrawioctl(struct fdctlr *fdc, int unit, intptr_t arg, int mode) 2566 { 2567 struct fd_raw fdr; 2568 #ifdef _MULTI_DATAMODEL 2569 struct fd_raw32 fdr32; 2570 #endif 2571 struct fdcsb *csb; 2572 int i, err, flag; 2573 caddr_t fa; 2574 uint_t fc; 2575 size_t real_length; 2576 int res; 2577 ddi_device_acc_attr_t attr; 2578 ddi_acc_handle_t mem_handle; 2579 2580 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 2581 attr.devacc_attr_endian_flags = DDI_STRUCTURE_BE_ACC; 2582 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 2583 2584 ASSERT(fdc->c_un->un_unit_no == unit); 2585 2586 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2587 (C, "fdrawioctl: cmd[0]=0x%x\n", fdr.fdr_cmd[0])); 2588 2589 flag = B_READ; 2590 err = 0; 2591 fa = NULL; 2592 fc = (uint_t)0; 2593 2594 /* Copy in the arguments */ 2595 switch (ddi_model_convert_from(mode)) { 2596 #ifdef _MULTI_DATAMODEL 2597 case DDI_MODEL_ILP32: 2598 if (ddi_copyin((caddr_t)arg, (caddr_t)&fdr32, 2599 sizeof (fdr32), mode)) { 2600 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2601 (C, "fdrawioctl: copyin error, args32\n")); 2602 return (EFAULT); 2603 } 2604 bcopy(fdr32.fdr_cmd, fdr.fdr_cmd, sizeof (fdr.fdr_cmd)); 2605 fdr.fdr_cnum = fdr32.fdr_cnum; 2606 bcopy(fdr32.fdr_result, fdr.fdr_result, 2607 sizeof (fdr.fdr_result)); 2608 fdr.fdr_nbytes = fdr32.fdr_nbytes; 2609 fdr.fdr_addr = (caddr_t)fdr32.fdr_addr; 2610 break; 2611 #endif 2612 default: 2613 case DDI_MODEL_NONE: 2614 if (ddi_copyin((caddr_t)arg, (caddr_t)&fdr, 2615 sizeof (fdr), mode)) { 2616 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2617 (C, "fdrawioctl: copyin error, args\n")); 2618 return (EFAULT); 2619 } 2620 break; 2621 } 2622 2623 mutex_enter(&fdc->c_lolock); 2624 2625 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 2626 2627 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 2628 mutex_exit(&fdc->c_lolock); 2629 if ((pm_raise_power(fdc->c_dip, 0, PM_LEVEL_ON)) 2630 != DDI_SUCCESS) { 2631 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "Power change \ 2632 failed. \n")); 2633 2634 (void) pm_idle_component(fdc->c_dip, 0); 2635 return (EIO); 2636 } 2637 mutex_enter(&fdc->c_lolock); 2638 } 2639 2640 fdgetcsb(fdc); 2641 csb = &fdc->c_csb; 2642 csb->csb_unit = (uchar_t)unit; 2643 2644 /* copy cmd bytes into csb */ 2645 for (i = 0; i <= fdr.fdr_cnum; i++) 2646 csb->csb_cmds[i] = fdr.fdr_cmd[i]; 2647 csb->csb_ncmds = (uchar_t)fdr.fdr_cnum; 2648 2649 csb->csb_maxretry = 0; /* let the application deal with errors */ 2650 csb->csb_retrys = 0; 2651 2652 switch (fdr.fdr_cmd[0] & 0x0f) { 2653 2654 case FDRAW_SPECIFY: 2655 /* 2656 * Ensure that the right DMA mode is selected. There is 2657 * currently no way for the user to tell if DMA is 2658 * happening so set the value for the user. 2659 */ 2660 2661 if (fdc->c_fdtype & FDCTYPE_DMA) 2662 csb->csb_cmds[2] = csb->csb_cmds[2] & 0xFE; 2663 else 2664 csb->csb_cmds[2] = csb->csb_cmds[2] | 0x1; 2665 2666 csb->csb_opflags = CSB_OFNORESULTS; 2667 csb->csb_nrslts = 0; 2668 break; 2669 2670 case FDRAW_SENSE_DRV: 2671 /* Insert the appropriate drive number */ 2672 csb->csb_cmds[1] = csb->csb_cmds[1] | (unit & DRV_MASK); 2673 csb->csb_opflags = CSB_OFIMMEDIATE; 2674 csb->csb_nrslts = 1; 2675 break; 2676 2677 case FDRAW_REZERO: 2678 case FDRAW_SEEK: 2679 /* Insert the appropriate drive number */ 2680 csb->csb_cmds[1] = csb->csb_cmds[1] | (unit & DRV_MASK); 2681 csb->csb_opflags = CSB_OFSEEKOPS + CSB_OFTIMEIT; 2682 csb->csb_nrslts = 2; 2683 break; 2684 2685 case FDRAW_FORMAT: 2686 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2687 (C, "fdrawioctl: cmd is fdfraw format\n")); 2688 2689 /* Insert the appropriate drive number */ 2690 csb->csb_cmds[1] = csb->csb_cmds[1] | (unit & DRV_MASK); 2691 csb->csb_opflags = CSB_OFXFEROPS + CSB_OFTIMEIT; 2692 csb->csb_nrslts = NRBRW; 2693 flag = B_WRITE; 2694 2695 /* 2696 * Allocate memory for the command. 2697 * If PIO is being used, then add an extra 16 bytes 2698 */ 2699 if (fdc->c_fdtype & FDCTYPE_DMA) { 2700 2701 fc = (uint_t)(fdr.fdr_nbytes); 2702 mutex_enter(&fdc->c_hilock); 2703 2704 res = ddi_dma_mem_alloc(fdc->c_dmahandle, fc, 2705 &attr, DDI_DMA_STREAMING, 2706 DDI_DMA_DONTWAIT, 0, &fa, &real_length, 2707 &mem_handle); 2708 2709 if (res != DDI_SUCCESS) { 2710 fdretcsb(fdc); 2711 mutex_exit(&fdc->c_lolock); 2712 mutex_exit(&fdc->c_hilock); 2713 return (EIO); 2714 } 2715 2716 fdc->c_csb.csb_read = CSB_WRITE; 2717 if (fdstart_dma(fdc, fa, fc) != 0) { 2718 ddi_dma_mem_free(&mem_handle); 2719 fdretcsb(fdc); 2720 mutex_exit(&fdc->c_lolock); 2721 mutex_exit(&fdc->c_hilock); 2722 return (EIO); 2723 } 2724 mutex_exit(&fdc->c_hilock); 2725 2726 } else { 2727 fc = (uint_t)(fdr.fdr_nbytes + 16); 2728 fa = kmem_zalloc(fc, KM_SLEEP); 2729 } 2730 2731 /* copy in the user's command bytes */ 2732 if (ddi_copyin(fdr.fdr_addr, fa, 2733 (uint_t)fdr.fdr_nbytes, mode)) { 2734 fdretcsb(fdc); 2735 mutex_exit(&fdc->c_lolock); 2736 2737 if (fdc->c_fdtype & FDCTYPE_DMA) { 2738 ddi_dma_mem_free(&mem_handle); 2739 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2740 (C, "fdrawioctl: (err)free dma memory\n")); 2741 } else { 2742 kmem_free(fa, fc); 2743 } 2744 2745 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2746 (C, "fdrawioctl: ddi_copyin error\n")); 2747 return (EFAULT); 2748 } 2749 2750 break; 2751 case FDRAW_WRCMD: 2752 case FDRAW_WRITEDEL: 2753 flag = B_WRITE; 2754 /* FALLTHROUGH */ 2755 case FDRAW_RDCMD: 2756 case FDRAW_READDEL: 2757 case FDRAW_READTRACK: 2758 /* Insert the appropriate drive number */ 2759 csb->csb_cmds[1] = csb->csb_cmds[1] | (unit & DRV_MASK); 2760 if (fdc->c_fdtype & FDCTYPE_SB) 2761 csb->csb_cmds[1] |= IPS; 2762 csb->csb_opflags = CSB_OFXFEROPS + CSB_OFTIMEIT; 2763 csb->csb_nrslts = NRBRW; 2764 break; 2765 2766 default: 2767 fdretcsb(fdc); 2768 mutex_exit(&fdc->c_lolock); 2769 return (EINVAL); 2770 } 2771 2772 if ((csb->csb_opflags & CSB_OFXFEROPS) && (fdr.fdr_nbytes == 0)) { 2773 fdretcsb(fdc); 2774 mutex_exit(&fdc->c_lolock); 2775 return (EINVAL); 2776 } 2777 csb->csb_opflags |= CSB_OFRAWIOCTL; 2778 2779 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2780 (C, "fdrawioctl: nbytes = %u\n", fdr.fdr_nbytes)); 2781 2782 if ((fdr.fdr_cmd[0] & 0x0f) != FDRAW_FORMAT) { 2783 if ((fc = (uint_t)fdr.fdr_nbytes) > 0) { 2784 /* 2785 * In SunOS 4.X, we used to as_fault things in. 2786 * We really cannot do this in 5.0/SVr4. Unless 2787 * someone really believes that speed is of the 2788 * essence here, it is just much simpler to do 2789 * this in kernel space and use copyin/copyout. 2790 */ 2791 if (fdc->c_fdtype & FDCTYPE_DMA) { 2792 mutex_enter(&fdc->c_hilock); 2793 res = ddi_dma_mem_alloc(fdc->c_dmahandle, fc, 2794 &attr, DDI_DMA_STREAMING, 2795 DDI_DMA_DONTWAIT, 0, &fa, &real_length, 2796 &mem_handle); 2797 2798 if (res != DDI_SUCCESS) { 2799 fdretcsb(fdc); 2800 mutex_exit(&fdc->c_lolock); 2801 mutex_exit(&fdc->c_hilock); 2802 return (EIO); 2803 } 2804 2805 if (flag == B_WRITE) 2806 fdc->c_csb.csb_read = CSB_WRITE; 2807 else 2808 fdc->c_csb.csb_read = CSB_READ; 2809 2810 if (fdstart_dma(fdc, fa, fc) != 0) { 2811 ddi_dma_mem_free(&mem_handle); 2812 fdretcsb(fdc); 2813 mutex_exit(&fdc->c_lolock); 2814 mutex_exit(&fdc->c_hilock); 2815 return (EIO); 2816 } 2817 mutex_exit(&fdc->c_hilock); 2818 2819 } else { 2820 fa = kmem_zalloc(fc, KM_SLEEP); 2821 } 2822 2823 if (flag == B_WRITE) { 2824 if (ddi_copyin(fdr.fdr_addr, fa, fc, mode)) { 2825 if (fdc->c_fdtype & FDCTYPE_DMA) 2826 ddi_dma_mem_free(&mem_handle); 2827 else 2828 kmem_free(fa, fc); 2829 fdretcsb(fdc); 2830 mutex_exit(&fdc->c_lolock); 2831 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2832 (C, "fdrawioctl: can't copy data\n")); 2833 2834 return (EFAULT); 2835 } 2836 } 2837 csb->csb_addr = fa; 2838 csb->csb_len = fc; 2839 } else { 2840 csb->csb_addr = 0; 2841 csb->csb_len = 0; 2842 } 2843 } else { 2844 csb->csb_addr = fa; 2845 csb->csb_len = fc; 2846 } 2847 2848 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2849 (C, "cmd: %x %x %x %x %x %x %x %x %x %x\n", csb->csb_cmds[0], 2850 csb->csb_cmds[1], csb->csb_cmds[2], csb->csb_cmds[3], 2851 csb->csb_cmds[4], csb->csb_cmds[5], csb->csb_cmds[6], 2852 csb->csb_cmds[7], csb->csb_cmds[8], csb->csb_cmds[9])); 2853 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2854 (C, "nbytes: %x, opflags: %x, addr: %p, len: %x\n", 2855 csb->csb_ncmds, csb->csb_opflags, (void *)csb->csb_addr, 2856 csb->csb_len)); 2857 2858 2859 /* 2860 * Note that we ignore any error return s from fdexec. 2861 * This is the way the driver has been, and it may be 2862 * that the raw ioctl senders simply don't want to 2863 * see any errors returned in this fashion. 2864 */ 2865 2866 if ((csb->csb_opflags & CSB_OFNORESULTS) || 2867 (csb->csb_opflags & CSB_OFIMMEDIATE)) { 2868 (void) fdexec(fdc, 0); /* don't sleep, don't check change */ 2869 } else { 2870 (void) fdexec(fdc, FDXC_SLEEP | FDXC_CHECKCHG); 2871 } 2872 2873 2874 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2875 (C, "rslt: %x %x %x %x %x %x %x %x %x %x\n", csb->csb_rslt[0], 2876 csb->csb_rslt[1], csb->csb_rslt[2], csb->csb_rslt[3], 2877 csb->csb_rslt[4], csb->csb_rslt[5], csb->csb_rslt[6], 2878 csb->csb_rslt[7], csb->csb_rslt[8], csb->csb_rslt[9])); 2879 2880 if ((fdr.fdr_cmd[0] & 0x0f) != FDRAW_FORMAT && fc && 2881 flag == B_READ && err == 0) { 2882 if (ddi_copyout(fa, fdr.fdr_addr, fc, mode)) { 2883 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2884 (C, "fdrawioctl: can't copy read data\n")); 2885 2886 err = EFAULT; 2887 } 2888 } 2889 2890 2891 if (fc) { 2892 if (fdc->c_fdtype & FDCTYPE_DMA) { 2893 ddi_dma_mem_free(&mem_handle); 2894 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2895 (C, "fdrawioctl: free dma memory\n")); 2896 } else { 2897 kmem_free(fa, fc); 2898 } 2899 } 2900 2901 2902 /* copy cmd results into fdr */ 2903 for (i = 0; (int)i <= (int)csb->csb_nrslts; i++) 2904 fdr.fdr_result[i] = csb->csb_rslt[i]; 2905 fdr.fdr_nbytes = fdc->c_csb.csb_rlen; /* return resid */ 2906 2907 switch (ddi_model_convert_from(mode)) { 2908 #ifdef _MULTI_DATAMODEL 2909 case DDI_MODEL_ILP32: 2910 bcopy(fdr.fdr_cmd, fdr32.fdr_cmd, sizeof (fdr32.fdr_cmd)); 2911 fdr32.fdr_cnum = fdr.fdr_cnum; 2912 bcopy(fdr.fdr_result, fdr32.fdr_result, 2913 sizeof (fdr32.fdr_result)); 2914 fdr32.fdr_nbytes = fdr.fdr_nbytes; 2915 fdr32.fdr_addr = (caddr32_t)fdr.fdr_addr; 2916 if (ddi_copyout(&fdr32, (caddr_t)arg, sizeof (fdr32), mode)) { 2917 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2918 (C, "fdrawioctl: can't copy results32\n")); 2919 err = EFAULT; 2920 } 2921 break; 2922 #endif 2923 case DDI_MODEL_NONE: 2924 default: 2925 if (ddi_copyout(&fdr, (caddr_t)arg, sizeof (fdr), mode)) { 2926 FDERRPRINT(FDEP_L1, FDEM_RAWI, 2927 (C, "fdrawioctl: can't copy results\n")); 2928 err = EFAULT; 2929 } 2930 break; 2931 } 2932 2933 fdretcsb(fdc); 2934 mutex_exit(&fdc->c_lolock); 2935 return (0); 2936 } 2937 2938 /* 2939 * fdformat 2940 * format a track 2941 * For PIO, builds a table of sector data values with 16 bytes 2942 * (sizeof fdc's fifo) of dummy on end. This is so than when fdc->c_len 2943 * goes to 0 and fd_intr sends a TC that all the real formatting will 2944 * have already been done. 2945 * 2946 * - called with the low level lock held 2947 */ 2948 static int 2949 fdformat(struct fdctlr *fdc, int unit, int cyl, int hd) 2950 { 2951 struct fdcsb *csb; 2952 struct fdunit *un; 2953 struct fd_char *ch; 2954 int cmdresult; 2955 uchar_t *fmthdrs; 2956 caddr_t fd; 2957 int i; 2958 size_t real_length; 2959 ddi_device_acc_attr_t attr; 2960 ddi_acc_handle_t mem_handle; 2961 2962 FDERRPRINT(FDEP_L1, FDEM_FORM, 2963 (C, "fdformat cyl %d, hd %d\n", cyl, hd)); 2964 fdgetcsb(fdc); 2965 2966 ASSERT(fdc->c_un->un_unit_no == unit); 2967 2968 csb = &fdc->c_csb; 2969 un = fdc->c_un; 2970 ch = un->un_chars; 2971 2972 /* setup common things in csb */ 2973 csb->csb_unit = (uchar_t)unit; 2974 2975 /* 2976 * The controller needs to do a seek before 2977 * each format to get to right cylinder. 2978 */ 2979 if (fdrecalseek(fdc, unit, cyl, FDXC_CHECKCHG)) { 2980 fdretcsb(fdc); 2981 return (EIO); 2982 } 2983 2984 /* 2985 * now do the format itself 2986 */ 2987 csb->csb_nrslts = NRBRW; 2988 csb->csb_opflags = CSB_OFXFEROPS | CSB_OFTIMEIT; 2989 2990 csb->csb_cmds[0] = FDRAW_FORMAT; 2991 /* always or in MFM bit */ 2992 csb->csb_cmds[0] |= MFM; 2993 csb->csb_cmds[1] = (hd << 2) | (unit & 0x03); 2994 csb->csb_cmds[2] = ch->fdc_medium ? 3 : 2; 2995 csb->csb_cmds[3] = ch->fdc_secptrack; 2996 csb->csb_cmds[4] = GPLF; 2997 csb->csb_cmds[5] = FDATA; 2998 csb->csb_ncmds = 6; 2999 csb->csb_maxretry = rwretry; 3000 csb->csb_retrys = 0; 3001 3002 /* 3003 * NOTE: have to add size of fifo also - for dummy format action 3004 * if PIO is being used. 3005 */ 3006 3007 3008 if (fdc->c_fdtype & FDCTYPE_DMA) { 3009 3010 csb->csb_len = (uint_t)4 * ch->fdc_secptrack; 3011 3012 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 3013 attr.devacc_attr_endian_flags = DDI_STRUCTURE_BE_ACC; 3014 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 3015 3016 mutex_enter(&fdc->c_hilock); 3017 3018 cmdresult = ddi_dma_mem_alloc(fdc->c_dmahandle, csb->csb_len, 3019 &attr, DDI_DMA_STREAMING, 3020 DDI_DMA_DONTWAIT, 0, &fd, &real_length, 3021 &mem_handle); 3022 3023 if (cmdresult != DDI_SUCCESS) { 3024 mutex_exit(&fdc->c_hilock); 3025 return (cmdresult); 3026 } 3027 3028 fdc->c_csb.csb_read = CSB_WRITE; 3029 if (fdstart_dma(fdc, fd, csb->csb_len) != 0) { 3030 ddi_dma_mem_free(&mem_handle); 3031 mutex_exit(&fdc->c_hilock); 3032 return (-1); 3033 } 3034 mutex_exit(&fdc->c_hilock); 3035 3036 3037 } else { 3038 csb->csb_len = (uint_t)4 * ch->fdc_secptrack + 16; 3039 fd = kmem_zalloc(csb->csb_len, KM_SLEEP); 3040 fmthdrs = (uchar_t *)fd; 3041 } 3042 3043 csb->csb_addr = (caddr_t)fd; 3044 3045 for (i = 1; i <= ch->fdc_secptrack; i++) { 3046 *fd++ = (uchar_t)cyl; /* cylinder */ 3047 *fd++ = (uchar_t)hd; /* head */ 3048 *fd++ = (uchar_t)i; /* sector number */ 3049 *fd++ = ch->fdc_medium ? 3 : 2; /* sec_size code */ 3050 } 3051 3052 if ((cmdresult = fdexec(fdc, FDXC_SLEEP | FDXC_CHECKCHG)) == 0) { 3053 if (csb->csb_cmdstat) 3054 cmdresult = EIO; /* XXX TBD NYD for now */ 3055 } 3056 3057 if (fdc->c_fdtype & FDCTYPE_DMA) { 3058 ddi_dma_mem_free(&mem_handle); 3059 } else { 3060 kmem_free((caddr_t)fmthdrs, csb->csb_len); 3061 } 3062 3063 fdretcsb(fdc); 3064 3065 return (cmdresult); 3066 } 3067 3068 /* 3069 * fdstart 3070 * called from fd_strategy() or from fdXXXX() to setup and 3071 * start operations of read or write only (using buf structs). 3072 * Because the chip doesn't handle crossing cylinder boundaries on 3073 * the fly, this takes care of those boundary conditions. Note that 3074 * it sleeps until the operation is done *within fdstart* - so that 3075 * when fdstart returns, the operation is already done. 3076 * 3077 * - called with the low level lock held 3078 * 3079 */ 3080 3081 static int slavio_index_pulse_work_around = 0; 3082 3083 static void 3084 fdstart(struct fdctlr *fdc) 3085 { 3086 struct buf *bp; 3087 struct fdcsb *csb; 3088 struct fdunit *un; 3089 struct fd_char *ch; 3090 struct dk_map32 *dkm; 3091 uint_t part; /* partition number for the transfer */ 3092 uint_t start_part; /* starting block of the partition */ 3093 uint_t last_part; /* last block of the partition */ 3094 uint_t blk; /* starting block of transfer on diskette */ 3095 uint_t sect; /* starting block's offset into track */ 3096 uint_t cyl; /* starting cylinder of the transfer */ 3097 uint_t bincyl; /* starting blocks's offset into cylinder */ 3098 uint_t secpcyl; /* number of sectors per cylinder */ 3099 uint_t phys_blkno; /* no. of blocks on the diskette */ 3100 uint_t head; /* one of two diskette heads */ 3101 uint_t unit; 3102 uint_t len, tlen; 3103 caddr_t addr; 3104 caddr_t temp_addr; 3105 uint_t partial_read = 0; 3106 int sb_temp_buf_used = 0; 3107 3108 bp = fdc->c_actf; 3109 3110 while (bp != NULL) { 3111 3112 fdc->c_actf = bp->av_forw; 3113 fdc->c_current = bp; 3114 3115 /* 3116 * Initialize the buf structure. The residual count is 3117 * initially the number of bytes to be read or written 3118 */ 3119 bp->b_flags &= ~B_ERROR; 3120 bp->b_error = 0; 3121 bp->b_resid = bp->b_bcount; 3122 bp_mapin(bp); /* map in buffers */ 3123 3124 addr = bp->b_un.b_addr; /* assign buffer address */ 3125 3126 /* 3127 * Find the unit and partition numbers. 3128 */ 3129 unit = fdc->c_un->un_unit_no; 3130 un = fdc->c_un; 3131 ch = un->un_chars; 3132 part = FDPARTITION(bp->b_edev); 3133 dkm = &un->un_label.dkl_map[part]; 3134 3135 if (un->un_chars->fdc_medium) { 3136 phys_blkno = bp->b_blkno >> 1; 3137 } else { 3138 phys_blkno = bp->b_blkno; 3139 } 3140 3141 if (un->un_iostat) { 3142 kstat_waitq_to_runq(KIOSP); 3143 } 3144 3145 FDERRPRINT(FDEP_L1, FDEM_STRT, 3146 (C, "fdstart: bp=0x%p blkno=0x%x bcount=0x%x\n", 3147 (void *)bp, (int)bp->b_blkno, (int)bp->b_bcount)); 3148 3149 /* 3150 * Get the csb and initialize the values that are the same 3151 * for DMA and PIO. 3152 */ 3153 fdgetcsb(fdc); /* get csb (maybe wait for it) */ 3154 csb = &fdc->c_csb; 3155 csb->csb_unit = unit; /* floppy unit number */ 3156 3157 3158 /* 3159 * bugID:4133425 : If the controller is SLAVIO, and 3160 * the read does not reach end of track, then modify 3161 * the tlen to read until the end of track to a temp 3162 * buffer and disable MT. After the read is over, 3163 * copy the useful portion of the data to 'addr'. 3164 * Enable this feature only when 3165 * slavio_index_pulse_work_aound variable is 3166 * set in /etc/system. 3167 */ 3168 3169 3170 if (bp->b_flags & B_READ) { 3171 if (((fdc->c_fdtype & FDCTYPE_SLAVIO) && 3172 slavio_index_pulse_work_around) || 3173 (fdc->c_fdtype & FDCTYPE_TCBUG)) 3174 csb->csb_cmds[0] = SK | FDRAW_RDCMD | MFM; 3175 else 3176 csb->csb_cmds[0] = MT | SK | FDRAW_RDCMD | MFM; 3177 } else { 3178 if (fdc->c_fdtype & FDCTYPE_TCBUG) 3179 csb->csb_cmds[0] = FDRAW_WRCMD | MFM; 3180 else 3181 csb->csb_cmds[0] = MT | FDRAW_WRCMD | MFM; 3182 } 3183 3184 3185 if (bp->b_flags & B_READ) 3186 fdc->c_csb.csb_read = CSB_READ; 3187 else 3188 fdc->c_csb.csb_read = CSB_WRITE; 3189 3190 3191 csb->csb_cmds[5] = ch->fdc_medium ? 3 : 2; /* sector size */ 3192 csb->csb_cmds[6] = ch->fdc_secptrack; /* EOT-# of sectors/trk */ 3193 csb->csb_cmds[7] = GPLN; /* GPL - gap 3 size code */ 3194 csb->csb_cmds[8] = SSSDTL; /* DTL - be 0xFF if N != 0 */ 3195 3196 csb->csb_ncmds = NCBRW; /* number of command bytes */ 3197 csb->csb_nrslts = NRBRW; /* number of result bytes */ 3198 3199 3200 /* 3201 * opflags for interrupt handler, et.al. 3202 */ 3203 csb->csb_opflags = CSB_OFXFEROPS | CSB_OFTIMEIT; 3204 3205 3206 /* 3207 * Make sure the transfer does not go off the end 3208 * of the partition. Limit the actual amount transferred 3209 * to fit the partition. 3210 */ 3211 3212 blk = phys_blkno; 3213 start_part = (dkm->dkl_cylno * ch->fdc_secptrack 3214 * ch->fdc_nhead); 3215 blk = blk + start_part; 3216 last_part = start_part + dkm->dkl_nblk; 3217 3218 if ((blk + (bp->b_bcount / ch->fdc_sec_size)) > last_part) 3219 len = (last_part - blk) * ch->fdc_sec_size; 3220 else 3221 len = (uint_t)bp->b_bcount; 3222 3223 /* 3224 * now we have the real start blk, 3225 * addr and len for xfer op 3226 * sectors per cylinder 3227 */ 3228 secpcyl = ch->fdc_nhead * ch->fdc_secptrack; 3229 3230 /* 3231 * The controller can transfer up to a cylinder at a time. 3232 * Early revs of the 82077 have a bug that causes the chip to 3233 * fail to respond to the Terminal Count signal. Due to this 3234 * bug, controllers with type FDCTYPE_TCBUG, only transfer up 3235 * to a track at a time. 3236 * See earlier comment for bugID:4133425 for index pulse 3237 * work around. 3238 */ 3239 3240 while (len != 0) { 3241 3242 cyl = blk / secpcyl; /* cylinder of transfer */ 3243 bincyl = blk % secpcyl; /* blk within cylinder */ 3244 head = bincyl / ch->fdc_secptrack; 3245 sect = (bincyl % ch->fdc_secptrack) + 1; 3246 /* sect w/in track */ 3247 3248 /* 3249 * If the desired block and length will go beyond the 3250 * cylinder end, limit it to the cylinder end. 3251 */ 3252 3253 if ((fdc->c_fdtype & FDCTYPE_SLAVIO) && 3254 slavio_index_pulse_work_around && 3255 (fdc->c_csb.csb_read == CSB_READ)) { 3256 3257 tlen = (ch->fdc_secptrack - sect + 1) * 3258 ch->fdc_sec_size; 3259 if (len < tlen) { 3260 partial_read = 1; 3261 temp_addr = (caddr_t)kmem_alloc(tlen, 3262 KM_SLEEP); 3263 } 3264 3265 } else if (fdc->c_fdtype & FDCTYPE_TCBUG) { 3266 tlen = len; 3267 if (len > ((ch->fdc_secptrack - sect + 1) * 3268 ch->fdc_sec_size)) 3269 tlen = (ch->fdc_secptrack - sect + 1) 3270 * ch->fdc_sec_size; 3271 } else { 3272 if (len > ((secpcyl - bincyl) 3273 * ch->fdc_sec_size)) 3274 tlen = (secpcyl - bincyl) 3275 * ch->fdc_sec_size; 3276 3277 else 3278 tlen = len; 3279 } 3280 if (fdc->c_fdtype & FDCTYPE_SB) { 3281 /* 3282 * To avoid underrun errors during IFB activity. 3283 */ 3284 if (tlen > max_fd_dma_len) 3285 tlen = max_fd_dma_len; 3286 } 3287 3288 FDERRPRINT(FDEP_L1, FDEM_STRT, 3289 (C, " blk 0x%x, addr 0x%p, len 0x%x\n", 3290 blk, (void *)addr, len)); 3291 FDERRPRINT(FDEP_L1, FDEM_STRT, 3292 (C, "cyl:%x, head:%x, sec:%x\n", 3293 cyl, head, sect)); 3294 3295 FDERRPRINT(FDEP_L1, FDEM_STRT, 3296 (C, " resid 0x%lx, tlen %d\n", 3297 bp->b_resid, tlen)); 3298 3299 /* 3300 * Finish programming the command 3301 */ 3302 csb->csb_cmds[1] = (head << 2) | unit; 3303 if (fdc->c_fdtype & FDCTYPE_SB) 3304 csb->csb_cmds[1] |= IPS; 3305 3306 csb->csb_cmds[2] = cyl; /* C - cylinder address */ 3307 csb->csb_cmds[3] = head; /* H - head number */ 3308 csb->csb_cmds[4] = sect; /* R - sector number */ 3309 if (fdc->c_fdtype & FDCTYPE_TCBUG) 3310 csb->csb_cmds[6] = sect + 3311 (tlen / ch->fdc_sec_size) - 1; 3312 3313 csb->csb_len = tlen; 3314 if (partial_read) 3315 csb->csb_addr = temp_addr; 3316 else 3317 csb->csb_addr = addr; 3318 3319 /* retry this many times max */ 3320 csb->csb_maxretry = rwretry; 3321 csb->csb_retrys = 0; 3322 3323 /* If platform supports DMA, set up DMA resources */ 3324 if (fdc->c_fdtype & FDCTYPE_DMA) { 3325 if ((fdc->c_fdtype & FDCTYPE_SB) && 3326 (((uint32_t)addr & 0xFFFF0000) != 3327 (((uint32_t)addr + tlen) & 0xFFFF0000))) { 3328 csb->csb_addr = fdc->dma_buf; 3329 sb_temp_buf_used = 1; 3330 if (csb->csb_read != CSB_READ) { 3331 bcopy(addr, fdc->dma_buf, tlen); 3332 } 3333 } 3334 mutex_enter(&fdc->c_hilock); 3335 3336 if (fdstart_dma(fdc, csb->csb_addr, 3337 tlen) != 0) { 3338 3339 bp->b_flags |= B_ERROR; 3340 bp->b_error = EAGAIN; 3341 3342 mutex_exit(&fdc->c_hilock); 3343 FDERRPRINT(FDEP_L1, FDEM_STRT, 3344 (C, "fdstart: no dma resources\n")); 3345 3346 break; 3347 } 3348 mutex_exit(&fdc->c_hilock); 3349 3350 } 3351 3352 bp->b_error = fdexec(fdc, FDXC_SLEEP|FDXC_CHECKCHG); 3353 if (bp->b_error != 0) { 3354 /* 3355 * error in fdexec 3356 */ 3357 FDERRPRINT(FDEP_L1, FDEM_STRT, (C, 3358 "fdstart: bad exec of bp: 0x%p, err %d\n", 3359 (void *)bp, bp->b_error)); 3360 3361 bp->b_flags |= B_ERROR; 3362 if (partial_read) { 3363 partial_read = 0; 3364 kmem_free(temp_addr, tlen); 3365 } 3366 break; 3367 } 3368 3369 /* 3370 * If it was a partial read, copy the useful 3371 * portion of data to 'addr'. 3372 */ 3373 if (partial_read) { 3374 partial_read = 0; 3375 bcopy(temp_addr, addr, len); 3376 kmem_free(temp_addr, tlen); 3377 tlen = len; 3378 } 3379 if ((fdc->c_fdtype & FDCTYPE_SB) && 3380 (csb->csb_read == CSB_READ)) { 3381 if (sb_temp_buf_used) { 3382 bcopy(fdc->dma_buf, addr, tlen); 3383 sb_temp_buf_used = 0; 3384 } 3385 } 3386 3387 blk += tlen / ch->fdc_sec_size; 3388 len -= tlen; 3389 addr += tlen; 3390 bp->b_resid -= tlen; 3391 3392 } 3393 3394 FDERRPRINT(FDEP_L1, FDEM_STRT, 3395 (C, "fdstart done: b_resid %lu, b_count %lu, csb_rlen %d\n", 3396 bp->b_resid, bp->b_bcount, fdc->c_csb.csb_rlen)); 3397 3398 fdc->c_current = 0; 3399 fdretcsb(fdc); 3400 if (un->un_iostat) { 3401 if (bp->b_flags & B_READ) { 3402 KIOSP->reads++; 3403 KIOSP->nread += 3404 (bp->b_bcount - bp->b_resid); 3405 } else { 3406 KIOSP->writes++; 3407 KIOSP->nwritten += (bp->b_bcount - bp->b_resid); 3408 } 3409 kstat_runq_exit(KIOSP); 3410 } 3411 biodone(bp); 3412 3413 /* 3414 * Look at the next buffer 3415 */ 3416 bp = fdc->c_actf; 3417 3418 } 3419 } 3420 3421 /* 3422 * Set up DMA resources 3423 * The DMA handle was initialized in fd_attach() 3424 * Assumes the handle has already been allocated by fd_attach() 3425 */ 3426 static int 3427 fdstart_dma(struct fdctlr *fdc, caddr_t addr, uint_t len) 3428 { 3429 int flags; /* flags for setting up resources */ 3430 int res; 3431 3432 FDERRPRINT(FDEP_L1, FDEM_SDMA, (C, "fdstart_dma: start\n")); 3433 3434 if (fdc->c_csb.csb_read == CSB_READ) { 3435 flags = DDI_DMA_READ; 3436 } else { 3437 flags = DDI_DMA_WRITE; 3438 } 3439 3440 3441 /* allow partial mapping to maximize the portability of the driver */ 3442 flags = flags | DDI_DMA_PARTIAL; 3443 3444 FDERRPRINT(FDEP_L1, FDEM_SDMA, (C, "fdstart_dma: amt. asked for %d\n", 3445 len)); 3446 3447 /* 3448 * Zero out the current cookie. This is done to ensure that 3449 * the previous transfers cookie information can in no way be 3450 * used. 3451 */ 3452 bzero((char *)&fdc->c_csb.csb_dmacookie, 3453 sizeof (fdc->c_csb.csb_dmacookie)); 3454 fdc->c_csb.csb_nwin = 0; 3455 fdc->c_csb.csb_windex = 0; 3456 fdc->c_csb.csb_ccount = 0; 3457 3458 res = ddi_dma_addr_bind_handle(fdc->c_dmahandle, NULL, addr, len, 3459 flags, DDI_DMA_DONTWAIT, 0, &fdc->c_csb.csb_dmacookie, 3460 &fdc->c_csb.csb_ccount); 3461 3462 switch (res) { 3463 case DDI_DMA_MAPPED: 3464 /* 3465 * There is one window. csb_windex is the index 3466 * into the array of windows. If there are n 3467 * windows then, (0 <= windex <= n-1). csb_windex 3468 * represents the index of the next window 3469 * to be processed. 3470 */ 3471 fdc->c_csb.csb_nwin = 1; 3472 fdc->c_csb.csb_windex = 1; 3473 3474 3475 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3476 (C, "fdstart_dma: DDI_DMA_MAPPED\n")); 3477 3478 break; 3479 case DDI_DMA_PARTIAL_MAP: 3480 3481 /* 3482 * obtain the number of DMA windows 3483 */ 3484 if (ddi_dma_numwin(fdc->c_dmahandle, 3485 &fdc->c_csb.csb_nwin) != DDI_SUCCESS) { 3486 return (-1); 3487 } 3488 3489 3490 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3491 (C, "fdstart_dma: partially mapped %d windows\n", 3492 fdc->c_csb.csb_nwin)); 3493 3494 /* 3495 * The DMA window currently in use is window number 3496 * one. 3497 */ 3498 fdc->c_csb.csb_windex = 1; 3499 3500 break; 3501 case DDI_DMA_NORESOURCES: 3502 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3503 (C, "fdstart_dma: no resources\n")); 3504 return (-1); 3505 case DDI_DMA_NOMAPPING: 3506 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3507 (C, "fdstart_dma: no mapping\n")); 3508 return (-1); 3509 case DDI_DMA_TOOBIG: 3510 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3511 (C, "fdstart_dma: too big\n")); 3512 return (-1); 3513 3514 case DDI_DMA_INUSE: 3515 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3516 (C, "fdstart_dma: dma inuse\n")); 3517 return (-1); 3518 default: 3519 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3520 (C, "fdstart_dma: result is 0x%x\n", res)); 3521 return (-1); 3522 3523 }; 3524 3525 FDERRPRINT(FDEP_L1, FDEM_SDMA, 3526 (C, "fdstart_dma: bound the handle\n")); 3527 3528 ASSERT(fdc->c_csb.csb_dmacookie.dmac_size); 3529 3530 FDERRPRINT(FDEP_L1, FDEM_SDMA, (C, "fdstart_dma: done\n")); 3531 return (0); 3532 } 3533 3534 3535 /* 3536 * fd_unbind_handle: unbind a dma handle if one exists 3537 * return EIO if unbind failes 3538 */ 3539 static int 3540 fd_unbind_handle(struct fdctlr *fdc) 3541 { 3542 if ((fdc->c_fdtype & FDCTYPE_DMA) && 3543 ((fdc->c_csb.csb_read == CSB_READ) || 3544 (fdc->c_csb.csb_read == CSB_WRITE))) { 3545 mutex_enter(&fdc->c_hilock); 3546 3547 if (fdc->c_fdtype & FDCTYPE_SB) { 3548 if (fdc->sb_dma_lock) { 3549 release_sb_dma(fdc); 3550 } 3551 } 3552 3553 /* 3554 * If the byte count isn't zero, then the DMA engine is 3555 * still doing a transfer. If the byte count is nonzero, 3556 * reset the DMA engine to cause it to drain. 3557 */ 3558 3559 if (get_data_count_register(fdc) != 0) { 3560 FDERRPRINT(FDEP_L1, FDEM_EXEC, 3561 (C, "unbind & byte count isn't zero\n")); 3562 3563 reset_dma_controller(fdc); 3564 set_dma_control_register(fdc, DCSR_INIT_BITS); 3565 } 3566 3567 if (ddi_dma_unbind_handle(fdc->c_dmahandle) != DDI_SUCCESS) { 3568 FDERRPRINT(FDEP_L1, FDEM_EXEC, 3569 (C, "problem unbinding the handle\n")); 3570 mutex_exit(&fdc->c_hilock); 3571 return (EIO); 3572 } 3573 mutex_exit(&fdc->c_hilock); 3574 } 3575 return (0); 3576 } 3577 3578 /* 3579 * fdexec 3580 * all commands go through here. Assumes the command block 3581 * fdctlr.c_csb is filled in. The bytes are sent to the 3582 * controller and then we do whatever else the csb says - 3583 * like wait for immediate results, etc. 3584 * 3585 * All waiting for operations done is in here - to allow retrys 3586 * and checking for disk changed - so we don't have to worry 3587 * about sleeping at interrupt level. 3588 * 3589 * RETURNS: 0 if all ok, 3590 * ENXIO - diskette not in drive 3591 * EBUSY - if chip is locked or busy 3592 * EIO - for timeout during sending cmds to chip 3593 * 3594 * to sleep: set FDXC_SLEEP, to check for disk 3595 * changed: set FDXC_CHECKCHG 3596 * 3597 * - called with the lock held 3598 */ 3599 static int 3600 fdexec(struct fdctlr *fdc, int flags) 3601 { 3602 struct fdcsb *csb; 3603 int i; 3604 int to, unit; 3605 uchar_t tmp; 3606 caddr_t a = (caddr_t)fdc; 3607 3608 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: flags:%x\n", flags)); 3609 3610 ASSERT(mutex_owned(&fdc->c_lolock)); 3611 3612 csb = &fdc->c_csb; 3613 unit = csb->csb_unit; 3614 3615 3616 ASSERT(unit == fdc->c_un->un_unit_no); 3617 3618 retry: 3619 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: cmd is %s\n", 3620 fdcmds[csb->csb_cmds[0] & 0x1f].cmdname)); 3621 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: transfer rate = %d\n", 3622 fdc->c_un->un_chars->fdc_transfer_rate)); 3623 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: sec size = %d\n", 3624 fdc->c_un->un_chars->fdc_sec_size)); 3625 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: nblocks (512) = %d\n", 3626 fdc->c_un->un_label.dkl_map[2].dkl_nblk)); 3627 3628 if ((fdc->c_fdtype & FDCTYPE_CTRLMASK) == FDCTYPE_82077) { 3629 fdexec_turn_on_motor(fdc, flags, unit); 3630 } 3631 3632 3633 fdselect(fdc, unit, 1); /* select drive */ 3634 3635 /* 3636 * select data rate for this unit/command 3637 */ 3638 switch (fdc->c_un->un_chars->fdc_transfer_rate) { 3639 case 500: 3640 Dsr(fdc, 0); 3641 break; 3642 case 300: 3643 Dsr(fdc, 1); 3644 break; 3645 case 250: 3646 Dsr(fdc, 2); 3647 break; 3648 } 3649 drv_usecwait(2); 3650 3651 3652 /* 3653 * If checking for changed is enabled (i.e., not seeking in checkdisk), 3654 * we sample the DSKCHG line to see if the diskette has wandered away. 3655 */ 3656 if ((flags & FDXC_CHECKCHG) && fdsense_chng(fdc, unit)) { 3657 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "diskette changed\n")); 3658 fdc->c_un->un_flags |= FDUNIT_CHANGED; 3659 3660 if (fdcheckdisk(fdc, unit)) { 3661 3662 (void) fd_unbind_handle(fdc); 3663 return (ENXIO); 3664 3665 } 3666 } 3667 3668 /* 3669 * gather some statistics 3670 */ 3671 switch (csb->csb_cmds[0] & 0x1f) { 3672 case FDRAW_RDCMD: 3673 fdc->fdstats.rd++; 3674 break; 3675 case FDRAW_WRCMD: 3676 fdc->fdstats.wr++; 3677 break; 3678 case FDRAW_REZERO: 3679 fdc->fdstats.recal++; 3680 break; 3681 case FDRAW_FORMAT: 3682 fdc->fdstats.form++; 3683 break; 3684 default: 3685 fdc->fdstats.other++; 3686 break; 3687 } 3688 3689 /* 3690 * Always set the opmode *prior* to poking the chip. 3691 * This way we don't have to do any locking at high level. 3692 */ 3693 csb->csb_raddr = 0; 3694 csb->csb_rlen = 0; 3695 if (csb->csb_opflags & CSB_OFSEEKOPS) { 3696 csb->csb_opmode = 2; 3697 } else if (csb->csb_opflags & CSB_OFIMMEDIATE) { 3698 csb->csb_opmode = 0; 3699 } else { 3700 csb->csb_opmode = 1; /* normal data xfer commands */ 3701 csb->csb_raddr = csb->csb_addr; 3702 csb->csb_rlen = csb->csb_len; 3703 } 3704 3705 bzero((caddr_t)csb->csb_rslt, 10); 3706 csb->csb_status = 0; 3707 csb->csb_cmdstat = 0; 3708 3709 3710 /* 3711 * Program the DMA engine with the length and address of the transfer 3712 * (DMA is only used on a read or a write) 3713 */ 3714 if ((fdc->c_fdtype & FDCTYPE_DMA) && 3715 ((fdc->c_csb.csb_read == CSB_READ) || 3716 (fdc->c_csb.csb_read == CSB_WRITE))) { 3717 mutex_enter(&fdc->c_hilock); 3718 3719 /* Reset the dcsr to clear it of all errors */ 3720 3721 reset_dma_controller(fdc); 3722 3723 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "cookie addr 0x%p\n", 3724 (void *)fdc->c_csb.csb_dmacookie.dmac_laddress)); 3725 3726 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "cookie length %ld\n", 3727 fdc->c_csb.csb_dmacookie.dmac_size)); 3728 ASSERT(fdc->c_csb.csb_dmacookie.dmac_size); 3729 3730 set_data_count_register(fdc, 3731 fdc->c_csb.csb_dmacookie.dmac_size); 3732 set_data_address_register(fdc, 3733 fdc->c_csb.csb_dmacookie.dmac_laddress); 3734 3735 /* Program the DCSR */ 3736 3737 if (fdc->c_csb.csb_read == CSB_READ) 3738 set_dma_mode(fdc, CSB_READ); 3739 else 3740 set_dma_mode(fdc, CSB_WRITE); 3741 mutex_exit(&fdc->c_hilock); 3742 } 3743 3744 /* 3745 * I saw this (chip unexpectedly busy) happen when i shoved the 3746 * floppy into the drive while 3747 * running a dd if= /dev/rfd0c. so it *is* possible for this to happen. 3748 * we need to do a ctlr reset ... 3749 */ 3750 3751 if (Msr(fdc) & CB) { 3752 /* tried to give command to chip when it is busy! */ 3753 FDERRPRINT(FDEP_L3, FDEM_EXEC, 3754 (C, "fdc: unexpectedly busy-stat 0x%x\n", Msr(fdc))); 3755 csb->csb_cmdstat = 1; /* XXX TBD ERRS NYD for now */ 3756 3757 (void) fd_unbind_handle(fdc); 3758 return (EBUSY); 3759 } 3760 3761 /* Give command to the controller */ 3762 for (i = 0; i < (int)csb->csb_ncmds; i++) { 3763 3764 /* Test the readiness of the controller to receive the cmd */ 3765 for (to = FD_CRETRY; to; to--) { 3766 if ((Msr(fdc) & (DIO|RQM)) == RQM) 3767 break; 3768 } 3769 if (to == 0) { 3770 FDERRPRINT(FDEP_L2, FDEM_EXEC, 3771 (C, "fdc: no RQM - stat 0x%x\n", Msr(fdc))); 3772 csb->csb_cmdstat = 1; 3773 3774 (void) fd_unbind_handle(fdc); 3775 return (EIO); 3776 } 3777 3778 Set_Fifo(fdc, csb->csb_cmds[i]); 3779 3780 FDERRPRINT(FDEP_L1, FDEM_EXEC, 3781 (C, "fdexec: sent 0x%x, Msr 0x%x\n", csb->csb_cmds[i], 3782 Msr(fdc))); 3783 3784 } 3785 3786 3787 /* 3788 * Start watchdog timer on data transfer type commands - required 3789 * in case a diskette is not present or is unformatted 3790 */ 3791 if (csb->csb_opflags & CSB_OFTIMEIT) { 3792 fdc->c_timeid = timeout(fdwatch, a, 3793 tosec * drv_usectohz(1000000)); 3794 } 3795 3796 FDERRPRINT(FDEP_L1, FDEM_EXEC, 3797 (C, "fdexec: cmd sent, Msr 0x%x\n", Msr(fdc))); 3798 3799 /* If the operation has no results - then just return */ 3800 if (csb->csb_opflags & CSB_OFNORESULTS) { 3801 if (fdc->c_fdtype & FDCTYPE_82077) { 3802 if (fdc->c_mtimeid == 0) { 3803 fdc->c_mtimeid = timeout(fdmotoff, a, 3804 Motoff_delay); 3805 } 3806 } 3807 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: O K ..\n")); 3808 3809 /* 3810 * Make sure the last byte is received well by the 3811 * controller. On faster CPU, it may still be busy 3812 * by the time another command comes here. 3813 */ 3814 for (to = FD_CRETRY; to; to--) { 3815 if ((Msr(fdc) & (DIO|RQM)) == RQM) 3816 break; 3817 } 3818 if (to == 0) { 3819 csb->csb_cmdstat = 1; 3820 return (EIO); 3821 } 3822 3823 /* 3824 * An operation that has no results isn't doing DMA so, 3825 * there is no reason to try to unbind a handle 3826 */ 3827 return (0); 3828 } 3829 3830 /* 3831 * If this operation has no interrupt AND an immediate result 3832 * then we just busy wait for the results and stuff them into 3833 * the csb 3834 */ 3835 if (csb->csb_opflags & CSB_OFIMMEDIATE) { 3836 to = FD_RRETRY; 3837 csb->csb_nrslts = 0; 3838 /* 3839 * Wait while this command is still going on. 3840 */ 3841 while ((tmp = Msr(fdc)) & CB) { 3842 /* 3843 * If RQM + DIO, then a result byte is at hand. 3844 */ 3845 if ((tmp & (RQM|DIO|CB)) == (RQM|DIO|CB)) { 3846 csb->csb_rslt[csb->csb_nrslts++] = 3847 Fifo(fdc); 3848 /* 3849 * FDERRPRINT(FDEP_L4, FDEM_EXEC, 3850 * (C, "fdexec: got result 0x%x\n", 3851 * csb->csb_nrslts)); 3852 */ 3853 } else if (--to == 0) { 3854 FDERRPRINT(FDEP_L4, FDEM_EXEC, 3855 (C, "fdexec: timeout, Msr%x, nr%x\n", 3856 Msr(fdc), csb->csb_nrslts)); 3857 3858 csb->csb_status = 2; 3859 if (fdc->c_fdtype & FDCTYPE_82077) { 3860 if (fdc->c_mtimeid == 0) { 3861 fdc->c_mtimeid = timeout( 3862 fdmotoff, a, Motoff_delay); 3863 } 3864 } 3865 /* 3866 * There is no DMA happening. No need to 3867 * try freeing a handle. 3868 */ 3869 3870 return (EIO); 3871 } 3872 } 3873 } 3874 3875 /* 3876 * If told to sleep here, well then sleep! 3877 */ 3878 3879 if (flags & FDXC_SLEEP) { 3880 fdc->c_flags |= FDCFLG_WAITING; 3881 while (fdc->c_flags & FDCFLG_WAITING) { 3882 cv_wait(&fdc->c_iocv, &fdc->c_lolock); 3883 } 3884 } 3885 3886 /* 3887 * kludge for end-of-cylinder error which must be ignored!!! 3888 */ 3889 3890 if ((fdc->c_fdtype & FDCTYPE_TCBUG) && 3891 ((csb->csb_rslt[0] & IC_SR0) == 0x40) && 3892 (csb->csb_rslt[1] & EN_SR1)) 3893 csb->csb_rslt[0] &= ~IC_SR0; 3894 3895 /* 3896 * See if there was an error detected, if so, fdrecover() 3897 * will check it out and say what to do. 3898 * 3899 * Don't do this, though, if this was the Sense Drive Status 3900 * or the Dump Registers command. 3901 */ 3902 if (((csb->csb_rslt[0] & IC_SR0) || (fdc->c_csb.csb_dcsr_rslt) || 3903 (csb->csb_status)) && 3904 ((csb->csb_cmds[0] != FDRAW_SENSE_DRV) && 3905 (csb->csb_cmds[0] != DUMPREG))) { 3906 /* if it can restarted OK, then do so, else return error */ 3907 if (fdrecover(fdc) != 0) { 3908 if (fdc->c_fdtype & FDCTYPE_82077) { 3909 if (fdc->c_mtimeid == 0) { 3910 fdc->c_mtimeid = timeout(fdmotoff, 3911 a, Motoff_delay); 3912 } 3913 } 3914 3915 /* 3916 * If this was a dma transfer, unbind the handle so 3917 * that other transfers may use it. 3918 */ 3919 3920 (void) fd_unbind_handle(fdc); 3921 return (EIO); 3922 } else { 3923 /* ASSUMES that cmd is still intact in csb */ 3924 goto retry; 3925 } 3926 } 3927 3928 /* things went ok */ 3929 if (fdc->c_fdtype & FDCTYPE_82077) { 3930 if (fdc->c_mtimeid == 0) { 3931 fdc->c_mtimeid = timeout(fdmotoff, a, Motoff_delay); 3932 } 3933 } 3934 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "fdexec: O K ..........\n")); 3935 3936 if (fd_unbind_handle(fdc)) 3937 return (EIO); 3938 3939 return (0); 3940 } 3941 3942 /* 3943 * Turn on the drive's motor 3944 * 3945 * - called with the low level lock held 3946 */ 3947 static void 3948 fdexec_turn_on_motor(struct fdctlr *fdc, int flags, uint_t unit) 3949 { 3950 clock_t local_lbolt; 3951 timeout_id_t timeid; 3952 3953 /* 3954 * The low level mutex may not be held over the call to 3955 * untimeout(). See the manpage for details. 3956 */ 3957 timeid = fdc->c_mtimeid; 3958 fdc->c_mtimeid = 0; 3959 if (timeid) { 3960 mutex_exit(&fdc->c_lolock); 3961 (void) untimeout(timeid); 3962 mutex_enter(&fdc->c_lolock); 3963 } 3964 3965 ASSERT(fdc->c_un->un_unit_no == unit); 3966 3967 3968 set_rotational_speed(fdc, unit); 3969 3970 if (!(Dor(fdc) & (MOTEN(unit)))) { 3971 /* 3972 * Turn on the motor 3973 */ 3974 FDERRPRINT(FDEP_L1, FDEM_EXEC, 3975 (C, "fdexec: turning on motor\n")); 3976 3977 /* LINTED */ 3978 Set_dor(fdc, (MOTEN(unit)), 1); 3979 3980 if (flags & FDXC_SLEEP) { 3981 local_lbolt = ddi_get_lbolt(); 3982 (void) cv_timedwait(&fdc->c_motoncv, 3983 &fdc->c_lolock, local_lbolt + Moton_delay); 3984 } else { 3985 drv_usecwait(1000000); 3986 } 3987 } 3988 3989 } 3990 3991 /* 3992 * fdrecover 3993 * see if possible to retry an operation. 3994 * All we can do is restart the operation. If we are out of allowed 3995 * retries - return non-zero so that the higher levels will be notified. 3996 * 3997 * RETURNS: 0 if ok to restart, !0 if can't or out of retries 3998 * - called with the low level lock held 3999 */ 4000 static int 4001 fdrecover(struct fdctlr *fdc) 4002 { 4003 struct fdcsb *csb; 4004 4005 FDERRPRINT(FDEP_L1, FDEM_RECO, (C, "fdrecover\n")); 4006 csb = &fdc->c_csb; 4007 4008 if (fdc->c_flags & FDCFLG_TIMEDOUT) { 4009 struct fdcsb savecsb; 4010 4011 fdc->c_flags ^= FDCFLG_TIMEDOUT; 4012 csb->csb_rslt[1] |= TO_SR1; 4013 FDERRPRINT(FDEP_L1, FDEM_RECO, 4014 (C, "fd%d: %s timed out\n", csb->csb_unit, 4015 fdcmds[csb->csb_cmds[0] & 0x1f].cmdname)); 4016 4017 /* use private csb */ 4018 savecsb = fdc->c_csb; 4019 bzero(&fdc->c_csb, sizeof (struct fdcsb)); 4020 FDERRPRINT(FDEP_L1, FDEM_RECO, (C, "fdc: resetting\n")); 4021 4022 (void) fdreset(fdc); 4023 4024 if (fdc->c_fdtype & FDCTYPE_DMA) { 4025 mutex_enter(&fdc->c_hilock); 4026 /* Reset the DMA engine as well */ 4027 reset_dma_controller(fdc); 4028 set_dma_control_register(fdc, DCSR_INIT_BITS); 4029 mutex_exit(&fdc->c_hilock); 4030 } 4031 4032 4033 /* check change first?? */ 4034 /* don't ckchg in fdexec, too convoluted */ 4035 (void) fdrecalseek(fdc, savecsb.csb_unit, -1, 0); 4036 fdc->c_csb = savecsb; /* restore original csb */ 4037 } 4038 4039 /* 4040 * gather statistics on errors 4041 */ 4042 if (csb->csb_rslt[1] & DE_SR1) { 4043 fdc->fdstats.de++; 4044 } 4045 if (csb->csb_rslt[1] & OR_SR1) { 4046 fdc->fdstats.run++; 4047 } 4048 if (csb->csb_rslt[1] & (ND_SR1+MA_SR1)) { 4049 fdc->fdstats.bfmt++; 4050 } 4051 if (csb->csb_rslt[1] & TO_SR1) { 4052 fdc->fdstats.to++; 4053 } 4054 4055 /* 4056 * If raw ioctl don't examine results just pass status 4057 * back via fdraw. Raw commands are timed too, so put this 4058 * after the above check. 4059 */ 4060 if (csb->csb_opflags & CSB_OFRAWIOCTL) { 4061 return (1); 4062 } 4063 4064 4065 /* 4066 * if there was a pci bus error, do not retry 4067 */ 4068 4069 if (csb->csb_dcsr_rslt == 1) { 4070 FDERRPRINT(FDEP_L3, FDEM_RECO, 4071 (C, "fd%d: host bus error\n", 0)); 4072 return (1); 4073 } 4074 4075 /* 4076 * If there was an error with the DMA functions, do not retry 4077 */ 4078 if (csb->csb_dma_rslt == 1) { 4079 FDERRPRINT(FDEP_L1, FDEM_RECO, 4080 (C, "fd%d: DMA interface error\n", csb->csb_unit)); 4081 return (1); 4082 } 4083 4084 4085 /* 4086 * if we have run out of retries, return an error 4087 * XXX need better status interp 4088 */ 4089 4090 csb->csb_retrys++; 4091 if (csb->csb_retrys > csb->csb_maxretry) { 4092 FDERRPRINT(FDEP_L3, FDEM_RECO, 4093 (C, "fd%d: %s failed (%x %x %x)\n", 4094 0, fdcmds[csb->csb_cmds[0] & 0x1f].cmdname, 4095 csb->csb_rslt[0], csb->csb_rslt[1], csb->csb_rslt[2])); 4096 if (csb->csb_rslt[1] & NW_SR1) { 4097 FDERRPRINT(FDEP_L3, FDEM_RECO, 4098 (C, "fd%d: not writable\n", 0)); 4099 } 4100 if (csb->csb_rslt[1] & DE_SR1) { 4101 FDERRPRINT(FDEP_L3, FDEM_RECO, 4102 (C, "fd%d: crc error blk %d\n", 0, 4103 (int)fdc->c_current->b_blkno)); 4104 } 4105 if (csb->csb_rslt[1] & OR_SR1) { 4106 if (fdc->c_fdtype & FDCTYPE_SB) { 4107 /* 4108 * When using southbridge chip we need to 4109 * retry atleast 10 times to shake off the 4110 * underrun err. 4111 */ 4112 if (csb->csb_retrys <= rwretry) 4113 return (0); 4114 } 4115 FDERRPRINT(FDEP_L3, FDEM_RECO, 4116 (C, "fd%d: over/underrun\n", 0)); 4117 } 4118 4119 if (csb->csb_rslt[1] & (ND_SR1+MA_SR1)) { 4120 FDERRPRINT(FDEP_L3, FDEM_RECO, 4121 (C, "fd%d: bad format\n", 0)); 4122 } 4123 4124 if (csb->csb_rslt[1] & TO_SR1) { 4125 FDERRPRINT(FDEP_L3, FDEM_RECO, 4126 (C, "fd%d: timeout\n", 0)); 4127 } 4128 4129 csb->csb_cmdstat = 1; /* failed - give up */ 4130 return (1); 4131 } 4132 4133 if (csb->csb_opflags & CSB_OFSEEKOPS) { 4134 /* seek, recal type commands - just look at st0 */ 4135 FDERRPRINT(FDEP_L2, FDEM_RECO, 4136 (C, "fd%d: %s error : st0 0x%x\n", csb->csb_unit, 4137 fdcmds[csb->csb_cmds[0] & 0x1f].cmdname, 4138 csb->csb_rslt[0])); 4139 } 4140 if (csb->csb_opflags & CSB_OFXFEROPS) { 4141 /* rd, wr, fmt type commands - look at st0, st1, st2 */ 4142 FDERRPRINT(FDEP_L2, FDEM_RECO, 4143 (C, "fd%d: %s error : st0=0x%x st1=0x%x st2=0x%x\n", 4144 csb->csb_unit, fdcmds[csb->csb_cmds[0] & 0x1f].cmdname, 4145 csb->csb_rslt[0], csb->csb_rslt[1], csb->csb_rslt[2])); 4146 } 4147 4148 return (0); /* tell fdexec to retry */ 4149 } 4150 4151 /* 4152 * Interrupt handle for DMA 4153 */ 4154 4155 static uint_t 4156 fdintr_dma() 4157 { 4158 struct fdctlr *fdc; 4159 off_t off; 4160 size_t len; 4161 uint_t ccount; 4162 uint_t windex; 4163 uint_t done = 0; 4164 int tmp_dcsr; 4165 int to; 4166 uchar_t tmp; 4167 int i = 0; 4168 int res = DDI_INTR_UNCLAIMED; 4169 int not_cheerio = 1; 4170 4171 /* search for a controller that's expecting an interrupt */ 4172 fdc = fdctlrs; 4173 4174 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 4175 tmp_dcsr = get_dma_control_register(fdc); 4176 if (!(tmp_dcsr & DCSR_INT_PEND) && !(DCSR_ERR_PEND & tmp_dcsr)) 4177 return (res); 4178 not_cheerio = 0; 4179 } 4180 4181 mutex_enter(&fdc->c_hilock); 4182 4183 if (fdc->c_csb.csb_opmode == 0x0) { 4184 fdc->c_csb.csb_opmode = 2; 4185 } 4186 if (fdc->sb_dma_lock) { 4187 release_sb_dma(fdc); 4188 } 4189 4190 /* 4191 * An interrupt can come from either the floppy controller or 4192 * or the DMA engine. The DMA engine will only issue an 4193 * interrupt if there was an error. 4194 */ 4195 4196 switch (fdc->c_csb.csb_opmode) { 4197 case 0x1: 4198 /* read/write/format data-xfer case */ 4199 4200 FDERRPRINT(FDEP_L1, FDEM_INTR, 4201 (C, "fdintr_dma: opmode 1\n")); 4202 4203 /* 4204 * See if the interrupt is from the floppy 4205 * controller. If there is, take out the status bytes. 4206 */ 4207 4208 if (not_cheerio || (tmp_dcsr & DCSR_INT_PEND)) { 4209 4210 FDERRPRINT(FDEP_L1, FDEM_INTR, 4211 (C, "fdintr_dma: INT_PEND \n")); 4212 4213 res = DDI_INTR_CLAIMED; 4214 4215 to = FD_RRETRY; 4216 fdc->c_csb.csb_nrslts = 0; 4217 4218 /* check status */ 4219 i = 0; 4220 4221 /* 4222 * CB turns off once all the result bytes are 4223 * read. 4224 * 4225 * NOTE: the counters are there so that the 4226 * handler will never get stuck in a loop. 4227 * If the counters do reach their maximum 4228 * values, then a catastrophic error has 4229 * occurred. This should never be the case. 4230 * The counters only came into play during 4231 * development. 4232 */ 4233 while (((tmp = Msr(fdc)) & CB) && 4234 (i < 1000001)) { 4235 4236 /* 4237 * If RQM + DIO, then a result byte 4238 * is at hand. 4239 */ 4240 if ((tmp & (RQM|DIO|CB)) == 4241 (RQM|DIO|CB)) { 4242 fdc->c_csb.csb_rslt 4243 [fdc->c_csb.csb_nrslts++] 4244 = Fifo(fdc); 4245 4246 FDERRPRINT(FDEP_L1, FDEM_INTR, 4247 (C, "fdintr_dma: res 0x%x\n", 4248 fdc->c_csb.csb_rslt 4249 [fdc->c_csb.csb_nrslts 4250 - 1])); 4251 4252 } else if (--to == 0) { 4253 /* 4254 * controller was never 4255 * ready to give results 4256 */ 4257 fdc->c_csb.csb_status = 2; 4258 break; 4259 } 4260 i++; 4261 } 4262 if (i == 10000) { 4263 FDERRPRINT(FDEP_L1, FDEM_INTR, 4264 (C, "First loop overran\n")); 4265 } 4266 } 4267 4268 /* 4269 * See if the interrupt is from the DMA engine, 4270 * which will only interrupt on an error 4271 */ 4272 if ((!not_cheerio) && (tmp_dcsr & DCSR_ERR_PEND)) { 4273 4274 res = DDI_INTR_CLAIMED; 4275 4276 done = 1; 4277 fdc->c_csb.csb_dcsr_rslt = 1; 4278 FDERRPRINT(FDEP_L1, FDEM_INTR, 4279 (C, "fdintr_dma: Error pending\n")); 4280 reset_dma_controller(fdc); 4281 set_dma_control_register(fdc, DCSR_INIT_BITS); 4282 break; 4283 } 4284 4285 /* TCBUG kludge */ 4286 if ((fdc->c_fdtype & FDCTYPE_TCBUG) && 4287 ((fdc->c_csb.csb_rslt[0] & IC_SR0) == 0x40) && 4288 (fdc->c_csb.csb_rslt[1] & EN_SR1)) { 4289 4290 fdc->c_csb.csb_rslt[0] &= ~IC_SR0; 4291 4292 fdc->c_csb.csb_rslt[1] &= ~EN_SR1; 4293 4294 4295 } 4296 4297 4298 /* Exit if there were errors in the DMA */ 4299 if (((fdc->c_csb.csb_rslt[0] & IC_SR0) != 0) || 4300 (fdc->c_csb.csb_rslt[1] != 0) || 4301 (fdc->c_csb.csb_rslt[2] != 0)) { 4302 done = 1; 4303 FDERRPRINT(FDEP_L1, FDEM_INTR, 4304 (C, "fdintr_dma: errors in command\n")); 4305 4306 4307 break; 4308 } 4309 4310 4311 FDERRPRINT(FDEP_L1, FDEM_INTR, 4312 (C, "fdintr_dma: dbcr 0x%x\n", 4313 get_data_count_register(fdc))); 4314 /* 4315 * The csb_ccount is the number of cookies that still 4316 * need to be processed. A cookie was just processed 4317 * so decrement the cookie counter. 4318 */ 4319 if (fdc->c_csb.csb_ccount == 0) { 4320 done = 1; 4321 break; 4322 } 4323 fdc->c_csb.csb_ccount--; 4324 ccount = fdc->c_csb.csb_ccount; 4325 4326 windex = fdc->c_csb.csb_windex; 4327 4328 /* 4329 * If there are no more cookies and all the windows 4330 * have been DMA'd, then DMA is done. 4331 * 4332 */ 4333 if ((ccount == 0) && (windex == fdc->c_csb.csb_nwin)) { 4334 4335 done = 1; 4336 4337 /* 4338 * The handle is unbound in fdexec 4339 */ 4340 4341 break; 4342 } 4343 4344 if (ccount != 0) { 4345 /* process the next cookie */ 4346 ddi_dma_nextcookie(fdc->c_dmahandle, 4347 &fdc->c_csb.csb_dmacookie); 4348 4349 FDERRPRINT(FDEP_L1, FDEM_INTR, 4350 (C, "cookie addr 0x%" PRIx64 "\n", 4351 fdc->c_csb.csb_dmacookie.dmac_laddress)); 4352 4353 FDERRPRINT(FDEP_L1, FDEM_INTR, 4354 (C, "cookie length %lu\n", 4355 fdc->c_csb.csb_dmacookie.dmac_size)); 4356 4357 } else { 4358 4359 (void) ddi_dma_getwin(fdc->c_dmahandle, 4360 fdc->c_csb.csb_windex, 4361 &off, &len, 4362 &fdc->c_csb.csb_dmacookie, 4363 &fdc->c_csb.csb_ccount); 4364 fdc->c_csb.csb_windex++; 4365 4366 FDERRPRINT(FDEP_L1, FDEM_INTR, 4367 (C, "fdintr_dma: process %d window\n", 4368 fdc->c_csb.csb_windex)); 4369 4370 FDERRPRINT(FDEP_L1, FDEM_INTR, 4371 (C, "fdintr_dma: process no. cookies %d\n", 4372 fdc->c_csb.csb_ccount)); 4373 4374 FDERRPRINT(FDEP_L1, FDEM_INTR, 4375 (C, "cookie addr 0x%" PRIx64 "\n", 4376 fdc->c_csb.csb_dmacookie.dmac_laddress)); 4377 4378 FDERRPRINT(FDEP_L1, FDEM_INTR, 4379 (C, "cookie length %lu\n", 4380 fdc->c_csb.csb_dmacookie.dmac_size)); 4381 } 4382 4383 /* 4384 * Program the DMA engine with the length and 4385 * the address of the transfer 4386 */ 4387 4388 ASSERT(fdc->c_csb.csb_dmacookie.dmac_size); 4389 4390 set_data_count_register(fdc, 4391 fdc->c_csb.csb_dmacookie.dmac_size); 4392 set_data_address_register(fdc, 4393 fdc->c_csb.csb_dmacookie.dmac_laddress); 4394 4395 FDERRPRINT(FDEP_L1, FDEM_INTR, (C, 4396 "fdintr_dma: size 0x%lx\n", 4397 fdc->c_csb.csb_dmacookie.dmac_size)); 4398 4399 4400 /* reprogram the controller */ 4401 fdc->c_csb.csb_cmds[2] = fdc->c_csb.csb_rslt[3]; 4402 fdc->c_csb.csb_cmds[3] = fdc->c_csb.csb_rslt[4]; 4403 fdc->c_csb.csb_cmds[4] = fdc->c_csb.csb_rslt[5]; 4404 fdc->c_csb.csb_cmds[1] = (fdc->c_csb.csb_cmds[1] 4405 & ~0x04) | (fdc->c_csb.csb_rslt[4] << 2); 4406 4407 for (i = 0; i < (int)fdc->c_csb.csb_ncmds; i++) { 4408 4409 /* 4410 * Test the readiness of the controller 4411 * to receive the cmd 4412 */ 4413 for (to = FD_CRETRY; to; to--) { 4414 if ((Msr(fdc) & (DIO|RQM)) == RQM) 4415 break; 4416 } 4417 if (to == 0) { 4418 FDERRPRINT(FDEP_L2, FDEM_EXEC, 4419 (C, 4420 "fdc: no RQM - stat 0x%x\n", Msr(fdc))); 4421 /* stop the DMA from happening */ 4422 fdc->c_csb.csb_status = 2; 4423 done = 1; 4424 break; 4425 } 4426 4427 Set_Fifo(fdc, fdc->c_csb.csb_cmds[i]); 4428 4429 FDERRPRINT(FDEP_L1, FDEM_INTR, 4430 (C, 4431 "fdintr_dma: sent 0x%x, Msr 0x%x\n", 4432 fdc->c_csb.csb_cmds[i], Msr(fdc))); 4433 } 4434 4435 /* reenable DMA */ 4436 if ((!not_cheerio) && (!done)) 4437 set_dma_control_register(fdc, tmp_dcsr | 4438 DCSR_EN_DMA); 4439 break; 4440 4441 case 0x2: 4442 /* seek/recal type cmd */ 4443 FDERRPRINT(FDEP_L1, FDEM_INTR, 4444 (C, "fintr_dma: opmode 2\n")); 4445 4446 /* 4447 * See if the interrupt is from the DMA engine, 4448 * which will only interrupt if there was an error. 4449 */ 4450 if ((!not_cheerio) && (tmp_dcsr & DCSR_ERR_PEND)) { 4451 res = DDI_INTR_CLAIMED; 4452 done = 1; 4453 fdc->c_csb.csb_dcsr_rslt = 1; 4454 reset_dma_controller(fdc); 4455 set_dma_control_register(fdc, DCSR_INIT_BITS); 4456 4457 break; 4458 } 4459 4460 4461 /* See if the interrupt is from the floppy controller */ 4462 if (not_cheerio || (tmp_dcsr & DCSR_INT_PEND)) { 4463 4464 res = DDI_INTR_CLAIMED; 4465 4466 4467 /* 4468 * Wait until there's no longer a command 4469 * in progress 4470 */ 4471 4472 FDERRPRINT(FDEP_L1, FDEM_INTR, 4473 (C, "fdintr_dma: interrupt pending\n")); 4474 i = 0; 4475 while (((Msr(fdc) & CB)) && (i < 10000)) { 4476 i++; 4477 } 4478 4479 if (i == 10000) 4480 FDERRPRINT(FDEP_L1, FDEM_INTR, 4481 (C, "2nd loop overran !!!\n")); 4482 4483 /* 4484 * Check the RQM bit to see if the controller is 4485 * ready to transfer status of the command. 4486 */ 4487 i = 0; 4488 while ((!(Msr(fdc) & RQM)) && (i < 10000)) { 4489 i++; 4490 } 4491 4492 if (i == 10000) 4493 FDERRPRINT(FDEP_L1, FDEM_INTR, 4494 (C, "3rd loop overran !!!\n")); 4495 4496 /* 4497 * Issue the Sense Interrupt Status Command 4498 */ 4499 Set_Fifo(fdc, SNSISTAT); 4500 4501 i = 0; 4502 while ((!(Msr(fdc) & RQM)) && (i < 10000)) { 4503 i++; 4504 } 4505 if (i == 10000) 4506 FDERRPRINT(FDEP_L1, FDEM_INTR, 4507 (C, "4th loop overran !!!\n")); 4508 4509 /* Store the first result byte */ 4510 fdc->c_csb.csb_rslt[0] = Fifo(fdc); 4511 4512 i = 0; 4513 while ((!(Msr(fdc) & RQM)) && (i < 10000)) { 4514 i++; 4515 } 4516 if (i == 10000) 4517 FDERRPRINT(FDEP_L1, FDEM_INTR, 4518 (C, "5th loop overran !!!\n")); 4519 4520 /* Store the second result byte */ 4521 fdc->c_csb.csb_rslt[1] = Fifo(fdc); 4522 4523 done = 1; 4524 } 4525 4526 } 4527 4528 /* 4529 * We are done with the actual interrupt handling here. 4530 * The portion below should be actually be done by fd_lointr(). 4531 * We should be triggering the fd_lointr here and exiting. 4532 * However for want of time this will be done in the next FIX. 4533 * 4534 * Hence for now we will release hilock only and keep the remaining 4535 * code as it is. 4536 * Releasing of hilock ensures that we don't hold on to the 4537 * lolock and hilock at the same time. 4538 * hilock is acquired each time dma related registers are accessed. 4539 */ 4540 mutex_exit(&fdc->c_hilock); 4541 /* Make signal and get out of interrupt handler */ 4542 if (done) { 4543 mutex_enter(&fdc->c_lolock); 4544 4545 fdc->c_csb.csb_opmode = 0; 4546 4547 /* reset watchdog timer if armed and not already triggered */ 4548 4549 4550 if (fdc->c_timeid) { 4551 timeout_id_t timeid = fdc->c_timeid; 4552 fdc->c_timeid = 0; 4553 mutex_exit(&fdc->c_lolock); 4554 (void) untimeout(timeid); 4555 mutex_enter(&fdc->c_lolock); 4556 } 4557 4558 4559 if (fdc->c_flags & FDCFLG_WAITING) { 4560 /* 4561 * somebody's waiting on finish of fdctlr/csb, 4562 * wake them 4563 */ 4564 4565 FDERRPRINT(FDEP_L1, FDEM_INTR, 4566 (C, "fdintr_dma: signal the waiter\n")); 4567 4568 fdc->c_flags ^= FDCFLG_WAITING; 4569 cv_signal(&fdc->c_iocv); 4570 4571 /* 4572 * FDCFLG_BUSY is NOT cleared, NOR is the csb given 4573 * back; the operation just finished can look at the csb 4574 */ 4575 } else { 4576 FDERRPRINT(FDEP_L1, FDEM_INTR, 4577 (C, "fdintr_dma: nobody sleeping (%x %x %x)\n", 4578 fdc->c_csb.csb_rslt[0], fdc->c_csb.csb_rslt[1], 4579 fdc->c_csb.csb_rslt[2])); 4580 } 4581 mutex_exit(&fdc->c_lolock); 4582 } 4583 /* update high level interrupt counter */ 4584 if (fdc->c_intrstat) 4585 KIOIP->intrs[KSTAT_INTR_HARD]++; 4586 4587 4588 FDERRPRINT(FDEP_L1, FDEM_INTR, (C, "fdintr_dma: done\n")); 4589 return (res); 4590 } 4591 4592 /* 4593 * fd_lointr 4594 * This is the low level SW interrupt handler triggered by the high 4595 * level interrupt handler (or by fdwatch). 4596 */ 4597 static uint_t 4598 fd_lointr(caddr_t arg) 4599 { 4600 struct fdctlr *fdc = (struct fdctlr *)arg; 4601 struct fdcsb *csb; 4602 4603 csb = &fdc->c_csb; 4604 FDERRPRINT(FDEP_L1, FDEM_INTR, (C, "fdintr: opmode %d\n", 4605 csb->csb_opmode)); 4606 /* 4607 * Check that lowlevel interrupt really meant to trigger us. 4608 */ 4609 if (csb->csb_opmode != 4) { 4610 /* 4611 * This should probably be protected, but, what the 4612 * heck...the cost isn't worth the accuracy for this 4613 * statistic. 4614 */ 4615 if (fdc->c_intrstat) 4616 KIOIP->intrs[KSTAT_INTR_SPURIOUS]++; 4617 return (DDI_INTR_UNCLAIMED); 4618 } 4619 4620 mutex_enter(&fdc->c_lolock); 4621 csb->csb_opmode = 0; 4622 4623 /* reset watchdog timer if armed and not already triggered */ 4624 if (fdc->c_timeid) { 4625 timeout_id_t timeid = fdc->c_timeid; 4626 fdc->c_timeid = 0; 4627 mutex_exit(&fdc->c_lolock); 4628 (void) untimeout(timeid); 4629 mutex_enter(&fdc->c_lolock); 4630 4631 } 4632 4633 if (fdc->c_flags & FDCFLG_WAITING) { 4634 /* 4635 * somebody's waiting on finish of fdctlr/csb, wake them 4636 */ 4637 fdc->c_flags ^= FDCFLG_WAITING; 4638 cv_signal(&fdc->c_iocv); 4639 4640 /* 4641 * FDCFLG_BUSY is NOT cleared, NOR is the csb given back; so 4642 * the operation just finished can look at the csb 4643 */ 4644 } else { 4645 FDERRPRINT(FDEP_L3, FDEM_INTR, 4646 (C, "fdintr: nobody sleeping (%x %x %x)\n", 4647 csb->csb_rslt[0], csb->csb_rslt[1], csb->csb_rslt[2])); 4648 } 4649 if (fdc->c_intrstat) 4650 KIOIP->intrs[KSTAT_INTR_SOFT]++; 4651 mutex_exit(&fdc->c_lolock); 4652 return (DDI_INTR_CLAIMED); 4653 } 4654 4655 /* 4656 * fdwatch 4657 * is called from timein() when a floppy operation has expired. 4658 */ 4659 static void 4660 fdwatch(void *arg) 4661 { 4662 struct fdctlr *fdc = arg; 4663 int old_opmode; 4664 struct fdcsb *csb; 4665 4666 FDERRPRINT(FDEP_L1, FDEM_WATC, (C, "fdwatch\n")); 4667 4668 mutex_enter(&fdc->c_lolock); 4669 if (fdc->c_timeid == 0) { 4670 /* 4671 * fdintr got here first, ergo, no timeout condition.. 4672 */ 4673 4674 FDERRPRINT(FDEP_L1, FDEM_WATC, 4675 (C, "fdwatch: no timeout\n")); 4676 4677 mutex_exit(&fdc->c_lolock); 4678 return; 4679 } 4680 fdc->c_timeid = 0; 4681 csb = &fdc->c_csb; 4682 4683 mutex_enter(&fdc->c_hilock); 4684 /* 4685 * XXXX: We should probably reset the bloody chip 4686 */ 4687 old_opmode = csb->csb_opmode; 4688 4689 FDERRPRINT(FDEP_L1, FDEM_WATC, 4690 (C, "fd%d: timeout, opmode:%d\n", csb->csb_unit, old_opmode)); 4691 4692 csb->csb_opmode = 4; 4693 mutex_exit(&fdc->c_hilock); 4694 4695 FDERRPRINT(FDEP_L1, FDEM_WATC, (C, "fdwatch: cmd %s timed out\n", 4696 fdcmds[csb->csb_cmds[0] & 0x1f].cmdname)); 4697 fdc->c_flags |= FDCFLG_TIMEDOUT; 4698 csb->csb_status = CSB_CMDTO; 4699 4700 if ((fdc->c_fdtype & FDCTYPE_DMA) == 0) { 4701 ddi_trigger_softintr(fdc->c_softid); 4702 KIOIP->intrs[KSTAT_INTR_WATCHDOG]++; 4703 mutex_exit(&fdc->c_lolock); 4704 } else { 4705 mutex_exit(&fdc->c_lolock); 4706 (void) fd_lointr((caddr_t)fdctlrs); 4707 } 4708 } 4709 4710 /* 4711 * fdgetcsb 4712 * wait until the csb is free 4713 */ 4714 static void 4715 fdgetcsb(struct fdctlr *fdc) 4716 { 4717 FDERRPRINT(FDEP_L1, FDEM_GETC, (C, "fdgetcsb\n")); 4718 ASSERT(mutex_owned(&fdc->c_lolock)); 4719 while (fdc->c_flags & FDCFLG_BUSY) { 4720 fdc->c_flags |= FDCFLG_WANT; 4721 cv_wait(&fdc->c_csbcv, &fdc->c_lolock); 4722 } 4723 fdc->c_flags |= FDCFLG_BUSY; /* got it! */ 4724 } 4725 4726 /* 4727 * fdretcsb 4728 * return csb 4729 */ 4730 static void 4731 fdretcsb(struct fdctlr *fdc) 4732 { 4733 4734 ASSERT(mutex_owned(&fdc->c_lolock)); 4735 FDERRPRINT(FDEP_L1, FDEM_RETC, (C, "fdretcsb\n")); 4736 fdc->c_flags &= ~FDCFLG_BUSY; /* let go */ 4737 4738 fdc->c_csb.csb_read = 0; 4739 4740 if (fdc->c_flags & FDCFLG_WANT) { 4741 fdc->c_flags ^= FDCFLG_WANT; 4742 /* 4743 * broadcast the signal. One thread will wake up and 4744 * set the flags to FDCFLG_BUSY. If more than one thread is 4745 * waiting then each thread will wake up in turn. The first 4746 * thread to wake-up will set the FDCFLG_BUSY flag and the 4747 * subsequent threads will will wake-up, but reset the 4748 * flag to FDCFLG_WANT because the FDCFLG_BUSY bit is set. 4749 */ 4750 cv_broadcast(&fdc->c_csbcv); 4751 } 4752 } 4753 4754 4755 /* 4756 * fdreset 4757 * reset THE controller, and configure it to be 4758 * the way it ought to be 4759 * ASSUMES: that it already owns the csb/fdctlr! 4760 * 4761 * - called with the low level lock held 4762 */ 4763 static int 4764 fdreset(struct fdctlr *fdc) 4765 { 4766 struct fdcsb *csb; 4767 clock_t local_lbolt = 0; 4768 timeout_id_t timeid; 4769 4770 FDERRPRINT(FDEP_L1, FDEM_RESE, (C, "fdreset\n")); 4771 4772 ASSERT(mutex_owned(&fdc->c_lolock)); 4773 4774 /* count resets */ 4775 fdc->fdstats.reset++; 4776 4777 /* 4778 * On the 82077, the DSR will clear itself after a reset. Upon exiting 4779 * the reset, a polling interrupt will be generated. If the floppy 4780 * interrupt is enabled, it's possible for cv_signal() to be called 4781 * before cv_wait(). This will cause the system to hang. Turn off 4782 * the floppy interrupt to avoid this race condition 4783 */ 4784 if ((fdc->c_fdtype & FDCTYPE_CTRLMASK) == FDCTYPE_82077) { 4785 /* 4786 * We need to perform any timeouts before we Reset the 4787 * controller. We cannot afford to drop the c_lolock mutex after 4788 * Resetting the controller. The reason is that we get a spate 4789 * of interrupts until we take the controller out of reset. 4790 * The way we avoid this spate of continuous interrupts is by 4791 * holding on to the c_lolock and forcing the fdintr_dma routine 4792 * to go to sleep waiting for this mutex. 4793 */ 4794 /* Do not hold the mutex across the untimeout call */ 4795 timeid = fdc->c_mtimeid; 4796 fdc->c_mtimeid = 0; 4797 if (timeid) { 4798 mutex_exit(&fdc->c_lolock); 4799 (void) untimeout(timeid); 4800 mutex_enter(&fdc->c_lolock); 4801 } 4802 /* LINTED */ 4803 Set_dor(fdc, DMAGATE, 0); 4804 FDERRPRINT(FDEP_L1, FDEM_RESE, (C, "fdreset: set dor\n")); 4805 } 4806 4807 /* toggle software reset */ 4808 Dsr(fdc, SWR); 4809 4810 drv_usecwait(5); 4811 4812 FDERRPRINT(FDEP_L1, FDEM_RESE, 4813 (C, "fdreset: toggled software reset\n")); 4814 4815 /* 4816 * This sets the data rate to 500Kbps (for high density) 4817 * XXX should use current characteristics instead XXX 4818 */ 4819 Dsr(fdc, 0); 4820 drv_usecwait(5); 4821 switch (fdc->c_fdtype & FDCTYPE_CTRLMASK) { 4822 case FDCTYPE_82077: 4823 /* 4824 * when we bring the controller out of reset it will generate 4825 * a polling interrupt. fdintr() will field it and schedule 4826 * fd_lointr(). There will be no one sleeping but we are 4827 * expecting an interrupt so.... 4828 */ 4829 fdc->c_flags |= FDCFLG_WAITING; 4830 4831 /* 4832 * The reset bit must be cleared to take the 077 out of 4833 * reset state and the DMAGATE bit must be high to enable 4834 * interrupts. 4835 */ 4836 /* LINTED */ 4837 Set_dor(fdc, DMAGATE|RESET, 1); 4838 4839 FDERRPRINT(FDEP_L1, FDEM_ATTA, 4840 (C, "fdattach: Dor 0x%x\n", Dor(fdc))); 4841 4842 local_lbolt = ddi_get_lbolt(); 4843 if (cv_timedwait(&fdc->c_iocv, &fdc->c_lolock, 4844 local_lbolt + drv_usectohz(1000000)) == -1) { 4845 return (-1); 4846 } 4847 break; 4848 4849 default: 4850 fdc->c_flags |= FDCFLG_WAITING; 4851 4852 /* 4853 * A timed wait is not used because it's possible for the timer 4854 * to go off before the controller has a chance to interrupt. 4855 */ 4856 cv_wait(&fdc->c_iocv, &fdc->c_lolock); 4857 break; 4858 } 4859 csb = &fdc->c_csb; 4860 4861 /* setup common things in csb */ 4862 csb->csb_unit = fdc->c_un->un_unit_no; 4863 csb->csb_nrslts = 0; 4864 csb->csb_opflags = CSB_OFNORESULTS; 4865 csb->csb_maxretry = 0; 4866 csb->csb_retrys = 0; 4867 4868 csb->csb_read = CSB_NULL; 4869 4870 /* send SPECIFY command to fdc */ 4871 /* csb->unit is don't care */ 4872 csb->csb_cmds[0] = FDRAW_SPECIFY; 4873 csb->csb_cmds[1] = fdspec[0]; /* step rate, head unload time */ 4874 if (fdc->c_fdtype & FDCTYPE_DMA) 4875 csb->csb_cmds[2] = SPEC_DMA_MODE; 4876 else 4877 csb->csb_cmds[2] = fdspec[1]; /* head load time, DMA mode */ 4878 4879 csb->csb_ncmds = 3; 4880 4881 /* XXX for now ignore errors, they "CAN'T HAPPEN" */ 4882 (void) fdexec(fdc, 0); /* no FDXC_CHECKCHG, ... */ 4883 /* no results */ 4884 4885 /* send CONFIGURE command to fdc */ 4886 /* csb->unit is don't care */ 4887 csb->csb_cmds[0] = CONFIGURE; 4888 csb->csb_cmds[1] = fdconf[0]; /* motor info, motor delays */ 4889 csb->csb_cmds[2] = fdconf[1]; /* enaimplsk, disapoll, fifothru */ 4890 csb->csb_cmds[3] = fdconf[2]; /* track precomp */ 4891 csb->csb_ncmds = 4; 4892 4893 csb->csb_read = CSB_NULL; 4894 4895 csb->csb_retrys = 0; 4896 4897 /* XXX for now ignore errors, they "CAN'T HAPPEN" */ 4898 (void) fdexec(fdc, 0); /* no FDXC_CHECKCHG, ... */ 4899 return (0); 4900 } 4901 4902 /* 4903 * fdrecalseek 4904 * performs recalibrates or seeks if the "arg" is -1 does a 4905 * recalibrate on a drive, else it seeks to the cylinder of 4906 * the drive. The recalibrate is also used to find a drive, 4907 * ie if the drive is not there, the controller says "error" 4908 * on the operation 4909 * NOTE: that there is special handling of this operation in the hardware 4910 * interrupt routine - it causes the operation to appear to have results; 4911 * ie the results of the SENSE INTERRUPT STATUS that the hardware interrupt 4912 * function did for us. 4913 * NOTE: because it uses sleep/wakeup it must be protected in a critical 4914 * section so create one before calling it! 4915 * 4916 * RETURNS: 0 for ok, 4917 * else errno from fdexec, 4918 * or ENODEV if error (infers hardware type error) 4919 * 4920 * - called with the low level lock held 4921 */ 4922 static int 4923 fdrecalseek(struct fdctlr *fdc, int unit, int arg, int execflg) 4924 { 4925 struct fdcsb *csb; 4926 int result; 4927 4928 ASSERT(fdc->c_un->un_unit_no == unit); 4929 4930 FDERRPRINT(FDEP_L1, FDEM_RECA, (C, "fdrecalseek to %d\n", arg)); 4931 4932 /* XXX TODO: check see argument for <= num cyls OR < 256 */ 4933 4934 csb = &fdc->c_csb; 4935 csb->csb_unit = (uchar_t)unit; 4936 csb->csb_cmds[1] = unit & 0x03; 4937 4938 if (arg == -1) { /* is recal... */ 4939 csb->csb_cmds[0] = FDRAW_REZERO; 4940 csb->csb_ncmds = 2; 4941 } else { 4942 csb->csb_cmds[0] = FDRAW_SEEK; 4943 csb->csb_cmds[2] = (uchar_t)arg; 4944 csb->csb_ncmds = 3; 4945 } 4946 csb->csb_nrslts = 2; /* 2 for SENSE INTERRUPTS */ 4947 csb->csb_opflags = CSB_OFSEEKOPS | CSB_OFTIMEIT; 4948 /* 4949 * MAYBE NYD need to set retries to different values? - depending on 4950 * drive characteristics - if we get to high capacity drives 4951 */ 4952 csb->csb_maxretry = skretry; 4953 csb->csb_retrys = 0; 4954 4955 /* send cmd off to fdexec */ 4956 if (result = fdexec(fdc, FDXC_SLEEP | execflg)) { 4957 goto out; 4958 } 4959 4960 /* 4961 * if recal, test for equipment check error 4962 * ASSUMES result = 0 from above call 4963 */ 4964 if (arg == -1) { 4965 result = 0; 4966 } else { 4967 /* for seeks, any old error will do */ 4968 if ((csb->csb_rslt[0] & IC_SR0) || csb->csb_cmdstat) 4969 result = ENODEV; 4970 } 4971 4972 out: 4973 return (result); 4974 } 4975 4976 /* 4977 * fdsensedrv 4978 * do a sense_drive command. used by fdopen and fdcheckdisk. 4979 * 4980 * - called with the lock held 4981 */ 4982 static int 4983 fdsensedrv(struct fdctlr *fdc, int unit) 4984 { 4985 struct fdcsb *csb; 4986 4987 ASSERT(fdc->c_un->un_unit_no == unit); 4988 4989 csb = &fdc->c_csb; 4990 4991 /* setup common things in csb */ 4992 csb->csb_unit = (uchar_t)unit; 4993 csb->csb_opflags = CSB_OFIMMEDIATE; 4994 csb->csb_cmds[0] = FDRAW_SENSE_DRV; 4995 /* MOT bit set means don't delay */ 4996 csb->csb_cmds[1] = MOT | (unit & 0x03); 4997 csb->csb_ncmds = 2; 4998 csb->csb_nrslts = 1; 4999 csb->csb_maxretry = skretry; 5000 csb->csb_retrys = 0; 5001 5002 /* XXX for now ignore errors, they "CAN'T HAPPEN" */ 5003 (void) fdexec(fdc, 0); /* DON't check changed!, no sleep */ 5004 5005 FDERRPRINT(FDEP_L1, FDEM_CHEK, 5006 (C, "fdsensedrv: result 0x%x", csb->csb_rslt[0])); 5007 5008 return (csb->csb_rslt[0]); /* return status byte 3 */ 5009 } 5010 5011 /* 5012 * fdcheckdisk 5013 * check to see if the disk is still there - do a recalibrate, 5014 * then see if DSKCHG line went away, if so, diskette is in; else 5015 * it's (still) out. 5016 */ 5017 5018 static int 5019 fdcheckdisk(struct fdctlr *fdc, int unit) 5020 { 5021 auto struct fdcsb savecsb; 5022 struct fdcsb *csb; 5023 int err, st3; 5024 int seekto; /* where to seek for reset of DSKCHG */ 5025 5026 FDERRPRINT(FDEP_L1, FDEM_CHEK, 5027 (C, "fdcheckdisk, unit %d\n", unit)); 5028 5029 ASSERT(fdc->c_un->un_unit_no == unit); 5030 5031 /* 5032 * save old csb 5033 */ 5034 5035 csb = &fdc->c_csb; 5036 savecsb = fdc->c_csb; 5037 bzero((caddr_t)csb, sizeof (*csb)); 5038 5039 /* 5040 * Read drive status to see if at TRK0, if so, seek to cyl 1, 5041 * else seek to cyl 0. We do this because the controller is 5042 * "smart" enough to not send any step pulses (which are how 5043 * the DSKCHG line gets reset) if it sees TRK0 'cause it 5044 * knows the drive is already recalibrated. 5045 */ 5046 st3 = fdsensedrv(fdc, unit); 5047 5048 /* check TRK0 bit in status */ 5049 if (st3 & T0_SR3) 5050 seekto = 1; /* at TRK0, seek out */ 5051 else 5052 seekto = 0; 5053 5054 /* 5055 * DON'T recurse check changed 5056 */ 5057 err = fdrecalseek(fdc, unit, seekto, 0); 5058 5059 /* "restore" old csb, check change state */ 5060 fdc->c_csb = savecsb; 5061 5062 /* any recal/seek errors are too serious to attend to */ 5063 if (err) { 5064 FDERRPRINT(FDEP_L2, FDEM_CHEK, 5065 (C, "fdcheckdisk err %d\n", err)); 5066 return (err); 5067 } 5068 5069 /* 5070 * if disk change still asserted, no diskette in drive! 5071 */ 5072 if (fdsense_chng(fdc, csb->csb_unit)) { 5073 FDERRPRINT(FDEP_L2, FDEM_CHEK, 5074 (C, "fdcheckdisk no disk\n")); 5075 return (1); 5076 } 5077 return (0); 5078 } 5079 5080 /* 5081 * fdselect() - select drive, needed for external to chip select logic 5082 * fdeject() - ejects drive, must be previously selected 5083 * fdsense_chng() - sense disk changed line from previously selected drive 5084 * return s 1 is signal asserted, else 0 5085 */ 5086 /* ARGSUSED */ 5087 static void 5088 fdselect(struct fdctlr *fdc, int unit, int on) 5089 { 5090 5091 ASSERT(fdc->c_un->un_unit_no == unit); 5092 5093 FDERRPRINT(FDEP_L1, FDEM_DSEL, 5094 (C, "fdselect, unit %d, on = %d\n", unit, on)); 5095 5096 switch (fdc->c_fdtype & FDCTYPE_AUXIOMASK) { 5097 case FDCTYPE_MACHIO: 5098 set_auxioreg(AUX_DRVSELECT, on); 5099 break; 5100 5101 case FDCTYPE_SLAVIO: 5102 case FDCTYPE_CHEERIO: 5103 FDERRPRINT(FDEP_L1, FDEM_ATTA, 5104 (C, "fdselect: (before) Dor 0x%x\n", Dor(fdc))); 5105 5106 if (unit == 0) { 5107 Set_dor(fdc, DRVSEL, !on); 5108 } else { 5109 Set_dor(fdc, DRVSEL, on); 5110 } 5111 5112 FDERRPRINT(FDEP_L1, FDEM_ATTA, 5113 (C, "fdselect: Dor 0x%x\n", Dor(fdc))); 5114 5115 break; 5116 5117 default: 5118 break; 5119 } 5120 } 5121 5122 /* ARGSUSED */ 5123 static void 5124 fdeject(struct fdctlr *fdc, int unit) 5125 { 5126 struct fdunit *un; 5127 5128 ASSERT(fdc->c_un->un_unit_no == unit); 5129 5130 un = fdc->c_un; 5131 5132 FDERRPRINT(FDEP_L1, FDEM_EJEC, (C, "fdeject\n")); 5133 /* 5134 * assume delay of function calling sufficient settling time 5135 * eject line is NOT driven by inverter so it is true low 5136 */ 5137 switch (fdc->c_fdtype & FDCTYPE_AUXIOMASK) { 5138 case FDCTYPE_MACHIO: 5139 set_auxioreg(AUX_EJECT, 0); 5140 drv_usecwait(2); 5141 set_auxioreg(AUX_EJECT, 1); 5142 break; 5143 5144 case FDCTYPE_SLAVIO: 5145 if (!(Dor(fdc) & MOTEN(unit))) { 5146 /* LINTED */ 5147 Set_dor(fdc, MOTEN(unit), 1); 5148 } 5149 drv_usecwait(2); /* just to settle */ 5150 /* LINTED */ 5151 Set_dor(fdc, EJECT, 1); 5152 drv_usecwait(2); 5153 /* LINTED */ 5154 Set_dor(fdc, EJECT, 0); 5155 break; 5156 case FDCTYPE_CHEERIO: 5157 if (!(Dor(fdc) & MOTEN(unit))) { 5158 /* LINTED */ 5159 Set_dor(fdc, MOTEN(unit), 1); 5160 } 5161 drv_usecwait(2); /* just to settle */ 5162 /* LINTED */ 5163 Set_dor(fdc, EJECT_DMA, 1); 5164 drv_usecwait(2); 5165 /* LINTED */ 5166 Set_dor(fdc, EJECT_DMA, 0); 5167 break; 5168 } 5169 /* 5170 * XXX set ejected state? 5171 */ 5172 un->un_ejected = 1; 5173 } 5174 5175 /* ARGSUSED */ 5176 static int 5177 fdsense_chng(struct fdctlr *fdc, int unit) 5178 { 5179 int changed = 0; 5180 5181 FDERRPRINT(FDEP_L1, FDEM_SCHG, (C, "fdsense_chng:start\n")); 5182 5183 ASSERT(fdc->c_un->un_unit_no == unit); 5184 5185 /* 5186 * Do not turn on the motor of a pollable drive 5187 */ 5188 if (fd_pollable) { 5189 FDERRPRINT(FDEP_L1, FDEM_SCHG, (C, "pollable: don't turn on motor\n")); 5190 /* 5191 * Invert the sense of the DSKCHG for pollable drives 5192 */ 5193 if (Dir(fdc) & DSKCHG) 5194 changed = 0; 5195 else 5196 changed = 1; 5197 5198 return (changed); 5199 } 5200 5201 switch (fdc->c_fdtype & FDCTYPE_AUXIOMASK) { 5202 case FDCTYPE_MACHIO: 5203 if (*fdc->c_auxiova & AUX_DISKCHG) 5204 changed = 1; 5205 break; 5206 5207 case FDCTYPE_SB: 5208 case FDCTYPE_SLAVIO: 5209 case FDCTYPE_CHEERIO: 5210 if (!(Dor(fdc) & MOTEN(unit))) { 5211 /* LINTED */ 5212 Set_dor(fdc, MOTEN(unit), 1); 5213 } 5214 drv_usecwait(2); /* just to settle */ 5215 if (Dir(fdc) & DSKCHG) 5216 changed = 1; 5217 break; 5218 } 5219 5220 FDERRPRINT(FDEP_L1, FDEM_SCHG, (C, "fdsense_chng:end\n")); 5221 5222 return (changed); 5223 } 5224 5225 /* 5226 * if it can read a valid label it does so, else it will use a 5227 * default. If it can`t read the diskette - that is an error. 5228 * 5229 * RETURNS: 0 for ok - meaning that it could at least read the device, 5230 * !0 for error XXX TBD NYD error codes 5231 * 5232 * - called with the low level lock held 5233 */ 5234 static int 5235 fdgetlabel(struct fdctlr *fdc, int unit) 5236 { 5237 struct dk_label *label = NULL; 5238 struct fdunit *un; 5239 short *sp; 5240 short count; 5241 short xsum; /* checksum */ 5242 int i, tries; 5243 int err = 0; 5244 short oldlvl; 5245 5246 FDERRPRINT(FDEP_L1, FDEM_GETL, 5247 (C, "fdgetlabel: unit %d\n", unit)); 5248 5249 un = fdc->c_un; 5250 un->un_flags &= ~(FDUNIT_UNLABELED); 5251 5252 ASSERT(fdc->c_un->un_unit_no == unit); 5253 5254 /* Do not print errors since this is a private cmd */ 5255 5256 oldlvl = fderrlevel; 5257 5258 5259 fderrlevel = FDEP_L4; 5260 5261 label = (struct dk_label *) 5262 kmem_zalloc(sizeof (struct dk_label), KM_SLEEP); 5263 5264 /* 5265 * try different characteristics (ie densities) by attempting to read 5266 * from the diskette. The diskette may not be present or 5267 * is unformatted. 5268 * 5269 * First, the last sector of the first track is read. If this 5270 * passes, attempt to read the last sector + 1 of the first track. 5271 * For example, for a high density diskette, sector 18 is read. If 5272 * the diskette is high density, this will pass. Next, try to 5273 * read sector 19 of the first track. This should fail. If it 5274 * passes, this is not a high density diskette. Finally, read 5275 * the first sector which should contain a label. 5276 * 5277 * if un->un_curfdtype is -1 then the current characteristics 5278 * were set by FDIOSCHAR and need to try it as well as everything 5279 * in the table 5280 */ 5281 if (un->un_curfdtype == -1) { 5282 tries = nfdtypes+1; 5283 FDERRPRINT(FDEP_L1, FDEM_GETL, 5284 (C, "fdgetl: un_curfdtype is -1\n")); 5285 5286 } else { 5287 tries = nfdtypes; 5288 5289 /* Always start with the highest density (1.7MB) */ 5290 un->un_curfdtype = 0; 5291 *(un->un_chars) = fdtypes[un->un_curfdtype]; 5292 } 5293 5294 FDERRPRINT(FDEP_L1, FDEM_GETL, 5295 (C, "fdgetl: no. of tries %d\n", tries)); 5296 FDERRPRINT(FDEP_L1, FDEM_GETL, 5297 (C, "fdgetl: no. of curfdtype %d\n", un->un_curfdtype)); 5298 5299 for (i = 0; i < tries; i++) { 5300 FDERRPRINT(FDEP_L1, FDEM_GETL, 5301 (C, "fdgetl: trying %d\n", i)); 5302 5303 if (!(err = fdrw(fdc, unit, FDREAD, 0, 0, 5304 un->un_chars->fdc_secptrack, (caddr_t)label, 5305 sizeof (struct dk_label))) && 5306 5307 fdrw(fdc, unit, FDREAD, 0, 0, 5308 un->un_chars->fdc_secptrack + 1, 5309 (caddr_t)label, sizeof (struct dk_label)) && 5310 5311 !(err = fdrw(fdc, unit, FDREAD, 0, 0, 1, (caddr_t)label, 5312 sizeof (struct dk_label)))) { 5313 5314 FDERRPRINT(FDEP_L1, FDEM_GETL, 5315 (C, "fdgetl: succeeded\n")); 5316 5317 break; 5318 } 5319 5320 /* 5321 * try the next entry in the characteristics tbl 5322 * If curfdtype is -1, the nxt entry in tbl is 0 (the first). 5323 */ 5324 5325 un->un_curfdtype = (un->un_curfdtype + 1) % nfdtypes; 5326 *(un->un_chars) = fdtypes[un->un_curfdtype]; 5327 5328 5329 } 5330 5331 /* print errors again */ 5332 fderrlevel = oldlvl; 5333 5334 /* Couldn't read anything */ 5335 if (err) { 5336 5337 /* The default characteristics are high density (1.4MB) */ 5338 un->un_curfdtype = 1; 5339 *(un->un_chars) = fdtypes[un->un_curfdtype]; 5340 5341 fdunpacklabel(&fdlbl_high_80, &un->un_label); 5342 5343 FDERRPRINT(FDEP_L1, FDEM_GETL, 5344 (C, "fdgetl: Can't autosense diskette\n")); 5345 5346 goto out; 5347 } 5348 5349 FDERRPRINT(FDEP_L1, FDEM_GETL, 5350 (C, "fdgetl: fdtype=%d !!!\n", un->un_curfdtype)); 5351 FDERRPRINT(FDEP_L1, FDEM_GETL, 5352 (C, "fdgetl: rate=%d ssize=%d !!!\n", 5353 un->un_chars->fdc_transfer_rate, un->un_chars->fdc_sec_size)); 5354 5355 /* 5356 * _something_ was read - look for unixtype label 5357 */ 5358 if (label->dkl_magic != DKL_MAGIC) { 5359 5360 /* 5361 * The label isn't a unix label. However, the diskette 5362 * is formatted because we were able to read the first 5363 * cylinder. 5364 */ 5365 5366 FDERRPRINT(FDEP_L1, FDEM_GETL, 5367 (C, "fdgetl: not unix label\n")); 5368 5369 goto nolabel; 5370 } 5371 5372 /* 5373 * Checksum the label 5374 */ 5375 count = sizeof (struct dk_label)/sizeof (short); 5376 sp = (short *)label; 5377 xsum = 0; 5378 while (count--) 5379 xsum ^= *sp++; /* should add up to 0 */ 5380 if (xsum) { 5381 5382 /* 5383 * The checksum fails. However, the diskette is formatted 5384 * because we were able to read the first cylinder 5385 */ 5386 5387 FDERRPRINT(FDEP_L1, FDEM_GETL, 5388 (C, "fdgetl: bad cksum\n")); 5389 5390 goto nolabel; 5391 } 5392 5393 /* 5394 * The diskette has a unix label with a correct checksum. 5395 * Copy the label into the unit structure 5396 */ 5397 un->un_label = *label; 5398 5399 goto out; 5400 5401 nolabel: 5402 /* 5403 * The diskette doesn't have a correct unix label, but it is formatted. 5404 * Use a default label according to the diskette's density 5405 * (mark default used) 5406 */ 5407 FDERRPRINT(FDEP_L1, FDEM_GETL, 5408 (C, "fdgetlabel: unit %d\n", unit)); 5409 un->un_flags |= FDUNIT_UNLABELED; 5410 switch (un->un_chars->fdc_secptrack) { 5411 case 9: 5412 fdunpacklabel(&fdlbl_low_80, &un->un_label); 5413 break; 5414 case 8: 5415 fdunpacklabel(&fdlbl_medium_80, &un->un_label); 5416 break; 5417 case 18: 5418 fdunpacklabel(&fdlbl_high_80, &un->un_label); 5419 break; 5420 case 21: 5421 fdunpacklabel(&fdlbl_high_21, &un->un_label); 5422 break; 5423 default: 5424 fdunpacklabel(&fdlbl_high_80, &un->un_label); 5425 break; 5426 } 5427 5428 out: 5429 if (label != NULL) 5430 kmem_free((caddr_t)label, sizeof (struct dk_label)); 5431 return (err); 5432 } 5433 5434 /* 5435 * fdrw- used only for reading labels and for DKIOCSVTOC ioctl 5436 * which reads the 1 sector. 5437 */ 5438 static int 5439 fdrw(struct fdctlr *fdc, int unit, int rw, int cyl, int head, 5440 int sector, caddr_t bufp, uint_t len) 5441 { 5442 struct fdcsb *csb; 5443 struct fd_char *ch; 5444 int cmdresult = 0; 5445 caddr_t dma_addr; 5446 size_t real_length; 5447 int res; 5448 ddi_device_acc_attr_t attr; 5449 ddi_acc_handle_t mem_handle = NULL; 5450 5451 FDERRPRINT(FDEP_L1, FDEM_RW, (C, "fdrw\n")); 5452 5453 ASSERT(fdc->c_un->un_unit_no == unit); 5454 5455 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 5456 5457 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 5458 mutex_exit(&fdc->c_lolock); 5459 if ((pm_raise_power(fdc->c_dip, 0, PM_LEVEL_ON)) 5460 != DDI_SUCCESS) { 5461 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "Power change \ 5462 failed. \n")); 5463 mutex_enter(&fdc->c_lolock); 5464 return (EIO); 5465 } 5466 5467 mutex_enter(&fdc->c_lolock); 5468 } 5469 5470 fdgetcsb(fdc); 5471 csb = &fdc->c_csb; 5472 ch = fdc->c_un->un_chars; 5473 if (rw == FDREAD) { 5474 if (fdc->c_fdtype & FDCTYPE_TCBUG) { 5475 /* 5476 * kludge for lack of Multitrack functionality 5477 */ 5478 csb->csb_cmds[0] = SK + FDRAW_RDCMD; 5479 } else 5480 csb->csb_cmds[0] = MT + SK + FDRAW_RDCMD; 5481 } else { /* write */ 5482 if (fdc->c_fdtype & FDCTYPE_TCBUG) { 5483 /* 5484 * kludge for lack of Multitrack functionality 5485 */ 5486 csb->csb_cmds[0] = FDRAW_WRCMD; 5487 } else 5488 csb->csb_cmds[0] = MT + FDRAW_WRCMD; 5489 } 5490 5491 if (rw == FDREAD) 5492 fdc->c_csb.csb_read = CSB_READ; 5493 else 5494 fdc->c_csb.csb_read = CSB_WRITE; 5495 5496 /* always or in MFM bit */ 5497 csb->csb_cmds[0] |= MFM; 5498 csb->csb_cmds[1] = (uchar_t)(unit | ((head & 0x1) << 2)); 5499 if (fdc->c_fdtype & FDCTYPE_SB) 5500 csb->csb_cmds[1] |= IPS; 5501 csb->csb_cmds[2] = (uchar_t)cyl; 5502 csb->csb_cmds[3] = (uchar_t)head; 5503 csb->csb_cmds[4] = (uchar_t)sector; 5504 csb->csb_cmds[5] = ch->fdc_medium ? 3 : 2; /* sector size code */ 5505 /* 5506 * kludge for end-of-cylinder error. 5507 */ 5508 if (fdc->c_fdtype & FDCTYPE_TCBUG) 5509 csb->csb_cmds[6] = sector + (len / ch->fdc_sec_size) - 1; 5510 else 5511 csb->csb_cmds[6] = 5512 (uchar_t)max(fdc->c_un->un_chars->fdc_secptrack, sector); 5513 csb->csb_len = len; 5514 csb->csb_cmds[7] = GPLN; 5515 csb->csb_cmds[8] = SSSDTL; 5516 csb->csb_ncmds = NCBRW; 5517 csb->csb_len = len; 5518 csb->csb_maxretry = 2; 5519 csb->csb_retrys = 0; 5520 bzero(csb->csb_rslt, NRBRW); 5521 csb->csb_nrslts = NRBRW; 5522 csb->csb_opflags = CSB_OFXFEROPS | CSB_OFTIMEIT; 5523 5524 /* If platform supports DMA, set up DMA resources */ 5525 if (fdc->c_fdtype & FDCTYPE_DMA) { 5526 5527 mutex_enter(&fdc->c_hilock); 5528 5529 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 5530 attr.devacc_attr_endian_flags = DDI_STRUCTURE_BE_ACC; 5531 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 5532 5533 res = ddi_dma_mem_alloc(fdc->c_dmahandle, len, 5534 &attr, DDI_DMA_STREAMING, 5535 DDI_DMA_DONTWAIT, 0, &dma_addr, &real_length, 5536 &mem_handle); 5537 5538 if (res != DDI_SUCCESS) { 5539 FDERRPRINT(FDEP_L1, FDEM_RW, 5540 (C, "fdrw: dma mem alloc failed\n")); 5541 5542 fdretcsb(fdc); 5543 mutex_exit(&fdc->c_hilock); 5544 return (EIO); 5545 } 5546 5547 FDERRPRINT(FDEP_L1, FDEM_RW, (C, "fdrw: allocated memory")); 5548 5549 if (fdstart_dma(fdc, dma_addr, len) != 0) { 5550 fdretcsb(fdc); 5551 ddi_dma_mem_free(&mem_handle); 5552 mutex_exit(&fdc->c_hilock); 5553 return (-1); 5554 5555 } 5556 5557 /* 5558 * If the command is a write, copy the data to be written to 5559 * dma_addr. 5560 */ 5561 5562 if (fdc->c_csb.csb_read == CSB_WRITE) { 5563 bcopy((char *)bufp, (char *)dma_addr, len); 5564 } 5565 5566 csb->csb_addr = dma_addr; 5567 mutex_exit(&fdc->c_hilock); 5568 } else { 5569 csb->csb_addr = bufp; 5570 } 5571 5572 5573 FDERRPRINT(FDEP_L1, FDEM_RW, (C, "fdrw: call fdexec\n")); 5574 5575 if (fdexec(fdc, FDXC_SLEEP | FDXC_CHECKCHG) != 0) { 5576 fdretcsb(fdc); 5577 5578 if (mem_handle) 5579 ddi_dma_mem_free(&mem_handle); 5580 5581 return (EIO); 5582 5583 } 5584 5585 FDERRPRINT(FDEP_L1, FDEM_RW, (C, "fdrw: fdexec returned\n")); 5586 5587 /* 5588 * if DMA was used and the command was a read 5589 * copy the results into bufp 5590 */ 5591 if (fdc->c_fdtype & FDCTYPE_DMA) { 5592 if (fdc->c_csb.csb_read == CSB_READ) { 5593 bcopy((char *)dma_addr, (char *)bufp, len); 5594 } 5595 ddi_dma_mem_free(&mem_handle); 5596 } 5597 5598 if (csb->csb_cmdstat) 5599 cmdresult = EIO; /* XXX TBD NYD for now */ 5600 5601 fdretcsb(fdc); 5602 return (cmdresult); 5603 } 5604 5605 /* 5606 * fdunpacklabel 5607 * this unpacks a (packed) struct dk_label into a standard dk_label. 5608 */ 5609 static void 5610 fdunpacklabel(struct packed_label *from, struct dk_label *to) 5611 { 5612 FDERRPRINT(FDEP_L1, FDEM_PACK, (C, "fdpacklabel\n")); 5613 bzero((caddr_t)to, sizeof (*to)); 5614 bcopy((caddr_t)&from->dkl_vname, (caddr_t)to->dkl_asciilabel, 5615 sizeof (to->dkl_asciilabel)); 5616 to->dkl_rpm = from->dkl_rpm; /* rotations per minute */ 5617 to->dkl_pcyl = from->dkl_pcyl; /* # physical cylinders */ 5618 to->dkl_apc = from->dkl_apc; /* alternates per cylinder */ 5619 to->dkl_intrlv = from->dkl_intrlv; /* interleave factor */ 5620 to->dkl_ncyl = from->dkl_ncyl; /* # of data cylinders */ 5621 to->dkl_acyl = from->dkl_acyl; /* # of alternate cylinders */ 5622 to->dkl_nhead = from->dkl_nhead; /* # of heads in this partition */ 5623 to->dkl_nsect = from->dkl_nsect; /* # of 512 byte sectors per track */ 5624 /* logical partitions */ 5625 bcopy((caddr_t)from->dkl_map, (caddr_t)to->dkl_map, 5626 sizeof (struct dk_map32) * NDKMAP); 5627 to->dkl_vtoc = from->dkl_vtoc; 5628 } 5629 5630 static struct fdctlr * 5631 fd_getctlr(dev_t dev) 5632 { 5633 5634 struct fdctlr *fdc = fdctlrs; 5635 int ctlr = FDCTLR(dev); 5636 5637 while (fdc) { 5638 if (ddi_get_instance(fdc->c_dip) == ctlr) 5639 return (fdc); 5640 fdc = fdc->c_next; 5641 } 5642 return (fdc); 5643 } 5644 5645 static int 5646 fd_unit_is_open(struct fdunit *un) 5647 { 5648 int i; 5649 for (i = 0; i < NDKMAP; i++) 5650 if (un->un_lyropen[i]) 5651 return (1); 5652 for (i = 0; i < OTYPCNT - 1; i++) 5653 if (un->un_regopen[i]) 5654 return (1); 5655 return (0); 5656 } 5657 5658 /* 5659 * Return the a vtoc structure in *vtoc. 5660 * The vtoc is built from information in 5661 * the diskette's label. 5662 */ 5663 static void 5664 fd_build_user_vtoc(struct fdunit *un, struct vtoc *vtoc) 5665 { 5666 int i; 5667 int nblks; /* DEV_BSIZE sectors per cylinder */ 5668 struct dk_map2 *lpart; 5669 struct dk_map32 *lmap; 5670 struct partition *vpart; 5671 5672 bzero(vtoc, sizeof (struct vtoc)); 5673 5674 /* Initialize info. needed by mboot. (unsupported) */ 5675 vtoc->v_bootinfo[0] = un->un_label.dkl_vtoc.v_bootinfo[0]; 5676 vtoc->v_bootinfo[1] = un->un_label.dkl_vtoc.v_bootinfo[1]; 5677 vtoc->v_bootinfo[2] = un->un_label.dkl_vtoc.v_bootinfo[2]; 5678 5679 /* Fill in vtoc sanity and version information */ 5680 vtoc->v_sanity = un->un_label.dkl_vtoc.v_sanity; 5681 vtoc->v_version = un->un_label.dkl_vtoc.v_version; 5682 5683 /* Copy the volume name */ 5684 bcopy(un->un_label.dkl_vtoc.v_volume, 5685 vtoc->v_volume, LEN_DKL_VVOL); 5686 5687 /* 5688 * The dk_map32 structure is based on DEV_BSIZE byte blocks. 5689 * However, medium density diskettes have 1024 byte blocks. 5690 * The number of sectors per partition listed in the dk_map32 structure 5691 * accounts for this by multiplying the number of 1024 byte 5692 * blocks by 2. (See the packed_label initializations.) The 5693 * 1024 byte block size can not be listed for medium density 5694 * diskettes because the kernel is hard coded for DEV_BSIZE 5695 * blocks. 5696 */ 5697 vtoc->v_sectorsz = DEV_BSIZE; 5698 vtoc->v_nparts = un->un_label.dkl_vtoc.v_nparts; 5699 5700 /* Copy the reserved space */ 5701 bcopy(un->un_label.dkl_vtoc.v_reserved, 5702 vtoc->v_reserved, sizeof (un->un_label.dkl_vtoc.v_reserved)); 5703 /* 5704 * Convert partitioning information. 5705 * 5706 * Note the conversion from starting cylinder number 5707 * to starting sector number. 5708 */ 5709 lmap = un->un_label.dkl_map; 5710 lpart = un->un_label.dkl_vtoc.v_part; 5711 vpart = vtoc->v_part; 5712 5713 nblks = (un->un_chars->fdc_nhead * un->un_chars->fdc_secptrack * 5714 un->un_chars->fdc_sec_size) / DEV_BSIZE; 5715 5716 for (i = 0; i < V_NUMPAR; i++) { 5717 vpart->p_tag = lpart->p_tag; 5718 vpart->p_flag = lpart->p_flag; 5719 vpart->p_start = lmap->dkl_cylno * nblks; 5720 vpart->p_size = lmap->dkl_nblk; 5721 5722 lmap++; 5723 lpart++; 5724 vpart++; 5725 } 5726 5727 /* Initialize timestamp and label */ 5728 bcopy(un->un_label.dkl_vtoc.v_timestamp, 5729 vtoc->timestamp, sizeof (vtoc->timestamp)); 5730 5731 bcopy(un->un_label.dkl_asciilabel, 5732 vtoc->v_asciilabel, LEN_DKL_ASCII); 5733 } 5734 5735 /* 5736 * Build a label out of a vtoc structure. 5737 */ 5738 static int 5739 fd_build_label_vtoc(struct fdunit *un, struct vtoc *vtoc) 5740 { 5741 struct dk_map32 *lmap; 5742 struct dk_map2 *lpart; 5743 struct partition *vpart; 5744 int nblks; /* no. blocks per cylinder */ 5745 int ncyl; 5746 int i; 5747 short sum, *sp; 5748 5749 /* Sanity-check the vtoc */ 5750 if ((vtoc->v_sanity != VTOC_SANE) || 5751 (vtoc->v_nparts > NDKMAP) || (vtoc->v_nparts <= 0)) { 5752 FDERRPRINT(FDEP_L1, FDEM_IOCT, 5753 (C, "fd_build_label: sanity check on vtoc failed\n")); 5754 return (EINVAL); 5755 } 5756 5757 nblks = (un->un_chars->fdc_nhead * un->un_chars->fdc_secptrack * 5758 un->un_chars->fdc_sec_size) / DEV_BSIZE; 5759 5760 vpart = vtoc->v_part; 5761 5762 /* 5763 * Check the partition information in the vtoc. The starting sectors 5764 * must lie along partition boundaries. (NDKMAP entries are checked 5765 * to ensure that the unused entries are set to 0 if vtoc->v_nparts 5766 * is less than NDKMAP) 5767 */ 5768 5769 for (i = 0; i < NDKMAP; i++) { 5770 if ((vpart->p_start % nblks) != 0) { 5771 return (EINVAL); 5772 } 5773 ncyl = vpart->p_start % nblks; 5774 ncyl += vpart->p_size % nblks; 5775 if ((vpart->p_size % nblks) != 0) 5776 ncyl++; 5777 if (ncyl > un->un_chars->fdc_ncyl) { 5778 return (EINVAL); 5779 } 5780 vpart++; 5781 } 5782 5783 /* 5784 * reinitialize the existing label 5785 */ 5786 bzero(&un->un_label, sizeof (un->un_label)); 5787 5788 /* Put appropriate vtoc structure fields into the disk label */ 5789 un->un_label.dkl_vtoc.v_bootinfo[0] = (uint32_t)vtoc->v_bootinfo[0]; 5790 un->un_label.dkl_vtoc.v_bootinfo[1] = (uint32_t)vtoc->v_bootinfo[1]; 5791 un->un_label.dkl_vtoc.v_bootinfo[2] = (uint32_t)vtoc->v_bootinfo[2]; 5792 5793 un->un_label.dkl_vtoc.v_sanity = vtoc->v_sanity; 5794 un->un_label.dkl_vtoc.v_version = vtoc->v_version; 5795 5796 bcopy(vtoc->v_volume, un->un_label.dkl_vtoc.v_volume, LEN_DKL_VVOL); 5797 5798 un->un_label.dkl_vtoc.v_nparts = vtoc->v_nparts; 5799 5800 bcopy(vtoc->v_reserved, un->un_label.dkl_vtoc.v_reserved, 5801 sizeof (un->un_label.dkl_vtoc.v_reserved)); 5802 5803 /* 5804 * Initialize cylinder information in the label. 5805 * Note the conversion from starting sector number 5806 * to starting cylinder number. 5807 * Return error if division results in a remainder. 5808 */ 5809 lmap = un->un_label.dkl_map; 5810 lpart = un->un_label.dkl_vtoc.v_part; 5811 vpart = vtoc->v_part; 5812 5813 for (i = 0; i < (int)vtoc->v_nparts; i++) { 5814 lpart->p_tag = vtoc->v_part[i].p_tag; 5815 lpart->p_flag = vtoc->v_part[i].p_flag; 5816 lmap->dkl_cylno = vpart->p_start / nblks; 5817 lmap->dkl_nblk = vpart->p_size; 5818 5819 lmap++; 5820 lpart++; 5821 vpart++; 5822 } 5823 5824 /* Copy the timestamp and ascii label */ 5825 for (i = 0; i < NDKMAP; i++) { 5826 un->un_label.dkl_vtoc.v_timestamp[i] = vtoc->timestamp[i]; 5827 } 5828 5829 5830 bcopy(vtoc->v_asciilabel, un->un_label.dkl_asciilabel, LEN_DKL_ASCII); 5831 5832 FDERRPRINT(FDEP_L1, FDEM_IOCT, 5833 (C, "fd_build_label: asciilabel %s\n", 5834 un->un_label.dkl_asciilabel)); 5835 5836 /* Initialize the magic number */ 5837 un->un_label.dkl_magic = DKL_MAGIC; 5838 5839 un->un_label.dkl_pcyl = un->un_chars->fdc_ncyl; 5840 5841 /* 5842 * The fdc_secptrack filed of the fd_char structure is the number 5843 * of sectors per track where the sectors are fdc_sec_size. The 5844 * dkl_nsect field of the dk_label structure is the number of 5845 * 512 (DEVBSIZE) byte sectors per track. 5846 */ 5847 un->un_label.dkl_nsect = (un->un_chars->fdc_secptrack * 5848 un->un_chars->fdc_sec_size) / DEV_BSIZE; 5849 5850 5851 un->un_label.dkl_ncyl = un->un_label.dkl_pcyl; 5852 un->un_label.dkl_nhead = un->un_chars->fdc_nhead; 5853 un->un_label.dkl_rpm = un->un_chars->fdc_medium ? 360 : 300; 5854 un->un_label.dkl_intrlv = 1; 5855 5856 /* Create the checksum */ 5857 sum = 0; 5858 un->un_label.dkl_cksum = 0; 5859 sp = (short *)&un->un_label; 5860 i = sizeof (struct dk_label)/sizeof (short); 5861 while (i--) { 5862 sum ^= *sp++; 5863 } 5864 un->un_label.dkl_cksum = sum; 5865 5866 return (0); 5867 } 5868 5869 /* 5870 * Check for auxio register node 5871 */ 5872 5873 int 5874 fd_isauxiodip(dev_info_t *dip) 5875 { 5876 if (strcmp(ddi_get_name(dip), "auxio") == 0 || 5877 strcmp(ddi_get_name(dip), "auxiliary-io") == 0) { 5878 return (1); 5879 } 5880 return (0); 5881 } 5882 5883 /* 5884 * Search for auxio register node, then for address property 5885 */ 5886 5887 caddr_t 5888 fd_getauxiova(dev_info_t *dip) 5889 { 5890 dev_info_t *auxdip; 5891 caddr_t addr; 5892 5893 /* 5894 * Search sibling list, which happens to be safe inside attach 5895 */ 5896 auxdip = ddi_get_child(ddi_get_parent(dip)); 5897 while (auxdip) { 5898 if (fd_isauxiodip(auxdip)) 5899 break; 5900 auxdip = ddi_get_next_sibling(auxdip); 5901 } 5902 5903 if (auxdip == NULL) 5904 return (NULL); 5905 5906 addr = (caddr_t)(caddr32_t)ddi_getprop(DDI_DEV_T_ANY, 5907 auxdip, DDI_PROP_DONTPASS, "address", 0); 5908 5909 /* 5910 * The device tree on some sun4c machines (SS1+) incorrectly 5911 * reports the "auxiliary-io" as being word wide at an 5912 * aligned address rather than byte wide at an offset of 3. 5913 * Here we correct for this .. 5914 */ 5915 if (strcmp(ddi_get_name(auxdip), "auxiliary-io") == 0 && 5916 (((int)addr & 3) == 0)) 5917 addr += 3; 5918 5919 return (addr); 5920 } 5921 5922 5923 /* 5924 * set_rotational speed 5925 * 300 rpm for high and low density. 5926 * 360 rpm for medium density. 5927 * for now, we assume that 3rd density is supported only for Sun4M, 5928 * not for Clones. (else we would have to check for 82077, and do 5929 * specific things for the MEDIUM_DENSITY BIT for clones. 5930 * this code should not break CLONES. 5931 * 5932 * REMARK: there is a SOny requirement, to deselect the drive then 5933 * select it again after the medium density change, since the 5934 * leading edge of the select line latches the rotational Speed. 5935 * then after that, we have to wait 500 ms for the rotation to 5936 * stabilize. 5937 * 5938 */ 5939 static void 5940 set_rotational_speed(struct fdctlr *fdc, int unit) 5941 { 5942 int check; 5943 int is_medium; 5944 5945 ASSERT(fdc->c_un->un_unit_no == unit); 5946 5947 /* 5948 * if we do not have a Sun4m, medium density is not supported. 5949 */ 5950 if (fdc->c_fdtype & FDCTYPE_MACHIO) 5951 return; 5952 5953 /* 5954 * if FDUNIT_SET_SPEED is set, set the speed. 5955 * else, 5956 * if there is a change, do it, if not leave it alone. 5957 * there is a change if un->un_chars->fdc_medium does not match 5958 * un->un_flags & FDUNIT_MEDIUM 5959 * un->un_flags & FDUNIT_MEDIUM specifies the last setting. 5960 * un->un_chars->fdc_medium specifies next setting. 5961 * if there is a change, wait 500ms according to Sony spec. 5962 */ 5963 5964 is_medium = fdc->c_un->un_chars->fdc_medium; 5965 5966 if (fdc->c_un->un_flags & FDUNIT_SET_SPEED) { 5967 check = 1; 5968 } else { 5969 check = is_medium ^ 5970 ((fdc->c_un->un_flags & FDUNIT_MEDIUM) ? 1 : 0); 5971 5972 /* Set the un_flags if necessary */ 5973 5974 if (check) 5975 fdc->c_un->un_flags ^= FDUNIT_MEDIUM; 5976 } 5977 5978 fdc->c_un->un_flags &= ~FDUNIT_SET_SPEED; 5979 5980 5981 if (check) { 5982 5983 fdselect(fdc, unit, 0); 5984 drv_usecwait(5); 5985 5986 if ((fdc->c_fdtype & FDCTYPE_AUXIOMASK) == FDCTYPE_SLAVIO) { 5987 Set_dor(fdc, MEDIUM_DENSITY, is_medium); 5988 } 5989 5990 if ((fdc->c_fdtype & FDCTYPE_AUXIOMASK) == FDCTYPE_CHEERIO) { 5991 if (is_medium) { 5992 Set_auxio(fdc, AUX_MEDIUM_DENSITY); 5993 } else { 5994 Set_auxio(fdc, AUX_HIGH_DENSITY); 5995 } 5996 5997 } 5998 5999 if (is_medium) { 6000 drv_usecwait(5); 6001 } 6002 6003 fdselect(fdc, unit, 1); /* Sony requirement */ 6004 FDERRPRINT(FDEP_L1, FDEM_EXEC, (C, "rotation:medium\n")); 6005 drv_usecwait(500000); 6006 } 6007 } 6008 6009 static void 6010 fd_media_watch(void *arg) 6011 { 6012 dev_t dev; 6013 struct fdunit *un; 6014 struct fdctlr *fdc; 6015 int unit; 6016 6017 dev = (dev_t)arg; 6018 fdc = fd_getctlr(dev); 6019 unit = fdc->c_un->un_unit_no; 6020 un = fdc->c_un; 6021 6022 mutex_enter(&fdc->c_lolock); 6023 6024 if (un->un_media_timeout_id == 0) { 6025 /* 6026 * Untimeout is about to be called. 6027 * Don't call fd_get_media_state again 6028 */ 6029 mutex_exit(&fdc->c_lolock); 6030 return; 6031 } 6032 6033 6034 un->un_media_state = fd_get_media_state(fdc, unit); 6035 cv_broadcast(&fdc->c_statecv); 6036 6037 mutex_exit(&fdc->c_lolock); 6038 6039 if (un->un_media_timeout) { 6040 un->un_media_timeout_id = timeout(fd_media_watch, 6041 (void *)(ulong_t)dev, un->un_media_timeout); 6042 } 6043 } 6044 6045 enum dkio_state 6046 fd_get_media_state(struct fdctlr *fdc, int unit) 6047 { 6048 enum dkio_state state; 6049 6050 ASSERT(fdc->c_un->un_unit_no == unit); 6051 6052 if (fdsense_chng(fdc, unit)) { 6053 /* check disk only if DSKCHG "high" */ 6054 if (fdcheckdisk(fdc, unit)) { 6055 state = DKIO_EJECTED; 6056 } else { 6057 state = DKIO_INSERTED; 6058 } 6059 } else { 6060 state = DKIO_INSERTED; 6061 } 6062 return (state); 6063 } 6064 6065 static int 6066 fd_check_media(dev_t dev, enum dkio_state state) 6067 { 6068 struct fdunit *un; 6069 struct fdctlr *fdc; 6070 int unit; 6071 6072 FDERRPRINT(FDEP_L1, FDEM_RW, (C, "fd_check_media: start\n")); 6073 6074 fdc = fd_getctlr(dev); 6075 unit = fdc->c_un->un_unit_no; 6076 un = fdc->c_un; 6077 6078 mutex_enter(&fdc->c_lolock); 6079 6080 CHECK_AND_WAIT_FD_STATE_SUSPENDED(fdc); 6081 6082 if (fdc->c_un->un_state == FD_STATE_STOPPED) { 6083 mutex_exit(&fdc->c_lolock); 6084 if ((pm_raise_power(fdc->c_dip, 0, PM_LEVEL_ON)) 6085 != DDI_SUCCESS) { 6086 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "Power change \ 6087 failed. \n")); 6088 6089 (void) pm_idle_component(fdc->c_dip, 0); 6090 return (EIO); 6091 } 6092 6093 mutex_enter(&fdc->c_lolock); 6094 } 6095 6096 un->un_media_state = fd_get_media_state(fdc, unit); 6097 6098 /* turn on timeout */ 6099 un->un_media_timeout = drv_usectohz(fd_check_media_time); 6100 un->un_media_timeout_id = timeout(fd_media_watch, 6101 (void *)(ulong_t)dev, un->un_media_timeout); 6102 6103 while (un->un_media_state == state) { 6104 if (cv_wait_sig(&fdc->c_statecv, &fdc->c_lolock) == 0) { 6105 un->un_media_timeout = 0; 6106 mutex_exit(&fdc->c_lolock); 6107 return (EINTR); 6108 } 6109 } 6110 6111 if (un->un_media_timeout_id) { 6112 timeout_id_t timeid = un->un_media_timeout_id; 6113 un->un_media_timeout_id = 0; 6114 6115 mutex_exit(&fdc->c_lolock); 6116 (void) untimeout(timeid); 6117 mutex_enter(&fdc->c_lolock); 6118 } 6119 6120 if (un->un_media_state == DKIO_INSERTED) { 6121 if (fdgetlabel(fdc, unit)) { 6122 mutex_exit(&fdc->c_lolock); 6123 return (EIO); 6124 } 6125 } 6126 mutex_exit(&fdc->c_lolock); 6127 6128 FDERRPRINT(FDEP_L1, FDEM_RW, (C, "fd_check_media: end\n")); 6129 return (0); 6130 } 6131 6132 /* 6133 * fd_get_media_info : 6134 * Collects medium information for 6135 * DKIOCGMEDIAINFO ioctl. 6136 */ 6137 6138 static int 6139 fd_get_media_info(struct fdunit *un, caddr_t buf, int flag) 6140 { 6141 struct dk_minfo media_info; 6142 int err = 0; 6143 6144 media_info.dki_media_type = DK_FLOPPY; 6145 media_info.dki_lbsize = un->un_chars->fdc_sec_size; 6146 media_info.dki_capacity = un->un_chars->fdc_ncyl * 6147 un->un_chars->fdc_secptrack * un->un_chars->fdc_nhead; 6148 6149 if (ddi_copyout((caddr_t)&media_info, buf, 6150 sizeof (struct dk_minfo), flag)) 6151 err = EFAULT; 6152 return (err); 6153 } 6154 6155 /* 6156 * fd_power : 6157 * Power entry point of fd driver. 6158 */ 6159 6160 static int 6161 fd_power(dev_info_t *dip, int component, int level) 6162 { 6163 6164 struct fdctlr *fdc; 6165 int instance; 6166 int rval; 6167 6168 if ((level < PM_LEVEL_OFF) || (level > PM_LEVEL_ON) || 6169 (component != 0)) { 6170 return (DDI_FAILURE); 6171 } 6172 6173 instance = ddi_get_instance(dip); 6174 fdc = fd_getctlr(instance << FDINSTSHIFT); 6175 if (fdc->c_un == NULL) 6176 return (DDI_FAILURE); 6177 6178 if (level == PM_LEVEL_OFF) { 6179 rval = fd_pm_lower_power(fdc); 6180 } 6181 if (level == PM_LEVEL_ON) { 6182 rval = fd_pm_raise_power(fdc); 6183 } 6184 return (rval); 6185 } 6186 6187 /* 6188 * fd_pm_lower_power : 6189 * This function is called only during pm suspend. At this point, 6190 * the power management framework thinks the device is idle for 6191 * long enough to go to a low power mode. If the device is busy, 6192 * then this function returns DDI_FAILURE. 6193 */ 6194 6195 static int 6196 fd_pm_lower_power(struct fdctlr *fdc) 6197 { 6198 6199 mutex_enter(&fdc->c_lolock); 6200 6201 if ((fdc->c_un->un_state == FD_STATE_SUSPENDED) || 6202 (fdc->c_un->un_state == FD_STATE_STOPPED)) { 6203 mutex_exit(&fdc->c_lolock); 6204 return (DDI_SUCCESS); 6205 } 6206 6207 6208 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "fd_pm_lower_power called\n")); 6209 6210 /* if the device is busy then we fail the lower power request */ 6211 if (fdc->c_flags & FDCFLG_BUSY) { 6212 FDERRPRINT(FDEP_L2, FDEM_PWR, (C, "fd_pm_lower_power : \ 6213 controller is busy.\n")); 6214 mutex_exit(&fdc->c_lolock); 6215 return (DDI_FAILURE); 6216 } 6217 6218 fdc->c_un->un_state = FD_STATE_STOPPED; 6219 6220 mutex_exit(&fdc->c_lolock); 6221 return (DDI_SUCCESS); 6222 } 6223 6224 /* 6225 * fd_pm_raise_power : 6226 * This function performs the necessary steps for resuming a 6227 * device, either from pm suspend or CPR. Here the controller 6228 * is reset, initialized and the state is set to FD_STATE_NORMAL. 6229 */ 6230 6231 static int 6232 fd_pm_raise_power(struct fdctlr *fdc) 6233 { 6234 6235 struct fdunit *un = fdc->c_un; 6236 int unit; 6237 6238 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "fd_pm_raise_power called\n")); 6239 mutex_enter(&fdc->c_lolock); 6240 fdgetcsb(fdc); 6241 6242 /* Reset the dma engine */ 6243 if (fdc->c_fdtype & FDCTYPE_DMA) { 6244 mutex_enter(&fdc->c_hilock); 6245 reset_dma_controller(fdc); 6246 set_dma_control_register(fdc, DCSR_INIT_BITS); 6247 mutex_exit(&fdc->c_hilock); 6248 } 6249 6250 /* 6251 * Force a rotational speed set in the next 6252 * call to set_rotational_speed(). 6253 */ 6254 6255 fdc->c_un->un_flags |= FDUNIT_SET_SPEED; 6256 6257 /* Reset and configure the controller */ 6258 (void) fdreset(fdc); 6259 6260 unit = fdc->c_un->un_unit_no; 6261 6262 /* Recalibrate the drive */ 6263 if (fdrecalseek(fdc, unit, -1, 0) != 0) { 6264 FDERRPRINT(FDEP_L1, FDEM_PWR, (C, "raise_power : recalibrate \ 6265 failed\n")); 6266 fdretcsb(fdc); 6267 mutex_exit(&fdc->c_lolock); 6268 return (DDI_FAILURE); 6269 } 6270 6271 /* Select the drive through the AUXIO registers */ 6272 fdselect(fdc, unit, 0); 6273 un->un_state = FD_STATE_NORMAL; 6274 fdretcsb(fdc); 6275 mutex_exit(&fdc->c_lolock); 6276 return (DDI_SUCCESS); 6277 } 6278 6279 /* 6280 * create_pm_components : 6281 * creates the power management components for auto pm framework. 6282 */ 6283 6284 static void 6285 create_pm_components(dev_info_t *dip) 6286 { 6287 char *un_pm_comp[] = { "NAME=spindle-motor", "0=off", "1=on"}; 6288 6289 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip, 6290 "pm-components", un_pm_comp, 3) == DDI_PROP_SUCCESS) { 6291 6292 (void) pm_raise_power(dip, 0, PM_LEVEL_ON); 6293 } 6294 } 6295 6296 /* 6297 * set_data_count_register(struct fdctlr *fdc, uint32_t count) 6298 * Set the data count in appropriate dma register. 6299 */ 6300 6301 static void 6302 set_data_count_register(struct fdctlr *fdc, uint32_t count) 6303 { 6304 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 6305 struct cheerio_dma_reg *dma_reg; 6306 dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs; 6307 ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dbcr, count); 6308 } else if (fdc->c_fdtype & FDCTYPE_SB) { 6309 struct sb_dma_reg *dma_reg; 6310 count = count - 1; /* 8237 needs it */ 6311 dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs; 6312 switch (fdc->sb_dma_channel) { 6313 case 0 : 6314 ddi_put16(fdc->c_handlep_dma, 6315 (ushort_t *)&dma_reg->sb_dma_regs[DMA_0WCNT], 6316 count & 0xFFFF); 6317 break; 6318 case 1 : 6319 ddi_put16(fdc->c_handlep_dma, 6320 (ushort_t *)&dma_reg->sb_dma_regs[DMA_1WCNT], 6321 count & 0xFFFF); 6322 break; 6323 case 2 : 6324 ddi_put16(fdc->c_handlep_dma, 6325 (ushort_t *)&dma_reg->sb_dma_regs[DMA_2WCNT], 6326 count & 0xFFFF); 6327 break; 6328 case 3 : 6329 ddi_put16(fdc->c_handlep_dma, 6330 (ushort_t *)&dma_reg->sb_dma_regs[DMA_3WCNT], 6331 count & 0xFFFF); 6332 break; 6333 default : 6334 FDERRPRINT(FDEP_L3, FDEM_SDMA, 6335 (C, "set_data_count: wrong channel %x\n", 6336 fdc->sb_dma_channel)); 6337 break; 6338 } 6339 } 6340 } 6341 6342 /* 6343 * get_data_count_register(struct fdctlr *fdc) 6344 * Read the data count from appropriate dma register. 6345 */ 6346 6347 static uint32_t 6348 get_data_count_register(struct fdctlr *fdc) 6349 { 6350 uint32_t retval = 0; 6351 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 6352 struct cheerio_dma_reg *dma_reg; 6353 dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs; 6354 retval = ddi_get32(fdc->c_handlep_dma, &dma_reg->fdc_dbcr); 6355 } else if (fdc->c_fdtype & FDCTYPE_SB) { 6356 struct sb_dma_reg *dma_reg; 6357 dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs; 6358 switch (fdc->sb_dma_channel) { 6359 case 0 : 6360 retval = ddi_get16(fdc->c_handlep_dma, 6361 (ushort_t *)&dma_reg->sb_dma_regs[DMA_0WCNT]); 6362 break; 6363 case 1 : 6364 retval = ddi_get16(fdc->c_handlep_dma, 6365 (ushort_t *)&dma_reg->sb_dma_regs[DMA_1WCNT]); 6366 break; 6367 case 2 : 6368 retval = ddi_get16(fdc->c_handlep_dma, 6369 (ushort_t *)&dma_reg->sb_dma_regs[DMA_2WCNT]); 6370 break; 6371 case 3 : 6372 retval = ddi_get16(fdc->c_handlep_dma, 6373 (ushort_t *)&dma_reg->sb_dma_regs[DMA_3WCNT]); 6374 break; 6375 default : 6376 FDERRPRINT(FDEP_L3, FDEM_SDMA, 6377 (C, "get_data_count: wrong channel %x\n", 6378 fdc->sb_dma_channel)); 6379 break; 6380 } 6381 retval = (uint32_t)((uint16_t)(retval +1)); 6382 } 6383 6384 return (retval); 6385 6386 } 6387 6388 /* 6389 * reset_dma_controller(struct fdctlr *fdc) 6390 * Reset and initialize the dma controller. 6391 */ 6392 6393 static void 6394 reset_dma_controller(struct fdctlr *fdc) 6395 { 6396 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 6397 struct cheerio_dma_reg *dma_reg; 6398 dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs; 6399 ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, DCSR_RESET); 6400 while (get_dma_control_register(fdc) & DCSR_CYC_PEND); 6401 ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, 0); 6402 } else if (fdc->c_fdtype & FDCTYPE_SB) { 6403 struct sb_dma_reg *dma_reg; 6404 dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs; 6405 ddi_put8(fdc->c_handlep_dma, &dma_reg->sb_dma_regs[DMAC1_MASK], 6406 (fdc->sb_dma_channel & 0x3)); 6407 6408 } 6409 } 6410 6411 /* 6412 * Get the DMA control register for CHEERIO. 6413 * For SouthBridge 8237 DMA controller, this register is not valid. 6414 * So, just return 0. 6415 */ 6416 static uint32_t 6417 get_dma_control_register(struct fdctlr *fdc) 6418 { 6419 uint32_t retval = 0; 6420 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 6421 struct cheerio_dma_reg *dma_reg; 6422 dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs; 6423 retval = ddi_get32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr); 6424 } 6425 6426 return (retval); 6427 } 6428 6429 6430 /* 6431 * set_data_address_register(struct fdctlr *fdc) 6432 * Set the data address in appropriate dma register. 6433 */ 6434 static void 6435 set_data_address_register(struct fdctlr *fdc, uint32_t address) 6436 { 6437 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 6438 struct cheerio_dma_reg *dma_reg; 6439 dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs; 6440 ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dacr, address); 6441 } else if (fdc->c_fdtype & FDCTYPE_SB) { 6442 struct sb_dma_reg *dma_reg; 6443 dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs; 6444 switch (fdc->sb_dma_channel) { 6445 case 0 : 6446 ddi_put8(fdc->c_handlep_dma, 6447 &dma_reg->sb_dma_regs[DMA_0PAGE], 6448 (address & 0xFF0000) >>16); 6449 ddi_put8(fdc->c_handlep_dma, 6450 &dma_reg->sb_dma_regs[DMA_0HPG], 6451 (address & 0xFF000000) >>24); 6452 ddi_put16(fdc->c_handlep_dma, 6453 (ushort_t *)&dma_reg->sb_dma_regs[DMA_0ADR], 6454 address & 0xFFFF); 6455 break; 6456 case 1 : 6457 ddi_put8(fdc->c_handlep_dma, 6458 &dma_reg->sb_dma_regs[DMA_1PAGE], 6459 (address & 0xFF0000) >>16); 6460 ddi_put8(fdc->c_handlep_dma, 6461 &dma_reg->sb_dma_regs[DMA_1HPG], 6462 (address & 0xFF000000) >>24); 6463 ddi_put16(fdc->c_handlep_dma, 6464 (ushort_t *)&dma_reg->sb_dma_regs[DMA_1ADR], 6465 address & 0xFFFF); 6466 break; 6467 case 2 : 6468 ddi_put8(fdc->c_handlep_dma, 6469 &dma_reg->sb_dma_regs[DMA_2PAGE], 6470 (address & 0xFF0000) >>16); 6471 ddi_put8(fdc->c_handlep_dma, 6472 &dma_reg->sb_dma_regs[DMA_2HPG], 6473 (address & 0xFF000000) >>24); 6474 ddi_put16(fdc->c_handlep_dma, 6475 (ushort_t *)&dma_reg->sb_dma_regs[DMA_2ADR], 6476 address & 0xFFFF); 6477 break; 6478 case 3 : 6479 ddi_put8(fdc->c_handlep_dma, 6480 &dma_reg->sb_dma_regs[DMA_3PAGE], 6481 (address & 0xFF0000) >>16); 6482 ddi_put8(fdc->c_handlep_dma, 6483 &dma_reg->sb_dma_regs[DMA_3HPG], 6484 (address & 0xFF000000) >>24); 6485 ddi_put16(fdc->c_handlep_dma, 6486 (ushort_t *)&dma_reg->sb_dma_regs[DMA_3ADR], 6487 address & 0xFFFF); 6488 break; 6489 default : 6490 FDERRPRINT(FDEP_L3, FDEM_SDMA, 6491 (C, "set_data_address: wrong channel %x\n", 6492 fdc->sb_dma_channel)); 6493 break; 6494 } 6495 } 6496 6497 } 6498 6499 6500 /* 6501 * set_dma_mode(struct fdctlr *fdc, int val) 6502 * Set the appropriate dma direction and registers. 6503 */ 6504 static void 6505 set_dma_mode(struct fdctlr *fdc, int val) 6506 { 6507 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 6508 struct cheerio_dma_reg *dma_reg; 6509 dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs; 6510 if (val == CSB_READ) 6511 ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, 6512 DCSR_INIT_BITS|DCSR_WRITE); 6513 else 6514 ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, 6515 DCSR_INIT_BITS); 6516 6517 } else if (fdc->c_fdtype & FDCTYPE_SB) { 6518 uint8_t mode_reg_val, chn_mask; 6519 struct sb_dma_reg *dma_reg; 6520 dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs; 6521 6522 if (val == CSB_READ) { 6523 mode_reg_val = fdc->sb_dma_channel | DMAMODE_READ 6524 | DMAMODE_SINGLE; 6525 } else { /* Read operation */ 6526 mode_reg_val = fdc->sb_dma_channel | DMAMODE_WRITE 6527 | DMAMODE_SINGLE; 6528 } 6529 ddi_put8(fdc->c_handlep_dma, &dma_reg->sb_dma_regs[DMAC1_MODE], 6530 mode_reg_val); 6531 chn_mask = 1 << (fdc->sb_dma_channel & 0x3); 6532 ddi_put8(fdc->c_handlep_dma, 6533 &dma_reg->sb_dma_regs[DMAC1_ALLMASK], ~chn_mask); 6534 fdc->sb_dma_lock = 1; 6535 } 6536 } 6537 6538 /* 6539 * This function is valid only for CHEERIO/RIO based 6540 * controllers. The control register for the dma channel 6541 * is initialized by this function. 6542 */ 6543 6544 static void 6545 set_dma_control_register(struct fdctlr *fdc, uint32_t val) 6546 { 6547 if (fdc->c_fdtype & FDCTYPE_CHEERIO) { 6548 struct cheerio_dma_reg *dma_reg; 6549 dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs; 6550 ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, val); 6551 } 6552 } 6553 6554 static void 6555 release_sb_dma(struct fdctlr *fdc) 6556 { 6557 struct sb_dma_reg *dma_reg; 6558 dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs; 6559 /* Unmask all the channels to release the DMA controller */ 6560 ddi_put8(fdc->c_handlep_dma, 6561 &dma_reg->sb_dma_regs[DMAC1_ALLMASK], NULL); 6562 fdc->sb_dma_lock = 0; 6563 } 6564 6565 static void 6566 quiesce_fd_interrupt(struct fdctlr *fdc) 6567 { 6568 /* 6569 * The following code is put here to take care of HW problem. 6570 * The HW problem is as follows: 6571 * 6572 * After poweron the Southbridge floppy controller asserts the 6573 * interrupt in tristate. This causes continuous interrupts to 6574 * be generated. 6575 * Until the Hardware is FIXED we will have to use the following code 6576 * to set the interrupt line to proper state after poweron. 6577 */ 6578 if (fdc->c_fdtype & FDCTYPE_SB) { 6579 ddi_put8(fdc->c_handlep_cont, ((uint8_t *)fdc->c_dor), 6580 0x0); 6581 drv_usecwait(200); 6582 ddi_put8(fdc->c_handlep_cont, ((uint8_t *)fdc->c_dor), 6583 0xC); 6584 drv_usecwait(200); 6585 Set_Fifo(fdc, 0xE6); 6586 drv_usecwait(200); 6587 } 6588 } 6589