1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright 2018 Joyent, Inc. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34 * Copyright 2018 Nexenta Systems, Inc. 35 */ 36 37 #ifndef _SYS_X86_ARCHEXT_H 38 #define _SYS_X86_ARCHEXT_H 39 40 #if !defined(_ASM) 41 #include <sys/regset.h> 42 #include <sys/processor.h> 43 #include <vm/seg_enum.h> 44 #include <vm/page.h> 45 #endif /* _ASM */ 46 47 #ifdef __cplusplus 48 extern "C" { 49 #endif 50 51 /* 52 * cpuid instruction feature flags in %edx (standard function 1) 53 */ 54 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 65 /* 0x400 - reserved */ 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 75 /* 0x100000 - reserved */ 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 87 88 /* 89 * cpuid instruction feature flags in %ecx (standard function 1) 90 */ 91 92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 94 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 103 /* 0x00000800 - reserved */ 104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 107 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 108 /* 0x00010000 - reserved */ 109 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 116 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 124 125 /* 126 * cpuid instruction feature flags in %edx (extended function 0x80000001) 127 */ 128 129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 137 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 138 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 139 /* 0x00000400 - sysc on K6m6 */ 140 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 141 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 142 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 143 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 144 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 145 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 146 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 147 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 148 /* 0x00040000 - reserved */ 149 /* 0x00080000 - reserved */ 150 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 151 /* 0x00200000 - reserved */ 152 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 153 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 158 /* 0x10000000 - reserved */ 159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 162 163 /* 164 * AMD extended function 0x80000001 %ecx 165 */ 166 167 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 168 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 169 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 170 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 171 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 172 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 173 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 174 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 175 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 176 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 177 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 178 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */ 179 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 180 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 181 /* 0x00004000 - reserved */ 182 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 183 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 184 /* 0x00020000 - reserved */ 185 /* 0x00040000 - reserved */ 186 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 187 /* 0x00100000 - reserved */ 188 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 189 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 190 #define CPUID_AMD_ECX_PCEC 0x00800000 /* AMD: Core ext perf counter */ 191 192 /* 193 * Intel now seems to have claimed part of the "extended" function 194 * space that we previously for non-Intel implementors to use. 195 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 196 * is available in long mode i.e. what AMD indicate using bit 0. 197 * On the other hand, everything else is labelled as reserved. 198 */ 199 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 200 201 /* 202 * Intel also uses cpuid leaf 7 to have additional instructions and features. 203 * Like some other leaves, but unlike the current ones we care about, it 204 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 205 * with the potential use of additional sub-leaves in the future, we now 206 * specifically label the EBX features with their leaf and sub-leaf. 207 */ 208 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 209 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 210 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 211 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 212 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 213 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 214 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 215 216 #define REG_PAT 0x277 217 #define REG_TSC 0x10 /* timestamp counter */ 218 #define REG_APIC_BASE_MSR 0x1b 219 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 220 221 #if !defined(__xpv) 222 /* 223 * AMD C1E 224 */ 225 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 226 #define AMD_ACTONCMPHALT_SHIFT 27 227 #define AMD_ACTONCMPHALT_MASK 3 228 #endif 229 230 #define MSR_DEBUGCTL 0x1d9 231 232 #define DEBUGCTL_LBR 0x01 233 #define DEBUGCTL_BTF 0x02 234 235 /* Intel P6, AMD */ 236 #define MSR_LBR_FROM 0x1db 237 #define MSR_LBR_TO 0x1dc 238 #define MSR_LEX_FROM 0x1dd 239 #define MSR_LEX_TO 0x1de 240 241 /* Intel P4 (pre-Prescott, non P4 M) */ 242 #define MSR_P4_LBSTK_TOS 0x1da 243 #define MSR_P4_LBSTK_0 0x1db 244 #define MSR_P4_LBSTK_1 0x1dc 245 #define MSR_P4_LBSTK_2 0x1dd 246 #define MSR_P4_LBSTK_3 0x1de 247 248 /* Intel Pentium M */ 249 #define MSR_P6M_LBSTK_TOS 0x1c9 250 #define MSR_P6M_LBSTK_0 0x040 251 #define MSR_P6M_LBSTK_1 0x041 252 #define MSR_P6M_LBSTK_2 0x042 253 #define MSR_P6M_LBSTK_3 0x043 254 #define MSR_P6M_LBSTK_4 0x044 255 #define MSR_P6M_LBSTK_5 0x045 256 #define MSR_P6M_LBSTK_6 0x046 257 #define MSR_P6M_LBSTK_7 0x047 258 259 /* Intel P4 (Prescott) */ 260 #define MSR_PRP4_LBSTK_TOS 0x1da 261 #define MSR_PRP4_LBSTK_FROM_0 0x680 262 #define MSR_PRP4_LBSTK_FROM_1 0x681 263 #define MSR_PRP4_LBSTK_FROM_2 0x682 264 #define MSR_PRP4_LBSTK_FROM_3 0x683 265 #define MSR_PRP4_LBSTK_FROM_4 0x684 266 #define MSR_PRP4_LBSTK_FROM_5 0x685 267 #define MSR_PRP4_LBSTK_FROM_6 0x686 268 #define MSR_PRP4_LBSTK_FROM_7 0x687 269 #define MSR_PRP4_LBSTK_FROM_8 0x688 270 #define MSR_PRP4_LBSTK_FROM_9 0x689 271 #define MSR_PRP4_LBSTK_FROM_10 0x68a 272 #define MSR_PRP4_LBSTK_FROM_11 0x68b 273 #define MSR_PRP4_LBSTK_FROM_12 0x68c 274 #define MSR_PRP4_LBSTK_FROM_13 0x68d 275 #define MSR_PRP4_LBSTK_FROM_14 0x68e 276 #define MSR_PRP4_LBSTK_FROM_15 0x68f 277 #define MSR_PRP4_LBSTK_TO_0 0x6c0 278 #define MSR_PRP4_LBSTK_TO_1 0x6c1 279 #define MSR_PRP4_LBSTK_TO_2 0x6c2 280 #define MSR_PRP4_LBSTK_TO_3 0x6c3 281 #define MSR_PRP4_LBSTK_TO_4 0x6c4 282 #define MSR_PRP4_LBSTK_TO_5 0x6c5 283 #define MSR_PRP4_LBSTK_TO_6 0x6c6 284 #define MSR_PRP4_LBSTK_TO_7 0x6c7 285 #define MSR_PRP4_LBSTK_TO_8 0x6c8 286 #define MSR_PRP4_LBSTK_TO_9 0x6c9 287 #define MSR_PRP4_LBSTK_TO_10 0x6ca 288 #define MSR_PRP4_LBSTK_TO_11 0x6cb 289 #define MSR_PRP4_LBSTK_TO_12 0x6cc 290 #define MSR_PRP4_LBSTK_TO_13 0x6cd 291 #define MSR_PRP4_LBSTK_TO_14 0x6ce 292 #define MSR_PRP4_LBSTK_TO_15 0x6cf 293 294 #define MCI_CTL_VALUE 0xffffffff 295 296 #define MTRR_TYPE_UC 0 297 #define MTRR_TYPE_WC 1 298 #define MTRR_TYPE_WT 4 299 #define MTRR_TYPE_WP 5 300 #define MTRR_TYPE_WB 6 301 #define MTRR_TYPE_UC_ 7 302 303 /* 304 * For Solaris we set up the page attritubute table in the following way: 305 * PAT0 Write-Back 306 * PAT1 Write-Through 307 * PAT2 Unchacheable- 308 * PAT3 Uncacheable 309 * PAT4 Write-Back 310 * PAT5 Write-Through 311 * PAT6 Write-Combine 312 * PAT7 Uncacheable 313 * The only difference from h/w default is entry 6. 314 */ 315 #define PAT_DEFAULT_ATTRIBUTE \ 316 ((uint64_t)MTRR_TYPE_WB | \ 317 ((uint64_t)MTRR_TYPE_WT << 8) | \ 318 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 319 ((uint64_t)MTRR_TYPE_UC << 24) | \ 320 ((uint64_t)MTRR_TYPE_WB << 32) | \ 321 ((uint64_t)MTRR_TYPE_WT << 40) | \ 322 ((uint64_t)MTRR_TYPE_WC << 48) | \ 323 ((uint64_t)MTRR_TYPE_UC << 56)) 324 325 #define X86FSET_LARGEPAGE 0 326 #define X86FSET_TSC 1 327 #define X86FSET_MSR 2 328 #define X86FSET_MTRR 3 329 #define X86FSET_PGE 4 330 #define X86FSET_DE 5 331 #define X86FSET_CMOV 6 332 #define X86FSET_MMX 7 333 #define X86FSET_MCA 8 334 #define X86FSET_PAE 9 335 #define X86FSET_CX8 10 336 #define X86FSET_PAT 11 337 #define X86FSET_SEP 12 338 #define X86FSET_SSE 13 339 #define X86FSET_SSE2 14 340 #define X86FSET_HTT 15 341 #define X86FSET_ASYSC 16 342 #define X86FSET_NX 17 343 #define X86FSET_SSE3 18 344 #define X86FSET_CX16 19 345 #define X86FSET_CMP 20 346 #define X86FSET_TSCP 21 347 #define X86FSET_MWAIT 22 348 #define X86FSET_SSE4A 23 349 #define X86FSET_CPUID 24 350 #define X86FSET_SSSE3 25 351 #define X86FSET_SSE4_1 26 352 #define X86FSET_SSE4_2 27 353 #define X86FSET_1GPG 28 354 #define X86FSET_CLFSH 29 355 #define X86FSET_64 30 356 #define X86FSET_AES 31 357 #define X86FSET_PCLMULQDQ 32 358 #define X86FSET_XSAVE 33 359 #define X86FSET_AVX 34 360 #define X86FSET_VMX 35 361 #define X86FSET_SVM 36 362 #define X86FSET_TOPOEXT 37 363 #define X86FSET_F16C 38 364 #define X86FSET_RDRAND 39 365 #define X86FSET_X2APIC 40 366 #define X86FSET_AVX2 41 367 #define X86FSET_BMI1 42 368 #define X86FSET_BMI2 43 369 #define X86FSET_FMA 44 370 #define X86FSET_SMEP 45 371 #define X86FSET_ADX 47 372 #define X86FSET_RDSEED 48 373 #define X86FSET_AMD_PCEC 92 374 375 /* 376 * Intel Deep C-State invariant TSC in leaf 0x80000007. 377 */ 378 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 379 380 /* 381 * Intel Deep C-state always-running local APIC timer 382 */ 383 #define CPUID_CSTATE_ARAT (0x4) 384 385 /* 386 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 387 */ 388 #define CPUID_EPB_SUPPORT (1 << 3) 389 390 /* 391 * Intel TSC deadline timer 392 */ 393 #define CPUID_DEADLINE_TSC (1 << 24) 394 395 /* 396 * x86_type is a legacy concept; this is supplanted 397 * for most purposes by x86_featureset; modern CPUs 398 * should be X86_TYPE_OTHER 399 */ 400 #define X86_TYPE_OTHER 0 401 #define X86_TYPE_486 1 402 #define X86_TYPE_P5 2 403 #define X86_TYPE_P6 3 404 #define X86_TYPE_CYRIX_486 4 405 #define X86_TYPE_CYRIX_6x86L 5 406 #define X86_TYPE_CYRIX_6x86 6 407 #define X86_TYPE_CYRIX_GXm 7 408 #define X86_TYPE_CYRIX_6x86MX 8 409 #define X86_TYPE_CYRIX_MediaGX 9 410 #define X86_TYPE_CYRIX_MII 10 411 #define X86_TYPE_VIA_CYRIX_III 11 412 #define X86_TYPE_P4 12 413 414 /* 415 * x86_vendor allows us to select between 416 * implementation features and helps guide 417 * the interpretation of the cpuid instruction. 418 */ 419 #define X86_VENDOR_Intel 0 420 #define X86_VENDORSTR_Intel "GenuineIntel" 421 422 #define X86_VENDOR_IntelClone 1 423 424 #define X86_VENDOR_AMD 2 425 #define X86_VENDORSTR_AMD "AuthenticAMD" 426 427 #define X86_VENDOR_Cyrix 3 428 #define X86_VENDORSTR_CYRIX "CyrixInstead" 429 430 #define X86_VENDOR_UMC 4 431 #define X86_VENDORSTR_UMC "UMC UMC UMC " 432 433 #define X86_VENDOR_NexGen 5 434 #define X86_VENDORSTR_NexGen "NexGenDriven" 435 436 #define X86_VENDOR_Centaur 6 437 #define X86_VENDORSTR_Centaur "CentaurHauls" 438 439 #define X86_VENDOR_Rise 7 440 #define X86_VENDORSTR_Rise "RiseRiseRise" 441 442 #define X86_VENDOR_SiS 8 443 #define X86_VENDORSTR_SiS "SiS SiS SiS " 444 445 #define X86_VENDOR_TM 9 446 #define X86_VENDORSTR_TM "GenuineTMx86" 447 448 #define X86_VENDOR_NSC 10 449 #define X86_VENDORSTR_NSC "Geode by NSC" 450 451 /* 452 * Vendor string max len + \0 453 */ 454 #define X86_VENDOR_STRLEN 13 455 456 /* 457 * Some vendor/family/model/stepping ranges are commonly grouped under 458 * a single identifying banner by the vendor. The following encode 459 * that "revision" in a uint32_t with the 8 most significant bits 460 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 461 * family, and the remaining 16 typically forming a bitmask of revisions 462 * within that family with more significant bits indicating "later" revisions. 463 */ 464 465 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 466 #define _X86_CHIPREV_VENDOR_SHIFT 24 467 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 468 #define _X86_CHIPREV_FAMILY_SHIFT 16 469 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 470 471 #define _X86_CHIPREV_VENDOR(x) \ 472 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 473 #define _X86_CHIPREV_FAMILY(x) \ 474 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 475 #define _X86_CHIPREV_REV(x) \ 476 ((x) & _X86_CHIPREV_REV_MASK) 477 478 /* True if x matches in vendor and family and if x matches the given rev mask */ 479 #define X86_CHIPREV_MATCH(x, mask) \ 480 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 481 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 482 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 483 484 /* True if x matches in vendor and family, and rev is at least minx */ 485 #define X86_CHIPREV_ATLEAST(x, minx) \ 486 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 487 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 488 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 489 490 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 491 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 492 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 493 494 /* True if x matches in vendor, and family is at least minx */ 495 #define X86_CHIPFAM_ATLEAST(x, minx) \ 496 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 497 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 498 499 /* Revision default */ 500 #define X86_CHIPREV_UNKNOWN 0x0 501 502 /* 503 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 504 * sufficiently different that we will distinguish them; in all other 505 * case we will identify the major revision. 506 */ 507 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 508 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 509 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 510 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 511 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 512 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 513 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 514 515 /* 516 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 517 */ 518 #define X86_CHIPREV_AMD_10_REV_A \ 519 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 520 #define X86_CHIPREV_AMD_10_REV_B \ 521 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 522 #define X86_CHIPREV_AMD_10_REV_C2 \ 523 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 524 #define X86_CHIPREV_AMD_10_REV_C3 \ 525 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 526 #define X86_CHIPREV_AMD_10_REV_D0 \ 527 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 528 #define X86_CHIPREV_AMD_10_REV_D1 \ 529 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 530 #define X86_CHIPREV_AMD_10_REV_E \ 531 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 532 533 /* 534 * Definitions for AMD Family 0x11. 535 */ 536 #define X86_CHIPREV_AMD_11_REV_B \ 537 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 538 539 /* 540 * Definitions for AMD Family 0x12. 541 */ 542 #define X86_CHIPREV_AMD_12_REV_B \ 543 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 544 545 /* 546 * Definitions for AMD Family 0x14. 547 */ 548 #define X86_CHIPREV_AMD_14_REV_B \ 549 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 550 #define X86_CHIPREV_AMD_14_REV_C \ 551 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 552 553 /* 554 * Definitions for AMD Family 0x15 555 */ 556 #define X86_CHIPREV_AMD_15OR_REV_B2 \ 557 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 558 559 #define X86_CHIPREV_AMD_15TN_REV_A1 \ 560 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 561 562 /* 563 * Various socket/package types, extended as the need to distinguish 564 * a new type arises. The top 8 byte identfies the vendor and the 565 * remaining 24 bits describe 24 socket types. 566 */ 567 568 #define _X86_SOCKET_VENDOR_SHIFT 24 569 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 570 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 571 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 572 573 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 574 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 575 576 #define X86_SOCKET_MATCH(s, mask) \ 577 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 578 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 579 580 #define X86_SOCKET_UNKNOWN 0x0 581 /* 582 * AMD socket types 583 */ 584 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 585 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 586 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 587 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 588 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 589 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 590 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 591 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 592 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 593 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 594 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 595 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 596 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 597 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 598 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000) 599 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000) 600 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000) 601 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000) 602 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000) 603 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000) 604 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000) 605 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000) 606 607 608 /* 609 * Definitions for Intel processor models. These are all for Family 6 610 * processors. This list and the Atom set below it are not exhuastive. 611 */ 612 #define INTC_MODEL_MEROM 0x0f 613 #define INTC_MODEL_PENRYN 0x17 614 #define INTC_MODEL_DUNNINGTON 0x1d 615 616 #define INTC_MODEL_NEHALEM 0x1e 617 #define INTC_MODEL_NEHALEM2 0x1f 618 #define INTC_MODEL_NEHALEM_EP 0x1a 619 #define INTC_MODEL_NEHALEM_EX 0x2e 620 621 #define INTC_MODEL_WESTMERE 0x25 622 #define INTC_MODEL_WESTMERE_EP 0x2c 623 #define INTC_MODEL_WESTMERE_EX 0x2f 624 625 #define INTC_MODEL_SANDYBRIDGE 0x2a 626 #define INTC_MODEL_SANDYBRIDGE_XEON 0x2d 627 #define INTC_MODEL_IVYBRIDGE 0x3a 628 #define INTC_MODEL_IVYBRIDGE_XEON 0x3e 629 630 #define INTC_MODEL_HASWELL 0x3c 631 #define INTC_MODEL_HASWELL_ULT 0x45 632 #define INTC_MODEL_HASWELL_GT3E 0x46 633 #define INTC_MODEL_HASWELL_XEON 0x3f 634 635 #define INTC_MODEL_BROADWELL 0x3d 636 #define INTC_MODEL_BROADELL_2 0x47 637 #define INTC_MODEL_BROADWELL_XEON 0x4f 638 639 #define INCC_MODEL_SKYLAKE_MOBILE 0x4e 640 #define INTC_MODEL_SKYLAKE_DESKTOP 0x5e 641 642 #define INTC_MODEL_KABYLAKE_MOBILE 0x8e 643 #define INTC_MODEL_KABYLAKE_DESKTOP 0x9e 644 645 /* 646 * Atom Processors 647 */ 648 #define INTC_MODEL_SILVERTHORNE 0x1c 649 #define INTC_MODEL_LINCROFT 0x26 650 #define INTC_MODEL_PENWELL 0x27 651 #define INTC_MODEL_CLOVERVIEW 0x35 652 #define INTC_MODEL_CEDARVIEW 0x36 653 #define INTC_MODEL_BAY_TRAIL 0x37 654 #define INTC_MODEL_AVATON 0x4d 655 #define INTC_MODEL_AIRMONT 0x4c 656 #define INTC_MODEL_GOLDMONT 0x5c 657 #define INTC_MODEL_DENVERTON 0x5f 658 #define INTC_MODEL_GEMINI_LAKE 0x7a 659 660 /* 661 * xgetbv/xsetbv support 662 */ 663 664 #define XFEATURE_ENABLED_MASK 0x0 665 /* 666 * XFEATURE_ENABLED_MASK values (eax) 667 */ 668 #define XFEATURE_LEGACY_FP 0x1 669 #define XFEATURE_SSE 0x2 670 #define XFEATURE_AVX 0x4 671 #define XFEATURE_MAX XFEATURE_AVX 672 #define XFEATURE_FP_ALL \ 673 (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX) 674 675 #if !defined(_ASM) 676 677 #if defined(_KERNEL) || defined(_KMEMUSER) 678 679 #define NUM_X86_FEATURES 93 680 extern uchar_t x86_featureset[]; 681 682 extern void free_x86_featureset(void *featureset); 683 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 684 extern void add_x86_feature(void *featureset, uint_t feature); 685 extern void remove_x86_feature(void *featureset, uint_t feature); 686 extern boolean_t compare_x86_featureset(void *setA, void *setB); 687 extern void print_x86_featureset(void *featureset); 688 689 690 extern uint_t x86_type; 691 extern uint_t x86_vendor; 692 extern uint_t x86_clflush_size; 693 694 extern uint_t pentiumpro_bug4046376; 695 696 extern const char CyrixInstead[]; 697 698 #endif 699 700 #if defined(_KERNEL) 701 702 /* 703 * This structure is used to pass arguments and get return values back 704 * from the CPUID instruction in __cpuid_insn() routine. 705 */ 706 struct cpuid_regs { 707 uint32_t cp_eax; 708 uint32_t cp_ebx; 709 uint32_t cp_ecx; 710 uint32_t cp_edx; 711 }; 712 713 /* 714 * Utility functions to get/set extended control registers (XCR) 715 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 716 */ 717 extern uint64_t get_xcr(uint_t); 718 extern void set_xcr(uint_t, uint64_t); 719 720 extern uint64_t rdmsr(uint_t); 721 extern void wrmsr(uint_t, const uint64_t); 722 extern uint64_t xrdmsr(uint_t); 723 extern void xwrmsr(uint_t, const uint64_t); 724 extern int checked_rdmsr(uint_t, uint64_t *); 725 extern int checked_wrmsr(uint_t, uint64_t); 726 727 extern void invalidate_cache(void); 728 extern ulong_t getcr4(void); 729 extern void setcr4(ulong_t); 730 731 extern void mtrr_sync(void); 732 733 extern void cpu_fast_syscall_enable(void *); 734 extern void cpu_fast_syscall_disable(void *); 735 736 struct cpu; 737 738 extern int cpuid_checkpass(struct cpu *, int); 739 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 740 extern uint32_t __cpuid_insn(struct cpuid_regs *); 741 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 742 extern int cpuid_getidstr(struct cpu *, char *, size_t); 743 extern const char *cpuid_getvendorstr(struct cpu *); 744 extern uint_t cpuid_getvendor(struct cpu *); 745 extern uint_t cpuid_getfamily(struct cpu *); 746 extern uint_t cpuid_getmodel(struct cpu *); 747 extern uint_t cpuid_getstep(struct cpu *); 748 extern uint_t cpuid_getsig(struct cpu *); 749 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 750 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 751 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 752 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 753 extern int cpuid_get_chipid(struct cpu *); 754 extern id_t cpuid_get_coreid(struct cpu *); 755 extern int cpuid_get_pkgcoreid(struct cpu *); 756 extern int cpuid_get_clogid(struct cpu *); 757 extern int cpuid_get_cacheid(struct cpu *); 758 extern uint32_t cpuid_get_apicid(struct cpu *); 759 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 760 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 761 extern uint_t cpuid_get_compunitid(struct cpu *cpu); 762 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 763 extern int cpuid_is_cmt(struct cpu *); 764 extern int cpuid_syscall32_insn(struct cpu *); 765 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 766 767 extern uint32_t cpuid_getchiprev(struct cpu *); 768 extern const char *cpuid_getchiprevstr(struct cpu *); 769 extern uint32_t cpuid_getsockettype(struct cpu *); 770 extern const char *cpuid_getsocketstr(struct cpu *); 771 772 extern int cpuid_have_cr8access(struct cpu *); 773 774 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 775 776 struct cpuid_info; 777 778 extern void setx86isalist(void); 779 extern void cpuid_alloc_space(struct cpu *); 780 extern void cpuid_free_space(struct cpu *); 781 extern void cpuid_pass1(struct cpu *, uchar_t *); 782 extern void cpuid_pass2(struct cpu *); 783 extern void cpuid_pass3(struct cpu *); 784 extern void cpuid_pass4(struct cpu *, uint_t *); 785 extern void cpuid_set_cpu_properties(void *, processorid_t, 786 struct cpuid_info *); 787 788 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 789 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 790 791 #if !defined(__xpv) 792 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 793 extern void cpuid_mwait_free(struct cpu *); 794 extern int cpuid_deep_cstates_supported(void); 795 extern int cpuid_arat_supported(void); 796 extern int cpuid_iepb_supported(struct cpu *); 797 extern int cpuid_deadline_tsc_supported(void); 798 extern void vmware_port(int, uint32_t *); 799 #endif 800 801 struct cpu_ucode_info; 802 803 extern void ucode_alloc_space(struct cpu *); 804 extern void ucode_free_space(struct cpu *); 805 extern void ucode_check(struct cpu *); 806 extern void ucode_cleanup(); 807 808 #if !defined(__xpv) 809 extern char _tsc_mfence_start; 810 extern char _tsc_mfence_end; 811 extern char _tscp_start; 812 extern char _tscp_end; 813 extern char _no_rdtsc_start; 814 extern char _no_rdtsc_end; 815 extern char _tsc_lfence_start; 816 extern char _tsc_lfence_end; 817 #endif 818 819 #if !defined(__xpv) 820 extern char bcopy_patch_start; 821 extern char bcopy_patch_end; 822 extern char bcopy_ck_size; 823 #endif 824 825 extern void post_startup_cpu_fixups(void); 826 827 extern uint_t workaround_errata(struct cpu *); 828 829 #if defined(OPTERON_ERRATUM_93) 830 extern int opteron_erratum_93; 831 #endif 832 833 #if defined(OPTERON_ERRATUM_91) 834 extern int opteron_erratum_91; 835 #endif 836 837 #if defined(OPTERON_ERRATUM_100) 838 extern int opteron_erratum_100; 839 #endif 840 841 #if defined(OPTERON_ERRATUM_121) 842 extern int opteron_erratum_121; 843 #endif 844 845 #if defined(OPTERON_WORKAROUND_6323525) 846 extern int opteron_workaround_6323525; 847 extern void patch_workaround_6323525(void); 848 #endif 849 850 #if !defined(__xpv) 851 extern void determine_platform(void); 852 #endif 853 extern int get_hwenv(void); 854 extern int is_controldom(void); 855 856 extern void xsave_setup_msr(struct cpu *); 857 858 /* 859 * Hypervisor signatures 860 */ 861 #define HVSIG_XEN_HVM "XenVMMXenVMM" 862 #define HVSIG_VMWARE "VMwareVMware" 863 #define HVSIG_KVM "KVMKVMKVM" 864 #define HVSIG_MICROSOFT "Microsoft Hv" 865 866 /* 867 * Defined hardware environments 868 */ 869 #define HW_NATIVE (1 << 0) /* Running on bare metal */ 870 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 871 872 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 873 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 874 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 875 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 876 877 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT) 878 879 #endif /* _KERNEL */ 880 881 #endif /* !_ASM */ 882 883 /* 884 * VMware hypervisor related defines 885 */ 886 #define VMWARE_HVMAGIC 0x564d5868 887 #define VMWARE_HVPORT 0x5658 888 #define VMWARE_HVCMD_GETVERSION 0x0a 889 #define VMWARE_HVCMD_GETTSCFREQ 0x2d 890 891 #ifdef __cplusplus 892 } 893 #endif 894 895 #endif /* _SYS_X86_ARCHEXT_H */ 896