xref: /titanic_52/usr/src/uts/intel/sys/x86_archext.h (revision 0ba00e7a9ccbe1b6eb17ffb9692d015a7929e11f)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23  * Copyright (c) 2011 by Delphix. All rights reserved.
24  * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25  */
26 /*
27  * Copyright (c) 2010, Intel Corporation.
28  * All rights reserved.
29  */
30 /*
31  * Copyright 2016 Joyent, Inc.
32  * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
33  * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
34  * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
35  */
36 
37 #ifndef _SYS_X86_ARCHEXT_H
38 #define	_SYS_X86_ARCHEXT_H
39 
40 #if !defined(_ASM)
41 #include <sys/regset.h>
42 #include <sys/processor.h>
43 #include <vm/seg_enum.h>
44 #include <vm/page.h>
45 #endif	/* _ASM */
46 
47 #ifdef	__cplusplus
48 extern "C" {
49 #endif
50 
51 /*
52  * cpuid instruction feature flags in %edx (standard function 1)
53  */
54 
55 #define	CPUID_INTC_EDX_FPU	0x00000001	/* x87 fpu present */
56 #define	CPUID_INTC_EDX_VME	0x00000002	/* virtual-8086 extension */
57 #define	CPUID_INTC_EDX_DE	0x00000004	/* debugging extensions */
58 #define	CPUID_INTC_EDX_PSE	0x00000008	/* page size extension */
59 #define	CPUID_INTC_EDX_TSC	0x00000010	/* time stamp counter */
60 #define	CPUID_INTC_EDX_MSR	0x00000020	/* rdmsr and wrmsr */
61 #define	CPUID_INTC_EDX_PAE	0x00000040	/* physical addr extension */
62 #define	CPUID_INTC_EDX_MCE	0x00000080	/* machine check exception */
63 #define	CPUID_INTC_EDX_CX8	0x00000100	/* cmpxchg8b instruction */
64 #define	CPUID_INTC_EDX_APIC	0x00000200	/* local APIC */
65 						/* 0x400 - reserved */
66 #define	CPUID_INTC_EDX_SEP	0x00000800	/* sysenter and sysexit */
67 #define	CPUID_INTC_EDX_MTRR	0x00001000	/* memory type range reg */
68 #define	CPUID_INTC_EDX_PGE	0x00002000	/* page global enable */
69 #define	CPUID_INTC_EDX_MCA	0x00004000	/* machine check arch */
70 #define	CPUID_INTC_EDX_CMOV	0x00008000	/* conditional move insns */
71 #define	CPUID_INTC_EDX_PAT	0x00010000	/* page attribute table */
72 #define	CPUID_INTC_EDX_PSE36	0x00020000	/* 36-bit pagesize extension */
73 #define	CPUID_INTC_EDX_PSN	0x00040000	/* processor serial number */
74 #define	CPUID_INTC_EDX_CLFSH	0x00080000	/* clflush instruction */
75 						/* 0x100000 - reserved */
76 #define	CPUID_INTC_EDX_DS	0x00200000	/* debug store exists */
77 #define	CPUID_INTC_EDX_ACPI	0x00400000	/* monitoring + clock ctrl */
78 #define	CPUID_INTC_EDX_MMX	0x00800000	/* MMX instructions */
79 #define	CPUID_INTC_EDX_FXSR	0x01000000	/* fxsave and fxrstor */
80 #define	CPUID_INTC_EDX_SSE	0x02000000	/* streaming SIMD extensions */
81 #define	CPUID_INTC_EDX_SSE2	0x04000000	/* SSE extensions */
82 #define	CPUID_INTC_EDX_SS	0x08000000	/* self-snoop */
83 #define	CPUID_INTC_EDX_HTT	0x10000000	/* Hyper Thread Technology */
84 #define	CPUID_INTC_EDX_TM	0x20000000	/* thermal monitoring */
85 #define	CPUID_INTC_EDX_IA64	0x40000000	/* Itanium emulating IA32 */
86 #define	CPUID_INTC_EDX_PBE	0x80000000	/* Pending Break Enable */
87 
88 /*
89  * cpuid instruction feature flags in %ecx (standard function 1)
90  */
91 
92 #define	CPUID_INTC_ECX_SSE3	0x00000001	/* Yet more SSE extensions */
93 #define	CPUID_INTC_ECX_PCLMULQDQ 0x00000002 	/* PCLMULQDQ insn */
94 						/* 0x00000004 - reserved */
95 #define	CPUID_INTC_ECX_MON	0x00000008	/* MONITOR/MWAIT */
96 #define	CPUID_INTC_ECX_DSCPL	0x00000010	/* CPL-qualified debug store */
97 #define	CPUID_INTC_ECX_VMX	0x00000020	/* Hardware VM extensions */
98 #define	CPUID_INTC_ECX_SMX	0x00000040	/* Secure mode extensions */
99 #define	CPUID_INTC_ECX_EST	0x00000080	/* enhanced SpeedStep */
100 #define	CPUID_INTC_ECX_TM2	0x00000100	/* thermal monitoring */
101 #define	CPUID_INTC_ECX_SSSE3	0x00000200	/* Supplemental SSE3 insns */
102 #define	CPUID_INTC_ECX_CID	0x00000400	/* L1 context ID */
103 						/* 0x00000800 - reserved */
104 #define	CPUID_INTC_ECX_FMA	0x00001000	/* Fused Multiply Add */
105 #define	CPUID_INTC_ECX_CX16	0x00002000	/* cmpxchg16 */
106 #define	CPUID_INTC_ECX_ETPRD	0x00004000	/* extended task pri messages */
107 						/* 0x00008000 - reserved */
108 						/* 0x00010000 - reserved */
109 						/* 0x00020000 - reserved */
110 #define	CPUID_INTC_ECX_DCA	0x00040000	/* direct cache access */
111 #define	CPUID_INTC_ECX_SSE4_1	0x00080000	/* SSE4.1 insns */
112 #define	CPUID_INTC_ECX_SSE4_2	0x00100000	/* SSE4.2 insns */
113 #define	CPUID_INTC_ECX_X2APIC	0x00200000	/* x2APIC */
114 #define	CPUID_INTC_ECX_MOVBE	0x00400000	/* MOVBE insn */
115 #define	CPUID_INTC_ECX_POPCNT	0x00800000	/* POPCNT insn */
116 #define	CPUID_INTC_ECX_AES	0x02000000	/* AES insns */
117 #define	CPUID_INTC_ECX_XSAVE	0x04000000	/* XSAVE/XRESTOR insns */
118 #define	CPUID_INTC_ECX_OSXSAVE	0x08000000	/* OS supports XSAVE insns */
119 #define	CPUID_INTC_ECX_AVX	0x10000000	/* AVX supported */
120 #define	CPUID_INTC_ECX_F16C	0x20000000	/* F16C supported */
121 #define	CPUID_INTC_ECX_RDRAND	0x40000000	/* RDRAND supported */
122 #define	CPUID_INTC_ECX_HV	0x80000000	/* Hypervisor */
123 
124 /*
125  * cpuid instruction feature flags in %edx (extended function 0x80000001)
126  */
127 
128 #define	CPUID_AMD_EDX_FPU	0x00000001	/* x87 fpu present */
129 #define	CPUID_AMD_EDX_VME	0x00000002	/* virtual-8086 extension */
130 #define	CPUID_AMD_EDX_DE	0x00000004	/* debugging extensions */
131 #define	CPUID_AMD_EDX_PSE	0x00000008	/* page size extensions */
132 #define	CPUID_AMD_EDX_TSC	0x00000010	/* time stamp counter */
133 #define	CPUID_AMD_EDX_MSR	0x00000020	/* rdmsr and wrmsr */
134 #define	CPUID_AMD_EDX_PAE	0x00000040	/* physical addr extension */
135 #define	CPUID_AMD_EDX_MCE	0x00000080	/* machine check exception */
136 #define	CPUID_AMD_EDX_CX8	0x00000100	/* cmpxchg8b instruction */
137 #define	CPUID_AMD_EDX_APIC	0x00000200	/* local APIC */
138 						/* 0x00000400 - sysc on K6m6 */
139 #define	CPUID_AMD_EDX_SYSC	0x00000800	/* AMD: syscall and sysret */
140 #define	CPUID_AMD_EDX_MTRR	0x00001000	/* memory type and range reg */
141 #define	CPUID_AMD_EDX_PGE	0x00002000	/* page global enable */
142 #define	CPUID_AMD_EDX_MCA	0x00004000	/* machine check arch */
143 #define	CPUID_AMD_EDX_CMOV	0x00008000	/* conditional move insns */
144 #define	CPUID_AMD_EDX_PAT	0x00010000	/* K7: page attribute table */
145 #define	CPUID_AMD_EDX_FCMOV	0x00010000	/* FCMOVcc etc. */
146 #define	CPUID_AMD_EDX_PSE36	0x00020000	/* 36-bit pagesize extension */
147 				/* 0x00040000 - reserved */
148 				/* 0x00080000 - reserved */
149 #define	CPUID_AMD_EDX_NX	0x00100000	/* AMD: no-execute page prot */
150 				/* 0x00200000 - reserved */
151 #define	CPUID_AMD_EDX_MMXamd	0x00400000	/* AMD: MMX extensions */
152 #define	CPUID_AMD_EDX_MMX	0x00800000	/* MMX instructions */
153 #define	CPUID_AMD_EDX_FXSR	0x01000000	/* fxsave and fxrstor */
154 #define	CPUID_AMD_EDX_FFXSR	0x02000000	/* fast fxsave/fxrstor */
155 #define	CPUID_AMD_EDX_1GPG	0x04000000	/* 1GB page */
156 #define	CPUID_AMD_EDX_TSCP	0x08000000	/* rdtscp instruction */
157 				/* 0x10000000 - reserved */
158 #define	CPUID_AMD_EDX_LM	0x20000000	/* AMD: long mode */
159 #define	CPUID_AMD_EDX_3DNowx	0x40000000	/* AMD: extensions to 3DNow! */
160 #define	CPUID_AMD_EDX_3DNow	0x80000000	/* AMD: 3DNow! instructions */
161 
162 #define	CPUID_AMD_ECX_AHF64	0x00000001	/* LAHF and SAHF in long mode */
163 #define	CPUID_AMD_ECX_CMP_LGCY	0x00000002	/* AMD: multicore chip */
164 #define	CPUID_AMD_ECX_SVM	0x00000004	/* AMD: secure VM */
165 #define	CPUID_AMD_ECX_EAS	0x00000008	/* extended apic space */
166 #define	CPUID_AMD_ECX_CR8D	0x00000010	/* AMD: 32-bit mov %cr8 */
167 #define	CPUID_AMD_ECX_LZCNT	0x00000020	/* AMD: LZCNT insn */
168 #define	CPUID_AMD_ECX_SSE4A	0x00000040	/* AMD: SSE4A insns */
169 #define	CPUID_AMD_ECX_MAS	0x00000080	/* AMD: MisAlignSse mnode */
170 #define	CPUID_AMD_ECX_3DNP	0x00000100	/* AMD: 3DNowPrefectch */
171 #define	CPUID_AMD_ECX_OSVW	0x00000200	/* AMD: OSVW */
172 #define	CPUID_AMD_ECX_IBS	0x00000400	/* AMD: IBS */
173 #define	CPUID_AMD_ECX_SSE5	0x00000800	/* AMD: SSE5 */
174 #define	CPUID_AMD_ECX_SKINIT	0x00001000	/* AMD: SKINIT */
175 #define	CPUID_AMD_ECX_WDT	0x00002000	/* AMD: WDT */
176 #define	CPUID_AMD_ECX_TOPOEXT	0x00400000	/* AMD: Topology Extensions */
177 
178 /*
179  * Intel now seems to have claimed part of the "extended" function
180  * space that we previously for non-Intel implementors to use.
181  * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
182  * is available in long mode i.e. what AMD indicate using bit 0.
183  * On the other hand, everything else is labelled as reserved.
184  */
185 #define	CPUID_INTC_ECX_AHF64	0x00100000	/* LAHF and SAHF in long mode */
186 
187 /*
188  * Intel also uses cpuid leaf 7 to have additional instructions and features.
189  * Like some other leaves, but unlike the current ones we care about, it
190  * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
191  * with the potential use of additional sub-leaves in the future, we now
192  * specifically label the EBX features with their leaf and sub-leaf.
193  */
194 #define	CPUID_INTC_EBX_7_0_BMI1		0x00000008	/* BMI1 instrs */
195 #define	CPUID_INTC_EBX_7_0_AVX2		0x00000020	/* AVX2 supported */
196 #define	CPUID_INTC_EBX_7_0_SMEP		0x00000080	/* SMEP in CR4 */
197 #define	CPUID_INTC_EBX_7_0_BMI2		0x00000100	/* BMI2 instrs */
198 #define	CPUID_INTC_EBX_7_0_RDSEED	0x00040000	/* RDSEED instr */
199 #define	CPUID_INTC_EBX_7_0_ADX		0x00080000	/* ADX instrs */
200 
201 #define	P5_MCHADDR	0x0
202 #define	P5_CESR		0x11
203 #define	P5_CTR0		0x12
204 #define	P5_CTR1		0x13
205 
206 #define	K5_MCHADDR	0x0
207 #define	K5_MCHTYPE	0x01
208 #define	K5_TSC		0x10
209 #define	K5_TR12		0x12
210 
211 #define	REG_PAT		0x277
212 
213 #define	REG_MC0_CTL		0x400
214 #define	REG_MC5_MISC		0x417
215 #define	REG_PERFCTR0		0xc1
216 #define	REG_PERFCTR1		0xc2
217 
218 #define	REG_PERFEVNT0		0x186
219 #define	REG_PERFEVNT1		0x187
220 
221 #define	REG_TSC			0x10	/* timestamp counter */
222 #define	REG_APIC_BASE_MSR	0x1b
223 #define	REG_X2APIC_BASE_MSR	0x800	/* The MSR address offset of x2APIC */
224 
225 #if !defined(__xpv)
226 /*
227  * AMD C1E
228  */
229 #define	MSR_AMD_INT_PENDING_CMP_HALT	0xC0010055
230 #define	AMD_ACTONCMPHALT_SHIFT	27
231 #define	AMD_ACTONCMPHALT_MASK	3
232 #endif
233 
234 #define	MSR_DEBUGCTL		0x1d9
235 
236 #define	DEBUGCTL_LBR		0x01
237 #define	DEBUGCTL_BTF		0x02
238 
239 /* Intel P6, AMD */
240 #define	MSR_LBR_FROM		0x1db
241 #define	MSR_LBR_TO		0x1dc
242 #define	MSR_LEX_FROM		0x1dd
243 #define	MSR_LEX_TO		0x1de
244 
245 /* Intel P4 (pre-Prescott, non P4 M) */
246 #define	MSR_P4_LBSTK_TOS	0x1da
247 #define	MSR_P4_LBSTK_0		0x1db
248 #define	MSR_P4_LBSTK_1		0x1dc
249 #define	MSR_P4_LBSTK_2		0x1dd
250 #define	MSR_P4_LBSTK_3		0x1de
251 
252 /* Intel Pentium M */
253 #define	MSR_P6M_LBSTK_TOS	0x1c9
254 #define	MSR_P6M_LBSTK_0		0x040
255 #define	MSR_P6M_LBSTK_1		0x041
256 #define	MSR_P6M_LBSTK_2		0x042
257 #define	MSR_P6M_LBSTK_3		0x043
258 #define	MSR_P6M_LBSTK_4		0x044
259 #define	MSR_P6M_LBSTK_5		0x045
260 #define	MSR_P6M_LBSTK_6		0x046
261 #define	MSR_P6M_LBSTK_7		0x047
262 
263 /* Intel P4 (Prescott) */
264 #define	MSR_PRP4_LBSTK_TOS	0x1da
265 #define	MSR_PRP4_LBSTK_FROM_0	0x680
266 #define	MSR_PRP4_LBSTK_FROM_1	0x681
267 #define	MSR_PRP4_LBSTK_FROM_2	0x682
268 #define	MSR_PRP4_LBSTK_FROM_3	0x683
269 #define	MSR_PRP4_LBSTK_FROM_4	0x684
270 #define	MSR_PRP4_LBSTK_FROM_5	0x685
271 #define	MSR_PRP4_LBSTK_FROM_6	0x686
272 #define	MSR_PRP4_LBSTK_FROM_7	0x687
273 #define	MSR_PRP4_LBSTK_FROM_8 	0x688
274 #define	MSR_PRP4_LBSTK_FROM_9	0x689
275 #define	MSR_PRP4_LBSTK_FROM_10	0x68a
276 #define	MSR_PRP4_LBSTK_FROM_11 	0x68b
277 #define	MSR_PRP4_LBSTK_FROM_12	0x68c
278 #define	MSR_PRP4_LBSTK_FROM_13	0x68d
279 #define	MSR_PRP4_LBSTK_FROM_14	0x68e
280 #define	MSR_PRP4_LBSTK_FROM_15	0x68f
281 #define	MSR_PRP4_LBSTK_TO_0	0x6c0
282 #define	MSR_PRP4_LBSTK_TO_1	0x6c1
283 #define	MSR_PRP4_LBSTK_TO_2	0x6c2
284 #define	MSR_PRP4_LBSTK_TO_3	0x6c3
285 #define	MSR_PRP4_LBSTK_TO_4	0x6c4
286 #define	MSR_PRP4_LBSTK_TO_5	0x6c5
287 #define	MSR_PRP4_LBSTK_TO_6	0x6c6
288 #define	MSR_PRP4_LBSTK_TO_7	0x6c7
289 #define	MSR_PRP4_LBSTK_TO_8	0x6c8
290 #define	MSR_PRP4_LBSTK_TO_9 	0x6c9
291 #define	MSR_PRP4_LBSTK_TO_10	0x6ca
292 #define	MSR_PRP4_LBSTK_TO_11	0x6cb
293 #define	MSR_PRP4_LBSTK_TO_12	0x6cc
294 #define	MSR_PRP4_LBSTK_TO_13	0x6cd
295 #define	MSR_PRP4_LBSTK_TO_14	0x6ce
296 #define	MSR_PRP4_LBSTK_TO_15	0x6cf
297 
298 #define	MCI_CTL_VALUE		0xffffffff
299 
300 #define	MTRR_TYPE_UC		0
301 #define	MTRR_TYPE_WC		1
302 #define	MTRR_TYPE_WT		4
303 #define	MTRR_TYPE_WP		5
304 #define	MTRR_TYPE_WB		6
305 #define	MTRR_TYPE_UC_		7
306 
307 /*
308  * For Solaris we set up the page attritubute table in the following way:
309  * PAT0	Write-Back
310  * PAT1	Write-Through
311  * PAT2	Unchacheable-
312  * PAT3	Uncacheable
313  * PAT4 Write-Back
314  * PAT5	Write-Through
315  * PAT6	Write-Combine
316  * PAT7 Uncacheable
317  * The only difference from h/w default is entry 6.
318  */
319 #define	PAT_DEFAULT_ATTRIBUTE			\
320 	((uint64_t)MTRR_TYPE_WB |		\
321 	((uint64_t)MTRR_TYPE_WT << 8) |		\
322 	((uint64_t)MTRR_TYPE_UC_ << 16) |	\
323 	((uint64_t)MTRR_TYPE_UC << 24) |	\
324 	((uint64_t)MTRR_TYPE_WB << 32) |	\
325 	((uint64_t)MTRR_TYPE_WT << 40) |	\
326 	((uint64_t)MTRR_TYPE_WC << 48) |	\
327 	((uint64_t)MTRR_TYPE_UC << 56))
328 
329 #define	X86FSET_LARGEPAGE	0
330 #define	X86FSET_TSC		1
331 #define	X86FSET_MSR		2
332 #define	X86FSET_MTRR		3
333 #define	X86FSET_PGE		4
334 #define	X86FSET_DE		5
335 #define	X86FSET_CMOV		6
336 #define	X86FSET_MMX		7
337 #define	X86FSET_MCA		8
338 #define	X86FSET_PAE		9
339 #define	X86FSET_CX8		10
340 #define	X86FSET_PAT		11
341 #define	X86FSET_SEP		12
342 #define	X86FSET_SSE		13
343 #define	X86FSET_SSE2		14
344 #define	X86FSET_HTT		15
345 #define	X86FSET_ASYSC		16
346 #define	X86FSET_NX		17
347 #define	X86FSET_SSE3		18
348 #define	X86FSET_CX16		19
349 #define	X86FSET_CMP		20
350 #define	X86FSET_TSCP		21
351 #define	X86FSET_MWAIT		22
352 #define	X86FSET_SSE4A		23
353 #define	X86FSET_CPUID		24
354 #define	X86FSET_SSSE3		25
355 #define	X86FSET_SSE4_1		26
356 #define	X86FSET_SSE4_2		27
357 #define	X86FSET_1GPG		28
358 #define	X86FSET_CLFSH		29
359 #define	X86FSET_64		30
360 #define	X86FSET_AES		31
361 #define	X86FSET_PCLMULQDQ	32
362 #define	X86FSET_XSAVE		33
363 #define	X86FSET_AVX		34
364 #define	X86FSET_VMX		35
365 #define	X86FSET_SVM		36
366 #define	X86FSET_TOPOEXT		37
367 #define	X86FSET_F16C		38
368 #define	X86FSET_RDRAND		39
369 #define	X86FSET_X2APIC		40
370 #define	X86FSET_AVX2		41
371 #define	X86FSET_BMI1		42
372 #define	X86FSET_BMI2		43
373 #define	X86FSET_FMA		44
374 #define	X86FSET_SMEP		45
375 #define	X86FSET_ADX		47
376 #define	X86FSET_RDSEED		48
377 
378 /*
379  * Intel Deep C-State invariant TSC in leaf 0x80000007.
380  */
381 #define	CPUID_TSC_CSTATE_INVARIANCE	(0x100)
382 
383 /*
384  * Intel Deep C-state always-running local APIC timer
385  */
386 #define	CPUID_CSTATE_ARAT	(0x4)
387 
388 /*
389  * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
390  */
391 #define	CPUID_EPB_SUPPORT	(1 << 3)
392 
393 /*
394  * Intel TSC deadline timer
395  */
396 #define	CPUID_DEADLINE_TSC	(1 << 24)
397 
398 /*
399  * x86_type is a legacy concept; this is supplanted
400  * for most purposes by x86_featureset; modern CPUs
401  * should be X86_TYPE_OTHER
402  */
403 #define	X86_TYPE_OTHER		0
404 #define	X86_TYPE_486		1
405 #define	X86_TYPE_P5		2
406 #define	X86_TYPE_P6		3
407 #define	X86_TYPE_CYRIX_486	4
408 #define	X86_TYPE_CYRIX_6x86L	5
409 #define	X86_TYPE_CYRIX_6x86	6
410 #define	X86_TYPE_CYRIX_GXm	7
411 #define	X86_TYPE_CYRIX_6x86MX	8
412 #define	X86_TYPE_CYRIX_MediaGX	9
413 #define	X86_TYPE_CYRIX_MII	10
414 #define	X86_TYPE_VIA_CYRIX_III	11
415 #define	X86_TYPE_P4		12
416 
417 /*
418  * x86_vendor allows us to select between
419  * implementation features and helps guide
420  * the interpretation of the cpuid instruction.
421  */
422 #define	X86_VENDOR_Intel	0
423 #define	X86_VENDORSTR_Intel	"GenuineIntel"
424 
425 #define	X86_VENDOR_IntelClone	1
426 
427 #define	X86_VENDOR_AMD		2
428 #define	X86_VENDORSTR_AMD	"AuthenticAMD"
429 
430 #define	X86_VENDOR_Cyrix	3
431 #define	X86_VENDORSTR_CYRIX	"CyrixInstead"
432 
433 #define	X86_VENDOR_UMC		4
434 #define	X86_VENDORSTR_UMC	"UMC UMC UMC "
435 
436 #define	X86_VENDOR_NexGen	5
437 #define	X86_VENDORSTR_NexGen	"NexGenDriven"
438 
439 #define	X86_VENDOR_Centaur	6
440 #define	X86_VENDORSTR_Centaur	"CentaurHauls"
441 
442 #define	X86_VENDOR_Rise		7
443 #define	X86_VENDORSTR_Rise	"RiseRiseRise"
444 
445 #define	X86_VENDOR_SiS		8
446 #define	X86_VENDORSTR_SiS	"SiS SiS SiS "
447 
448 #define	X86_VENDOR_TM		9
449 #define	X86_VENDORSTR_TM	"GenuineTMx86"
450 
451 #define	X86_VENDOR_NSC		10
452 #define	X86_VENDORSTR_NSC	"Geode by NSC"
453 
454 /*
455  * Vendor string max len + \0
456  */
457 #define	X86_VENDOR_STRLEN	13
458 
459 /*
460  * Some vendor/family/model/stepping ranges are commonly grouped under
461  * a single identifying banner by the vendor.  The following encode
462  * that "revision" in a uint32_t with the 8 most significant bits
463  * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
464  * family, and the remaining 16 typically forming a bitmask of revisions
465  * within that family with more significant bits indicating "later" revisions.
466  */
467 
468 #define	_X86_CHIPREV_VENDOR_MASK	0xff000000u
469 #define	_X86_CHIPREV_VENDOR_SHIFT	24
470 #define	_X86_CHIPREV_FAMILY_MASK	0x00ff0000u
471 #define	_X86_CHIPREV_FAMILY_SHIFT	16
472 #define	_X86_CHIPREV_REV_MASK		0x0000ffffu
473 
474 #define	_X86_CHIPREV_VENDOR(x) \
475 	(((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
476 #define	_X86_CHIPREV_FAMILY(x) \
477 	(((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
478 #define	_X86_CHIPREV_REV(x) \
479 	((x) & _X86_CHIPREV_REV_MASK)
480 
481 /* True if x matches in vendor and family and if x matches the given rev mask */
482 #define	X86_CHIPREV_MATCH(x, mask) \
483 	(_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
484 	_X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
485 	((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
486 
487 /* True if x matches in vendor and family, and rev is at least minx */
488 #define	X86_CHIPREV_ATLEAST(x, minx) \
489 	(_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
490 	_X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
491 	_X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
492 
493 #define	_X86_CHIPREV_MKREV(vendor, family, rev) \
494 	((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
495 	(family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
496 
497 /* True if x matches in vendor, and family is at least minx */
498 #define	X86_CHIPFAM_ATLEAST(x, minx) \
499 	(_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
500 	_X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
501 
502 /* Revision default */
503 #define	X86_CHIPREV_UNKNOWN	0x0
504 
505 /*
506  * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
507  * sufficiently different that we will distinguish them; in all other
508  * case we will identify the major revision.
509  */
510 #define	X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
511 #define	X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
512 #define	X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
513 #define	X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
514 #define	X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
515 #define	X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
516 #define	X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
517 
518 /*
519  * Definitions for AMD Family 0x10.  Rev A was Engineering Samples only.
520  */
521 #define	X86_CHIPREV_AMD_10_REV_A \
522 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
523 #define	X86_CHIPREV_AMD_10_REV_B \
524 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
525 #define	X86_CHIPREV_AMD_10_REV_C2 \
526 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
527 #define	X86_CHIPREV_AMD_10_REV_C3 \
528 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
529 #define	X86_CHIPREV_AMD_10_REV_D0 \
530 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
531 #define	X86_CHIPREV_AMD_10_REV_D1 \
532 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
533 #define	X86_CHIPREV_AMD_10_REV_E \
534 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
535 
536 /*
537  * Definitions for AMD Family 0x11.
538  */
539 #define	X86_CHIPREV_AMD_11_REV_B \
540 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
541 
542 /*
543  * Definitions for AMD Family 0x12.
544  */
545 #define	X86_CHIPREV_AMD_12_REV_B \
546 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
547 
548 /*
549  * Definitions for AMD Family 0x14.
550  */
551 #define	X86_CHIPREV_AMD_14_REV_B \
552 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
553 #define	X86_CHIPREV_AMD_14_REV_C \
554 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
555 
556 /*
557  * Definitions for AMD Family 0x15
558  */
559 #define	X86_CHIPREV_AMD_15OR_REV_B2 \
560 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
561 
562 #define	X86_CHIPREV_AMD_15TN_REV_A1 \
563 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
564 
565 /*
566  * Various socket/package types, extended as the need to distinguish
567  * a new type arises.  The top 8 byte identfies the vendor and the
568  * remaining 24 bits describe 24 socket types.
569  */
570 
571 #define	_X86_SOCKET_VENDOR_SHIFT	24
572 #define	_X86_SOCKET_VENDOR(x)	((x) >> _X86_SOCKET_VENDOR_SHIFT)
573 #define	_X86_SOCKET_TYPE_MASK	0x00ffffff
574 #define	_X86_SOCKET_TYPE(x)		((x) & _X86_SOCKET_TYPE_MASK)
575 
576 #define	_X86_SOCKET_MKVAL(vendor, bitval) \
577 	((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
578 
579 #define	X86_SOCKET_MATCH(s, mask) \
580 	(_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
581 	(_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
582 
583 #define	X86_SOCKET_UNKNOWN 0x0
584 	/*
585 	 * AMD socket types
586 	 */
587 #define	X86_SOCKET_754		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
588 #define	X86_SOCKET_939		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
589 #define	X86_SOCKET_940		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
590 #define	X86_SOCKET_S1g1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
591 #define	X86_SOCKET_AM2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
592 #define	X86_SOCKET_F1207	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
593 #define	X86_SOCKET_S1g2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
594 #define	X86_SOCKET_S1g3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
595 #define	X86_SOCKET_AM		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
596 #define	X86_SOCKET_AM2R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
597 #define	X86_SOCKET_AM3		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
598 #define	X86_SOCKET_G34		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
599 #define	X86_SOCKET_ASB2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
600 #define	X86_SOCKET_C32		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
601 #define	X86_SOCKET_S1g4		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000)
602 #define	X86_SOCKET_FT1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000)
603 #define	X86_SOCKET_FM1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000)
604 #define	X86_SOCKET_FS1		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000)
605 #define	X86_SOCKET_AM3R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000)
606 #define	X86_SOCKET_FP2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000)
607 #define	X86_SOCKET_FS1R2	_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000)
608 #define	X86_SOCKET_FM2		_X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000)
609 
610 /*
611  * xgetbv/xsetbv support
612  */
613 
614 #define	XFEATURE_ENABLED_MASK	0x0
615 /*
616  * XFEATURE_ENABLED_MASK values (eax)
617  */
618 #define	XFEATURE_LEGACY_FP	0x1
619 #define	XFEATURE_SSE		0x2
620 #define	XFEATURE_AVX		0x4
621 #define	XFEATURE_MAX		XFEATURE_AVX
622 #define	XFEATURE_FP_ALL	\
623 	(XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX)
624 
625 #if !defined(_ASM)
626 
627 #if defined(_KERNEL) || defined(_KMEMUSER)
628 
629 #define	NUM_X86_FEATURES	49
630 extern uchar_t x86_featureset[];
631 
632 extern void free_x86_featureset(void *featureset);
633 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
634 extern void add_x86_feature(void *featureset, uint_t feature);
635 extern void remove_x86_feature(void *featureset, uint_t feature);
636 extern boolean_t compare_x86_featureset(void *setA, void *setB);
637 extern void print_x86_featureset(void *featureset);
638 
639 
640 extern uint_t x86_type;
641 extern uint_t x86_vendor;
642 extern uint_t x86_clflush_size;
643 
644 extern uint_t pentiumpro_bug4046376;
645 
646 extern const char CyrixInstead[];
647 
648 #endif
649 
650 #if defined(_KERNEL)
651 
652 /*
653  * This structure is used to pass arguments and get return values back
654  * from the CPUID instruction in __cpuid_insn() routine.
655  */
656 struct cpuid_regs {
657 	uint32_t	cp_eax;
658 	uint32_t	cp_ebx;
659 	uint32_t	cp_ecx;
660 	uint32_t	cp_edx;
661 };
662 
663 /*
664  * Utility functions to get/set extended control registers (XCR)
665  * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
666  */
667 extern uint64_t get_xcr(uint_t);
668 extern void set_xcr(uint_t, uint64_t);
669 
670 extern uint64_t rdmsr(uint_t);
671 extern void wrmsr(uint_t, const uint64_t);
672 extern uint64_t xrdmsr(uint_t);
673 extern void xwrmsr(uint_t, const uint64_t);
674 extern int checked_rdmsr(uint_t, uint64_t *);
675 extern int checked_wrmsr(uint_t, uint64_t);
676 
677 extern void invalidate_cache(void);
678 extern ulong_t getcr4(void);
679 extern void setcr4(ulong_t);
680 
681 extern void mtrr_sync(void);
682 
683 extern void cpu_fast_syscall_enable(void *);
684 extern void cpu_fast_syscall_disable(void *);
685 
686 struct cpu;
687 
688 extern int cpuid_checkpass(struct cpu *, int);
689 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
690 extern uint32_t __cpuid_insn(struct cpuid_regs *);
691 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
692 extern int cpuid_getidstr(struct cpu *, char *, size_t);
693 extern const char *cpuid_getvendorstr(struct cpu *);
694 extern uint_t cpuid_getvendor(struct cpu *);
695 extern uint_t cpuid_getfamily(struct cpu *);
696 extern uint_t cpuid_getmodel(struct cpu *);
697 extern uint_t cpuid_getstep(struct cpu *);
698 extern uint_t cpuid_getsig(struct cpu *);
699 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
700 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
701 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
702 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
703 extern int cpuid_get_chipid(struct cpu *);
704 extern id_t cpuid_get_coreid(struct cpu *);
705 extern int cpuid_get_pkgcoreid(struct cpu *);
706 extern int cpuid_get_clogid(struct cpu *);
707 extern int cpuid_get_cacheid(struct cpu *);
708 extern uint32_t cpuid_get_apicid(struct cpu *);
709 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
710 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
711 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
712 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
713 extern int cpuid_is_cmt(struct cpu *);
714 extern int cpuid_syscall32_insn(struct cpu *);
715 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
716 
717 extern uint32_t cpuid_getchiprev(struct cpu *);
718 extern const char *cpuid_getchiprevstr(struct cpu *);
719 extern uint32_t cpuid_getsockettype(struct cpu *);
720 extern const char *cpuid_getsocketstr(struct cpu *);
721 
722 extern int cpuid_have_cr8access(struct cpu *);
723 
724 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
725 
726 struct cpuid_info;
727 
728 extern void setx86isalist(void);
729 extern void cpuid_alloc_space(struct cpu *);
730 extern void cpuid_free_space(struct cpu *);
731 extern void cpuid_pass1(struct cpu *, uchar_t *);
732 extern void cpuid_pass2(struct cpu *);
733 extern void cpuid_pass3(struct cpu *);
734 extern void cpuid_pass4(struct cpu *, uint_t *);
735 extern void cpuid_set_cpu_properties(void *, processorid_t,
736     struct cpuid_info *);
737 
738 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
739 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
740 
741 #if !defined(__xpv)
742 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
743 extern void cpuid_mwait_free(struct cpu *);
744 extern int cpuid_deep_cstates_supported(void);
745 extern int cpuid_arat_supported(void);
746 extern int cpuid_iepb_supported(struct cpu *);
747 extern int cpuid_deadline_tsc_supported(void);
748 extern void vmware_port(int, uint32_t *);
749 #endif
750 
751 struct cpu_ucode_info;
752 
753 extern void ucode_alloc_space(struct cpu *);
754 extern void ucode_free_space(struct cpu *);
755 extern void ucode_check(struct cpu *);
756 extern void ucode_cleanup();
757 
758 #if !defined(__xpv)
759 extern	char _tsc_mfence_start;
760 extern	char _tsc_mfence_end;
761 extern	char _tscp_start;
762 extern	char _tscp_end;
763 extern	char _no_rdtsc_start;
764 extern	char _no_rdtsc_end;
765 extern	char _tsc_lfence_start;
766 extern	char _tsc_lfence_end;
767 #endif
768 
769 #if !defined(__xpv)
770 extern	char bcopy_patch_start;
771 extern	char bcopy_patch_end;
772 extern	char bcopy_ck_size;
773 #endif
774 
775 extern void post_startup_cpu_fixups(void);
776 
777 extern uint_t workaround_errata(struct cpu *);
778 
779 #if defined(OPTERON_ERRATUM_93)
780 extern int opteron_erratum_93;
781 #endif
782 
783 #if defined(OPTERON_ERRATUM_91)
784 extern int opteron_erratum_91;
785 #endif
786 
787 #if defined(OPTERON_ERRATUM_100)
788 extern int opteron_erratum_100;
789 #endif
790 
791 #if defined(OPTERON_ERRATUM_121)
792 extern int opteron_erratum_121;
793 #endif
794 
795 #if defined(OPTERON_WORKAROUND_6323525)
796 extern int opteron_workaround_6323525;
797 extern void patch_workaround_6323525(void);
798 #endif
799 
800 #if !defined(__xpv)
801 extern void determine_platform(void);
802 #endif
803 extern int get_hwenv(void);
804 extern int is_controldom(void);
805 
806 extern void xsave_setup_msr(struct cpu *);
807 
808 /*
809  * Hypervisor signatures
810  */
811 #define	HVSIG_XEN_HVM	"XenVMMXenVMM"
812 #define	HVSIG_VMWARE	"VMwareVMware"
813 #define	HVSIG_KVM	"KVMKVMKVM"
814 #define	HVSIG_MICROSOFT	"Microsoft Hv"
815 
816 /*
817  * Defined hardware environments
818  */
819 #define	HW_NATIVE	(1 << 0)	/* Running on bare metal */
820 #define	HW_XEN_PV	(1 << 1)	/* Running on Xen PVM */
821 
822 #define	HW_XEN_HVM	(1 << 2)	/* Running on Xen HVM */
823 #define	HW_VMWARE	(1 << 3)	/* Running on VMware hypervisor */
824 #define	HW_KVM		(1 << 4)	/* Running on KVM hypervisor */
825 #define	HW_MICROSOFT	(1 << 5)	/* Running on Microsoft hypervisor */
826 
827 #define	HW_VIRTUAL	(HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT)
828 
829 #endif	/* _KERNEL */
830 
831 #endif	/* !_ASM */
832 
833 /*
834  * VMware hypervisor related defines
835  */
836 #define	VMWARE_HVMAGIC		0x564d5868
837 #define	VMWARE_HVPORT		0x5658
838 #define	VMWARE_HVCMD_GETVERSION	0x0a
839 #define	VMWARE_HVCMD_GETTSCFREQ	0x2d
840 
841 #ifdef	__cplusplus
842 }
843 #endif
844 
845 #endif	/* _SYS_X86_ARCHEXT_H */
846