1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_X86_ARCHEXT_H 27 #define _SYS_X86_ARCHEXT_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #if !defined(_ASM) 32 #include <sys/regset.h> 33 #include <sys/processor.h> 34 #include <vm/seg_enum.h> 35 #include <vm/page.h> 36 #endif /* _ASM */ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /* 43 * cpuid instruction feature flags in %edx (standard function 1) 44 */ 45 46 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 47 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 48 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 49 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 50 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 51 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 52 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 53 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 54 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 55 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 56 /* 0x400 - reserved */ 57 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 58 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 59 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 60 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 61 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 62 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 63 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 64 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 65 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 66 /* 0x100000 - reserved */ 67 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 68 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 69 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 70 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 71 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 72 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 73 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 74 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 75 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 76 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 77 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 78 79 #define FMT_CPUID_INTC_EDX \ 80 "\20" \ 81 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 82 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \ 83 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 84 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 85 86 /* 87 * cpuid instruction feature flags in %ecx (standard function 1) 88 */ 89 90 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 91 /* 0x00000002 - reserved */ 92 /* 0x00000004 - reserved */ 93 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 94 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 95 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 96 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 97 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 98 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 99 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 100 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 101 /* 0x00000800 - reserved */ 102 /* 0x00001000 - reserved */ 103 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 104 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 105 /* 0x00008000 - reserved */ 106 /* 0x00010000 - reserved */ 107 /* 0x00020000 - reserved */ 108 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 109 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 110 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 111 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 112 113 #define FMT_CPUID_INTC_ECX \ 114 "\20" \ 115 "\30popcnt\25sse4.2\24sse4.1\23dca" \ 116 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \ 117 "\10est\7smx\6vmx\5dscpl\4mon\1sse3" 118 119 /* 120 * cpuid instruction feature flags in %edx (extended function 0x80000001) 121 */ 122 123 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 124 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 125 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 126 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 127 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 128 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 129 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 130 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 131 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 132 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 133 /* 0x00000400 - sysc on K6m6 */ 134 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 135 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 136 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 137 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 138 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 139 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 140 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 141 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 142 /* 0x00040000 - reserved */ 143 /* 0x00080000 - reserved */ 144 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 145 /* 0x00200000 - reserved */ 146 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 147 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 148 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 149 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 150 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 151 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 152 /* 0x10000000 - reserved */ 153 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 154 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 155 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 156 157 #define FMT_CPUID_AMD_EDX \ 158 "\20" \ 159 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \ 160 "\30mmx\27mmxext\25nx\22pse\21pat" \ 161 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 162 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 163 164 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 165 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 166 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 167 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 168 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 169 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 170 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 171 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 172 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 173 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 174 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 175 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */ 176 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 177 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 178 179 #define FMT_CPUID_AMD_ECX \ 180 "\20" \ 181 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \ 182 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 183 184 /* 185 * Intel now seems to have claimed part of the "extended" function 186 * space that we previously for non-Intel implementors to use. 187 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 188 * is available in long mode i.e. what AMD indicate using bit 0. 189 * On the other hand, everything else is labelled as reserved. 190 */ 191 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 192 193 194 #define P5_MCHADDR 0x0 195 #define P5_CESR 0x11 196 #define P5_CTR0 0x12 197 #define P5_CTR1 0x13 198 199 #define K5_MCHADDR 0x0 200 #define K5_MCHTYPE 0x01 201 #define K5_TSC 0x10 202 #define K5_TR12 0x12 203 204 #define REG_PAT 0x277 205 206 #define REG_MC0_CTL 0x400 207 #define REG_MC5_MISC 0x417 208 #define REG_PERFCTR0 0xc1 209 #define REG_PERFCTR1 0xc2 210 211 #define REG_PERFEVNT0 0x186 212 #define REG_PERFEVNT1 0x187 213 214 #define REG_TSC 0x10 /* timestamp counter */ 215 #define REG_APIC_BASE_MSR 0x1b 216 217 #define MSR_DEBUGCTL 0x1d9 218 219 #define DEBUGCTL_LBR 0x01 220 #define DEBUGCTL_BTF 0x02 221 222 /* Intel P6, AMD */ 223 #define MSR_LBR_FROM 0x1db 224 #define MSR_LBR_TO 0x1dc 225 #define MSR_LEX_FROM 0x1dd 226 #define MSR_LEX_TO 0x1de 227 228 /* Intel P4 (pre-Prescott, non P4 M) */ 229 #define MSR_P4_LBSTK_TOS 0x1da 230 #define MSR_P4_LBSTK_0 0x1db 231 #define MSR_P4_LBSTK_1 0x1dc 232 #define MSR_P4_LBSTK_2 0x1dd 233 #define MSR_P4_LBSTK_3 0x1de 234 235 /* Intel Pentium M */ 236 #define MSR_P6M_LBSTK_TOS 0x1c9 237 #define MSR_P6M_LBSTK_0 0x040 238 #define MSR_P6M_LBSTK_1 0x041 239 #define MSR_P6M_LBSTK_2 0x042 240 #define MSR_P6M_LBSTK_3 0x043 241 #define MSR_P6M_LBSTK_4 0x044 242 #define MSR_P6M_LBSTK_5 0x045 243 #define MSR_P6M_LBSTK_6 0x046 244 #define MSR_P6M_LBSTK_7 0x047 245 246 /* Intel P4 (Prescott) */ 247 #define MSR_PRP4_LBSTK_TOS 0x1da 248 #define MSR_PRP4_LBSTK_FROM_0 0x680 249 #define MSR_PRP4_LBSTK_FROM_1 0x681 250 #define MSR_PRP4_LBSTK_FROM_2 0x682 251 #define MSR_PRP4_LBSTK_FROM_3 0x683 252 #define MSR_PRP4_LBSTK_FROM_4 0x684 253 #define MSR_PRP4_LBSTK_FROM_5 0x685 254 #define MSR_PRP4_LBSTK_FROM_6 0x686 255 #define MSR_PRP4_LBSTK_FROM_7 0x687 256 #define MSR_PRP4_LBSTK_FROM_8 0x688 257 #define MSR_PRP4_LBSTK_FROM_9 0x689 258 #define MSR_PRP4_LBSTK_FROM_10 0x68a 259 #define MSR_PRP4_LBSTK_FROM_11 0x68b 260 #define MSR_PRP4_LBSTK_FROM_12 0x68c 261 #define MSR_PRP4_LBSTK_FROM_13 0x68d 262 #define MSR_PRP4_LBSTK_FROM_14 0x68e 263 #define MSR_PRP4_LBSTK_FROM_15 0x68f 264 #define MSR_PRP4_LBSTK_TO_0 0x6c0 265 #define MSR_PRP4_LBSTK_TO_1 0x6c1 266 #define MSR_PRP4_LBSTK_TO_2 0x6c2 267 #define MSR_PRP4_LBSTK_TO_3 0x6c3 268 #define MSR_PRP4_LBSTK_TO_4 0x6c4 269 #define MSR_PRP4_LBSTK_TO_5 0x6c5 270 #define MSR_PRP4_LBSTK_TO_6 0x6c6 271 #define MSR_PRP4_LBSTK_TO_7 0x6c7 272 #define MSR_PRP4_LBSTK_TO_8 0x6c8 273 #define MSR_PRP4_LBSTK_TO_9 0x6c9 274 #define MSR_PRP4_LBSTK_TO_10 0x6ca 275 #define MSR_PRP4_LBSTK_TO_11 0x6cb 276 #define MSR_PRP4_LBSTK_TO_12 0x6cc 277 #define MSR_PRP4_LBSTK_TO_13 0x6cd 278 #define MSR_PRP4_LBSTK_TO_14 0x6ce 279 #define MSR_PRP4_LBSTK_TO_15 0x6cf 280 281 #define MCI_CTL_VALUE 0xffffffff 282 283 #define MTRR_TYPE_UC 0 284 #define MTRR_TYPE_WC 1 285 #define MTRR_TYPE_WT 4 286 #define MTRR_TYPE_WP 5 287 #define MTRR_TYPE_WB 6 288 #define MTRR_TYPE_UC_ 7 289 290 /* 291 * For Solaris we set up the page attritubute table in the following way: 292 * PAT0 Write-Back 293 * PAT1 Write-Through 294 * PAT2 Unchacheable- 295 * PAT3 Uncacheable 296 * PAT4 Write-Back 297 * PAT5 Write-Through 298 * PAT6 Write-Combine 299 * PAT7 Uncacheable 300 * The only difference from h/w default is entry 6. 301 */ 302 #define PAT_DEFAULT_ATTRIBUTE \ 303 ((uint64_t)MTRR_TYPE_WB | \ 304 ((uint64_t)MTRR_TYPE_WT << 8) | \ 305 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 306 ((uint64_t)MTRR_TYPE_UC << 24) | \ 307 ((uint64_t)MTRR_TYPE_WB << 32) | \ 308 ((uint64_t)MTRR_TYPE_WT << 40) | \ 309 ((uint64_t)MTRR_TYPE_WC << 48) | \ 310 ((uint64_t)MTRR_TYPE_UC << 56)) 311 312 #define X86_LARGEPAGE 0x00000001 313 #define X86_TSC 0x00000002 314 #define X86_MSR 0x00000004 315 #define X86_MTRR 0x00000008 316 #define X86_PGE 0x00000010 317 #define X86_DE 0x00000020 318 #define X86_CMOV 0x00000040 319 #define X86_MMX 0x00000080 320 #define X86_MCA 0x00000100 321 #define X86_PAE 0x00000200 322 #define X86_CX8 0x00000400 323 #define X86_PAT 0x00000800 324 #define X86_SEP 0x00001000 325 #define X86_SSE 0x00002000 326 #define X86_SSE2 0x00004000 327 #define X86_HTT 0x00008000 328 #define X86_ASYSC 0x00010000 329 #define X86_NX 0x00020000 330 #define X86_SSE3 0x00040000 331 #define X86_CX16 0x00080000 332 #define X86_CMP 0x00100000 333 #define X86_TSCP 0x00200000 334 #define X86_MWAIT 0x00400000 335 #define X86_SSE4A 0x00800000 336 #define X86_CPUID 0x01000000 337 #define X86_SSSE3 0x02000000 338 #define X86_SSE4_1 0x04000000 339 #define X86_SSE4_2 0x08000000 340 #define X86_1GPG 0x10000000 341 342 /* 343 * flags to patch tsc_read routine. 344 */ 345 #define X86_NO_TSC 0x0 346 #define X86_HAVE_TSCP 0x1 347 #define X86_TSC_MFENCE 0x2 348 #define X86_TSC_LFENCE 0x4 349 350 #define FMT_X86_FEATURE \ 351 "\20" \ 352 "\34sse4_2\33sse4_1\32ssse3\31cpuid" \ 353 "\30sse4a\27mwait\26tscp\25cmp\24cx16\23sse3\22nx\21asysc"\ 354 "\20htt\17sse2\16sse\15sep\14pat\13cx8\12pae\11mca" \ 355 "\10mmx\7cmov\6de\5pge\4mtrr\3msr\2tsc\1lgpg" 356 357 /* 358 * x86_type is a legacy concept; this is supplanted 359 * for most purposes by x86_feature; modern CPUs 360 * should be X86_TYPE_OTHER 361 */ 362 #define X86_TYPE_OTHER 0 363 #define X86_TYPE_486 1 364 #define X86_TYPE_P5 2 365 #define X86_TYPE_P6 3 366 #define X86_TYPE_CYRIX_486 4 367 #define X86_TYPE_CYRIX_6x86L 5 368 #define X86_TYPE_CYRIX_6x86 6 369 #define X86_TYPE_CYRIX_GXm 7 370 #define X86_TYPE_CYRIX_6x86MX 8 371 #define X86_TYPE_CYRIX_MediaGX 9 372 #define X86_TYPE_CYRIX_MII 10 373 #define X86_TYPE_VIA_CYRIX_III 11 374 #define X86_TYPE_P4 12 375 376 /* 377 * x86_vendor allows us to select between 378 * implementation features and helps guide 379 * the interpretation of the cpuid instruction. 380 */ 381 #define X86_VENDOR_Intel 0 /* GenuineIntel */ 382 #define X86_VENDOR_IntelClone 1 /* (an Intel clone) */ 383 #define X86_VENDOR_AMD 2 /* AuthenticAMD */ 384 #define X86_VENDOR_Cyrix 3 /* CyrixInstead */ 385 #define X86_VENDOR_UMC 4 /* UMC UMC UMC */ 386 #define X86_VENDOR_NexGen 5 /* NexGenDriven */ 387 #define X86_VENDOR_Centaur 6 /* CentaurHauls */ 388 #define X86_VENDOR_Rise 7 /* RiseRiseRise */ 389 #define X86_VENDOR_SiS 8 /* SiS SiS SiS */ 390 #define X86_VENDOR_TM 9 /* GenuineTMx86 */ 391 #define X86_VENDOR_NSC 10 /* Geode by NSC */ 392 393 #define X86_VENDOR_STRLEN 13 /* vendor string max len + \0 */ 394 395 /* 396 * Some vendor/family/model/stepping ranges are commonly grouped under 397 * a single identifying banner by the vendor. The following encode 398 * that "revision" in a uint32_t with the 8 most significant bits 399 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 400 * family, and the remaining 16 typically forming a bitmask of revisions 401 * within that family with more significant bits indicating "later" revisions. 402 */ 403 404 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 405 #define _X86_CHIPREV_VENDOR_SHIFT 24 406 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 407 #define _X86_CHIPREV_FAMILY_SHIFT 16 408 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 409 410 #define _X86_CHIPREV_VENDOR(x) \ 411 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 412 #define _X86_CHIPREV_FAMILY(x) \ 413 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 414 #define _X86_CHIPREV_REV(x) \ 415 ((x) & _X86_CHIPREV_REV_MASK) 416 417 /* True if x matches in vendor and family and if x matches the given rev mask */ 418 #define X86_CHIPREV_MATCH(x, mask) \ 419 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 420 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 421 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 422 423 /* True if x matches in vendor and family and rev is at least minx */ 424 #define X86_CHIPREV_ATLEAST(x, minx) \ 425 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 426 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 427 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 428 429 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 430 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 431 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 432 433 /* Revision default */ 434 #define X86_CHIPREV_UNKNOWN 0x0 435 436 /* 437 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 438 * sufficiently different that we will distinguish them; in all other 439 * case we will identify the major revision. 440 */ 441 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 442 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 443 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 444 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 445 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 446 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 447 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 448 449 /* 450 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 451 */ 452 #define X86_CHIPREV_AMD_10_REV_A \ 453 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 454 #define X86_CHIPREV_AMD_10_REV_B \ 455 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 456 457 /* 458 * Various socket/package types, extended as the need to distinguish 459 * a new type arises. The top 8 byte identfies the vendor and the 460 * remaining 24 bits describe 24 socket types. 461 */ 462 463 #define _X86_SOCKET_VENDOR_SHIFT 24 464 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 465 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 466 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 467 468 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 469 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 470 471 #define X86_SOCKET_MATCH(s, mask) \ 472 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 473 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 474 475 #define X86_SOCKET_UNKNOWN 0x0 476 /* 477 * AMD socket types 478 */ 479 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 480 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 481 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 482 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 483 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 484 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 485 486 #if !defined(_ASM) 487 488 #if defined(_KERNEL) || defined(_KMEMUSER) 489 490 extern uint_t x86_feature; 491 extern uint_t x86_type; 492 extern uint_t x86_vendor; 493 494 extern uint_t pentiumpro_bug4046376; 495 extern uint_t pentiumpro_bug4064495; 496 497 extern uint_t enable486; 498 499 extern const char CyrixInstead[]; 500 501 #endif 502 503 #if defined(_KERNEL) 504 505 /* 506 * This structure is used to pass arguments and get return values back 507 * from the CPUID instruction in __cpuid_insn() routine. 508 */ 509 struct cpuid_regs { 510 uint32_t cp_eax; 511 uint32_t cp_ebx; 512 uint32_t cp_ecx; 513 uint32_t cp_edx; 514 }; 515 516 extern uint64_t rdmsr(uint_t); 517 extern void wrmsr(uint_t, const uint64_t); 518 extern uint64_t xrdmsr(uint_t); 519 extern void xwrmsr(uint_t, const uint64_t); 520 extern int checked_rdmsr(uint_t, uint64_t *); 521 extern int checked_wrmsr(uint_t, uint64_t); 522 523 extern void invalidate_cache(void); 524 extern ulong_t getcr4(void); 525 extern void setcr4(ulong_t); 526 527 extern void mtrr_sync(void); 528 529 extern void cpu_fast_syscall_enable(void *); 530 extern void cpu_fast_syscall_disable(void *); 531 532 struct cpu; 533 534 extern int cpuid_checkpass(struct cpu *, int); 535 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 536 extern uint32_t __cpuid_insn(struct cpuid_regs *); 537 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 538 extern int cpuid_getidstr(struct cpu *, char *, size_t); 539 extern const char *cpuid_getvendorstr(struct cpu *); 540 extern uint_t cpuid_getvendor(struct cpu *); 541 extern uint_t cpuid_getfamily(struct cpu *); 542 extern uint_t cpuid_getmodel(struct cpu *); 543 extern uint_t cpuid_getstep(struct cpu *); 544 extern uint_t cpuid_getsig(struct cpu *); 545 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 546 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 547 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 548 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 549 extern int cpuid_get_chipid(struct cpu *); 550 extern id_t cpuid_get_coreid(struct cpu *); 551 extern int cpuid_get_pkgcoreid(struct cpu *); 552 extern int cpuid_get_clogid(struct cpu *); 553 extern int cpuid_is_cmt(struct cpu *); 554 extern int cpuid_syscall32_insn(struct cpu *); 555 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 556 557 extern uint32_t cpuid_getchiprev(struct cpu *); 558 extern const char *cpuid_getchiprevstr(struct cpu *); 559 extern uint32_t cpuid_getsockettype(struct cpu *); 560 561 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 562 563 struct cpuid_info; 564 565 extern void setx86isalist(void); 566 extern void cpuid_alloc_space(struct cpu *); 567 extern void cpuid_free_space(struct cpu *); 568 extern uint_t cpuid_pass1(struct cpu *); 569 extern void cpuid_pass2(struct cpu *); 570 extern void cpuid_pass3(struct cpu *); 571 extern uint_t cpuid_pass4(struct cpu *); 572 extern void add_cpunode2devtree(processorid_t, struct cpuid_info *); 573 574 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 575 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 576 577 #if !defined(__xpv) 578 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 579 extern void cpuid_mwait_free(struct cpu *); 580 #endif 581 582 struct cpu_ucode_info; 583 584 #if !defined(__xpv) 585 extern void ucode_alloc_space(struct cpu *); 586 extern void ucode_free_space(struct cpu *); 587 extern void ucode_check(struct cpu *); 588 extern void ucode_free(); 589 #endif 590 591 #if !defined(__xpv) 592 extern char _tsc_mfence_start; 593 extern char _tsc_mfence_end; 594 extern char _tscp_start; 595 extern char _tscp_end; 596 extern char _no_rdtsc_start; 597 extern char _no_rdtsc_end; 598 extern char _tsc_lfence_start; 599 extern char _tsc_lfence_end; 600 #endif 601 602 extern uint_t workaround_errata(struct cpu *); 603 604 #if defined(OPTERON_ERRATUM_93) 605 extern int opteron_erratum_93; 606 #endif 607 608 #if defined(OPTERON_ERRATUM_91) 609 extern int opteron_erratum_91; 610 #endif 611 612 #if defined(OPTERON_ERRATUM_100) 613 extern int opteron_erratum_100; 614 #endif 615 616 #if defined(OPTERON_ERRATUM_121) 617 extern int opteron_erratum_121; 618 #endif 619 620 #if defined(OPTERON_WORKAROUND_6323525) 621 extern int opteron_workaround_6323525; 622 extern void patch_workaround_6323525(void); 623 #endif 624 625 #endif /* _KERNEL */ 626 627 #endif 628 629 #ifdef __cplusplus 630 } 631 #endif 632 633 #endif /* _SYS_X86_ARCHEXT_H */ 634