1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 22 * Use is subject to license terms. 23 */ 24 25 #ifndef _MC_AMD_H 26 #define _MC_AMD_H 27 28 #pragma ident "%Z%%M% %I% %E% SMI" 29 30 #include <sys/mc.h> 31 #include <sys/x86_archext.h> 32 33 /* 34 * The mc-amd driver exports an nvlist to userland, where the primary 35 * consumer is the "chip" topology enumerator for this platform type which 36 * builds a full topology subtree from this information. Others can use 37 * it, too, but don't depend on it not changing without an ARC contract. 38 * 39 * In the initial mc-amd implementation this nvlist was not versioned; 40 * we'll think of that as version 0 and it may be recognised by the absence 41 * of a "mcamd-nvlist-version member. 42 * 43 * Version 1 is defined as follows. A name in square brackets indicates 44 * that member is optional (only present if the actual value is valid). 45 * 46 * Name Type Description 47 * -------------------- --------------- --------------------------------------- 48 * mcamd-nvlist-version uint8 Exported nvlist version number 49 * num uint64 Chip id of this memory controller 50 * revision uint64 cpuid_getchiprev() result 51 * revname string cpuid_getchiprevstr() result 52 * socket string "Socket 755|939|940|AM2|F(1207)|S1g1" 53 * ecc-type string "ChipKill 128/16" or "Normal 64/8" 54 * base-addr uint64 Node base address 55 * lim-addr uint64 Node limit address 56 * node-ilen uint64 0|1|3|7 for 0/2/4/8 way node interleave 57 * node-ilsel uint64 Node interleave position of this node 58 * cs-intlv-factor uint64 chip-select interleave: 1/2/4/8 59 * dram-hole-size uint64 size in bytes from dram hole addr reg 60 * access-width uint64 MC mode, 64 or 128 bit 61 * bank-mapping uint64 Raw DRAM Bank Address Mapping Register 62 * bankswizzle uint64 1 if bank swizzling enabled; else 0 63 * mismatched-dimm-support uint64 1 if active; else 0 64 * [spare-csnum] uint64 Chip-select pair number of any spare 65 * [bad-csnum] uint64 Chip-select pair number of swapped cs 66 * cslist nvlist array See below; may have 0 members 67 * dimmlist nvlist array See below; may have 0 members 68 * 69 * cslist is an array of nvlist, each as follows: 70 * 71 * Name Type Description 72 * -------------------- --------------- --------------------------------------- 73 * num uint64 Chip-select base/mask pair number 74 * base-addr uint64 Chip-select base address (rel to node) 75 * mask uint64 Chip-select mask 76 * size uint64 Chip-select size in bytes 77 * dimm1-num uint64 First dimm (lodimm if a pair) 78 * dimm1-csname string Socket cs# line name for 1st dimm rank 79 * [dimm2-num] uint64 Second dimm if applicable (updimm) 80 * [dimm2-csname] string Socket cs# line name for 2nd dimm rank 81 * 82 * dimmlist is an array of nvlist, each as follows: 83 * 84 * Name Type Description 85 * -------------------- --------------- --------------------------------------- 86 * num uint64 DIMM instance number 87 * size uint64 DIMM size in bytes 88 * csnums uint64 array CS base/mask pair(s) on this DIMM 89 * csnames string array Socket cs# line name(s) on this DIMM 90 * 91 * The n'th csnums entry corresponds to the n'th csnames entry 92 */ 93 #define MC_NVLIST_VERSTR "mcamd-nvlist-version" 94 #define MC_NVLIST_VERS0 0 95 #define MC_NVLIST_VERS1 1 96 #define MC_NVLIST_VERS MC_NVLIST_VERS1 97 98 /* 99 * Definitions describing various memory controller constant properties and 100 * the structure of configuration registers. 101 */ 102 103 #ifdef __cplusplus 104 extern "C" { 105 #endif 106 107 /* 108 * Constants and feature/revision test macros that are not expected to vary 109 * among different AMD family 0xf processor revisions. 110 */ 111 112 /* 113 * Configuration constants 114 */ 115 #define MC_CHIP_MAXNODES 8 /* max number of MCs in system */ 116 #define MC_CHIP_NDIMM 8 /* max dimms per MC */ 117 #define MC_CHIP_NCS 8 /* number of chip-selects per MC */ 118 #define MC_CHIP_NDRAMCHAN 2 /* maximum number of dram channels */ 119 #define MC_CHIP_DIMMRANKMAX 4 /* largest number of ranks per dimm */ 120 #define MC_CHIP_DIMMPERCS 2 /* max number of dimms per cs */ 121 #define MC_CHIP_DIMMPAIR(csnum) (csnum / MC_CHIP_DIMMPERCS) 122 123 #if MC_CHIP_DIMMPERCS > MC_UNUM_NDIMM 124 #error "MC_CHIP_DIMMPERCS exceeds MC_UNUM_NDIMM" 125 #endif 126 127 /* 128 * MC_REV_* are used a a convenient shorter form of the X86_CHIPREV 129 * counterparts; these must map directly as we fill mcp_rev from 130 * a cpuid_getchiprev call. 131 */ 132 #define MC_REV_UNKNOWN X86_CHIPREV_UNKNOWN 133 #define MC_REV_B X86_CHIPREV_AMD_F_REV_B 134 #define MC_REV_C (X86_CHIPREV_AMD_F_REV_C0 | X86_CHIPREV_AMD_F_REV_CG) 135 #define MC_REV_D X86_CHIPREV_AMD_F_REV_D 136 #define MC_REV_E X86_CHIPREV_AMD_F_REV_E 137 #define MC_REV_F X86_CHIPREV_AMD_F_REV_F 138 #define MC_REV_G X86_CHIPREV_AMD_F_REV_G 139 140 /* 141 * The most common groupings for memory controller features. 142 */ 143 #define MC_REVS_BC (MC_REV_B | MC_REV_C) 144 #define MC_REVS_DE (MC_REV_D | MC_REV_E) 145 #define MC_REVS_BCDE (MC_REVS_BC | MC_REVS_DE) 146 #define MC_REVS_FG (MC_REV_F | MC_REV_G) 147 148 /* 149 * Is 'rev' included in the 'revmask' bitmask? 150 */ 151 #define MC_REV_MATCH(rev, revmask) X86_CHIPREV_MATCH(rev, revmask) 152 153 /* 154 * Is 'rev' at least revision 'revmin' or greater 155 */ 156 #define MC_REV_ATLEAST(rev, minrev) X86_CHIPREV_ATLEAST(rev, minrev) 157 158 /* 159 * Chip socket types 160 */ 161 #define MC_SKT_UNKNOWN 0x0 162 #define MC_SKT_754 0x1 163 #define MC_SKT_939 0x2 164 #define MC_SKT_940 0x3 165 #define MC_SKT_S1g1 0x4 166 #define MC_SKT_AM2 0x5 167 #define MC_SKT_F1207 0x6 168 169 /* 170 * Memory controller registers are read via PCI config space accesses on 171 * bus 0, device 24 + NodeId, and function as follows: 172 * 173 * Function 0: HyperTransport Technology Configuration 174 * Function 1: Address Map 175 * Function 2: DRAM Controller & HyperTransport Technology Trace Mode 176 * Function 3: Miscellaneous Control 177 * 178 * For a given (bus, device, function) a particular offset selects the 179 * desired register. All registers are 32-bits wide. 180 * 181 * Different family 0xf processor revisions vary slightly in the content 182 * of these configuration registers. The biggest change is with rev F 183 * where DDR2 support has been introduced along with some hardware-controlled 184 * correctable memory error thresholding. Fortunately most of the config info 185 * required by the mc-amd driver is similar across revisions. 186 * 187 * We will try to insulate most of the driver code from config register 188 * details by reading all memory-controller PCI config registers that we 189 * will need at driver attach time for each of functions 0 through 3, and 190 * storing them in a "cooked" form as memory controller properties. 191 * These are to be accessed directly where we have an mc_t to hand, otherwise 192 * through mcamd_get_numprop. As such we expect most/all use of the 193 * structures and macros defined below to be in those attach codepaths. 194 */ 195 196 /* 197 * Registers will be represented as unions, with one fixed-width unsigned 198 * integer member providing access to the raw register value and one or more 199 * structs breaking the register out into bitfields (more than one struct if 200 * the register definitions varies across processor revisions). 201 * 202 * The "raw" union member will always be '_val32'. Use MCREG_VAL32 to 203 * access this member. 204 * 205 * The bitfield structs are all named _fmt_xxx where xxx identifies the 206 * processor revision to which it applies. At this point the only xxx 207 * values in use are: 208 * 'cmn' - applies to all revisions 209 * 'preF' - applies to revisions E and earlier 210 * 'revFG' - applies to revisions F and G 211 * Variants such as 'preD', 'revDE', 'postCG' etc should be introduced 212 * as requirements arise. The MC_REV_* and MC_REV_MATCH etc macros 213 * will also need to grow to match. Use MCREG_FIELD_* to access the 214 * individual bitfields of a register, perhaps using MC_REV_* and MC_REV_MATCH 215 * to decide which revision suffix to provide. Where a bitfield appears 216 * in different revisions but has the same use it should be named identically 217 * (even if the BKDG varies a little) so that the MC_REG_FIELD_* macros 218 * can lookup that member based on revision only. 219 */ 220 221 #define _MCREG_FIELD(up, revsuffix, field) ((up)->_fmt_##revsuffix.field) 222 223 #define MCREG_VAL32(up) ((up)->_val32) 224 225 #define MCREG_FIELD_CMN(up, field) _MCREG_FIELD(up, cmn, field) 226 #define MCREG_FIELD_preF(up, field) _MCREG_FIELD(up, preF, field) 227 #define MCREG_FIELD_revFG(up, field) _MCREG_FIELD(up, revFG, field) 228 229 /* 230 * Function 1 - DRAM Address Map: DRAM Base i Registers 231 * 232 */ 233 234 union mcreg_drambase { 235 uint32_t _val32; 236 struct { 237 uint32_t RE:1; /* 0:0 - Read Enable */ 238 uint32_t WE:1; /* 1:1 - Write Enable */ 239 uint32_t reserved1:6; /* 7:2 */ 240 uint32_t IntlvEn:3; /* 10:8 - Interleave Enable */ 241 uint32_t reserved2:5; /* 15:11 */ 242 uint32_t DRAMBasei:16; /* 31:16 - Base Addr 39:24 */ 243 } _fmt_cmn; 244 }; 245 246 #define MC_DRAMBASE(up) ((uint64_t)MCREG_FIELD_CMN(up, DRAMBasei) << 24) 247 248 /* 249 * Function 1 - DRAM Address Map: DRAM Limit i Registers 250 * 251 */ 252 253 union mcreg_dramlimit { 254 uint32_t _val32; 255 struct { 256 uint32_t DstNode:3; /* 2:0 - Destination Node */ 257 uint32_t reserved1:5; /* 7:3 */ 258 uint32_t IntlvSel:3; /* 10:8 - Interleave Select */ 259 uint32_t reserved2:5; /* 15:11 */ 260 uint32_t DRAMLimiti:16; /* 31:16 - Limit Addr 39:24 */ 261 } _fmt_cmn; 262 }; 263 264 #define MC_DRAMLIM(up) \ 265 ((uint64_t)MCREG_FIELD_CMN(up, DRAMLimiti) << 24 | \ 266 (MCREG_FIELD_CMN(up, DRAMLimiti) ? ((1 << 24) - 1) : 0)) 267 268 /* 269 * Function 1 - DRAM Address Map: DRAM Hole Address Register 270 */ 271 272 union mcreg_dramhole { 273 uint32_t _val32; 274 struct { 275 uint32_t DramHoleValid:1; /* 0:0 */ 276 uint32_t reserved1:7; /* 7:1 */ 277 uint32_t DramHoleOffset:8; /* 15:8 */ 278 uint32_t reserved2:8; /* 23:16 */ 279 uint32_t DramHoleBase:8; /* 31:24 */ 280 } _fmt_cmn; 281 }; 282 283 #define MC_DRAMHOLE_SIZE(up) (MCREG_FIELD_CMN(up, DramHoleOffset) << 24) 284 285 /* 286 * Function 2 - DRAM Controller: DRAM CS Base Address Registers 287 */ 288 289 union mcreg_csbase { 290 uint32_t _val32; 291 /* 292 * Register format in revisions E and earlier 293 */ 294 struct { 295 uint32_t CSEnable:1; /* 0:0 - CS Bank Enable */ 296 uint32_t reserved1:8; /* 8:1 */ 297 uint32_t BaseAddrLo:7; /* 15:9 - Base Addr 19:13 */ 298 uint32_t reserved2:5; /* 20:16 */ 299 uint32_t BaseAddrHi:11; /* 31:21 - Base Addr 35:25 */ 300 } _fmt_preF; 301 /* 302 * Register format in revisions F and G 303 */ 304 struct { 305 uint32_t CSEnable:1; /* 0:0 - CS Bank Enable */ 306 uint32_t Spare:1; /* 1:1 - Spare Rank */ 307 uint32_t TestFail:1; /* 2:2 - Memory Test Failed */ 308 uint32_t reserved1:2; /* 4:3 */ 309 uint32_t BaseAddrLo:9; /* 13:5 - Base Addr 21:13 */ 310 uint32_t reserved2:5; /* 18:14 */ 311 uint32_t BaseAddrHi:10; /* 28:19 - Base Addr 36:27 */ 312 uint32_t reserved3:3; /* 31:39 */ 313 } _fmt_revFG; 314 }; 315 316 #define MC_CSBASE(up, rev) (MC_REV_MATCH(rev, MC_REV_F) ? \ 317 (uint64_t)MCREG_FIELD_revFG(up, BaseAddrHi) << 27 | \ 318 (uint64_t)MCREG_FIELD_revFG(up, BaseAddrLo) << 13 : \ 319 (uint64_t)MCREG_FIELD_preF(up, BaseAddrHi) << 25 | \ 320 (uint64_t)MCREG_FIELD_preF(up, BaseAddrLo) << 13) 321 322 /* 323 * Function 2 - DRAM Controller: DRAM CS Mask Registers 324 */ 325 326 union mcreg_csmask { 327 uint32_t _val32; 328 /* 329 * Register format in revisions E and earlier 330 */ 331 struct { 332 uint32_t reserved1:9; /* 8:0 */ 333 uint32_t AddrMaskLo:7; /* 15:9 - Addr Mask 19:13 */ 334 uint32_t reserved2:5; /* 20:16 */ 335 uint32_t AddrMaskHi:9; /* 29:21 - Addr Mask 33:25 */ 336 uint32_t reserved3:2; /* 31:30 */ 337 } _fmt_preF; 338 /* 339 * Register format in revisions F and G 340 */ 341 struct { 342 uint32_t reserved1:5; /* 4:0 */ 343 uint32_t AddrMaskLo:9; /* 13:5 - Addr Mask 21:13 */ 344 uint32_t reserved2:5; /* 18:14 */ 345 uint32_t AddrMaskHi:10; /* 28:19 - Addr Mask 36:27 */ 346 uint32_t reserved3:3; /* 31:29 */ 347 } _fmt_revFG; 348 }; 349 350 #define MC_CSMASKLO_LOBIT(rev) (MC_REV_MATCH(rev, MC_REV_F) ? 13 : 13) 351 #define MC_CSMASKLO_HIBIT(rev) (MC_REV_MATCH(rev, MC_REV_F) ? 21 : 19) 352 353 #define MC_CSMASKHI_LOBIT(rev) (MC_REV_MATCH(rev, MC_REV_F) ? 27 : 25) 354 #define MC_CSMASKHI_HIBIT(rev) (MC_REV_MATCH(rev, MC_REV_F) ? 36 : 33) 355 356 #define MC_CSMASK_UNMASKABLE(rev) (MC_REV_MATCH(rev, MC_REV_F) ? 0 : 2) 357 358 #define MC_CSMASK(up, rev) (MC_REV_MATCH(rev, MC_REV_F) ? \ 359 (uint64_t)MCREG_FIELD_revFG(up, AddrMaskHi) << 27 | \ 360 (uint64_t)MCREG_FIELD_revFG(up, AddrMaskLo) << 13 | 0x7c01fff : \ 361 (uint64_t)MCREG_FIELD_preF(up, AddrMaskHi) << 25 | \ 362 (uint64_t)MCREG_FIELD_preF(up, AddrMaskLo) << 13 | 0x1f01fff) 363 364 /* 365 * Function 2 - DRAM Controller: DRAM Bank Address Mapping Registers 366 */ 367 368 union mcreg_bankaddrmap { 369 uint32_t _val32; 370 /* 371 * Register format in revisions E and earlier 372 */ 373 struct { 374 uint32_t cs10:4; /* 3:0 - CS1/0 */ 375 uint32_t cs32:4; /* 7:4 - CS3/2 */ 376 uint32_t cs54:4; /* 11:8 - CS5/4 */ 377 uint32_t cs76:4; /* 15:12 - CS7/6 */ 378 uint32_t reserved1:14; /* 29:16 */ 379 uint32_t BankSwizzleMode:1; /* 30:30 */ 380 uint32_t reserved2:1; /* 31:31 */ 381 } _fmt_preF; 382 /* 383 * Register format in revisions F and G 384 */ 385 struct { 386 uint32_t cs10:4; /* 3:0 - CS1/0 */ 387 uint32_t cs32:4; /* 7:4 - CS3/2 */ 388 uint32_t cs54:4; /* 11:8 - CS5/4 */ 389 uint32_t cs76:4; /* 15:12 - CS7/6 */ 390 uint32_t reserved1:16; /* 31:16 */ 391 } _fmt_revFG; 392 /* 393 * Accessing all mode encodings as one uint16 394 */ 395 struct { 396 uint32_t allcsmodes:16; /* 15:0 */ 397 uint32_t pad:16; /* 31:16 */ 398 } _fmt_bankmodes; 399 }; 400 401 #define MC_DC_BAM_CSBANK_MASK 0x0000000f 402 #define MC_DC_BAM_CSBANK_SHIFT 4 403 404 #define MC_CSBANKMODE(up, csnum) ((up)->_fmt_bankmodes.allcsmodes >> \ 405 MC_DC_BAM_CSBANK_SHIFT * MC_CHIP_DIMMPAIR(csnum) & MC_DC_BAM_CSBANK_MASK) 406 407 /* 408 * Function 2 - DRAM Controller: DRAM Configuration Low and High 409 */ 410 411 union mcreg_dramcfg_lo { 412 uint32_t _val32; 413 /* 414 * Register format in revisions E and earlier. 415 * Bit 7 is a BIOS ScratchBit in revs D and earlier, 416 * PwrDwnTriEn in revision E; we don't use it so 417 * we'll call it ambig1. 418 */ 419 struct { 420 uint32_t DLL_Dis:1; /* 0 */ 421 uint32_t D_DRV:1; /* 1 */ 422 uint32_t QFC_EN:1; /* 2 */ 423 uint32_t DisDqsHys:1; /* 3 */ 424 uint32_t reserved1:1; /* 4 */ 425 uint32_t Burst2Opt:1; /* 5 */ 426 uint32_t Mod64BitMux:1; /* 6 */ 427 uint32_t ambig1:1; /* 7 */ 428 uint32_t DramInit:1; /* 8 */ 429 uint32_t DualDimmEn:1; /* 9 */ 430 uint32_t DramEnable:1; /* 10 */ 431 uint32_t MemClrStatus:1; /* 11 */ 432 uint32_t ESR:1; /* 12 */ 433 uint32_t SR_S:1; /* 13 */ 434 uint32_t RdWrQByp:2; /* 15:14 */ 435 uint32_t Width128:1; /* 16 */ 436 uint32_t DimmEcEn:1; /* 17 */ 437 uint32_t UnBufDimm:1; /* 18 */ 438 uint32_t ByteEn32:1; /* 19 */ 439 uint32_t x4DIMMs:4; /* 23:20 */ 440 uint32_t DisInRcvrs:1; /* 24 */ 441 uint32_t BypMax:3; /* 27:25 */ 442 uint32_t En2T:1; /* 28 */ 443 uint32_t UpperCSMap:1; /* 29 */ 444 uint32_t PwrDownCtl:2; /* 31:30 */ 445 } _fmt_preF; 446 /* 447 * Register format in revisions F and G 448 */ 449 struct { 450 uint32_t InitDram:1; /* 0 */ 451 uint32_t ExitSelfRef:1; /* 1 */ 452 uint32_t reserved1:2; /* 3:2 */ 453 uint32_t DramTerm:2; /* 5:4 */ 454 uint32_t reserved2:1; /* 6 */ 455 uint32_t DramDrvWeak:1; /* 7 */ 456 uint32_t ParEn:1; /* 8 */ 457 uint32_t SelRefRateEn:1; /* 9 */ 458 uint32_t BurstLength32:1; /* 10 */ 459 uint32_t Width128:1; /* 11 */ 460 uint32_t x4DIMMs:4; /* 15:12 */ 461 uint32_t UnBuffDimm:1; /* 16 */ 462 uint32_t reserved3:2; /* 18:17 */ 463 uint32_t DimmEccEn:1; /* 19 */ 464 uint32_t reserved4:12; /* 31:20 */ 465 } _fmt_revFG; 466 }; 467 468 /* 469 * Function 2 - DRAM Controller: DRAM Controller Miscellaneous Data 470 */ 471 472 union mcreg_drammisc { 473 uint32_t _val32; 474 /* 475 * Register format in revisions F and G 476 */ 477 struct { 478 uint32_t reserved2:1; /* 0 */ 479 uint32_t DisableJitter:1; /* 1 */ 480 uint32_t RdWrQByp:2; /* 3:2 */ 481 uint32_t Mod64Mux:1; /* 4 */ 482 uint32_t DCC_EN:1; /* 5 */ 483 uint32_t ILD_lmt:3; /* 8:6 */ 484 uint32_t DramEnabled:1; /* 9 */ 485 uint32_t PwrSavingsEn:1; /* 10 */ 486 uint32_t reserved1:13; /* 23:11 */ 487 uint32_t MemClkDis:8; /* 31:24 */ 488 } _fmt_revFG; 489 }; 490 491 union mcreg_dramcfg_hi { 492 uint32_t _val32; 493 /* 494 * Register format in revisions E and earlier. 495 */ 496 struct { 497 uint32_t AsyncLat:4; /* 3:0 */ 498 uint32_t reserved1:4; /* 7:4 */ 499 uint32_t RdPreamble:4; /* 11:8 */ 500 uint32_t reserved2:1; /* 12 */ 501 uint32_t MemDQDrvStren:2; /* 14:13 */ 502 uint32_t DisableJitter:1; /* 15 */ 503 uint32_t ILD_lmt:3; /* 18:16 */ 504 uint32_t DCC_EN:1; /* 19 */ 505 uint32_t MemClk:3; /* 22:20 */ 506 uint32_t reserved3:2; /* 24:23 */ 507 uint32_t MCR:1; /* 25 */ 508 uint32_t MC0_EN:1; /* 26 */ 509 uint32_t MC1_EN:1; /* 27 */ 510 uint32_t MC2_EN:1; /* 28 */ 511 uint32_t MC3_EN:1; /* 29 */ 512 uint32_t reserved4:1; /* 30 */ 513 uint32_t OddDivisorCorrect:1; /* 31 */ 514 } _fmt_preF; 515 /* 516 * Register format in revisions F and G 517 */ 518 struct { 519 uint32_t MemClkFreq:3; /* 2:0 */ 520 uint32_t MemClkFreqVal:1; /* 3 */ 521 uint32_t MaxAsyncLat:4; /* 7:4 */ 522 uint32_t reserved1:4; /* 11:8 */ 523 uint32_t RDqsEn:1; /* 12 */ 524 uint32_t reserved2:1; /* 13 */ 525 uint32_t DisDramInterface:1; /* 14 */ 526 uint32_t PowerDownEn:1; /* 15 */ 527 uint32_t PowerDownMode:1; /* 16 */ 528 uint32_t FourRankSODimm:1; /* 17 */ 529 uint32_t FourRankRDimm:1; /* 18 */ 530 uint32_t reserved3:1; /* 19 */ 531 uint32_t SlowAccessMode:1; /* 20 */ 532 uint32_t reserved4:1; /* 21 */ 533 uint32_t BankSwizzleMode:1; /* 22 */ 534 uint32_t undocumented1:1; /* 23 */ 535 uint32_t DcqBypassMax:4; /* 27:24 */ 536 uint32_t FourActWindow:4; /* 31:28 */ 537 } _fmt_revFG; 538 }; 539 540 /* 541 * Function 3 - Miscellaneous Control: Scrub Control Register 542 */ 543 544 union mcreg_scrubctl { 545 uint32_t _val32; 546 struct { 547 uint32_t DramScrub:5; /* 4:0 */ 548 uint32_t reserved3:3; /* 7:5 */ 549 uint32_t L2Scrub:5; /* 12:8 */ 550 uint32_t reserved2:3; /* 15:13 */ 551 uint32_t DcacheScrub:5; /* 20:16 */ 552 uint32_t reserved1:11; /* 31:21 */ 553 } _fmt_cmn; 554 }; 555 556 /* 557 * Function 3 - Miscellaneous Control: On-Line Spare Control Register 558 */ 559 560 union mcreg_nbcfg { 561 uint32_t _val32; 562 /* 563 * Register format in revisions E and earlier. 564 */ 565 struct { 566 uint32_t CpuEccErrEn:1; /* 0 */ 567 uint32_t CpuRdDatErrEn:1; /* 1 */ 568 uint32_t SyncOnUcEccEn:1; /* 2 */ 569 uint32_t SyncPktGenDis:1; /* 3 */ 570 uint32_t SyncPktPropDis:1; /* 4 */ 571 uint32_t IoMstAbortDis:1; /* 5 */ 572 uint32_t CpuErrDis:1; /* 6 */ 573 uint32_t IoErrDis:1; /* 7 */ 574 uint32_t WdogTmrDis:1; /* 8 */ 575 uint32_t WdogTmrCntSel:3; /* 11:9 */ 576 uint32_t WdogTmrBaseSel:2; /* 13:12 */ 577 uint32_t LdtLinkSel:2; /* 15:14 */ 578 uint32_t GenCrcErrByte0:1; /* 16 */ 579 uint32_t GenCrcErrByte1:1; /* 17 */ 580 uint32_t reserved1:2; /* 19:18 */ 581 uint32_t SyncOnWdogEn:1; /* 20 */ 582 uint32_t SyncOnAnyErrEn:1; /* 21 */ 583 uint32_t EccEn:1; /* 22 */ 584 uint32_t ChipKillEccEn:1; /* 23 */ 585 uint32_t IoRdDatErrEn:1; /* 24 */ 586 uint32_t DisPciCfgCpuErrRsp:1; /* 25 */ 587 uint32_t reserved2:1; /* 26 */ 588 uint32_t NbMcaToMstCpuEn:1; /* 27 */ 589 uint32_t reserved3:4; /* 31:28 */ 590 } _fmt_preF; 591 /* 592 * Register format in revisions F and G 593 */ 594 struct { 595 uint32_t CpuEccErrEn:1; /* 0 */ 596 uint32_t CpuRdDatErrEn:1; /* 1 */ 597 uint32_t SyncOnUcEccEn:1; /* 2 */ 598 uint32_t SyncPktGenDis:1; /* 3 */ 599 uint32_t SyncPktPropDis:1; /* 4 */ 600 uint32_t IoMstAbortDis:1; /* 5 */ 601 uint32_t CpuErrDis:1; /* 6 */ 602 uint32_t IoErrDis:1; /* 7 */ 603 uint32_t WdogTmrDis:1; /* 8 */ 604 uint32_t WdogTmrCntSel:3; /* 11:9 */ 605 uint32_t WdogTmrBaseSel:2; /* 13:12 */ 606 uint32_t LdtLinkSel:2; /* 15:14 */ 607 uint32_t GenCrcErrByte0:1; /* 16 */ 608 uint32_t GenCrcErrByte1:1; /* 17 */ 609 uint32_t reserved1:2; /* 19:18 */ 610 uint32_t SyncOnWdogEn:1; /* 20 */ 611 uint32_t SyncOnAnyErrEn:1; /* 21 */ 612 uint32_t EccEn:1; /* 22 */ 613 uint32_t ChipKillEccEn:1; /* 23 */ 614 uint32_t IoRdDatErrEn:1; /* 24 */ 615 uint32_t DisPciCfgCpuErrRsp:1; /* 25 */ 616 uint32_t reserved2:1; /* 26 */ 617 uint32_t NbMcaToMstCpuEn:1; /* 27 */ 618 uint32_t DisTgtAbtCpuErrRsp:1; /* 28 */ 619 uint32_t DisMstAbtCpuErrRsp:1; /* 29 */ 620 uint32_t SyncOnDramAdrParErrEn:1; /* 30 */ 621 uint32_t reserved3:1; /* 31 */ 622 623 } _fmt_revFG; 624 }; 625 626 /* 627 * Function 3 - Miscellaneous Control: On-Line Spare Control Register 628 */ 629 630 union mcreg_sparectl { 631 uint32_t _val32; 632 /* 633 * Register format in revisions F and G 634 */ 635 struct { 636 uint32_t SwapEn:1; /* 0 */ 637 uint32_t SwapDone:1; /* 1 */ 638 uint32_t reserved1:2; /* 3:2 */ 639 uint32_t BadDramCs:3; /* 6:4 */ 640 uint32_t reserved2:5; /* 11:7 */ 641 uint32_t SwapDoneInt:2; /* 13:12 */ 642 uint32_t EccErrInt:2; /* 15:14 */ 643 uint32_t EccErrCntDramCs:3; /* 18:16 */ 644 uint32_t reserved3:1; /* 19 */ 645 uint32_t EccErrCntDramChan:1; /* 20 */ 646 uint32_t reserved4:2; /* 22:21 */ 647 uint32_t EccErrCntWrEn:1; /* 23 */ 648 uint32_t EccErrCnt:4; /* 27:24 */ 649 uint32_t reserved5:4; /* 31:28 */ 650 } _fmt_revFG; 651 }; 652 653 #ifdef __cplusplus 654 } 655 #endif 656 657 #endif /* _MC_AMD_H */ 658