1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_MACHLOCK_H 27 #define _SYS_MACHLOCK_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifndef _ASM 32 #include <sys/types.h> 33 #include <sys/time.h> 34 #endif /* _ASM */ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #ifndef _ASM 41 42 #ifdef _KERNEL 43 44 extern void lock_set(lock_t *lp); 45 extern int lock_try(lock_t *lp); 46 extern int lock_spin_try(lock_t *lp); 47 extern int ulock_try(lock_t *lp); 48 extern void lock_clear(lock_t *lp); 49 extern void ulock_clear(lock_t *lp); 50 extern void lock_set_spl(lock_t *lp, int new_pil, ushort_t *old_pil); 51 extern void lock_clear_splx(lock_t *lp, int s); 52 53 #endif /* _KERNEL */ 54 55 #define LOCK_HELD_VALUE 0xff 56 #define LOCK_INIT_CLEAR(lp) (*(lp) = 0) 57 #define LOCK_INIT_HELD(lp) (*(lp) = LOCK_HELD_VALUE) 58 #define LOCK_HELD(lp) (*(volatile lock_t *)(lp) != 0) 59 60 typedef lock_t disp_lock_t; /* dispatcher lock type */ 61 62 /* 63 * SPIN_LOCK() macro indicates whether lock is implemented as a spin lock or 64 * an adaptive mutex, depending on what interrupt levels use it. 65 */ 66 #define SPIN_LOCK(pl) ((pl) > ipltospl(LOCK_LEVEL)) 67 68 /* 69 * Macro to control loops which spin on a lock and then check state 70 * periodically. Its passed an integer, and returns a boolean value 71 * that if true indicates its a good time to get the scheduler lock and 72 * check the state of the current owner of the lock. 73 */ 74 #define LOCK_SAMPLE_INTERVAL(i) (((i) & 0xff) == 0) 75 76 /* 77 * Externs for CLOCK_LOCK and clock resolution 78 */ 79 extern volatile int hres_lock; 80 extern hrtime_t hrtime_base; 81 extern int clock_res; 82 83 #endif /* _ASM */ 84 85 /* 86 * The definitions of the symbolic interrupt levels: 87 * 88 * CLOCK_LEVEL => The level at which one must be to block the clock. 89 * 90 * LOCK_LEVEL => The highest level at which one may block (and thus the 91 * highest level at which one may acquire adaptive locks) 92 * Also the highest level at which one may be preempted. 93 * 94 * DISP_LEVEL => The level at which one must be to perform dispatcher 95 * operations. 96 * 97 * The constraints on the platform: 98 * 99 * - CLOCK_LEVEL must be less than or equal to LOCK_LEVEL 100 * - LOCK_LEVEL must be less than DISP_LEVEL 101 * - DISP_LEVEL should be as close to LOCK_LEVEL as possible 102 * 103 * Note that LOCK_LEVEL and CLOCK_LEVEL have historically always been equal; 104 * changing this relationship is probably possible but not advised. 105 * 106 */ 107 108 #define PIL_MAX 15 109 110 #define CLOCK_LEVEL 10 111 #define LOCK_LEVEL 10 112 #define DISP_LEVEL (LOCK_LEVEL + 1) 113 114 #define HIGH_LEVELS (PIL_MAX - LOCK_LEVEL) 115 116 /* 117 * The following mask is for the cpu_intr_actv bits corresponding to 118 * high-level PILs. It should equal: 119 * ((((1 << PIL_MAX + 1) - 1) >> LOCK_LEVEL + 1) << LOCK_LEVEL + 1) 120 */ 121 #define CPU_INTR_ACTV_HIGH_LEVEL_MASK 0xF800 122 123 /* 124 * The semaphore code depends on being able to represent a lock plus 125 * owner in a single 32-bit word. (Mutexes used to have a similar 126 * dependency, but no longer.) Thus the owner must contain at most 127 * 24 significant bits. At present only threads and semaphores 128 * must be aware of this vile constraint. Different ISAs may handle this 129 * differently depending on their capabilities (e.g. compare-and-swap) 130 * and limitations (e.g. constraints on alignment and/or KERNELBASE). 131 */ 132 #define PTR24_LSB 5 /* lower bits all zero */ 133 #define PTR24_MSB (PTR24_LSB + 24) /* upper bits all one */ 134 #define PTR24_ALIGN 32 /* minimum alignment (1 << lsb) */ 135 #define PTR24_BASE 0xe0000000 /* minimum ptr value (-1 >> (32-msb)) */ 136 137 #ifdef __cplusplus 138 } 139 #endif 140 141 #endif /* _SYS_MACHLOCK_H */ 142