1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2015 Nexenta Systems, Inc. All rights reserved. 23 * 24 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved. 25 */ 26 27 /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */ 28 /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */ 29 /* All Rights Reserved */ 30 31 #ifndef _SYS_FP_H 32 #define _SYS_FP_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* 39 * 80287/80387 and SSE/SSE2 floating point processor definitions 40 */ 41 42 /* 43 * values that go into fp_kind 44 */ 45 #define FP_NO 0 /* no fp chip, no emulator (no fp support) */ 46 #define FP_SW 1 /* no fp chip, using software emulator */ 47 #define FP_HW 2 /* chip present bit */ 48 #define FP_287 2 /* 80287 chip present */ 49 #define FP_387 3 /* 80387 chip present */ 50 #define FP_487 6 /* 80487 chip present */ 51 #define FP_486 6 /* 80486 chip present */ 52 /* 53 * The following values are bit flags instead of actual values. 54 * E.g. to know if we are using SSE, test (value & __FP_SSE) instead 55 * of (value == __FP_SSE). 56 */ 57 #define __FP_SSE 0x100 /* .. plus SSE-capable CPU */ 58 #define __FP_AVX 0x200 /* .. plus AVX-capable CPU */ 59 60 /* 61 * values that go into fp_save_mech 62 */ 63 #define FP_FNSAVE 1 /* fnsave/frstor instructions */ 64 #define FP_FXSAVE 2 /* fxsave/fxrstor instructions */ 65 #define FP_XSAVE 3 /* xsave/xrstor instructions */ 66 67 /* 68 * masks for 80387 control word 69 */ 70 #define FPIM 0x00000001 /* invalid operation */ 71 #define FPDM 0x00000002 /* denormalized operand */ 72 #define FPZM 0x00000004 /* zero divide */ 73 #define FPOM 0x00000008 /* overflow */ 74 #define FPUM 0x00000010 /* underflow */ 75 #define FPPM 0x00000020 /* precision */ 76 #define FPPC 0x00000300 /* precision control */ 77 #define FPRC 0x00000C00 /* rounding control */ 78 #define FPIC 0x00001000 /* infinity control */ 79 #define WFPDE 0x00000080 /* data chain exception */ 80 81 /* 82 * (Old symbol compatibility) 83 */ 84 #define FPINV FPIM 85 #define FPDNO FPDM 86 #define FPZDIV FPZM 87 #define FPOVR FPOM 88 #define FPUNR FPUM 89 #define FPPRE FPPM 90 91 /* 92 * precision, rounding, and infinity options in control word 93 */ 94 #define FPSIG24 0x00000000 /* 24-bit significand precision (short) */ 95 #define FPSIG53 0x00000200 /* 53-bit significand precision (long) */ 96 #define FPSIG64 0x00000300 /* 64-bit significand precision (temp) */ 97 #define FPRTN 0x00000000 /* round to nearest or even */ 98 #define FPRD 0x00000400 /* round down */ 99 #define FPRU 0x00000800 /* round up */ 100 #define FPCHOP 0x00000C00 /* chop (truncate toward zero) */ 101 #define FPP 0x00000000 /* projective infinity */ 102 #define FPA 0x00001000 /* affine infinity */ 103 #define WFPB17 0x00020000 /* bit 17 */ 104 #define WFPB24 0x00040000 /* bit 24 */ 105 106 /* 107 * masks for 80387 status word 108 */ 109 #define FPS_IE 0x00000001 /* invalid operation */ 110 #define FPS_DE 0x00000002 /* denormalized operand */ 111 #define FPS_ZE 0x00000004 /* zero divide */ 112 #define FPS_OE 0x00000008 /* overflow */ 113 #define FPS_UE 0x00000010 /* underflow */ 114 #define FPS_PE 0x00000020 /* precision */ 115 #define FPS_SF 0x00000040 /* stack fault */ 116 #define FPS_ES 0x00000080 /* error summary bit */ 117 #define FPS_C0 0x00000100 /* C0 bit */ 118 #define FPS_C1 0x00000200 /* C1 bit */ 119 #define FPS_C2 0x00000400 /* C2 bit */ 120 #define FPS_TOP 0x00003800 /* top of stack pointer */ 121 #define FPS_C3 0x00004000 /* C3 bit */ 122 #define FPS_B 0x00008000 /* busy bit */ 123 124 /* 125 * Exception flags manually cleared during x87 exception handling. 126 */ 127 #define FPS_SW_EFLAGS \ 128 (FPS_IE|FPS_DE|FPS_ZE|FPS_OE|FPS_UE|FPS_PE|FPS_SF|FPS_ES|FPS_B) 129 130 /* 131 * Initial value of FPU control word as per 4th ed. ABI document 132 * - affine infinity 133 * - round to nearest or even 134 * - 64-bit double precision 135 * - all exceptions masked 136 */ 137 #define FPU_CW_INIT 0x133f 138 139 /* 140 * masks and flags for SSE/SSE2 MXCSR 141 */ 142 #define SSE_IE 0x00000001 /* invalid operation */ 143 #define SSE_DE 0x00000002 /* denormalized operand */ 144 #define SSE_ZE 0x00000004 /* zero divide */ 145 #define SSE_OE 0x00000008 /* overflow */ 146 #define SSE_UE 0x00000010 /* underflow */ 147 #define SSE_PE 0x00000020 /* precision */ 148 #define SSE_DAZ 0x00000040 /* denormals are zero */ 149 #define SSE_IM 0x00000080 /* invalid op exception mask */ 150 #define SSE_DM 0x00000100 /* denormalize exception mask */ 151 #define SSE_ZM 0x00000200 /* zero-divide exception mask */ 152 #define SSE_OM 0x00000400 /* overflow exception mask */ 153 #define SSE_UM 0x00000800 /* underflow exception mask */ 154 #define SSE_PM 0x00001000 /* precision exception mask */ 155 #define SSE_RC 0x00006000 /* rounding control */ 156 #define SSE_RD 0x00002000 /* rounding control: round down */ 157 #define SSE_RU 0x00004000 /* rounding control: round up */ 158 #define SSE_FZ 0x00008000 /* flush to zero for masked underflow */ 159 160 #define SSE_MXCSR_EFLAGS \ 161 (SSE_IE|SSE_DE|SSE_ZE|SSE_OE|SSE_UE|SSE_PE) /* 0x3f */ 162 163 #define SSE_MXCSR_INIT \ 164 (SSE_IM|SSE_DM|SSE_ZM|SSE_OM|SSE_UM|SSE_PM) /* 0x1f80 */ 165 166 #define SSE_MXCSR_MASK_DEFAULT \ 167 (0xffff & ~SSE_DAZ) /* 0xffbf */ 168 169 #define SSE_FMT_MXCSR \ 170 "\20\20fz\17ru\16rd\15pm\14um\13om\12zm\11dm" \ 171 "\10im\7daz\6pe\5ue\4oe\3ze\2de\1ie" 172 173 /* 174 * This structure is written to memory by an 'fnsave' instruction 175 */ 176 struct fnsave_state { 177 uint16_t f_fcw; 178 uint16_t __f_ign0; 179 uint16_t f_fsw; 180 uint16_t __f_ign1; 181 uint16_t f_ftw; 182 uint16_t __f_ign2; 183 uint32_t f_eip; 184 uint16_t f_cs; 185 uint16_t f_fop; 186 uint32_t f_dp; 187 uint16_t f_ds; 188 uint16_t __f_ign3; 189 union { 190 uint16_t fpr_16[5]; /* 80-bits of x87 state */ 191 } f_st[8]; 192 }; /* 108 bytes */ 193 194 /* 195 * This structure is written to memory by an 'fxsave' instruction 196 * Note the variant behaviour of this instruction between long mode 197 * and legacy environments! 198 */ 199 struct fxsave_state { 200 uint16_t fx_fcw; 201 uint16_t fx_fsw; 202 uint16_t fx_fctw; /* compressed tag word */ 203 uint16_t fx_fop; 204 #if defined(__amd64) 205 uint64_t fx_rip; 206 uint64_t fx_rdp; 207 #else 208 uint32_t fx_eip; 209 uint16_t fx_cs; 210 uint16_t __fx_ign0; 211 uint32_t fx_dp; 212 uint16_t fx_ds; 213 uint16_t __fx_ign1; 214 #endif 215 uint32_t fx_mxcsr; 216 uint32_t fx_mxcsr_mask; 217 union { 218 uint16_t fpr_16[5]; /* 80-bits of x87 state */ 219 u_longlong_t fpr_mmx; /* 64-bit mmx register */ 220 uint32_t __fpr_pad[4]; /* (pad out to 128-bits) */ 221 } fx_st[8]; 222 #if defined(__amd64) 223 upad128_t fx_xmm[16]; /* 128-bit registers */ 224 upad128_t __fx_ign2[6]; 225 #else 226 upad128_t fx_xmm[8]; /* 128-bit registers */ 227 upad128_t __fx_ign2[14]; 228 #endif 229 }; /* 512 bytes */ 230 231 /* 232 * This structure is written to memory by an 'xsave' instruction. 233 * First 512 byte is compatible with the format of an 'fxsave' area. 234 */ 235 struct xsave_state { 236 struct fxsave_state xs_fxsave; 237 uint64_t xs_xstate_bv; /* 512 */ 238 uint64_t xs_rsv_mbz[2]; 239 uint64_t xs_reserved[5]; 240 upad128_t xs_ymm[16]; /* avx - 576 */ 241 }; /* 832 bytes, asserted in fpnoextflt() */ 242 243 /* 244 * Kernel's FPU save area 245 */ 246 typedef struct { 247 union _kfpu_u { 248 struct fxsave_state kfpu_fx; 249 #if defined(__i386) 250 struct fnsave_state kfpu_fn; 251 #endif 252 struct xsave_state kfpu_xs; 253 } kfpu_u; 254 uint32_t kfpu_status; /* saved at #mf exception */ 255 uint32_t kfpu_xstatus; /* saved at #xm exception */ 256 } kfpu_t; 257 258 extern int fp_kind; /* kind of fp support */ 259 extern int fp_save_mech; /* fp save/restore mechanism */ 260 extern int fpu_exists; /* FPU hw exists */ 261 262 #ifdef _KERNEL 263 264 extern int fpu_ignored; 265 extern int fpu_pentium_fdivbug; 266 267 extern uint32_t sse_mxcsr_mask; 268 269 extern void fpu_probe(void); 270 extern uint_t fpu_initial_probe(void); 271 extern int fpu_probe_pentium_fdivbug(void); 272 273 extern void fpnsave_ctxt(void *); 274 extern void fpxsave_ctxt(void *); 275 extern void xsave_ctxt(void *); 276 extern void (*fpsave_ctxt)(void *); 277 278 extern void fxsave_insn(struct fxsave_state *); 279 extern void fpsave(struct fnsave_state *); 280 extern void fprestore(struct fnsave_state *); 281 extern void fpxsave(struct fxsave_state *); 282 extern void fpxrestore(struct fxsave_state *); 283 extern void xsave(struct xsave_state *, uint64_t); 284 extern void xrestore(struct xsave_state *, uint64_t); 285 286 extern void fpenable(void); 287 extern void fpdisable(void); 288 extern void fpinit(void); 289 290 extern uint32_t fperr_reset(void); 291 extern uint32_t fpxerr_reset(void); 292 293 extern uint32_t fpgetcwsw(void); 294 extern uint32_t fpgetmxcsr(void); 295 296 struct regs; 297 extern int fpnoextflt(struct regs *); 298 extern int fpextovrflt(struct regs *); 299 extern int fpexterrflt(struct regs *); 300 extern int fpsimderrflt(struct regs *); 301 extern void fpsetcw(uint16_t, uint32_t); 302 303 #endif /* _KERNEL */ 304 305 #ifdef __cplusplus 306 } 307 #endif 308 309 #endif /* _SYS_FP_H */ 310