1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_CONTROLREGS_H 27 #define _SYS_CONTROLREGS_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifndef _ASM 32 #include <sys/types.h> 33 #endif 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 /* 40 * This file describes the x86 architecture control registers which 41 * are part of the privileged architecture. 42 * 43 * Many of these definitions are shared between IA-32-style and 44 * AMD64-style processors. 45 */ 46 47 /* CR0 Register */ 48 49 #define CR0_PG 0x80000000 /* paging enabled */ 50 #define CR0_CD 0x40000000 /* cache disable */ 51 #define CR0_NW 0x20000000 /* not writethrough */ 52 #define CR0_AM 0x00040000 /* alignment mask */ 53 #define CR0_WP 0x00010000 /* write protect */ 54 #define CR0_NE 0x00000020 /* numeric error */ 55 #define CR0_ET 0x00000010 /* extension type */ 56 #define CR0_TS 0x00000008 /* task switch */ 57 #define CR0_EM 0x00000004 /* emulation */ 58 #define CR0_MP 0x00000002 /* monitor coprocessor */ 59 #define CR0_PE 0x00000001 /* protection enabled */ 60 61 /* XX64 eliminate these compatibility defines */ 62 63 #define CR0_CE CR0_CD 64 #define CR0_WT CR0_NW 65 66 #define FMT_CR0 \ 67 "\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe" 68 69 /* CR3 Register */ 70 71 #define CR3_PCD 0x00000010 /* cache disable */ 72 #define CR3_PWT 0x00000008 /* write through */ 73 74 #define FMT_CR3 "\20\5pcd\4pwt" 75 76 /* CR4 Register */ 77 78 #define CR4_VME 0x0001 /* virtual-8086 mode extensions */ 79 #define CR4_PVI 0x0002 /* protected-mode virtual interrupts */ 80 #define CR4_TSD 0x0004 /* time stamp disable */ 81 #define CR4_DE 0x0008 /* debugging extensions */ 82 #define CR4_PSE 0x0010 /* page size extensions */ 83 #define CR4_PAE 0x0020 /* physical address extension */ 84 #define CR4_MCE 0x0040 /* machine check enable */ 85 #define CR4_PGE 0x0080 /* page global enable */ 86 #define CR4_PCE 0x0100 /* perf-monitoring counter enable */ 87 #define CR4_OSFXSR 0x0200 /* OS fxsave/fxrstor support */ 88 #define CR4_OSXMMEXCPT 0x0400 /* OS unmasked exception support */ 89 90 #define FMT_CR4 \ 91 "\20\13xmme\12fxsr\11pce\10pge\7mce\6pae\5pse\4de\3tsd\2pvi\1vme" 92 93 /* Intel's SYSENTER configuration registers */ 94 95 #define MSR_INTC_SEP_CS 0x174 /* kernel code selector MSR */ 96 #define MSR_INTC_SEP_ESP 0x175 /* kernel esp MSR */ 97 #define MSR_INTC_SEP_EIP 0x176 /* kernel eip MSR */ 98 99 /* AMD's EFER register */ 100 101 #define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */ 102 103 #define AMD_EFER_NXE 0x800 /* no-execute enable */ 104 #define AMD_EFER_LMA 0x400 /* long mode active (read-only) */ 105 #define AMD_EFER_LME 0x100 /* long mode enable */ 106 #define AMD_EFER_SCE 0x001 /* system call extensions */ 107 108 #define FMT_AMD_EFER \ 109 "\20\14nxe\13lma\11lme\1sce" 110 111 /* AMD's SYSCFG register */ 112 113 #define MSR_AMD_SYSCFG 0xc0000010 /* system configuration MSR */ 114 115 #define AMD_SYSCFG_TOM2 0x200000 /* MtrrTom2En */ 116 #define AMD_SYSCFG_MVDM 0x100000 /* MtrrVarDramEn */ 117 #define AMD_SYSCFG_MFDM 0x080000 /* MtrrFixDramModEn */ 118 #define AMD_SYSCFG_MFDE 0x040000 /* MtrrFixDramEn */ 119 120 #define FMT_AMD_SYSCFG \ 121 "\20\26tom2\25mvdm\24mfdm\23mfde" 122 123 /* AMD's syscall/sysret MSRs */ 124 125 #define MSR_AMD_STAR 0xc0000081 /* %cs:%ss:%cs:%ss:%eip for syscall */ 126 #define MSR_AMD_LSTAR 0xc0000082 /* target %rip of 64-bit syscall */ 127 #define MSR_AMD_CSTAR 0xc0000083 /* target %rip of 32-bit syscall */ 128 #define MSR_AMD_SFMASK 0xc0000084 /* syscall flag mask */ 129 130 /* AMD's FS.base and GS.base MSRs */ 131 132 #define MSR_AMD_FSBASE 0xc0000100 /* 64-bit base address for %fs */ 133 #define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */ 134 #define MSR_AMD_KGSBASE 0xc0000102 /* swapgs swaps this with gsbase */ 135 136 /* AMD's configuration MSRs, weakly documented in the revision guide */ 137 138 #define MSR_AMD_DC_CFG 0xc0011022 139 140 #define AMD_DC_CFG_DIS_CNV_WC_SSO (UINT64_C(1) << 3) 141 #define AMD_DC_CFG_DIS_SMC_CHK_BUF (UINT64_C(1) << 10) 142 143 /* AMD's HWCR MSR */ 144 145 #define MSR_AMD_HWCR 0xc0010015 146 147 #define AMD_HWCR_FFDIS 0x00040 /* disable TLB Flush Filter */ 148 #define AMD_HWCR_MCI_STATUS_WREN 0x40000 /* enable write of MCi_STATUS */ 149 150 /* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */ 151 152 #define MSR_AMD_NB_CFG 0xc001001f 153 154 #define MSR_BU_CFG 0xc0011023 155 156 #define AMD_NB_CFG_SRQ_HEARTBEAT (UINT64_C(1) << 20) 157 158 /* AMD */ 159 #define MSR_AMD_PATCHLEVEL 0x8b 160 161 #ifdef __cplusplus 162 } 163 #endif 164 165 #endif /* !_SYS_CONTROLREGS_H */ 166