1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/stat.h> 30 #include <sys/sunndi.h> 31 #include <sys/pci.h> 32 #include <sys/pci_impl.h> 33 #include <sys/pci_cfgspace.h> 34 #include <sys/memlist.h> 35 #include <sys/bootconf.h> 36 #include <io/pci/mps_table.h> 37 #include <sys/pci_cfgspace.h> 38 #include <sys/pci_cfgspace_impl.h> 39 #include <sys/psw.h> 40 #include "../../../../common/pci/pci_strings.h" 41 #include <sys/apic.h> 42 #include <io/pciex/pcie_nvidia.h> 43 #include <io/hotplug/pciehpc/pciehpc_acpi.h> 44 #include <sys/acpi/acpi.h> 45 #include <sys/acpica.h> 46 47 #define pci_getb (*pci_getb_func) 48 #define pci_getw (*pci_getw_func) 49 #define pci_getl (*pci_getl_func) 50 #define pci_putb (*pci_putb_func) 51 #define pci_putw (*pci_putw_func) 52 #define pci_putl (*pci_putl_func) 53 #define dcmn_err if (pci_boot_debug) cmn_err 54 55 #define CONFIG_INFO 0 56 #define CONFIG_UPDATE 1 57 #define CONFIG_NEW 2 58 #define CONFIG_FIX 3 59 #define COMPAT_BUFSIZE 512 60 61 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 62 #define LPC_IO_CONTROL_REG_1 0x40 63 #define AMD8111_ENABLENMI (uint8_t)0x80 64 #define DEVID_AMD8111_LPC 0x7468 65 66 struct pci_fixundo { 67 uint8_t bus; 68 uint8_t dev; 69 uint8_t fn; 70 void (*undofn)(uint8_t, uint8_t, uint8_t); 71 struct pci_fixundo *next; 72 }; 73 74 extern int pci_bios_nbus; 75 static uchar_t max_dev_pci = 32; /* PCI standard */ 76 int pci_boot_debug = 0; 77 extern struct memlist *find_bus_res(int, int); 78 static struct pci_fixundo *undolist = NULL; 79 80 /* 81 * Module prototypes 82 */ 83 static void enumerate_bus_devs(uchar_t bus, int config_op); 84 static void create_root_bus_dip(uchar_t bus); 85 static dev_info_t *process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 86 ushort_t, int); 87 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 88 ushort_t, ushort_t, uchar_t, uint_t, int); 89 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 90 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int); 91 static void add_model_prop(dev_info_t *, uint_t); 92 static void add_bus_range_prop(int); 93 static void add_bus_slot_names_prop(int); 94 static void add_ppb_ranges_prop(int); 95 static void add_bus_available_prop(int); 96 static ACPI_STATUS lookup_acpi_obj(ACPI_HANDLE, char *, ACPI_HANDLE *); 97 static int check_ppb_hotplug(dev_info_t *); 98 static void fix_ppb_res(uchar_t); 99 static void alloc_res_array(); 100 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 101 ushort_t deviceid); 102 static void pciex_slot_names_prop(dev_info_t *, ushort_t); 103 104 extern int pci_slot_names_prop(int, char *, int); 105 extern ACPI_STATUS pciehpc_acpi_eval_osc(ACPI_HANDLE, uint32_t *); 106 107 /* set non-zero to force PCI peer-bus renumbering */ 108 int pci_bus_always_renumber = 0; 109 110 /* get the subordinate bus # for a root/peer bus */ 111 static int 112 pci_root_subbus(int bus, uchar_t *subbus) 113 { 114 ACPI_HANDLE hdl; 115 ACPI_BUFFER rb; 116 ACPI_RESOURCE *rp; 117 int rv; 118 119 if (pci_bus_res[bus].dip == NULL) { 120 /* non-used bus # */ 121 return (AE_ERROR); 122 } 123 if (acpica_get_handle(pci_bus_res[bus].dip, &hdl) != AE_OK) { 124 cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus); 125 return (AE_ERROR); 126 } 127 128 rb.Length = ACPI_ALLOCATE_BUFFER; 129 if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) { 130 cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus); 131 return (AE_ERROR); 132 } 133 134 rv = AE_ERROR; 135 136 for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG; 137 rp = ACPI_NEXT_RESOURCE(rp)) { 138 139 switch (rp->Type) { 140 case ACPI_RESOURCE_TYPE_ADDRESS16: 141 if (rp->Data.Address.ResourceType != 142 ACPI_BUS_NUMBER_RANGE) 143 continue; 144 *subbus = (uchar_t)rp->Data.Address16.Maximum; 145 dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus); 146 break; 147 case ACPI_RESOURCE_TYPE_ADDRESS32: 148 if (rp->Data.Address.ResourceType != 149 ACPI_BUS_NUMBER_RANGE) 150 continue; 151 *subbus = (uchar_t)rp->Data.Address32.Maximum; 152 dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus); 153 break; 154 case ACPI_RESOURCE_TYPE_ADDRESS64: 155 if (rp->Data.Address.ResourceType != 156 ACPI_BUS_NUMBER_RANGE) 157 continue; 158 *subbus = (uchar_t)rp->Data.Address64.Maximum; 159 dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus); 160 break; 161 case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64: 162 if (rp->Data.Address.ResourceType != 163 ACPI_BUS_NUMBER_RANGE) 164 continue; 165 *subbus = (uchar_t)rp->Data.ExtAddress64.Maximum; 166 dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus); 167 break; 168 default: 169 dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type); 170 continue; 171 } 172 173 /* found the bus-range resource */ 174 dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus); 175 rv = AE_OK; 176 177 /* This breaks out of the resource scanning loop */ 178 break; 179 } 180 181 AcpiOsFree(rb.Pointer); 182 if (rv != AE_OK) 183 cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus); 184 185 return (rv); 186 187 } 188 189 /* 190 * Enumerate all PCI devices 191 */ 192 void 193 pci_setup_tree() 194 { 195 uchar_t i, root_bus_addr = 0; 196 197 alloc_res_array(); 198 for (i = 0; i <= pci_bios_nbus; i++) { 199 pci_bus_res[i].par_bus = (uchar_t)-1; 200 pci_bus_res[i].root_addr = (uchar_t)-1; 201 pci_bus_res[i].sub_bus = i; 202 } 203 204 pci_bus_res[0].root_addr = root_bus_addr++; 205 create_root_bus_dip(0); 206 enumerate_bus_devs(0, CONFIG_INFO); 207 208 /* 209 * Now enumerate peer busses 210 * 211 * We loop till pci_bios_nbus. On most systems, there is 212 * one more bus at the high end, which implements the ISA 213 * compatibility bus. We don't care about that. 214 * 215 * Note: In the old (bootconf) enumeration, the peer bus 216 * address did not use the bus number, and there were 217 * too many peer busses created. The root_bus_addr is 218 * used to maintain the old peer bus address assignment. 219 * However, we stop enumerating phantom peers with no 220 * device below. 221 */ 222 for (i = 1; i <= pci_bios_nbus; i++) { 223 if (pci_bus_res[i].dip == NULL) { 224 pci_bus_res[i].root_addr = root_bus_addr++; 225 } 226 enumerate_bus_devs(i, CONFIG_INFO); 227 228 /* add slot-names property for named pci hot-plug slots */ 229 add_bus_slot_names_prop(i); 230 } 231 232 } 233 234 /* 235 * >0 = present, 0 = not present, <0 = error 236 */ 237 static int 238 pci_bbn_present(int bus) 239 { 240 ACPI_HANDLE hdl; 241 ACPI_BUFFER rb; 242 int rv; 243 244 /* no dip means no _BBN */ 245 if (pci_bus_res[bus].dip == NULL) 246 return (0); 247 248 rv = acpica_get_handle(pci_bus_res[bus].dip, &hdl); 249 if (rv != AE_OK) 250 return (-1); 251 252 rb.Length = ACPI_ALLOCATE_BUFFER; 253 254 rv = AcpiEvaluateObject(hdl, "_BBN", NULL, &rb); 255 256 if (rb.Length > 0) 257 AcpiOsFree(rb.Pointer); 258 259 if (rv == AE_OK) 260 return (1); 261 else if (rv == AE_NOT_FOUND) 262 return (0); 263 else 264 return (-1); 265 } 266 267 /* 268 * Return non-zero if any PCI bus in the system has an associated 269 * _BBN object, 0 otherwise. 270 */ 271 static int 272 pci_roots_have_bbn(void) 273 { 274 int i; 275 276 /* 277 * Scan the PCI busses and look for at least 1 _BBN 278 */ 279 for (i = 0; i <= pci_bios_nbus; i++) { 280 /* skip non-root (peer) PCI busses */ 281 if (pci_bus_res[i].par_bus != (uchar_t)-1) 282 continue; 283 284 if (pci_bbn_present(i) > 0) 285 return (1); 286 } 287 return (0); 288 289 } 290 291 /* 292 * return non-zero if the machine is one on which we renumber 293 * the internal pci unit-addresses 294 */ 295 static int 296 pci_bus_renumber() 297 { 298 ACPI_TABLE_HEADER *fadt; 299 300 if (pci_bus_always_renumber) 301 return (1); 302 303 /* get the FADT */ 304 if (AcpiGetFirmwareTable(FADT_SIG, 1, ACPI_LOGICAL_ADDRESSING, 305 (ACPI_TABLE_HEADER **)&fadt) != AE_OK) 306 return (0); 307 308 /* compare OEM Table ID to "SUNm31" */ 309 if (strncmp("SUNm31", fadt->OemId, 6)) 310 return (0); 311 else 312 return (1); 313 } 314 315 /* 316 * Initial enumeration of the physical PCI bus hierarchy can 317 * leave 'gaps' in the order of peer PCI bus unit-addresses. 318 * Systems with more than one peer PCI bus *must* have an ACPI 319 * _BBN object associated with each peer bus; use the presence 320 * of this object to remove gaps in the numbering of the peer 321 * PCI bus unit-addresses - only peer busses with an associated 322 * _BBN are counted. 323 */ 324 static void 325 pci_renumber_root_busses(void) 326 { 327 int pci_regs[] = {0, 0, 0}; 328 int i, root_addr = 0; 329 330 /* 331 * Currently, we only enable the re-numbering on specific 332 * Sun machines; this is a work-around for the more complicated 333 * issue of upgrade changing physical device paths 334 */ 335 if (!pci_bus_renumber()) 336 return; 337 338 /* 339 * If we find no _BBN objects at all, we either don't need 340 * to do anything or can't do anything anyway 341 */ 342 if (!pci_roots_have_bbn()) 343 return; 344 345 for (i = 0; i <= pci_bios_nbus; i++) { 346 /* skip non-root (peer) PCI busses */ 347 if (pci_bus_res[i].par_bus != (uchar_t)-1) 348 continue; 349 350 if (pci_bbn_present(i) < 1) { 351 pci_bus_res[i].root_addr = (uchar_t)-1; 352 continue; 353 } 354 355 ASSERT(pci_bus_res[i].dip != NULL); 356 if (pci_bus_res[i].root_addr != root_addr) { 357 /* update reg property for node */ 358 pci_bus_res[i].root_addr = root_addr; 359 pci_regs[0] = pci_bus_res[i].root_addr; 360 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 361 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 362 } 363 root_addr++; 364 } 365 } 366 367 static void 368 remove_resource_range(struct memlist **list, int *ranges, int range_count) 369 { 370 struct range { 371 uint32_t base; 372 uint32_t len; 373 }; 374 int index; 375 376 for (index = 0; index < range_count; index++) { 377 /* all done if list is or has become empty */ 378 if (*list == NULL) 379 break; 380 (void) memlist_remove(list, 381 (uint64_t)((struct range *)ranges)[index].base, 382 (uint64_t)((struct range *)ranges)[index].len); 383 } 384 } 385 386 static void 387 remove_used_resources() 388 { 389 dev_info_t *used; 390 int *narray; 391 uint_t ncount; 392 int status; 393 int bus; 394 395 used = ddi_find_devinfo("used-resources", -1, 0); 396 if (used == NULL) 397 return; 398 399 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 400 DDI_PROP_DONTPASS, "io-space", &narray, &ncount); 401 if (status == DDI_PROP_SUCCESS) { 402 for (bus = 0; bus <= pci_bios_nbus; bus++) 403 remove_resource_range(&pci_bus_res[bus].io_ports, 404 narray, ncount / 2); 405 ddi_prop_free(narray); 406 } 407 408 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 409 DDI_PROP_DONTPASS, "device-memory", &narray, &ncount); 410 if (status == DDI_PROP_SUCCESS) { 411 for (bus = 0; bus <= pci_bios_nbus; bus++) 412 remove_resource_range(&pci_bus_res[bus].mem_space, 413 narray, ncount / 2); 414 ddi_prop_free(narray); 415 } 416 } 417 418 /* 419 * Walk up ACPI namespace starting from parobj looking for object with name 420 */ 421 static ACPI_STATUS 422 lookup_acpi_obj(ACPI_HANDLE parobj, char *name, ACPI_HANDLE *retobjp) 423 { 424 ACPI_HANDLE obj; 425 426 do { 427 if (AcpiGetHandle(parobj, name, retobjp) == AE_OK) { 428 ASSERT(*retobjp != NULL); 429 return (AE_OK); 430 } 431 obj = parobj; 432 } while (AcpiGetParent(obj, &parobj) == AE_OK); 433 434 *retobjp = NULL; 435 return (AE_NOT_FOUND); 436 } 437 438 static int 439 check_ppb_hotplug(dev_info_t *dip) 440 { 441 ACPI_HANDLE pcibus_obj; 442 ACPI_HANDLE obj; 443 uint32_t hp_mode = ACPI_HP_MODE; 444 445 if (ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 446 "pci-hotplug-type", INBAND_HPC_NONE) != INBAND_HPC_PCIE) 447 return (0); 448 449 if (acpica_get_handle(dip, &pcibus_obj) != AE_OK) 450 return (0); 451 452 if (lookup_acpi_obj(pcibus_obj, "_OSC", &obj) == AE_OK) { 453 if (pciehpc_acpi_eval_osc(obj, &hp_mode) != AE_OK) 454 hp_mode = ACPI_HP_MODE; 455 } 456 457 if (hp_mode == NATIVE_HP_MODE) 458 return (1); 459 460 /* 461 * if ACPI hotplug mode, a child obj for the slot is also required 462 */ 463 if (AcpiGetNextObject(ACPI_TYPE_DEVICE, pcibus_obj, NULL, &obj) != 464 AE_OK) 465 return (0); 466 467 return (1); 468 } 469 470 /* 471 * Assign i/o resources to unconfigured hotplug bridges after the first pass. 472 * It must be after the first pass in order to use the ports left over after 473 * accounting for i/o resources of bridges that have been configured by bios. 474 * We are expecting unconfigured bridges to be empty bridges otherwise 475 * this resource assignment needs to be done at an earlier stage. 476 */ 477 static void 478 fix_ppb_res(uchar_t secbus) 479 { 480 uchar_t bus, dev, func; 481 uint_t base, limit; 482 uint_t io_size = 0x1000; /* io range must be mult of and 4k aligned */ 483 uint64_t addr; 484 int *regp = NULL; 485 uint_t reglen; 486 int rv, cap_ptr, physhi; 487 dev_info_t *dip; 488 489 /* some entries may be empty due to discontiguous bus numbering */ 490 dip = pci_bus_res[secbus].dip; 491 if (dip == NULL) 492 return; 493 494 if (!check_ppb_hotplug(dip)) 495 return; 496 497 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 498 "reg", ®p, ®len); 499 ASSERT(rv == DDI_PROP_SUCCESS && reglen > 0); 500 physhi = regp[0]; 501 ddi_prop_free(regp); 502 503 func = (uchar_t)PCI_REG_FUNC_G(physhi); 504 dev = (uchar_t)PCI_REG_DEV_G(physhi); 505 bus = (uchar_t)PCI_REG_BUS_G(physhi); 506 ASSERT(bus == pci_bus_res[secbus].par_bus); 507 508 /* 509 * Check if the slot is enabled 510 */ 511 cap_ptr = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 512 "pcie-capid-pointer", PCI_CAP_NEXT_PTR_NULL); 513 if (cap_ptr == PCI_CAP_NEXT_PTR_NULL) 514 return; 515 516 if (pci_getw(bus, dev, func, (uint16_t)cap_ptr + PCIE_LINKCTL) & 517 PCIE_LINKCTL_LINK_DISABLE) 518 return; 519 520 /* 521 * base >= limit means that the bridge was not configured 522 * This may have been set by the bios or by add_ppb_props() upon 523 * detecting that I/O was disabled 524 */ 525 526 /* 527 * I/O; check and attempt to allocate io_size amount from parent 528 */ 529 base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 530 limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 531 ASSERT(base != 0xff && limit != 0xff); 532 533 base = (base & 0xf0) << 8; 534 limit = ((limit & 0xf0) << 8) | 0xfff; 535 536 addr = 0; 537 if ((base > limit || base == 0) && 538 pci_bus_res[bus].io_ports != NULL) { 539 addr = memlist_find(&pci_bus_res[bus].io_ports, io_size, 540 0x1000); 541 ASSERT(addr <= 0xffff - io_size); 542 } 543 if (addr != 0) { 544 memlist_insert(&pci_bus_res[secbus].io_ports, addr, io_size); 545 base = addr; 546 limit = addr + io_size - 1; 547 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 548 (uint8_t)((base >> 8) & 0xf0)); 549 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 550 (uint8_t)((limit >> 8) & 0xf0)); 551 } 552 553 /* 554 * Account for new resources 555 */ 556 add_ppb_ranges_prop(secbus); 557 } 558 559 void 560 pci_reprogram(void) 561 { 562 int i, pci_reconfig = 1; 563 char *onoff; 564 565 /* 566 * Excise phantom roots if possible 567 */ 568 pci_renumber_root_busses(); 569 570 /* add bus-range property for root/peer bus nodes */ 571 for (i = 0; i <= pci_bios_nbus; i++) { 572 if (pci_bus_res[i].par_bus == (uchar_t)-1) { 573 uchar_t subbus; 574 if (pci_root_subbus(i, &subbus) == AE_OK) 575 pci_bus_res[i].sub_bus = subbus; 576 add_bus_range_prop(i); 577 } 578 } 579 580 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 581 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 582 if (strcmp(onoff, "off") == 0) { 583 pci_reconfig = 0; 584 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 585 } 586 ddi_prop_free(onoff); 587 } 588 589 /* remove used-resources from PCI resource maps */ 590 remove_used_resources(); 591 592 for (i = 0; i <= pci_bios_nbus; i++) { 593 /* configure devices not configured by bios */ 594 if (pci_reconfig) { 595 fix_ppb_res(i); 596 enumerate_bus_devs(i, CONFIG_NEW); 597 } 598 /* All dev programmed, so we can create available prop */ 599 add_bus_available_prop(i); 600 } 601 } 602 603 /* 604 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 605 */ 606 static void 607 create_root_bus_dip(uchar_t bus) 608 { 609 int pci_regs[] = {0, 0, 0}; 610 dev_info_t *dip; 611 612 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 613 614 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 615 (pnode_t)DEVI_SID_NODEID, &dip); 616 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 617 "#address-cells", 3); 618 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 619 "#size-cells", 2); 620 pci_regs[0] = pci_bus_res[bus].root_addr; 621 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 622 "reg", (int *)pci_regs, 3); 623 624 /* 625 * If system has PCIe bus, then create different properties 626 */ 627 if (create_pcie_root_bus(bus, dip) == B_FALSE) 628 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 629 "device_type", "pci"); 630 631 (void) ndi_devi_bind_driver(dip, 0); 632 pci_bus_res[bus].dip = dip; 633 pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 634 pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 635 pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 636 637 if (bus != 0) 638 return; 639 640 /* 641 * Special treatment of bus 0: 642 * If no resource from MPSPEC/HRT, copy pcimem from boot 643 * and make I/O space the entire range starting at 0x100. There 644 * is no difference between prefetchable memory or not. 645 */ 646 if (pci_bus_res[0].mem_space == NULL) 647 pci_bus_res[0].mem_space = 648 memlist_dup(bootops->boot_mem->pcimem); 649 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 650 if (pci_bus_res[0].io_ports == NULL) 651 memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xffff); 652 } 653 654 /* 655 * For any fixed configuration (often compatability) pci devices 656 * and those with their own expansion rom, create device nodes 657 * to hold the already configured device details. 658 */ 659 void 660 enumerate_bus_devs(uchar_t bus, int config_op) 661 { 662 uchar_t dev, func, nfunc, header; 663 ushort_t venid; 664 dev_info_t *dip; 665 struct pci_devfunc { 666 struct pci_devfunc *next; 667 dev_info_t *dip; 668 uchar_t bus; 669 uchar_t dev; 670 uchar_t func; 671 } *devlist = NULL, *entry; 672 673 if (config_op == CONFIG_NEW) { 674 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 675 } else if (config_op == CONFIG_FIX) { 676 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 677 } else 678 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 679 680 for (dev = 0; dev < max_dev_pci; dev++) { 681 nfunc = 1; 682 for (func = 0; func < nfunc; func++) { 683 684 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 685 dev, func); 686 687 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 688 689 if ((venid == 0xffff) || (venid == 0)) { 690 /* no function at this address */ 691 continue; 692 } 693 694 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 695 if (header == 0xff) { 696 continue; /* illegal value */ 697 } 698 699 /* 700 * according to some mail from Microsoft posted 701 * to the pci-drivers alias, their only requirement 702 * for a multifunction device is for the 1st 703 * function to have to PCI_HEADER_MULTI bit set. 704 */ 705 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 706 nfunc = 8; 707 } 708 709 if (config_op == CONFIG_FIX) { 710 /* 711 * If we're processing PCI fixes, no dip 712 * will be returned. 713 */ 714 (void) process_devfunc(bus, dev, func, header, 715 venid, config_op); 716 717 } else if (config_op == CONFIG_INFO) { 718 /* 719 * Create the node, unconditionally, on the 720 * first pass only. It may still need 721 * resource assignment, which will be 722 * done on the second, CONFIG_NEW, pass. 723 */ 724 dip = process_devfunc(bus, dev, func, header, 725 venid, config_op); 726 /* 727 * If dip isn't null, put on a list to 728 * save for reprogramming when config_op 729 * is CONFIG_NEW. 730 */ 731 732 if (dip) { 733 entry = kmem_alloc(sizeof (*entry), 734 KM_SLEEP); 735 entry->dip = dip; 736 entry->dev = dev; 737 entry->func = func; 738 entry->next = devlist; 739 devlist = entry; 740 } 741 } 742 } 743 } 744 745 if (config_op == CONFIG_NEW) { 746 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 747 while (devlist) { 748 entry = devlist; 749 devlist = entry->next; 750 cmn_err(CE_NOTE, 751 "!reprogram pci device [%d/%d/%d] (%s)", 752 bus, entry->dev, entry->func, 753 ddi_driver_name(entry->dip)); 754 (void) add_reg_props(entry->dip, bus, entry->dev, 755 entry->func, CONFIG_UPDATE, 0); 756 kmem_free(entry, sizeof (*entry)); 757 } 758 pci_bus_res[bus].privdata = NULL; 759 } else if (config_op != CONFIG_FIX) { 760 pci_bus_res[bus].privdata = devlist; 761 } 762 } 763 764 static int 765 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 766 ushort_t subvenid, ushort_t subdevid) 767 { 768 static int prop_exist = -1; 769 static char *pciide_str; 770 char compat[32]; 771 772 if (prop_exist == -1) { 773 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 774 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 775 &pciide_str) == DDI_SUCCESS); 776 } 777 778 if (!prop_exist) 779 return (0); 780 781 /* compare property value against various forms of compatible */ 782 if (subvenid) { 783 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 784 venid, devid, subvenid, subdevid, revid); 785 if (strcmp(pciide_str, compat) == 0) 786 return (1); 787 788 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 789 venid, devid, subvenid, subdevid); 790 if (strcmp(pciide_str, compat) == 0) 791 return (1); 792 793 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 794 subvenid, subdevid); 795 if (strcmp(pciide_str, compat) == 0) 796 return (1); 797 } 798 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 799 venid, devid, revid); 800 if (strcmp(pciide_str, compat) == 0) 801 return (1); 802 803 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 804 if (strcmp(pciide_str, compat) == 0) 805 return (1); 806 807 return (0); 808 } 809 810 static int 811 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 812 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 813 { 814 struct ide_table { /* table for PCI_MASS_OTHER */ 815 ushort_t venid; 816 ushort_t devid; 817 } *entry; 818 819 /* XXX SATA devices: need a way to add dynamically */ 820 static struct ide_table ide_other[] = { 821 {0x1095, 0x3112}, 822 {0x1095, 0x3114}, 823 {0x1095, 0x3512}, 824 {0, 0} 825 }; 826 827 if (basecl != PCI_CLASS_MASS) 828 return (0); 829 830 if (subcl == PCI_MASS_IDE) { 831 return (1); 832 } 833 834 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 835 return (0); 836 } 837 838 entry = &ide_other[0]; 839 while (entry->venid) { 840 if (entry->venid == venid && entry->devid == devid) 841 return (1); 842 entry++; 843 } 844 return (check_pciide_prop(revid, venid, devid, subvenid, subdevid)); 845 } 846 847 static int 848 is_display(uint_t classcode) 849 { 850 static uint_t disp_classes[] = { 851 0x000100, 852 0x030000, 853 0x030001 854 }; 855 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 856 857 for (i = 0; i < nclasses; i++) { 858 if (classcode == disp_classes[i]) 859 return (1); 860 } 861 return (0); 862 } 863 864 static void 865 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 866 void (*undofn)(uint8_t, uint8_t, uint8_t)) 867 { 868 struct pci_fixundo *newundo; 869 870 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 871 872 /* 873 * Adding an item to this list means that we must turn its NMIENABLE 874 * bit back on at a later time. 875 */ 876 newundo->bus = bus; 877 newundo->dev = dev; 878 newundo->fn = fn; 879 newundo->undofn = undofn; 880 newundo->next = undolist; 881 882 /* add to the undo list in LIFO order */ 883 undolist = newundo; 884 } 885 886 void 887 add_pci_fixes(void) 888 { 889 int i; 890 891 for (i = 0; i <= pci_bios_nbus; i++) { 892 /* 893 * For each bus, apply needed fixes to the appropriate devices. 894 * This must be done before the main enumeration loop because 895 * some fixes must be applied to devices normally encountered 896 * later in the pci scan (e.g. if a fix to device 7 must be 897 * applied before scanning device 6, applying fixes in the 898 * normal enumeration loop would obviously be too late). 899 */ 900 enumerate_bus_devs(i, CONFIG_FIX); 901 } 902 } 903 904 void 905 undo_pci_fixes(void) 906 { 907 struct pci_fixundo *nextundo; 908 uint8_t bus, dev, fn; 909 910 /* 911 * All fixes in the undo list are performed unconditionally. Future 912 * fixes may require selective undo. 913 */ 914 while (undolist != NULL) { 915 916 bus = undolist->bus; 917 dev = undolist->dev; 918 fn = undolist->fn; 919 920 (*(undolist->undofn))(bus, dev, fn); 921 922 nextundo = undolist->next; 923 kmem_free(undolist, sizeof (struct pci_fixundo)); 924 undolist = nextundo; 925 } 926 } 927 928 static void 929 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 930 { 931 uint8_t val8; 932 933 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 934 /* 935 * The NMIONERR bit is turned back on to allow the SMM BIOS 936 * to handle more critical PCI errors (e.g. PERR#). 937 */ 938 val8 |= AMD8111_ENABLENMI; 939 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 940 } 941 942 static void 943 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 944 { 945 uint8_t val8; 946 947 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 948 949 if ((val8 & AMD8111_ENABLENMI) == 0) 950 return; 951 952 /* 953 * We reset NMIONERR in the LPC because master-abort on the PCI 954 * bridge side of the 8111 will cause NMI, which might cause SMI, 955 * which sometimes prevents all devices from being enumerated. 956 */ 957 val8 &= ~AMD8111_ENABLENMI; 958 959 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 960 961 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 962 } 963 964 static dev_info_t * 965 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 966 ushort_t vendorid, int config_op) 967 { 968 char nodename[32], unitaddr[5]; 969 dev_info_t *dip; 970 uchar_t basecl, subcl, progcl, intr, revid; 971 ushort_t subvenid, subdevid, status; 972 ushort_t slot_num; 973 uint_t classcode, revclass; 974 int reprogram = 0, pciide = 0; 975 int power[2] = {1, 1}; 976 int pciex = 0; 977 ushort_t is_pci_bridge = 0; 978 979 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 980 981 switch (header & PCI_HEADER_TYPE_M) { 982 case PCI_HEADER_ZERO: 983 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 984 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 985 break; 986 case PCI_HEADER_CARDBUS: 987 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 988 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 989 break; 990 default: 991 subvenid = 0; 992 subdevid = 0; 993 break; 994 } 995 996 if (config_op == CONFIG_FIX) { 997 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 998 pci_fix_amd8111(bus, dev, func); 999 } 1000 return (NULL); 1001 } 1002 1003 /* XXX should be use generic names? derive from class? */ 1004 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 1005 classcode = revclass >> 8; 1006 revid = revclass & 0xff; 1007 1008 /* figure out if this is pci-ide */ 1009 basecl = classcode >> 16; 1010 subcl = (classcode >> 8) & 0xff; 1011 progcl = classcode & 0xff; 1012 1013 1014 if (is_display(classcode)) 1015 (void) snprintf(nodename, sizeof (nodename), "display"); 1016 else if (subvenid != 0) 1017 (void) snprintf(nodename, sizeof (nodename), 1018 "pci%x,%x", subvenid, subdevid); 1019 else 1020 (void) snprintf(nodename, sizeof (nodename), 1021 "pci%x,%x", vendorid, deviceid); 1022 1023 /* make sure parent bus dip has been created */ 1024 if (pci_bus_res[bus].dip == NULL) { 1025 create_root_bus_dip(bus); 1026 } 1027 1028 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 1029 DEVI_SID_NODEID, &dip); 1030 1031 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 1032 &is_pci_bridge) == B_TRUE) 1033 pciex = 1; 1034 1035 /* add properties */ 1036 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 1037 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 1038 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 1039 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1040 "class-code", classcode); 1041 if (func == 0) 1042 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 1043 else 1044 (void) snprintf(unitaddr, sizeof (unitaddr), 1045 "%x,%x", dev, func); 1046 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1047 "unit-address", unitaddr); 1048 1049 /* add device_type for display nodes */ 1050 if (is_display(classcode)) { 1051 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1052 "device_type", "display"); 1053 } 1054 /* add special stuff for header type */ 1055 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 1056 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 1057 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 1058 1059 if (subvenid != 0) { 1060 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1061 "subsystem-id", subdevid); 1062 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1063 "subsystem-vendor-id", subvenid); 1064 } 1065 if (!pciex) 1066 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1067 "min-grant", mingrant); 1068 if (!pciex) 1069 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1070 "max-latency", maxlatency); 1071 } 1072 1073 /* interrupt, record if not 0 */ 1074 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 1075 if (intr != 0) 1076 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1077 "interrupts", intr); 1078 1079 /* 1080 * Add support for 133 mhz pci eventually 1081 */ 1082 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1083 1084 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1085 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 1086 if (!pciex && (status & PCI_STAT_FBBC)) 1087 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1088 "fast-back-to-back"); 1089 if (!pciex && (status & PCI_STAT_66MHZ)) 1090 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1091 "66mhz-capable"); 1092 if (status & PCI_STAT_UDF) 1093 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1094 "udf-supported"); 1095 if (pciex && slot_num) { 1096 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1097 "physical-slot#", slot_num); 1098 if (!is_pci_bridge) 1099 pciex_slot_names_prop(dip, slot_num); 1100 } 1101 1102 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1103 "power-consumption", power, 2); 1104 1105 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 1106 add_ppb_props(dip, bus, dev, func, pciex); 1107 1108 if (config_op == CONFIG_INFO && 1109 IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 1110 create_ioapic_node(bus, dev, func, vendorid, deviceid); 1111 } 1112 1113 /* check for ck8-04 based PCI ISA bridge only */ 1114 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 1115 (func == 0)) 1116 add_nvidia_isa_bridge_props(dip, bus, dev, func); 1117 1118 if (pciex && is_pci_bridge) 1119 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1120 (char *)"PCIe-PCI bridge"); 1121 else 1122 add_model_prop(dip, classcode); 1123 1124 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 1125 revid, classcode, pciex); 1126 1127 /* 1128 * See if this device is a controller that advertises 1129 * itself to be a standard ATA task file controller, or one that 1130 * has been hard coded. 1131 * 1132 * If it is, check if any other higher precedence driver listed in 1133 * driver_aliases will claim the node by calling 1134 * ddi_compatibile_driver_major. If so, clear pciide and do not 1135 * create a pci-ide node or any other special handling. 1136 * 1137 * If another driver does not bind, set the node name to pci-ide 1138 * and then let the special pci-ide handling for registers and 1139 * child pci-ide nodes proceed below. 1140 */ 1141 if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 1142 subvenid, subdevid) == 1) { 1143 if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 1144 (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 1145 pciide = 1; 1146 } 1147 } 1148 1149 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 1150 (void) ndi_devi_bind_driver(dip, 0); 1151 1152 /* special handling for pci-ide */ 1153 if (pciide) { 1154 dev_info_t *cdip; 1155 1156 /* 1157 * Create properties specified by P1275 Working Group 1158 * Proposal #414 Version 1 1159 */ 1160 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1161 "device_type", "pci-ide"); 1162 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1163 "#address-cells", 1); 1164 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1165 "#size-cells", 0); 1166 1167 /* allocate two child nodes */ 1168 ndi_devi_alloc_sleep(dip, "ide", 1169 (pnode_t)DEVI_SID_NODEID, &cdip); 1170 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1171 "reg", 0); 1172 (void) ndi_devi_bind_driver(cdip, 0); 1173 ndi_devi_alloc_sleep(dip, "ide", 1174 (pnode_t)DEVI_SID_NODEID, &cdip); 1175 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1176 "reg", 1); 1177 (void) ndi_devi_bind_driver(cdip, 0); 1178 1179 reprogram = 0; /* don't reprogram pci-ide bridge */ 1180 } 1181 1182 1183 if (reprogram) 1184 return (dip); 1185 return (NULL); 1186 } 1187 1188 /* 1189 * Set the compatible property to a value compliant with 1190 * rev 2.1 of the IEEE1275 PCI binding. 1191 * (Also used for PCI-Express devices). 1192 * 1193 * pciVVVV,DDDD.SSSS.ssss.RR (0) 1194 * pciVVVV,DDDD.SSSS.ssss (1) 1195 * pciSSSS,ssss (2) 1196 * pciVVVV,DDDD.RR (3) 1197 * pciVVVV,DDDD (4) 1198 * pciclass,CCSSPP (5) 1199 * pciclass,CCSS (6) 1200 * 1201 * The Subsystem (SSSS) forms are not inserted if 1202 * subsystem-vendor-id is 0. 1203 * 1204 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 1205 * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 1206 * 1207 * Set with setprop and \x00 between each 1208 * to generate the encoded string array form. 1209 */ 1210 void 1211 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 1212 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 1213 int pciex) 1214 { 1215 int i = 0; 1216 int size = COMPAT_BUFSIZE; 1217 char *compat[13]; 1218 char *buf, *curr; 1219 1220 curr = buf = kmem_alloc(size, KM_SLEEP); 1221 1222 if (pciex) { 1223 if (subvenid) { 1224 compat[i++] = curr; /* form 0 */ 1225 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 1226 vendorid, deviceid, subvenid, subdevid, revid); 1227 size -= strlen(curr) + 1; 1228 curr += strlen(curr) + 1; 1229 1230 compat[i++] = curr; /* form 1 */ 1231 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 1232 vendorid, deviceid, subvenid, subdevid); 1233 size -= strlen(curr) + 1; 1234 curr += strlen(curr) + 1; 1235 1236 } 1237 compat[i++] = curr; /* form 3 */ 1238 (void) snprintf(curr, size, "pciex%x,%x.%x", 1239 vendorid, deviceid, revid); 1240 size -= strlen(curr) + 1; 1241 curr += strlen(curr) + 1; 1242 1243 compat[i++] = curr; /* form 4 */ 1244 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 1245 size -= strlen(curr) + 1; 1246 curr += strlen(curr) + 1; 1247 1248 compat[i++] = curr; /* form 5 */ 1249 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 1250 size -= strlen(curr) + 1; 1251 curr += strlen(curr) + 1; 1252 1253 compat[i++] = curr; /* form 6 */ 1254 (void) snprintf(curr, size, "pciexclass,%04x", 1255 (classcode >> 8)); 1256 size -= strlen(curr) + 1; 1257 curr += strlen(curr) + 1; 1258 } 1259 1260 if (subvenid) { 1261 compat[i++] = curr; /* form 0 */ 1262 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 1263 vendorid, deviceid, subvenid, subdevid, revid); 1264 size -= strlen(curr) + 1; 1265 curr += strlen(curr) + 1; 1266 1267 compat[i++] = curr; /* form 1 */ 1268 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 1269 vendorid, deviceid, subvenid, subdevid); 1270 size -= strlen(curr) + 1; 1271 curr += strlen(curr) + 1; 1272 1273 compat[i++] = curr; /* form 2 */ 1274 (void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid); 1275 size -= strlen(curr) + 1; 1276 curr += strlen(curr) + 1; 1277 } 1278 compat[i++] = curr; /* form 3 */ 1279 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 1280 size -= strlen(curr) + 1; 1281 curr += strlen(curr) + 1; 1282 1283 compat[i++] = curr; /* form 4 */ 1284 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 1285 size -= strlen(curr) + 1; 1286 curr += strlen(curr) + 1; 1287 1288 compat[i++] = curr; /* form 5 */ 1289 (void) snprintf(curr, size, "pciclass,%06x", classcode); 1290 size -= strlen(curr) + 1; 1291 curr += strlen(curr) + 1; 1292 1293 compat[i++] = curr; /* form 6 */ 1294 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 1295 size -= strlen(curr) + 1; 1296 curr += strlen(curr) + 1; 1297 1298 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1299 "compatible", compat, i); 1300 kmem_free(buf, COMPAT_BUFSIZE); 1301 } 1302 1303 /* 1304 * Adjust the reg properties for a dual channel PCI-IDE device. 1305 * 1306 * NOTE: don't do anything that changes the order of the hard-decodes 1307 * and programmed BARs. The kernel driver depends on these values 1308 * being in this order regardless of whether they're for a 'native' 1309 * mode BAR or not. 1310 */ 1311 /* 1312 * config info for pci-ide devices 1313 */ 1314 static struct { 1315 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 1316 uchar_t bar_offset; /* offset for alt status register */ 1317 ushort_t addr; /* compatibility mode base address */ 1318 ushort_t length; /* number of ports for this BAR */ 1319 } pciide_bar[] = { 1320 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 1321 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 1322 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 1323 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 1324 }; 1325 1326 static int 1327 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 1328 { 1329 int hard_decode = 0; 1330 1331 /* 1332 * Adjust the base and len for the BARs of the PCI-IDE 1333 * device's primary and secondary controllers. The first 1334 * two BARs are for the primary controller and the next 1335 * two BARs are for the secondary controller. The fifth 1336 * and sixth bars are never adjusted. 1337 */ 1338 if (index >= 0 && index <= 3) { 1339 *lenp = pciide_bar[index].length; 1340 1341 if (progcl & pciide_bar[index].native_mask) { 1342 *basep += pciide_bar[index].bar_offset; 1343 } else { 1344 *basep = pciide_bar[index].addr; 1345 hard_decode = 1; 1346 } 1347 } 1348 1349 /* 1350 * if either base or len is zero make certain both are zero 1351 */ 1352 if (*basep == 0 || *lenp == 0) { 1353 *basep = 0; 1354 *lenp = 0; 1355 hard_decode = 0; 1356 } 1357 1358 return (hard_decode); 1359 } 1360 1361 1362 /* 1363 * Add the "reg" and "assigned-addresses" property 1364 */ 1365 static int 1366 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1367 int config_op, int pciide) 1368 { 1369 uchar_t baseclass, subclass, progclass, header; 1370 ushort_t bar_sz; 1371 uint_t value = 0, len, devloc; 1372 uint_t base, base_hi, type; 1373 ushort_t offset, end; 1374 int max_basereg, j, reprogram = 0; 1375 uint_t phys_hi; 1376 struct memlist **io_res, **mres, **mem_res, **pmem_res; 1377 uint16_t cmd_reg; 1378 1379 pci_regspec_t regs[16] = {{0}}; 1380 pci_regspec_t assigned[15] = {{0}}; 1381 int nreg, nasgn, enable = 0; 1382 1383 io_res = &pci_bus_res[bus].io_ports; 1384 mem_res = &pci_bus_res[bus].mem_space; 1385 if (bus == 0) /* for bus 0, there is only mem_space */ 1386 pmem_res = mem_res; 1387 else 1388 pmem_res = &pci_bus_res[bus].pmem_space; 1389 1390 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 1391 regs[0].pci_phys_hi = devloc; 1392 nreg = 1; /* rest of regs[0] is all zero */ 1393 nasgn = 0; 1394 1395 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 1396 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 1397 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 1398 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1399 1400 switch (header) { 1401 case PCI_HEADER_ZERO: 1402 max_basereg = PCI_BASE_NUM; 1403 break; 1404 case PCI_HEADER_PPB: 1405 max_basereg = PCI_BCNF_BASE_NUM; 1406 break; 1407 case PCI_HEADER_CARDBUS: 1408 max_basereg = PCI_CBUS_BASE_NUM; 1409 break; 1410 default: 1411 max_basereg = 0; 1412 break; 1413 } 1414 1415 /* 1416 * Create the register property by saving the current 1417 * value of the base register. Write 0xffffffff to the 1418 * base register. Read the value back to determine the 1419 * required size of the address space. Restore the base 1420 * register contents. 1421 * 1422 * Do not disable I/O and memory access; this isn't necessary 1423 * since no driver is yet attached to this device, and disabling 1424 * I/O and memory access has the side-effect of disabling PCI-PCI 1425 * bridge mappings, which makes the bridge transparent to secondary- 1426 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 1427 * Spec V1.2). 1428 */ 1429 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 1430 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 1431 j++, offset += bar_sz) { 1432 int hard_decode = 0; 1433 1434 /* determine the size of the address space */ 1435 base = pci_getl(bus, dev, func, offset); 1436 pci_putl(bus, dev, func, offset, 0xffffffff); 1437 value = pci_getl(bus, dev, func, offset); 1438 pci_putl(bus, dev, func, offset, base); 1439 1440 /* construct phys hi,med.lo, size hi, lo */ 1441 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 1442 /* i/o space */ 1443 bar_sz = PCI_BAR_SZ_32; 1444 value &= PCI_BASE_IO_ADDR_M; 1445 len = ((value ^ (value-1)) + 1) >> 1; 1446 1447 /* XXX Adjust first 4 IDE registers */ 1448 if (pciide) { 1449 if (subclass != PCI_MASS_IDE) 1450 progclass = (PCI_IDE_IF_NATIVE_PRI | 1451 PCI_IDE_IF_NATIVE_SEC); 1452 hard_decode = pciIdeAdjustBAR(progclass, j, 1453 &base, &len); 1454 } else if (value == 0) { 1455 /* skip base regs with size of 0 */ 1456 continue; 1457 } 1458 1459 regs[nreg].pci_size_low = 1460 assigned[nasgn].pci_size_low = len; 1461 if (!hard_decode) { 1462 regs[nreg].pci_phys_hi = 1463 (PCI_ADDR_IO | devloc) + offset; 1464 } else { 1465 regs[nreg].pci_phys_hi = 1466 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 1467 offset; 1468 regs[nreg].pci_phys_low = 1469 base & PCI_BASE_IO_ADDR_M; 1470 } 1471 assigned[nasgn].pci_phys_hi = 1472 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 1473 type = base & (~PCI_BASE_IO_ADDR_M); 1474 base &= PCI_BASE_IO_ADDR_M; 1475 1476 /* 1477 * first pass - gather what's there 1478 * update/second pass - adjust/allocate regions 1479 * config - allocate regions 1480 */ 1481 if (config_op == CONFIG_INFO) { /* first pass */ 1482 /* take out of the resource map of the bus */ 1483 if (*io_res && base != 0) 1484 (void) memlist_remove(io_res, 1485 (uint64_t)base, (uint64_t)len); 1486 else if (*io_res) 1487 reprogram = 1; 1488 } else if (*io_res && base == 0) { 1489 base = (uint_t)memlist_find(io_res, 1490 (uint64_t)len, (uint64_t)0x4); 1491 if (base != 0) { 1492 /* XXX need to worry about 64-bit? */ 1493 pci_putl(bus, dev, func, offset, 1494 base | type); 1495 base = pci_getl(bus, dev, func, offset); 1496 base &= PCI_BASE_IO_ADDR_M; 1497 } 1498 if (base == 0) { 1499 cmn_err(CE_WARN, "failed to program" 1500 " IO space [%d/%d/%d] BAR@0x%x" 1501 " length 0x%x", 1502 bus, dev, func, offset, len); 1503 } else 1504 enable |= PCI_COMM_IO; 1505 } 1506 assigned[nasgn].pci_phys_low = base; 1507 nreg++, nasgn++; 1508 1509 } else { 1510 /* memory space */ 1511 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 1512 bar_sz = PCI_BAR_SZ_64; 1513 base_hi = pci_getl(bus, dev, func, offset + 4); 1514 phys_hi = PCI_ADDR_MEM64; 1515 } else { 1516 bar_sz = PCI_BAR_SZ_32; 1517 base_hi = 0; 1518 phys_hi = PCI_ADDR_MEM32; 1519 } 1520 1521 /* skip base regs with size of 0 */ 1522 value &= PCI_BASE_M_ADDR_M; 1523 1524 if (value == 0) { 1525 continue; 1526 } 1527 len = ((value ^ (value-1)) + 1) >> 1; 1528 regs[nreg].pci_size_low = 1529 assigned[nasgn].pci_size_low = len; 1530 1531 phys_hi |= (devloc | offset); 1532 if (base & PCI_BASE_PREF_M) { 1533 mres = pmem_res; 1534 phys_hi |= PCI_PREFETCH_B; 1535 } else { 1536 mres = mem_res; 1537 } 1538 regs[nreg].pci_phys_hi = 1539 assigned[nasgn].pci_phys_hi = phys_hi; 1540 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 1541 assigned[nasgn].pci_phys_mid = base_hi; 1542 type = base & ~PCI_BASE_M_ADDR_M; 1543 base &= PCI_BASE_M_ADDR_M; 1544 1545 if (config_op == CONFIG_INFO) { 1546 /* take out of the resource map of the bus */ 1547 if (*mres && base != 0) { 1548 (void) memlist_remove(mres, 1549 (uint64_t)base, (uint64_t)len); 1550 } else if (*mres) 1551 reprogram = 1; 1552 } else if (*mres && base == 0) { 1553 base = (uint_t)memlist_find(mres, 1554 (uint64_t)len, (uint64_t)0x1000); 1555 if (base != NULL) { 1556 pci_putl(bus, dev, func, offset, 1557 base | type); 1558 base = pci_getl(bus, dev, func, offset); 1559 base &= PCI_BASE_M_ADDR_M; 1560 } 1561 1562 if (base == 0) { 1563 cmn_err(CE_WARN, "failed to program " 1564 "mem space [%d/%d/%d] BAR@0x%x" 1565 " length 0x%x", 1566 bus, dev, func, offset, len); 1567 } else 1568 enable |= PCI_COMM_MAE; 1569 } 1570 assigned[nasgn].pci_phys_low = base; 1571 nreg++, nasgn++; 1572 } 1573 } 1574 switch (header) { 1575 case PCI_HEADER_ZERO: 1576 offset = PCI_CONF_ROM; 1577 break; 1578 case PCI_HEADER_PPB: 1579 offset = PCI_BCNF_ROM; 1580 break; 1581 default: /* including PCI_HEADER_CARDBUS */ 1582 goto done; 1583 } 1584 1585 /* 1586 * Add the expansion rom memory space 1587 * Determine the size of the ROM base reg; don't write reserved bits 1588 * ROM isn't in the PCI memory space. 1589 */ 1590 base = pci_getl(bus, dev, func, offset); 1591 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 1592 value = pci_getl(bus, dev, func, offset); 1593 pci_putl(bus, dev, func, offset, base); 1594 if (value & PCI_BASE_ROM_ENABLE) 1595 value &= PCI_BASE_ROM_ADDR_M; 1596 else 1597 value = 0; 1598 1599 if (value != 0) { 1600 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 1601 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 1602 PCI_ADDR_MEM32 | devloc) + offset; 1603 base &= PCI_BASE_ROM_ADDR_M; 1604 assigned[nasgn].pci_phys_low = base; 1605 len = ((value ^ (value-1)) + 1) >> 1; 1606 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 1607 nreg++, nasgn++; 1608 /* take it out of the memory resource */ 1609 if (*mem_res && base != 0) 1610 (void) memlist_remove(mem_res, 1611 (uint64_t)base, (uint64_t)len); 1612 } 1613 1614 /* 1615 * The following are ISA resources. There are not part 1616 * of the PCI local bus resources. So don't attempt to 1617 * do resource accounting against PCI. 1618 */ 1619 1620 /* add the three hard-decode, aliased address spaces for VGA */ 1621 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 1622 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 1623 1624 /* VGA hard decode 0x3b0-0x3bb */ 1625 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1626 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1627 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 1628 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 1629 nreg++, nasgn++; 1630 1631 /* VGA hard decode 0x3c0-0x3df */ 1632 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1633 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1634 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 1635 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 1636 nreg++, nasgn++; 1637 1638 /* Video memory */ 1639 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1640 (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 1641 regs[nreg].pci_phys_low = 1642 assigned[nasgn].pci_phys_low = 0xa0000; 1643 regs[nreg].pci_size_low = 1644 assigned[nasgn].pci_size_low = 0x20000; 1645 nreg++, nasgn++; 1646 } 1647 1648 /* add the hard-decode, aliased address spaces for 8514 */ 1649 if ((baseclass == PCI_CLASS_DISPLAY) && 1650 (subclass == PCI_DISPLAY_VGA) && 1651 (progclass & PCI_DISPLAY_IF_8514)) { 1652 1653 /* hard decode 0x2e8 */ 1654 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1655 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1656 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 1657 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 1658 nreg++, nasgn++; 1659 1660 /* hard decode 0x2ea-0x2ef */ 1661 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1662 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1663 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 1664 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 1665 nreg++, nasgn++; 1666 } 1667 1668 done: 1669 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 1670 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 1671 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1672 "assigned-addresses", 1673 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 1674 if (config_op == CONFIG_NEW && enable) { 1675 cmn_err(CE_NOTE, 1676 "!enable PCI device [%d/%d/%d]", bus, dev, func); 1677 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 1678 cmd_reg |= (enable | PCI_COMM_ME); 1679 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 1680 } 1681 return (reprogram); 1682 } 1683 1684 static void 1685 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1686 int pciex) 1687 { 1688 char *dev_type; 1689 int i; 1690 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 1691 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1692 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1693 ASSERT(secbus <= subbus); 1694 1695 /* 1696 * Some BIOSes lie about max pci busses, we allow for 1697 * such mistakes here 1698 */ 1699 if (subbus > pci_bios_nbus) { 1700 pci_bios_nbus = subbus; 1701 alloc_res_array(); 1702 } 1703 1704 ASSERT(pci_bus_res[secbus].dip == NULL); 1705 pci_bus_res[secbus].dip = dip; 1706 pci_bus_res[secbus].par_bus = bus; 1707 1708 dev_type = pciex ? "pciex" : "pci"; 1709 1710 /* setup bus number hierarchy */ 1711 pci_bus_res[secbus].sub_bus = subbus; 1712 /* 1713 * Keep track of the largest subordinate bus number (this is essential 1714 * for peer busses because there is no other way of determining its 1715 * subordinate bus number). 1716 */ 1717 if (subbus > pci_bus_res[bus].sub_bus) 1718 pci_bus_res[bus].sub_bus = subbus; 1719 /* 1720 * Loop through subordinate busses, initializing their parent bus 1721 * field to this bridge's parent. The subordinate busses' parent 1722 * fields may very well be further refined later, as child bridges 1723 * are enumerated. (The value is to note that the subordinate busses 1724 * are not peer busses by changing their par_bus fields to anything 1725 * other than -1.) 1726 */ 1727 for (i = secbus + 1; i <= subbus; i++) 1728 pci_bus_res[i].par_bus = bus; 1729 1730 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1731 "device_type", dev_type); 1732 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1733 "#address-cells", 3); 1734 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1735 "#size-cells", 2); 1736 1737 /* 1738 * According to PPB spec, the base register should be programmed 1739 * with a value bigger than the limit register when there are 1740 * no resources available. This applies to io, memory, and 1741 * prefetchable memory. 1742 */ 1743 1744 /* 1745 * io range 1746 * We determine i/o windows that are left unconfigured by bios 1747 * through its i/o enable bit as Microsoft recommends OEMs to do. 1748 * If it is unset, we disable i/o and mark it for reconfiguration in 1749 * later passes by setting the base > limit 1750 */ 1751 val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 1752 if (val & PCI_COMM_IO) { 1753 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 1754 io_range[0] = ((val & 0xf0) << 8); 1755 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 1756 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 1757 } else { 1758 io_range[0] = 0x9fff; 1759 io_range[1] = 0x1000; 1760 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 1761 (uint8_t)((io_range[0] >> 8) & 0xf0)); 1762 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 1763 (uint8_t)((io_range[1] >> 8) & 0xf0)); 1764 pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 1765 pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 1766 } 1767 1768 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 1769 memlist_insert(&pci_bus_res[secbus].io_ports, 1770 (uint64_t)io_range[0], 1771 (uint64_t)(io_range[1] - io_range[0] + 1)); 1772 if (pci_bus_res[bus].io_ports != NULL) { 1773 (void) memlist_remove(&pci_bus_res[bus].io_ports, 1774 (uint64_t)io_range[0], 1775 (uint64_t)(io_range[1] - io_range[0] + 1)); 1776 } 1777 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 1778 secbus, io_range[0], io_range[1]); 1779 /* if 32-bit supported, make sure upper bits are not set */ 1780 if ((val & 0xf) == 1 && 1781 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 1782 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 1783 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1784 } 1785 } 1786 1787 /* mem range */ 1788 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 1789 mem_range[0] = ((val & 0xFFF0) << 16); 1790 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1791 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1792 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 1793 memlist_insert(&pci_bus_res[secbus].mem_space, 1794 (uint64_t)mem_range[0], 1795 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1796 /* remove from parent resouce list */ 1797 if (pci_bus_res[bus].mem_space != NULL) { 1798 (void) memlist_remove(&pci_bus_res[bus].mem_space, 1799 (uint64_t)mem_range[0], 1800 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1801 } 1802 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 1803 secbus, mem_range[0], mem_range[1]); 1804 } 1805 1806 /* prefetchable memory range */ 1807 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 1808 pmem_range[0] = ((val & 0xFFF0) << 16); 1809 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 1810 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1811 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 1812 memlist_insert(&pci_bus_res[secbus].pmem_space, 1813 (uint64_t)pmem_range[0], 1814 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1815 if (pci_bus_res[bus].pmem_space != NULL) { 1816 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 1817 (uint64_t)pmem_range[0], 1818 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1819 } 1820 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 1821 secbus, pmem_range[0], pmem_range[1]); 1822 /* if 64-bit supported, make sure upper bits are not set */ 1823 if ((val & 0xf) == 1 && 1824 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 1825 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 1826 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1827 } 1828 } 1829 1830 add_bus_range_prop(secbus); 1831 add_ppb_ranges_prop(secbus); 1832 } 1833 1834 extern const struct pci_class_strings_s class_pci[]; 1835 extern int class_pci_items; 1836 1837 static void 1838 add_model_prop(dev_info_t *dip, uint_t classcode) 1839 { 1840 const char *desc; 1841 int i; 1842 uchar_t baseclass = classcode >> 16; 1843 uchar_t subclass = (classcode >> 8) & 0xff; 1844 uchar_t progclass = classcode & 0xff; 1845 1846 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 1847 desc = "IDE controller"; 1848 } else { 1849 for (desc = 0, i = 0; i < class_pci_items; i++) { 1850 if ((baseclass == class_pci[i].base_class) && 1851 (subclass == class_pci[i].sub_class) && 1852 (progclass == class_pci[i].prog_class)) { 1853 desc = class_pci[i].actual_desc; 1854 break; 1855 } 1856 } 1857 if (i == class_pci_items) 1858 desc = "Unknown class of pci/pnpbios device"; 1859 } 1860 1861 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1862 (char *)desc); 1863 } 1864 1865 static void 1866 add_bus_range_prop(int bus) 1867 { 1868 int bus_range[2]; 1869 1870 if (pci_bus_res[bus].dip == NULL) 1871 return; 1872 bus_range[0] = bus; 1873 bus_range[1] = pci_bus_res[bus].sub_bus; 1874 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1875 "bus-range", (int *)bus_range, 2); 1876 } 1877 1878 /* 1879 * Add slot-names property for any named pci hot-plug slots 1880 */ 1881 static void 1882 add_bus_slot_names_prop(int bus) 1883 { 1884 char slotprop[256]; 1885 int len; 1886 1887 if (pci_bus_res[bus].dip != NULL) { 1888 /* simply return if the property is already defined */ 1889 if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip, 1890 DDI_PROP_DONTPASS, "slot-names")) 1891 return; 1892 } 1893 1894 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 1895 if (len > 0) { 1896 /* 1897 * Only create a peer bus node if this bus may be a peer bus. 1898 * It may be a peer bus if the dip is NULL and if par_bus is 1899 * -1 (par_bus is -1 if this bus was not found to be 1900 * subordinate to any PCI-PCI bridge). 1901 * If it's not a peer bus, then the ACPI BBN-handling code 1902 * will remove it later. 1903 */ 1904 if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 1905 pci_bus_res[bus].dip == NULL) { 1906 1907 create_root_bus_dip(bus); 1908 } 1909 if (pci_bus_res[bus].dip != NULL) { 1910 ASSERT((len % sizeof (int)) == 0); 1911 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1912 pci_bus_res[bus].dip, "slot-names", 1913 (int *)slotprop, len / sizeof (int)); 1914 } else { 1915 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 1916 "IRQ routing table; Not adding slot-names " 1917 "property for incorrect bus %d", bus); 1918 } 1919 } 1920 } 1921 1922 static int 1923 memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type) 1924 { 1925 if (entry == NULL) 1926 return (0); 1927 1928 /* assume 32-bit addresses */ 1929 rp->child_high = rp->parent_high = type; 1930 rp->child_mid = rp->parent_mid = 0; 1931 rp->child_low = rp->parent_low = (uint32_t)entry->address; 1932 rp->size_high = 0; 1933 rp->size_low = (uint32_t)entry->size; 1934 return (1); 1935 } 1936 1937 static void 1938 add_ppb_ranges_prop(int bus) 1939 { 1940 int i = 0; 1941 ppb_ranges_t *rp; 1942 1943 rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP); 1944 1945 i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports, 1946 PCI_ADDR_IO | PCI_REG_REL_M); 1947 i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space, 1948 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1949 i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space, 1950 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1951 1952 if (i != 0) 1953 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1954 pci_bus_res[bus].dip, "ranges", (int *)rp, 1955 i * sizeof (ppb_ranges_t) / sizeof (int)); 1956 kmem_free(rp, 3 * sizeof (*rp)); 1957 } 1958 1959 static int 1960 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 1961 { 1962 int i = 0; 1963 1964 while (list) { 1965 /* assume 32-bit addresses */ 1966 sp->pci_phys_hi = type; 1967 sp->pci_phys_mid = 0; 1968 sp->pci_phys_low = (uint32_t)list->address; 1969 sp->pci_size_hi = 0; 1970 sp->pci_size_low = (uint32_t)list->size; 1971 1972 list = list->next; 1973 sp++, i++; 1974 } 1975 return (i); 1976 } 1977 1978 static void 1979 add_bus_available_prop(int bus) 1980 { 1981 int i, count; 1982 struct pci_phys_spec *sp; 1983 1984 count = memlist_count(pci_bus_res[bus].io_ports) + 1985 memlist_count(pci_bus_res[bus].mem_space) + 1986 memlist_count(pci_bus_res[bus].pmem_space); 1987 1988 if (count == 0) /* nothing available */ 1989 return; 1990 1991 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 1992 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 1993 PCI_ADDR_IO | PCI_REG_REL_M); 1994 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 1995 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1996 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 1997 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1998 ASSERT(i == count); 1999 2000 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2001 "available", (int *)sp, 2002 i * sizeof (struct pci_phys_spec) / sizeof (int)); 2003 kmem_free(sp, count * sizeof (*sp)); 2004 } 2005 2006 static void 2007 alloc_res_array(void) 2008 { 2009 static int array_max = 0; 2010 int old_max; 2011 void *old_res; 2012 2013 if (array_max > pci_bios_nbus + 1) 2014 return; /* array is big enough */ 2015 2016 old_max = array_max; 2017 old_res = pci_bus_res; 2018 2019 if (array_max == 0) 2020 array_max = 16; /* start with a reasonable number */ 2021 2022 while (array_max < pci_bios_nbus + 1) 2023 array_max <<= 1; 2024 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 2025 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 2026 2027 if (old_res) { /* copy content and free old array */ 2028 bcopy(old_res, pci_bus_res, 2029 old_max * sizeof (struct pci_bus_resource)); 2030 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 2031 } 2032 } 2033 2034 static void 2035 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 2036 ushort_t deviceid) 2037 { 2038 static dev_info_t *ioapicsnode = NULL; 2039 static int numioapics = 0; 2040 dev_info_t *ioapic_node; 2041 uint64_t physaddr; 2042 uint32_t lobase, hibase = 0; 2043 2044 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 2045 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 2046 2047 /* We (and the rest of the world) only support memory-mapped IOAPICs */ 2048 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 2049 return; 2050 2051 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 2052 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 2053 2054 lobase &= PCI_BASE_M_ADDR_M; 2055 2056 physaddr = (((uint64_t)hibase) << 32) | lobase; 2057 2058 /* 2059 * Create a nexus node for all IOAPICs under the root node. 2060 */ 2061 if (ioapicsnode == NULL) { 2062 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 2063 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 2064 return; 2065 } 2066 (void) ndi_devi_online(ioapicsnode, 0); 2067 } 2068 2069 /* 2070 * Create a child node for this IOAPIC 2071 */ 2072 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 2073 DEVI_SID_NODEID, numioapics++); 2074 if (ioapic_node == NULL) { 2075 return; 2076 } 2077 2078 /* Vendor and Device ID */ 2079 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2080 IOAPICS_PROP_VENID, vendorid); 2081 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2082 IOAPICS_PROP_DEVID, deviceid); 2083 2084 /* device_type */ 2085 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 2086 "device_type", IOAPICS_DEV_TYPE); 2087 2088 /* reg */ 2089 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 2090 "reg", physaddr); 2091 } 2092 2093 /* 2094 * NOTE: For PCIe slots, the name is generated from the slot number 2095 * information obtained from Slot Capabilities register. 2096 * For non-PCIe slots, it is generated based on the slot number 2097 * information in the PCI IRQ table. 2098 */ 2099 static void 2100 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 2101 { 2102 char slotprop[256]; 2103 int len; 2104 2105 bzero(slotprop, sizeof (slotprop)); 2106 2107 /* set mask to 1 as there is only one slot (i.e dev 0) */ 2108 *(uint32_t *)slotprop = 1; 2109 len = 4; 2110 (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 2111 slot_num); 2112 len += strlen(slotprop + len) + 1; 2113 len += len % 4; 2114 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 2115 (int *)slotprop, len / sizeof (int)); 2116 } 2117