xref: /titanic_52/usr/src/uts/intel/io/pci/pci_boot.c (revision a1d92fe4831144630aa0b262cde1629785c37f23)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 #include <sys/types.h>
29 #include <sys/stat.h>
30 #include <sys/sunndi.h>
31 #include <sys/pci.h>
32 #include <sys/pci_impl.h>
33 #include <sys/pci_cfgspace.h>
34 #include <sys/memlist.h>
35 #include <sys/bootconf.h>
36 #include <io/pci/mps_table.h>
37 #include <sys/pci_cfgspace.h>
38 #include <sys/pci_cfgspace_impl.h>
39 #include <sys/psw.h>
40 #include "../../../../common/pci/pci_strings.h"
41 #include <sys/apic.h>
42 #include <io/pciex/pcie_nvidia.h>
43 #include <io/hotplug/pciehpc/pciehpc_acpi.h>
44 #include <sys/acpi/acpi.h>
45 #include <sys/acpica.h>
46 
47 #define	pci_getb	(*pci_getb_func)
48 #define	pci_getw	(*pci_getw_func)
49 #define	pci_getl	(*pci_getl_func)
50 #define	pci_putb	(*pci_putb_func)
51 #define	pci_putw	(*pci_putw_func)
52 #define	pci_putl	(*pci_putl_func)
53 #define	dcmn_err	if (pci_boot_debug) cmn_err
54 
55 #define	CONFIG_INFO	0
56 #define	CONFIG_UPDATE	1
57 #define	CONFIG_NEW	2
58 #define	CONFIG_FIX	3
59 #define	COMPAT_BUFSIZE	512
60 
61 #define	PPB_IO_ALIGNMENT	0x1000		/* 4K aligned */
62 #define	PPB_MEM_ALIGNMENT	0x100000	/* 1M aligned */
63 
64 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */
65 #define	LPC_IO_CONTROL_REG_1	0x40
66 #define	AMD8111_ENABLENMI	(uint8_t)0x80
67 #define	DEVID_AMD8111_LPC	0x7468
68 
69 struct pci_fixundo {
70 	uint8_t			bus;
71 	uint8_t			dev;
72 	uint8_t			fn;
73 	void			(*undofn)(uint8_t, uint8_t, uint8_t);
74 	struct pci_fixundo	*next;
75 };
76 
77 struct pci_devfunc {
78 	struct pci_devfunc *next;
79 	dev_info_t *dip;
80 	uchar_t dev;
81 	uchar_t func;
82 	boolean_t reprogram;	/* this device needs to be reprogrammed */
83 };
84 
85 extern int pci_bios_nbus;
86 static uchar_t max_dev_pci = 32;	/* PCI standard */
87 int pci_boot_debug = 0;
88 extern struct memlist *find_bus_res(int, int);
89 static struct pci_fixundo *undolist = NULL;
90 static int num_root_bus = 0;	/* count of root buses */
91 
92 /*
93  * Module prototypes
94  */
95 static void enumerate_bus_devs(uchar_t bus, int config_op);
96 static void create_root_bus_dip(uchar_t bus);
97 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t,
98     ushort_t, int);
99 static void add_compatible(dev_info_t *, ushort_t, ushort_t,
100     ushort_t, ushort_t, uchar_t, uint_t, int);
101 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int);
102 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int);
103 static void add_model_prop(dev_info_t *, uint_t);
104 static void add_bus_range_prop(int);
105 static void add_bus_slot_names_prop(int);
106 static void add_ppb_ranges_prop(int);
107 static void add_bus_available_prop(int);
108 static void fix_ppb_res(uchar_t, boolean_t);
109 static void alloc_res_array();
110 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
111     ushort_t deviceid);
112 static void pciex_slot_names_prop(dev_info_t *, ushort_t);
113 
114 extern int pci_slot_names_prop(int, char *, int);
115 
116 /* set non-zero to force PCI peer-bus renumbering */
117 int pci_bus_always_renumber = 0;
118 
119 /* get the subordinate bus # for a root/peer bus */
120 static int
121 pci_root_subbus(int bus, uchar_t *subbus)
122 {
123 	ACPI_HANDLE	hdl;
124 	ACPI_BUFFER	rb;
125 	ACPI_RESOURCE	*rp;
126 	int	rv;
127 
128 	if (pci_bus_res[bus].dip == NULL) {
129 		/* non-used bus # */
130 		return (AE_ERROR);
131 	}
132 	if (acpica_get_handle(pci_bus_res[bus].dip, &hdl) != AE_OK) {
133 		cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus);
134 		return (AE_ERROR);
135 	}
136 
137 	rb.Length = ACPI_ALLOCATE_BUFFER;
138 	if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) {
139 		cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus);
140 		return (AE_ERROR);
141 	}
142 
143 	rv = AE_ERROR;
144 
145 	for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG;
146 	    rp = ACPI_NEXT_RESOURCE(rp)) {
147 
148 		switch (rp->Type) {
149 		case ACPI_RESOURCE_TYPE_ADDRESS16:
150 			if (rp->Data.Address.ResourceType !=
151 			    ACPI_BUS_NUMBER_RANGE)
152 				continue;
153 			*subbus = (uchar_t)rp->Data.Address16.Maximum;
154 			dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus);
155 			break;
156 		case ACPI_RESOURCE_TYPE_ADDRESS32:
157 			if (rp->Data.Address.ResourceType !=
158 			    ACPI_BUS_NUMBER_RANGE)
159 				continue;
160 			*subbus = (uchar_t)rp->Data.Address32.Maximum;
161 			dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus);
162 			break;
163 		case ACPI_RESOURCE_TYPE_ADDRESS64:
164 			if (rp->Data.Address.ResourceType !=
165 			    ACPI_BUS_NUMBER_RANGE)
166 				continue;
167 			*subbus = (uchar_t)rp->Data.Address64.Maximum;
168 			dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus);
169 			break;
170 		case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64:
171 			if (rp->Data.Address.ResourceType !=
172 			    ACPI_BUS_NUMBER_RANGE)
173 				continue;
174 			*subbus = (uchar_t)rp->Data.ExtAddress64.Maximum;
175 			dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus);
176 			break;
177 		default:
178 			dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type);
179 			continue;
180 		}
181 
182 		/* found the bus-range resource */
183 		dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus);
184 		rv = AE_OK;
185 
186 		/* This breaks out of the resource scanning loop */
187 		break;
188 	}
189 
190 	AcpiOsFree(rb.Pointer);
191 	if (rv != AE_OK)
192 		cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus);
193 
194 	return (rv);
195 
196 }
197 
198 /*
199  * Enumerate all PCI devices
200  */
201 void
202 pci_setup_tree()
203 {
204 	uchar_t i, root_bus_addr = 0;
205 
206 	alloc_res_array();
207 	for (i = 0; i <= pci_bios_nbus; i++) {
208 		pci_bus_res[i].par_bus = (uchar_t)-1;
209 		pci_bus_res[i].root_addr = (uchar_t)-1;
210 		pci_bus_res[i].sub_bus = i;
211 	}
212 
213 	pci_bus_res[0].root_addr = root_bus_addr++;
214 	create_root_bus_dip(0);
215 	enumerate_bus_devs(0, CONFIG_INFO);
216 
217 	/*
218 	 * Now enumerate peer busses
219 	 *
220 	 * We loop till pci_bios_nbus. On most systems, there is
221 	 * one more bus at the high end, which implements the ISA
222 	 * compatibility bus. We don't care about that.
223 	 *
224 	 * Note: In the old (bootconf) enumeration, the peer bus
225 	 *	address did not use the bus number, and there were
226 	 *	too many peer busses created. The root_bus_addr is
227 	 *	used to maintain the old peer bus address assignment.
228 	 *	However, we stop enumerating phantom peers with no
229 	 *	device below.
230 	 */
231 	for (i = 1; i <= pci_bios_nbus; i++) {
232 		if (pci_bus_res[i].dip == NULL) {
233 			pci_bus_res[i].root_addr = root_bus_addr++;
234 		}
235 		enumerate_bus_devs(i, CONFIG_INFO);
236 
237 		/* add slot-names property for named pci hot-plug slots */
238 		add_bus_slot_names_prop(i);
239 	}
240 
241 }
242 
243 /*
244  * >0 = present, 0 = not present, <0 = error
245  */
246 static int
247 pci_bbn_present(int bus)
248 {
249 	ACPI_HANDLE	hdl;
250 	ACPI_BUFFER	rb;
251 	int	rv;
252 
253 	/* no dip means no _BBN */
254 	if (pci_bus_res[bus].dip == NULL)
255 		return (0);
256 
257 	rv = acpica_get_handle(pci_bus_res[bus].dip, &hdl);
258 	if (rv != AE_OK)
259 		return (-1);
260 
261 	rb.Length = ACPI_ALLOCATE_BUFFER;
262 
263 	rv = AcpiEvaluateObject(hdl, "_BBN", NULL, &rb);
264 
265 	if (rb.Length > 0)
266 		AcpiOsFree(rb.Pointer);
267 
268 	if (rv == AE_OK)
269 		return (1);
270 	else if (rv == AE_NOT_FOUND)
271 		return (0);
272 	else
273 		return (-1);
274 }
275 
276 /*
277  * Return non-zero if any PCI bus in the system has an associated
278  * _BBN object, 0 otherwise.
279  */
280 static int
281 pci_roots_have_bbn(void)
282 {
283 	int	i;
284 
285 	/*
286 	 * Scan the PCI busses and look for at least 1 _BBN
287 	 */
288 	for (i = 0; i <= pci_bios_nbus; i++) {
289 		/* skip non-root (peer) PCI busses */
290 		if (pci_bus_res[i].par_bus != (uchar_t)-1)
291 			continue;
292 
293 		if (pci_bbn_present(i) > 0)
294 			return (1);
295 	}
296 	return (0);
297 
298 }
299 
300 /*
301  * return non-zero if the machine is one on which we renumber
302  * the internal pci unit-addresses
303  */
304 static int
305 pci_bus_renumber()
306 {
307 	ACPI_TABLE_HEADER *fadt;
308 
309 	if (pci_bus_always_renumber)
310 		return (1);
311 
312 	/* get the FADT */
313 	if (AcpiGetFirmwareTable(FADT_SIG, 1, ACPI_LOGICAL_ADDRESSING,
314 	    (ACPI_TABLE_HEADER **)&fadt) != AE_OK)
315 		return (0);
316 
317 	/* compare OEM Table ID to "SUNm31" */
318 	if (strncmp("SUNm31", fadt->OemId, 6))
319 		return (0);
320 	else
321 		return (1);
322 }
323 
324 /*
325  * Initial enumeration of the physical PCI bus hierarchy can
326  * leave 'gaps' in the order of peer PCI bus unit-addresses.
327  * Systems with more than one peer PCI bus *must* have an ACPI
328  * _BBN object associated with each peer bus; use the presence
329  * of this object to remove gaps in the numbering of the peer
330  * PCI bus unit-addresses - only peer busses with an associated
331  * _BBN are counted.
332  */
333 static void
334 pci_renumber_root_busses(void)
335 {
336 	int pci_regs[] = {0, 0, 0};
337 	int	i, root_addr = 0;
338 
339 	/*
340 	 * Currently, we only enable the re-numbering on specific
341 	 * Sun machines; this is a work-around for the more complicated
342 	 * issue of upgrade changing physical device paths
343 	 */
344 	if (!pci_bus_renumber())
345 		return;
346 
347 	/*
348 	 * If we find no _BBN objects at all, we either don't need
349 	 * to do anything or can't do anything anyway
350 	 */
351 	if (!pci_roots_have_bbn())
352 		return;
353 
354 	for (i = 0; i <= pci_bios_nbus; i++) {
355 		/* skip non-root (peer) PCI busses */
356 		if (pci_bus_res[i].par_bus != (uchar_t)-1)
357 			continue;
358 
359 		if (pci_bbn_present(i) < 1) {
360 			pci_bus_res[i].root_addr = (uchar_t)-1;
361 			continue;
362 		}
363 
364 		ASSERT(pci_bus_res[i].dip != NULL);
365 		if (pci_bus_res[i].root_addr != root_addr) {
366 			/* update reg property for node */
367 			pci_bus_res[i].root_addr = root_addr;
368 			pci_regs[0] = pci_bus_res[i].root_addr;
369 			(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
370 			    pci_bus_res[i].dip, "reg", (int *)pci_regs, 3);
371 		}
372 		root_addr++;
373 	}
374 }
375 
376 static void
377 remove_resource_range(struct memlist **list, int *ranges, int range_count)
378 {
379 	struct range {
380 		uint32_t base;
381 		uint32_t len;
382 	};
383 	int index;
384 
385 	for (index = 0; index < range_count; index++) {
386 		/* all done if list is or has become empty */
387 		if (*list == NULL)
388 			break;
389 		(void) memlist_remove(list,
390 		    (uint64_t)((struct range *)ranges)[index].base,
391 		    (uint64_t)((struct range *)ranges)[index].len);
392 	}
393 }
394 
395 static void
396 remove_used_resources()
397 {
398 	dev_info_t *used;
399 	int	*narray;
400 	uint_t	ncount;
401 	int	status;
402 	int	bus;
403 
404 	used = ddi_find_devinfo("used-resources", -1, 0);
405 	if (used == NULL)
406 		return;
407 
408 	status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used,
409 	    DDI_PROP_DONTPASS, "io-space", &narray, &ncount);
410 	if (status == DDI_PROP_SUCCESS) {
411 		for (bus = 0; bus <= pci_bios_nbus; bus++)
412 			remove_resource_range(&pci_bus_res[bus].io_ports,
413 			    narray, ncount / 2);
414 		ddi_prop_free(narray);
415 	}
416 
417 	status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used,
418 	    DDI_PROP_DONTPASS, "device-memory", &narray, &ncount);
419 	if (status == DDI_PROP_SUCCESS) {
420 		for (bus = 0; bus <= pci_bios_nbus; bus++)
421 			remove_resource_range(&pci_bus_res[bus].mem_space,
422 			    narray, ncount / 2);
423 		ddi_prop_free(narray);
424 	}
425 }
426 
427 /*
428  * Remove the resources which are already used by devices under a subtractive
429  * bridge from the bus's resources lists, because they're not available, and
430  * shouldn't be allocated to other buses.  This is necessary because tracking
431  * resources for subtractive bridges is not complete.  (Subtractive bridges only
432  * track some of their claimed resources, not "the rest of the address space" as
433  * they should, so that allocation to peer non-subtractive PPBs is easier.  We
434  * need a fully-capable global resource allocator).
435  */
436 static void
437 remove_subtractive_res()
438 {
439 	int i, j;
440 	struct memlist *list;
441 
442 	for (i = 0; i <= pci_bios_nbus; i++) {
443 		if (pci_bus_res[i].subtractive) {
444 			/* remove used io ports */
445 			list = pci_bus_res[i].io_ports_used;
446 			while (list) {
447 				for (j = 0; j <= pci_bios_nbus; j++) {
448 					if (pci_bus_res[j].io_ports)
449 						(void) memlist_remove(
450 						    &pci_bus_res[j].io_ports,
451 						    list->address, list->size);
452 				}
453 				list = list->next;
454 			}
455 			/* remove used mem resource */
456 			list = pci_bus_res[i].mem_space_used;
457 			while (list) {
458 				for (j = 0; j <= pci_bios_nbus; j++) {
459 					if (pci_bus_res[j].mem_space)
460 						(void) memlist_remove(
461 						    &pci_bus_res[j].mem_space,
462 						    list->address, list->size);
463 				}
464 				list = list->next;
465 			}
466 			/* remove used prefetchable mem resource */
467 			list = pci_bus_res[i].pmem_space_used;
468 			while (list) {
469 				for (j = 0; j <= pci_bios_nbus; j++) {
470 					if (pci_bus_res[j].pmem_space)
471 						(void) memlist_remove(
472 						    &pci_bus_res[j].pmem_space,
473 						    list->address, list->size);
474 				}
475 				list = list->next;
476 			}
477 		}
478 	}
479 }
480 
481 /* Set up this bus's "bus_space" resource list */
482 static void
483 setup_bus_res(int bus)
484 {
485 	uchar_t par_bus;
486 	uchar_t sub_bus;
487 
488 	if (pci_bus_res[bus].dip == NULL)	/* unused bus */
489 		return;
490 
491 	sub_bus = pci_bus_res[bus].sub_bus;
492 	ASSERT(sub_bus >= bus);
493 	ASSERT(pci_bus_res[bus].bus_space == NULL);
494 	if (sub_bus > bus) {
495 		/*
496 		 * Keep the remaining available bus range in bus_space.
497 		 * ('bus' is already allocated)
498 		 */
499 		memlist_insert(&pci_bus_res[bus].bus_space, bus + 1,
500 		    sub_bus - bus);
501 	}
502 
503 	/*
504 	 * Remove resources from parent bus node if this is not a
505 	 * root bus.
506 	 */
507 	par_bus = pci_bus_res[bus].par_bus;
508 	if (par_bus != (uchar_t)-1) {
509 		ASSERT(pci_bus_res[par_bus].bus_space != NULL);
510 		(void) memlist_remove(&pci_bus_res[par_bus].bus_space,
511 		    bus, sub_bus - bus + 1);
512 	}
513 }
514 
515 static uint64_t
516 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
517 {
518 	uint64_t addr = 0;
519 	uchar_t res_bus;
520 
521 	/*
522 	 * Skip root(peer) buses in multiple-root-bus systems, as currently
523 	 * the initial resources set on each root bus might not be correctly
524 	 * accounted for.  (We need to read resources from ACPI as well as
525 	 * the MP tables and hotplug tables.)
526 	 */
527 	if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) &&
528 	    (num_root_bus > 1))
529 		return (0);
530 
531 	res_bus = parbus;
532 	while (pci_bus_res[res_bus].subtractive) {
533 		if (pci_bus_res[res_bus].io_ports)
534 			break;
535 		res_bus = pci_bus_res[res_bus].par_bus;
536 		if (res_bus == (uchar_t)-1)
537 			break; /* root bus already */
538 	}
539 
540 	if (pci_bus_res[res_bus].io_ports) {
541 		addr = memlist_find(&pci_bus_res[res_bus].io_ports,
542 		    size, align);
543 		if (addr) {
544 			memlist_insert(&pci_bus_res[res_bus].io_ports_used,
545 			    addr, size);
546 			/* free the old resource */
547 			memlist_free_all(&pci_bus_res[bus].io_ports);
548 			/* add the new resource */
549 			memlist_insert(&pci_bus_res[bus].io_ports, addr, size);
550 		}
551 	}
552 
553 	return (addr);
554 }
555 
556 static uint64_t
557 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
558 {
559 	uint64_t addr = 0;
560 	uchar_t res_bus;
561 
562 	/*
563 	 * Skip root(peer) buses in multiple-root-bus systems, as currently
564 	 * the initial resources set on each root bus might not be correctly
565 	 * accounted for.  (We need to read resources from ACPI as well as
566 	 * the MP tables and hotplug tables.)
567 	 */
568 	if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) &&
569 	    (num_root_bus > 1))
570 		return (0);
571 
572 	res_bus = parbus;
573 	while (pci_bus_res[res_bus].subtractive) {
574 		if (pci_bus_res[res_bus].mem_space)
575 			break;
576 		res_bus = pci_bus_res[res_bus].par_bus;
577 		if (res_bus == (uchar_t)-1)
578 			break; /* root bus already */
579 	}
580 
581 	if (pci_bus_res[res_bus].mem_space) {
582 		addr = memlist_find(&pci_bus_res[res_bus].mem_space,
583 		    size, align);
584 		if (addr) {
585 			memlist_insert(&pci_bus_res[res_bus].mem_space_used,
586 			    addr, size);
587 			/* free the old resource */
588 			memlist_free_all(&pci_bus_res[bus].mem_space);
589 			/* add the new resource */
590 			memlist_insert(&pci_bus_res[bus].mem_space, addr, size);
591 		}
592 	}
593 
594 	return (addr);
595 }
596 
597 /*
598  * Assign valid resources to unconfigured pci(e) bridges. We are trying
599  * to reprogram the bridge when its
600  * 		i)   SECBUS == SUBBUS	||
601  * 		ii)  IOBASE > IOLIM	||
602  * 		iii) MEMBASE > MEMLIM
603  * This must be done after one full pass through the PCI tree to collect
604  * all BIOS-configured resources, so that we know what resources are
605  * free and available to assign to the unconfigured PPBs.
606  */
607 static void
608 fix_ppb_res(uchar_t secbus, boolean_t prog_sub)
609 {
610 	uchar_t bus, dev, func;
611 	uchar_t parbus, subbus;
612 	uint_t io_base, io_limit, mem_base, mem_limit;
613 	uint_t io_size, mem_size;
614 	uint64_t addr = 0;
615 	int *regp = NULL;
616 	uint_t reglen;
617 	int rv, cap_ptr, physhi;
618 	dev_info_t *dip;
619 	uint16_t cmd_reg;
620 	struct memlist *list;
621 
622 	/* skip root (peer) PCI busses */
623 	if (pci_bus_res[secbus].par_bus == (uchar_t)-1)
624 		return;
625 
626 	/* skip subtractive PPB when prog_sub is not TRUE */
627 	if (pci_bus_res[secbus].subtractive && !prog_sub)
628 		return;
629 
630 	/* some entries may be empty due to discontiguous bus numbering */
631 	dip = pci_bus_res[secbus].dip;
632 	if (dip == NULL)
633 		return;
634 
635 	rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
636 	    "reg", &regp, &reglen);
637 	ASSERT(rv == DDI_PROP_SUCCESS && reglen > 0);
638 	physhi = regp[0];
639 	ddi_prop_free(regp);
640 
641 	func = (uchar_t)PCI_REG_FUNC_G(physhi);
642 	dev = (uchar_t)PCI_REG_DEV_G(physhi);
643 	bus = (uchar_t)PCI_REG_BUS_G(physhi);
644 
645 	/*
646 	 * If pcie bridge, check to see if link is enabled
647 	 */
648 	cap_ptr = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
649 	    "pcie-capid-pointer", PCI_CAP_NEXT_PTR_NULL);
650 	if (cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
651 		cmd_reg = pci_getw(bus, dev, func,
652 		    (uint16_t)cap_ptr + PCIE_LINKCTL);
653 		if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) {
654 			dcmn_err(CE_NOTE,
655 			    "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n",
656 			    bus, dev, func);
657 			return;
658 		}
659 	}
660 
661 	subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
662 	parbus = pci_bus_res[secbus].par_bus;
663 	ASSERT(parbus == bus);
664 	cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM);
665 
666 	/*
667 	 * If we have a Cardbus bridge, but no bus space
668 	 */
669 	if (pci_bus_res[secbus].num_cbb != 0 &&
670 	    pci_bus_res[secbus].bus_space == NULL) {
671 		uchar_t range;
672 
673 		/* normally there are 2 buses under a cardbus bridge */
674 		range = pci_bus_res[secbus].num_cbb * 2;
675 
676 		/*
677 		 * Try to find and allocate a bus-range starting at subbus+1
678 		 * from the parent of the PPB.
679 		 */
680 		for (; range != 0; range--) {
681 			if (memlist_find_with_startaddr(
682 			    &pci_bus_res[parbus].bus_space,
683 			    subbus + 1, range, 1) != NULL)
684 				break; /* find bus range resource at parent */
685 		}
686 		if (range != 0) {
687 			memlist_insert(&pci_bus_res[secbus].bus_space,
688 			    subbus + 1, range);
689 			subbus = subbus + range;
690 			pci_bus_res[secbus].sub_bus = subbus;
691 			pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus);
692 			add_bus_range_prop(secbus);
693 
694 			cmn_err(CE_NOTE, "!reprogram bus-range on ppb"
695 			    "[%x/%x/%x]: %x ~ %x\n", bus, dev, func,
696 			    secbus, subbus);
697 		}
698 	}
699 
700 	/*
701 	 * Calculate required IO size
702 	 * We are going to assign 512 bytes per bus. The size needs to be
703 	 * 4K aligned and the maximum size is 16K.
704 	 */
705 	io_size = (subbus - secbus + 1) * 0x200;
706 	io_size = (io_size + PPB_IO_ALIGNMENT) & (~(PPB_IO_ALIGNMENT - 1));
707 	if (io_size > 0x4 * PPB_IO_ALIGNMENT)
708 		io_size = 0x4 * PPB_IO_ALIGNMENT;
709 	/*
710 	 * Calculate required MEM size
711 	 * We are going to assign 1M bytes per bus. The size needs to be
712 	 * 1M aligned and the maximum size is 8M.
713 	 */
714 	mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT;
715 	if (mem_size > 0x8 * PPB_MEM_ALIGNMENT)
716 		mem_size = 0x8 * PPB_MEM_ALIGNMENT;
717 
718 	/* Subtractive bridge */
719 	if (pci_bus_res[secbus].subtractive && prog_sub) {
720 		/*
721 		 * We program an arbitrary amount of I/O and memory resource
722 		 * for the subtractive bridge so that child dynamic-resource-
723 		 * allocating devices (such as Cardbus bridges) have a chance
724 		 * of success.  Until we have full-tree resource rebalancing,
725 		 * dynamic resource allocation (thru busra) only looks at the
726 		 * parent bridge, so all PPBs must have some allocatable
727 		 * resource.  For non-subtractive bridges, the resources come
728 		 * from the base/limit register "windows", but subtractive
729 		 * bridges often don't program those (since they don't need to).
730 		 * If we put all the remaining resources on the subtractive
731 		 * bridge, then peer non-subtractive bridges can't allocate
732 		 * more space (even though this is probably most correct).
733 		 * If we put the resources only on the parent, then allocations
734 		 * from children of subtractive bridges will fail without
735 		 * special-case code for bypassing the subtractive bridge.
736 		 * This solution is the middle-ground temporary solution until
737 		 * we have fully-capable resource allocation.
738 		 */
739 
740 		/*
741 		 * Add an arbitrary I/O resource to the subtractive PPB
742 		 */
743 		if (pci_bus_res[secbus].io_ports == NULL) {
744 			addr = get_parbus_io_res(parbus, secbus, io_size,
745 			    PPB_IO_ALIGNMENT);
746 			if (addr) {
747 				add_ppb_ranges_prop(secbus);
748 				pci_bus_res[secbus].io_reprogram =
749 				    pci_bus_res[parbus].io_reprogram;
750 
751 				cmn_err(CE_NOTE, "!add io-range on subtractive"
752 				    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
753 				    bus, dev, func, (uint32_t)addr,
754 				    (uint32_t)addr + io_size - 1);
755 			}
756 		}
757 		/*
758 		 * Add an arbitrary memory resource to the subtractive PPB
759 		 */
760 		if (pci_bus_res[secbus].mem_space == NULL) {
761 			addr = get_parbus_mem_res(parbus, secbus, mem_size,
762 			    PPB_MEM_ALIGNMENT);
763 			if (addr) {
764 				add_ppb_ranges_prop(secbus);
765 				pci_bus_res[secbus].mem_reprogram =
766 				    pci_bus_res[parbus].mem_reprogram;
767 
768 				cmn_err(CE_NOTE, "!add mem-range on "
769 				    "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
770 				    bus, dev, func, (uint32_t)addr,
771 				    (uint32_t)addr + mem_size - 1);
772 			}
773 		}
774 
775 		goto cmd_enable;
776 	}
777 
778 	/*
779 	 * Check to see if we need to reprogram I/O space, either because the
780 	 * parent bus needed reprogramming and so do we, or because I/O space is
781 	 * disabled in base/limit or command register.
782 	 */
783 	io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
784 	io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
785 	io_base = (io_base & 0xf0) << 8;
786 	io_limit = ((io_limit & 0xf0) << 8) | 0xfff;
787 
788 	if (pci_bus_res[parbus].io_reprogram || (io_base > io_limit) ||
789 	    (!(cmd_reg & PCI_COMM_IO))) {
790 		if (pci_bus_res[secbus].io_ports_used) {
791 			memlist_merge(&pci_bus_res[secbus].io_ports_used,
792 			    &pci_bus_res[secbus].io_ports);
793 		}
794 		if (pci_bus_res[secbus].io_ports &&
795 		    (!pci_bus_res[parbus].io_reprogram) &&
796 		    (!pci_bus_res[parbus].subtractive)) {
797 			/* rechoose old io ports info */
798 			list = pci_bus_res[secbus].io_ports;
799 			io_base = (uint_t)list->address;
800 			/* 4K aligned */
801 			io_base = io_base & (~(PPB_IO_ALIGNMENT - 1));
802 			io_limit = (uint_t)(list->address + list->size);
803 			while (list->next) {
804 				list = list->next;
805 				if ((list->address + list->size) > io_limit)
806 					io_limit = (uint_t)
807 					    (list->address + list->size);
808 			}
809 			io_limit = io_limit - 1;
810 			/* 4K aligned */
811 			io_limit = (io_limit + PPB_IO_ALIGNMENT) &
812 			    (~(PPB_IO_ALIGNMENT - 1));
813 			io_size = io_limit - io_base;
814 			io_limit = io_limit - 1;
815 			ASSERT(io_base <= io_limit);
816 			memlist_free_all(&pci_bus_res[secbus].io_ports);
817 			memlist_insert(&pci_bus_res[secbus].io_ports,
818 			    io_base, io_size);
819 			memlist_insert(&pci_bus_res[parbus].io_ports_used,
820 			    io_base, io_size);
821 			if (pci_bus_res[parbus].io_ports)
822 				(void) memlist_remove(
823 				    &pci_bus_res[parbus].io_ports,
824 				    io_base, io_size);
825 			pci_bus_res[secbus].io_reprogram = B_TRUE;
826 		} else {
827 			/* get new io ports from parent bus */
828 			addr = get_parbus_io_res(parbus, secbus, io_size,
829 			    PPB_IO_ALIGNMENT);
830 			if (addr) {
831 				io_base = addr;
832 				io_limit = addr + io_size - 1;
833 				pci_bus_res[secbus].io_reprogram = B_TRUE;
834 			}
835 		}
836 		if (pci_bus_res[secbus].io_reprogram) {
837 			/* reprogram PPB regs */
838 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
839 			    (uchar_t)((io_base>>8) & 0xf0));
840 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
841 			    (uchar_t)((io_limit>>8) & 0xf0));
842 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
843 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
844 			add_ppb_ranges_prop(secbus);
845 
846 			cmn_err(CE_NOTE, "!reprogram io-range on"
847 			    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
848 			    bus, dev, func, io_base, io_limit);
849 		}
850 	}
851 
852 	/*
853 	 * Check memory space as we did I/O space.
854 	 */
855 	mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
856 	mem_base = (mem_base & 0xfff0) << 16;
857 	mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
858 	mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff;
859 
860 	if (pci_bus_res[parbus].mem_reprogram || (mem_base > mem_limit) ||
861 	    (!(cmd_reg & PCI_COMM_MAE))) {
862 		if (pci_bus_res[secbus].mem_space_used) {
863 			memlist_merge(&pci_bus_res[secbus].mem_space_used,
864 			    &pci_bus_res[secbus].mem_space);
865 		}
866 		if (pci_bus_res[secbus].mem_space &&
867 		    (!pci_bus_res[parbus].mem_reprogram) &&
868 		    (!pci_bus_res[parbus].subtractive)) {
869 			/* rechoose old mem resource */
870 			list = pci_bus_res[secbus].mem_space;
871 			mem_base = (uint_t)list->address;
872 			/* 1M aligned */
873 			mem_base = mem_base & (~0xfffff);
874 			mem_limit = (uint_t)(list->address + list->size);
875 			while (list->next) {
876 				list = list->next;
877 				if ((list->address + list->size) > mem_limit)
878 					mem_limit = (uint_t)
879 					    (list->address + list->size);
880 			}
881 			mem_limit = mem_limit - 1;
882 			/* 1M aligned */
883 			mem_limit = (mem_limit + PPB_MEM_ALIGNMENT) &
884 			    (~(PPB_MEM_ALIGNMENT - 1));
885 			mem_size = mem_limit - mem_base;
886 			mem_limit = mem_limit - 1;
887 			ASSERT(mem_base <= mem_limit);
888 			memlist_free_all(&pci_bus_res[secbus].mem_space);
889 			memlist_insert(&pci_bus_res[secbus].mem_space,
890 			    mem_base, mem_size);
891 			memlist_insert(&pci_bus_res[parbus].mem_space_used,
892 			    mem_base, mem_size);
893 			if (pci_bus_res[parbus].mem_space)
894 				(void) memlist_remove(
895 				    &pci_bus_res[parbus].mem_space,
896 				    mem_base, mem_size);
897 			pci_bus_res[secbus].mem_reprogram = B_TRUE;
898 		} else {
899 			/* get new mem resource from parent bus */
900 			addr = get_parbus_mem_res(parbus, secbus, mem_size,
901 			    PPB_MEM_ALIGNMENT);
902 			if (addr) {
903 				mem_base = addr;
904 				mem_limit = addr + mem_size - 1;
905 				pci_bus_res[secbus].mem_reprogram = B_TRUE;
906 			}
907 		}
908 
909 		if (pci_bus_res[secbus].mem_reprogram) {
910 			/* reprogram PPB regs */
911 			pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE,
912 			    (uint16_t)((mem_base>>16) & 0xfff0));
913 			pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT,
914 			    (uint16_t)((mem_limit>>16) & 0xfff0));
915 			add_ppb_ranges_prop(secbus);
916 
917 			cmn_err(CE_NOTE, "!reprogram mem-range on"
918 			    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
919 			    bus, dev, func, mem_base, mem_limit);
920 		}
921 	}
922 
923 cmd_enable:
924 	if (pci_bus_res[secbus].io_ports)
925 		cmd_reg |= PCI_COMM_IO | PCI_COMM_ME;
926 	if (pci_bus_res[secbus].mem_space)
927 		cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME;
928 	pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg);
929 }
930 
931 void
932 pci_reprogram(void)
933 {
934 	int i, pci_reconfig = 1;
935 	char *onoff;
936 
937 	/*
938 	 * Excise phantom roots if possible
939 	 */
940 	pci_renumber_root_busses();
941 
942 	/* add bus-range property for root/peer bus nodes */
943 	for (i = 0; i <= pci_bios_nbus; i++) {
944 		if (pci_bus_res[i].par_bus == (uchar_t)-1) {
945 			uchar_t subbus;
946 			if (pci_root_subbus(i, &subbus) == AE_OK)
947 				pci_bus_res[i].sub_bus = subbus;
948 			add_bus_range_prop(i);
949 		}
950 		/* setup bus range resource on each bus */
951 		setup_bus_res(i);
952 	}
953 
954 	if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(),
955 	    DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) {
956 		if (strcmp(onoff, "off") == 0) {
957 			pci_reconfig = 0;
958 			cmn_err(CE_NOTE, "pci device reprogramming disabled");
959 		}
960 		ddi_prop_free(onoff);
961 	}
962 
963 	/* remove used-resources from PCI resource maps */
964 	remove_used_resources();
965 	remove_subtractive_res();
966 
967 	/* reprogram the non-subtractive PPB */
968 	if (pci_reconfig)
969 		for (i = 0; i <= pci_bios_nbus; i++)
970 			fix_ppb_res(i, B_FALSE);
971 
972 	for (i = 0; i <= pci_bios_nbus; i++) {
973 		/* configure devices not configured by BIOS */
974 		if (pci_reconfig) {
975 			/*
976 			 * Reprogram the subtractive PPB. At this time, all its
977 			 * siblings should have got their resources already.
978 			 */
979 			if (pci_bus_res[i].subtractive)
980 				fix_ppb_res(i, B_TRUE);
981 			enumerate_bus_devs(i, CONFIG_NEW);
982 		}
983 		/* All dev programmed, so we can create available prop */
984 		add_bus_available_prop(i);
985 	}
986 }
987 
988 /*
989  * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0...
990  */
991 static void
992 create_root_bus_dip(uchar_t bus)
993 {
994 	int pci_regs[] = {0, 0, 0};
995 	dev_info_t *dip;
996 
997 	ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1);
998 
999 	num_root_bus++;
1000 	ndi_devi_alloc_sleep(ddi_root_node(), "pci",
1001 	    (pnode_t)DEVI_SID_NODEID, &dip);
1002 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1003 	    "#address-cells", 3);
1004 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1005 	    "#size-cells", 2);
1006 	pci_regs[0] = pci_bus_res[bus].root_addr;
1007 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1008 	    "reg", (int *)pci_regs, 3);
1009 
1010 	/*
1011 	 * If system has PCIe bus, then create different properties
1012 	 */
1013 	if (create_pcie_root_bus(bus, dip) == B_FALSE)
1014 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1015 		    "device_type", "pci");
1016 
1017 	(void) ndi_devi_bind_driver(dip, 0);
1018 	pci_bus_res[bus].dip = dip;
1019 	pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE);
1020 	pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE);
1021 	pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE);
1022 
1023 	if (bus != 0)
1024 		return;
1025 
1026 	/*
1027 	 * Special treatment of bus 0:
1028 	 * If no resource from MPSPEC/HRT, copy pcimem from boot
1029 	 * and make I/O space the entire range starting at 0x100. There
1030 	 * is no difference between prefetchable memory or not.
1031 	 */
1032 	if (pci_bus_res[0].mem_space == NULL)
1033 		pci_bus_res[0].mem_space =
1034 		    memlist_dup(bootops->boot_mem->pcimem);
1035 	/* Exclude 0x00 to 0xff of the I/O space, used by all PCs */
1036 	if (pci_bus_res[0].io_ports == NULL)
1037 		memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xffff);
1038 }
1039 
1040 /*
1041  * For any fixed configuration (often compatability) pci devices
1042  * and those with their own expansion rom, create device nodes
1043  * to hold the already configured device details.
1044  */
1045 void
1046 enumerate_bus_devs(uchar_t bus, int config_op)
1047 {
1048 	uchar_t dev, func, nfunc, header;
1049 	ushort_t venid;
1050 	struct pci_devfunc *devlist = NULL, *entry;
1051 
1052 	if (config_op == CONFIG_NEW) {
1053 		dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus);
1054 	} else if (config_op == CONFIG_FIX) {
1055 		dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus);
1056 	} else
1057 		dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus);
1058 
1059 	for (dev = 0; dev < max_dev_pci; dev++) {
1060 		nfunc = 1;
1061 		for (func = 0; func < nfunc; func++) {
1062 
1063 			dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x",
1064 			    dev, func);
1065 
1066 			venid = pci_getw(bus, dev, func, PCI_CONF_VENID);
1067 
1068 			if ((venid == 0xffff) || (venid == 0)) {
1069 				/* no function at this address */
1070 				continue;
1071 			}
1072 
1073 			header = pci_getb(bus, dev, func, PCI_CONF_HEADER);
1074 			if (header == 0xff) {
1075 				continue; /* illegal value */
1076 			}
1077 
1078 			/*
1079 			 * according to some mail from Microsoft posted
1080 			 * to the pci-drivers alias, their only requirement
1081 			 * for a multifunction device is for the 1st
1082 			 * function to have to PCI_HEADER_MULTI bit set.
1083 			 */
1084 			if ((func == 0) && (header & PCI_HEADER_MULTI)) {
1085 				nfunc = 8;
1086 			}
1087 
1088 			if (config_op == CONFIG_FIX ||
1089 			    config_op == CONFIG_INFO) {
1090 				/*
1091 				 * Create the node, unconditionally, on the
1092 				 * first pass only.  It may still need
1093 				 * resource assignment, which will be
1094 				 * done on the second, CONFIG_NEW, pass.
1095 				 */
1096 				process_devfunc(bus, dev, func, header,
1097 				    venid, config_op);
1098 
1099 			}
1100 		}
1101 	}
1102 
1103 	if (config_op == CONFIG_NEW) {
1104 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
1105 		while (devlist) {
1106 			entry = devlist;
1107 			devlist = entry->next;
1108 			if (entry->reprogram ||
1109 			    pci_bus_res[bus].io_reprogram ||
1110 			    pci_bus_res[bus].mem_reprogram) {
1111 				/* reprogram device(s) */
1112 				(void) add_reg_props(entry->dip, bus,
1113 				    entry->dev, entry->func, CONFIG_NEW, 0);
1114 			}
1115 			kmem_free(entry, sizeof (*entry));
1116 		}
1117 		pci_bus_res[bus].privdata = NULL;
1118 	}
1119 }
1120 
1121 static int
1122 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid,
1123     ushort_t subvenid, ushort_t subdevid)
1124 {
1125 	static int prop_exist = -1;
1126 	static char *pciide_str;
1127 	char compat[32];
1128 
1129 	if (prop_exist == -1) {
1130 		prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY,
1131 		    ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide",
1132 		    &pciide_str) == DDI_SUCCESS);
1133 	}
1134 
1135 	if (!prop_exist)
1136 		return (0);
1137 
1138 	/* compare property value against various forms of compatible */
1139 	if (subvenid) {
1140 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x",
1141 		    venid, devid, subvenid, subdevid, revid);
1142 		if (strcmp(pciide_str, compat) == 0)
1143 			return (1);
1144 
1145 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x",
1146 		    venid, devid, subvenid, subdevid);
1147 		if (strcmp(pciide_str, compat) == 0)
1148 			return (1);
1149 
1150 		(void) snprintf(compat, sizeof (compat), "pci%x,%x",
1151 		    subvenid, subdevid);
1152 		if (strcmp(pciide_str, compat) == 0)
1153 			return (1);
1154 	}
1155 	(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x",
1156 	    venid, devid, revid);
1157 	if (strcmp(pciide_str, compat) == 0)
1158 		return (1);
1159 
1160 	(void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid);
1161 	if (strcmp(pciide_str, compat) == 0)
1162 		return (1);
1163 
1164 	return (0);
1165 }
1166 
1167 static int
1168 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid,
1169     ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid)
1170 {
1171 	struct ide_table {	/* table for PCI_MASS_OTHER */
1172 		ushort_t venid;
1173 		ushort_t devid;
1174 	} *entry;
1175 
1176 	/* XXX SATA and other devices: need a way to add dynamically */
1177 	static struct ide_table ide_other[] = {
1178 		{0x1095, 0x3112},
1179 		{0x1095, 0x3114},
1180 		{0x1095, 0x3512},
1181 		{0x1283, 0x8211},	/* ITE 8211F is subcl PCI_MASS_OTHER */
1182 		{0, 0}
1183 	};
1184 
1185 	if (basecl != PCI_CLASS_MASS)
1186 		return (0);
1187 
1188 	if (subcl == PCI_MASS_IDE) {
1189 		return (1);
1190 	}
1191 
1192 	if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) {
1193 		return (0);
1194 	}
1195 
1196 	entry = &ide_other[0];
1197 	while (entry->venid) {
1198 		if (entry->venid == venid && entry->devid == devid)
1199 			return (1);
1200 		entry++;
1201 	}
1202 	return (check_pciide_prop(revid, venid, devid, subvenid, subdevid));
1203 }
1204 
1205 static int
1206 is_display(uint_t classcode)
1207 {
1208 	static uint_t disp_classes[] = {
1209 		0x000100,
1210 		0x030000,
1211 		0x030001
1212 	};
1213 	int i, nclasses = sizeof (disp_classes) / sizeof (uint_t);
1214 
1215 	for (i = 0; i < nclasses; i++) {
1216 		if (classcode == disp_classes[i])
1217 			return (1);
1218 	}
1219 	return (0);
1220 }
1221 
1222 static void
1223 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn,
1224     void (*undofn)(uint8_t, uint8_t, uint8_t))
1225 {
1226 	struct pci_fixundo *newundo;
1227 
1228 	newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP);
1229 
1230 	/*
1231 	 * Adding an item to this list means that we must turn its NMIENABLE
1232 	 * bit back on at a later time.
1233 	 */
1234 	newundo->bus = bus;
1235 	newundo->dev = dev;
1236 	newundo->fn = fn;
1237 	newundo->undofn = undofn;
1238 	newundo->next = undolist;
1239 
1240 	/* add to the undo list in LIFO order */
1241 	undolist = newundo;
1242 }
1243 
1244 void
1245 add_pci_fixes(void)
1246 {
1247 	int i;
1248 
1249 	for (i = 0; i <= pci_bios_nbus; i++) {
1250 		/*
1251 		 * For each bus, apply needed fixes to the appropriate devices.
1252 		 * This must be done before the main enumeration loop because
1253 		 * some fixes must be applied to devices normally encountered
1254 		 * later in the pci scan (e.g. if a fix to device 7 must be
1255 		 * applied before scanning device 6, applying fixes in the
1256 		 * normal enumeration loop would obviously be too late).
1257 		 */
1258 		enumerate_bus_devs(i, CONFIG_FIX);
1259 	}
1260 }
1261 
1262 void
1263 undo_pci_fixes(void)
1264 {
1265 	struct pci_fixundo *nextundo;
1266 	uint8_t bus, dev, fn;
1267 
1268 	/*
1269 	 * All fixes in the undo list are performed unconditionally.  Future
1270 	 * fixes may require selective undo.
1271 	 */
1272 	while (undolist != NULL) {
1273 
1274 		bus = undolist->bus;
1275 		dev = undolist->dev;
1276 		fn = undolist->fn;
1277 
1278 		(*(undolist->undofn))(bus, dev, fn);
1279 
1280 		nextundo = undolist->next;
1281 		kmem_free(undolist, sizeof (struct pci_fixundo));
1282 		undolist = nextundo;
1283 	}
1284 }
1285 
1286 static void
1287 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn)
1288 {
1289 	uint8_t val8;
1290 
1291 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1292 	/*
1293 	 * The NMIONERR bit is turned back on to allow the SMM BIOS
1294 	 * to handle more critical PCI errors (e.g. PERR#).
1295 	 */
1296 	val8 |= AMD8111_ENABLENMI;
1297 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1298 }
1299 
1300 static void
1301 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn)
1302 {
1303 	uint8_t val8;
1304 
1305 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1306 
1307 	if ((val8 & AMD8111_ENABLENMI) == 0)
1308 		return;
1309 
1310 	/*
1311 	 * We reset NMIONERR in the LPC because master-abort on the PCI
1312 	 * bridge side of the 8111 will cause NMI, which might cause SMI,
1313 	 * which sometimes prevents all devices from being enumerated.
1314 	 */
1315 	val8 &= ~AMD8111_ENABLENMI;
1316 
1317 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1318 
1319 	add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix);
1320 }
1321 
1322 static void
1323 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func)
1324 {
1325 	uint16_t status;
1326 	uint8_t header;
1327 	uint8_t cap_ptr;
1328 	uint8_t cap_id;
1329 	uint16_t pmcsr;
1330 
1331 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
1332 	if (!(status & PCI_STAT_CAP))
1333 		return;	/* No capabilities list */
1334 
1335 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
1336 	if (header == PCI_HEADER_CARDBUS)
1337 		cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_RESERVED1);
1338 	else
1339 		cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
1340 	/*
1341 	 * Walk the capabilities list searching for a PM entry.
1342 	 */
1343 	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) {
1344 		cap_ptr &= PCI_CAP_PTR_MASK;
1345 		cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID);
1346 		if (cap_id == PCI_CAP_ID_PM) {
1347 			pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR);
1348 			pmcsr &= ~(PCI_PMCSR_STATE_MASK);
1349 			pmcsr |= PCI_PMCSR_D0; /* D0 state */
1350 			pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr);
1351 			break;
1352 		}
1353 		cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR);
1354 	}
1355 
1356 }
1357 
1358 static void
1359 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header,
1360     ushort_t vendorid, int config_op)
1361 {
1362 	char nodename[32], unitaddr[5];
1363 	dev_info_t *dip;
1364 	uchar_t basecl, subcl, progcl, intr, revid;
1365 	ushort_t subvenid, subdevid, status;
1366 	ushort_t slot_num;
1367 	uint_t classcode, revclass;
1368 	int reprogram = 0, pciide = 0;
1369 	int power[2] = {1, 1};
1370 	int pciex = 0;
1371 	ushort_t is_pci_bridge = 0;
1372 	struct pci_devfunc *devlist = NULL, *entry = NULL;
1373 
1374 	ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID);
1375 
1376 	switch (header & PCI_HEADER_TYPE_M) {
1377 	case PCI_HEADER_ZERO:
1378 		subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID);
1379 		subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID);
1380 		break;
1381 	case PCI_HEADER_CARDBUS:
1382 		subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID);
1383 		subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID);
1384 		/* Record the # of cardbus bridges found on the bus */
1385 		if (config_op == CONFIG_INFO)
1386 			pci_bus_res[bus].num_cbb++;
1387 		break;
1388 	default:
1389 		subvenid = 0;
1390 		subdevid = 0;
1391 		break;
1392 	}
1393 
1394 	if (config_op == CONFIG_FIX) {
1395 		if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) {
1396 			pci_fix_amd8111(bus, dev, func);
1397 		}
1398 		return;
1399 	}
1400 
1401 	/* XXX should be use generic names? derive from class? */
1402 	revclass = pci_getl(bus, dev, func, PCI_CONF_REVID);
1403 	classcode = revclass >> 8;
1404 	revid = revclass & 0xff;
1405 
1406 	/* figure out if this is pci-ide */
1407 	basecl = classcode >> 16;
1408 	subcl = (classcode >> 8) & 0xff;
1409 	progcl = classcode & 0xff;
1410 
1411 
1412 	if (is_display(classcode))
1413 		(void) snprintf(nodename, sizeof (nodename), "display");
1414 	else if (subvenid != 0)
1415 		(void) snprintf(nodename, sizeof (nodename),
1416 		    "pci%x,%x", subvenid, subdevid);
1417 	else
1418 		(void) snprintf(nodename, sizeof (nodename),
1419 		    "pci%x,%x", vendorid, deviceid);
1420 
1421 	/* make sure parent bus dip has been created */
1422 	if (pci_bus_res[bus].dip == NULL) {
1423 		create_root_bus_dip(bus);
1424 	}
1425 
1426 	ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename,
1427 	    DEVI_SID_NODEID, &dip);
1428 
1429 	if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num,
1430 	    &is_pci_bridge) == B_TRUE)
1431 		pciex = 1;
1432 
1433 	/* add properties */
1434 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid);
1435 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid);
1436 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid);
1437 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1438 	    "class-code", classcode);
1439 	if (func == 0)
1440 		(void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev);
1441 	else
1442 		(void) snprintf(unitaddr, sizeof (unitaddr),
1443 		    "%x,%x", dev, func);
1444 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1445 	    "unit-address", unitaddr);
1446 
1447 	/* add device_type for display nodes */
1448 	if (is_display(classcode)) {
1449 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1450 		    "device_type", "display");
1451 	}
1452 	/* add special stuff for header type */
1453 	if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) {
1454 		uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G);
1455 		uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L);
1456 
1457 		if (subvenid != 0) {
1458 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1459 			    "subsystem-id", subdevid);
1460 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1461 			    "subsystem-vendor-id", subvenid);
1462 		}
1463 		if (!pciex)
1464 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1465 			    "min-grant", mingrant);
1466 		if (!pciex)
1467 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1468 			    "max-latency", maxlatency);
1469 	}
1470 
1471 	/* interrupt, record if not 0 */
1472 	intr = pci_getb(bus, dev, func, PCI_CONF_IPIN);
1473 	if (intr != 0)
1474 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1475 		    "interrupts", intr);
1476 
1477 	/*
1478 	 * Add support for 133 mhz pci eventually
1479 	 */
1480 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
1481 
1482 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1483 	    "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9);
1484 	if (!pciex && (status & PCI_STAT_FBBC))
1485 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
1486 		    "fast-back-to-back");
1487 	if (!pciex && (status & PCI_STAT_66MHZ))
1488 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
1489 		    "66mhz-capable");
1490 	if (status & PCI_STAT_UDF)
1491 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
1492 		    "udf-supported");
1493 	if (pciex && slot_num) {
1494 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1495 		    "physical-slot#", slot_num);
1496 		if (!is_pci_bridge)
1497 			pciex_slot_names_prop(dip, slot_num);
1498 	}
1499 
1500 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1501 	    "power-consumption", power, 2);
1502 
1503 	/* Set the device PM state to D0 */
1504 	set_devpm_d0(bus, dev, func);
1505 
1506 	if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI))
1507 		add_ppb_props(dip, bus, dev, func, pciex);
1508 	else {
1509 		/*
1510 		 * Record the non-PPB devices on the bus for possible
1511 		 * reprogramming at 2nd bus enumeration.
1512 		 * Note: PPB reprogramming is done in fix_ppb_res()
1513 		 */
1514 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
1515 		entry = kmem_zalloc(sizeof (*entry), KM_SLEEP);
1516 		entry->dip = dip;
1517 		entry->dev = dev;
1518 		entry->func = func;
1519 		entry->next = devlist;
1520 		pci_bus_res[bus].privdata = entry;
1521 	}
1522 
1523 	if (config_op == CONFIG_INFO &&
1524 	    IS_CLASS_IOAPIC(basecl, subcl, progcl)) {
1525 		create_ioapic_node(bus, dev, func, vendorid, deviceid);
1526 	}
1527 
1528 	/* check for ck8-04 based PCI ISA bridge only */
1529 	if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) &&
1530 	    (func == 0))
1531 		add_nvidia_isa_bridge_props(dip, bus, dev, func);
1532 
1533 	if (pciex && is_pci_bridge)
1534 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
1535 		    (char *)"PCIe-PCI bridge");
1536 	else
1537 		add_model_prop(dip, classcode);
1538 
1539 	add_compatible(dip, subvenid, subdevid, vendorid, deviceid,
1540 	    revid, classcode, pciex);
1541 
1542 	/*
1543 	 * See if this device is a controller that advertises
1544 	 * itself to be a standard ATA task file controller, or one that
1545 	 * has been hard coded.
1546 	 *
1547 	 * If it is, check if any other higher precedence driver listed in
1548 	 * driver_aliases will claim the node by calling
1549 	 * ddi_compatibile_driver_major.  If so, clear pciide and do not
1550 	 * create a pci-ide node or any other special handling.
1551 	 *
1552 	 * If another driver does not bind, set the node name to pci-ide
1553 	 * and then let the special pci-ide handling for registers and
1554 	 * child pci-ide nodes proceed below.
1555 	 */
1556 	if (is_pciide(basecl, subcl, revid, vendorid, deviceid,
1557 	    subvenid, subdevid) == 1) {
1558 		if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) {
1559 			(void) ndi_devi_set_nodename(dip, "pci-ide", 0);
1560 			pciide = 1;
1561 		}
1562 	}
1563 
1564 	reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide);
1565 	(void) ndi_devi_bind_driver(dip, 0);
1566 
1567 	/* special handling for pci-ide */
1568 	if (pciide) {
1569 		dev_info_t *cdip;
1570 
1571 		/*
1572 		 * Create properties specified by P1275 Working Group
1573 		 * Proposal #414 Version 1
1574 		 */
1575 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1576 		    "device_type", "pci-ide");
1577 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1578 		    "#address-cells", 1);
1579 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1580 		    "#size-cells", 0);
1581 
1582 		/* allocate two child nodes */
1583 		ndi_devi_alloc_sleep(dip, "ide",
1584 		    (pnode_t)DEVI_SID_NODEID, &cdip);
1585 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
1586 		    "reg", 0);
1587 		(void) ndi_devi_bind_driver(cdip, 0);
1588 		ndi_devi_alloc_sleep(dip, "ide",
1589 		    (pnode_t)DEVI_SID_NODEID, &cdip);
1590 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
1591 		    "reg", 1);
1592 		(void) ndi_devi_bind_driver(cdip, 0);
1593 
1594 		reprogram = 0;	/* don't reprogram pci-ide bridge */
1595 	}
1596 
1597 	if (reprogram && (entry != NULL))
1598 		entry->reprogram = B_TRUE;
1599 }
1600 
1601 /*
1602  * Set the compatible property to a value compliant with
1603  * rev 2.1 of the IEEE1275 PCI binding.
1604  * (Also used for PCI-Express devices).
1605  *
1606  *   pciVVVV,DDDD.SSSS.ssss.RR	(0)
1607  *   pciVVVV,DDDD.SSSS.ssss	(1)
1608  *   pciSSSS,ssss		(2)
1609  *   pciVVVV,DDDD.RR		(3)
1610  *   pciVVVV,DDDD		(4)
1611  *   pciclass,CCSSPP		(5)
1612  *   pciclass,CCSS		(6)
1613  *
1614  * The Subsystem (SSSS) forms are not inserted if
1615  * subsystem-vendor-id is 0.
1616  *
1617  * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above
1618  * property 2 is not created as per "1275 bindings for PCI Express Interconnect"
1619  *
1620  * Set with setprop and \x00 between each
1621  * to generate the encoded string array form.
1622  */
1623 void
1624 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid,
1625     ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode,
1626     int pciex)
1627 {
1628 	int i = 0;
1629 	int size = COMPAT_BUFSIZE;
1630 	char *compat[13];
1631 	char *buf, *curr;
1632 
1633 	curr = buf = kmem_alloc(size, KM_SLEEP);
1634 
1635 	if (pciex) {
1636 		if (subvenid) {
1637 			compat[i++] = curr;	/* form 0 */
1638 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x",
1639 			    vendorid, deviceid, subvenid, subdevid, revid);
1640 			size -= strlen(curr) + 1;
1641 			curr += strlen(curr) + 1;
1642 
1643 			compat[i++] = curr;	/* form 1 */
1644 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x",
1645 			    vendorid, deviceid, subvenid, subdevid);
1646 			size -= strlen(curr) + 1;
1647 			curr += strlen(curr) + 1;
1648 
1649 		}
1650 		compat[i++] = curr;	/* form 3 */
1651 		(void) snprintf(curr, size, "pciex%x,%x.%x",
1652 		    vendorid, deviceid, revid);
1653 		size -= strlen(curr) + 1;
1654 		curr += strlen(curr) + 1;
1655 
1656 		compat[i++] = curr;	/* form 4 */
1657 		(void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid);
1658 		size -= strlen(curr) + 1;
1659 		curr += strlen(curr) + 1;
1660 
1661 		compat[i++] = curr;	/* form 5 */
1662 		(void) snprintf(curr, size, "pciexclass,%06x", classcode);
1663 		size -= strlen(curr) + 1;
1664 		curr += strlen(curr) + 1;
1665 
1666 		compat[i++] = curr;	/* form 6 */
1667 		(void) snprintf(curr, size, "pciexclass,%04x",
1668 		    (classcode >> 8));
1669 		size -= strlen(curr) + 1;
1670 		curr += strlen(curr) + 1;
1671 	}
1672 
1673 	if (subvenid) {
1674 		compat[i++] = curr;	/* form 0 */
1675 		(void) snprintf(curr, size, "pci%x,%x.%x.%x.%x",
1676 		    vendorid, deviceid, subvenid, subdevid, revid);
1677 		size -= strlen(curr) + 1;
1678 		curr += strlen(curr) + 1;
1679 
1680 		compat[i++] = curr;	/* form 1 */
1681 		(void) snprintf(curr, size, "pci%x,%x.%x.%x",
1682 		    vendorid, deviceid, subvenid, subdevid);
1683 		size -= strlen(curr) + 1;
1684 		curr += strlen(curr) + 1;
1685 
1686 		compat[i++] = curr;	/* form 2 */
1687 		(void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid);
1688 		size -= strlen(curr) + 1;
1689 		curr += strlen(curr) + 1;
1690 	}
1691 	compat[i++] = curr;	/* form 3 */
1692 	(void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid);
1693 	size -= strlen(curr) + 1;
1694 	curr += strlen(curr) + 1;
1695 
1696 	compat[i++] = curr;	/* form 4 */
1697 	(void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid);
1698 	size -= strlen(curr) + 1;
1699 	curr += strlen(curr) + 1;
1700 
1701 	compat[i++] = curr;	/* form 5 */
1702 	(void) snprintf(curr, size, "pciclass,%06x", classcode);
1703 	size -= strlen(curr) + 1;
1704 	curr += strlen(curr) + 1;
1705 
1706 	compat[i++] = curr;	/* form 6 */
1707 	(void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8));
1708 	size -= strlen(curr) + 1;
1709 	curr += strlen(curr) + 1;
1710 
1711 	(void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip,
1712 	    "compatible", compat, i);
1713 	kmem_free(buf, COMPAT_BUFSIZE);
1714 }
1715 
1716 /*
1717  * Adjust the reg properties for a dual channel PCI-IDE device.
1718  *
1719  * NOTE: don't do anything that changes the order of the hard-decodes
1720  * and programmed BARs. The kernel driver depends on these values
1721  * being in this order regardless of whether they're for a 'native'
1722  * mode BAR or not.
1723  */
1724 /*
1725  * config info for pci-ide devices
1726  */
1727 static struct {
1728 	uchar_t  native_mask;	/* 0 == 'compatibility' mode, 1 == native */
1729 	uchar_t  bar_offset;	/* offset for alt status register */
1730 	ushort_t addr;		/* compatibility mode base address */
1731 	ushort_t length;	/* number of ports for this BAR */
1732 } pciide_bar[] = {
1733 	{ 0x01, 0, 0x1f0, 8 },	/* primary lower BAR */
1734 	{ 0x01, 2, 0x3f6, 1 },	/* primary upper BAR */
1735 	{ 0x04, 0, 0x170, 8 },	/* secondary lower BAR */
1736 	{ 0x04, 2, 0x376, 1 }	/* secondary upper BAR */
1737 };
1738 
1739 static int
1740 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp)
1741 {
1742 	int hard_decode = 0;
1743 
1744 	/*
1745 	 * Adjust the base and len for the BARs of the PCI-IDE
1746 	 * device's primary and secondary controllers. The first
1747 	 * two BARs are for the primary controller and the next
1748 	 * two BARs are for the secondary controller. The fifth
1749 	 * and sixth bars are never adjusted.
1750 	 */
1751 	if (index >= 0 && index <= 3) {
1752 		*lenp = pciide_bar[index].length;
1753 
1754 		if (progcl & pciide_bar[index].native_mask) {
1755 			*basep += pciide_bar[index].bar_offset;
1756 		} else {
1757 			*basep = pciide_bar[index].addr;
1758 			hard_decode = 1;
1759 		}
1760 	}
1761 
1762 	/*
1763 	 * if either base or len is zero make certain both are zero
1764 	 */
1765 	if (*basep == 0 || *lenp == 0) {
1766 		*basep = 0;
1767 		*lenp = 0;
1768 		hard_decode = 0;
1769 	}
1770 
1771 	return (hard_decode);
1772 }
1773 
1774 
1775 /*
1776  * Add the "reg" and "assigned-addresses" property
1777  */
1778 static int
1779 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
1780     int config_op, int pciide)
1781 {
1782 	uchar_t baseclass, subclass, progclass, header;
1783 	ushort_t bar_sz;
1784 	uint_t value = 0, len, devloc;
1785 	uint_t base, base_hi, type;
1786 	ushort_t offset, end;
1787 	int max_basereg, j, reprogram = 0;
1788 	uint_t phys_hi;
1789 	struct memlist **io_res, **mres, **mem_res, **pmem_res;
1790 	struct memlist **io_res_used, **mres_used;
1791 	struct memlist **mem_res_used, **pmem_res_used;
1792 	uchar_t res_bus;
1793 
1794 	pci_regspec_t regs[16] = {{0}};
1795 	pci_regspec_t assigned[15] = {{0}};
1796 	int nreg, nasgn;
1797 
1798 	io_res = &pci_bus_res[bus].io_ports;
1799 	io_res_used = &pci_bus_res[bus].io_ports_used;
1800 	mem_res = &pci_bus_res[bus].mem_space;
1801 	mem_res_used = &pci_bus_res[bus].mem_space_used;
1802 	if (bus == 0) {	/* for bus 0, there is only mem_space */
1803 		pmem_res = mem_res;
1804 		pmem_res_used = mem_res_used;
1805 	} else {
1806 		pmem_res = &pci_bus_res[bus].pmem_space;
1807 		pmem_res_used = &pci_bus_res[bus].pmem_space_used;
1808 	}
1809 
1810 	devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8;
1811 	regs[0].pci_phys_hi = devloc;
1812 	nreg = 1;	/* rest of regs[0] is all zero */
1813 	nasgn = 0;
1814 
1815 	baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS);
1816 	subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS);
1817 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
1818 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
1819 
1820 	switch (header) {
1821 	case PCI_HEADER_ZERO:
1822 		max_basereg = PCI_BASE_NUM;
1823 		break;
1824 	case PCI_HEADER_PPB:
1825 		max_basereg = PCI_BCNF_BASE_NUM;
1826 		break;
1827 	case PCI_HEADER_CARDBUS:
1828 		max_basereg = PCI_CBUS_BASE_NUM;
1829 		break;
1830 	default:
1831 		max_basereg = 0;
1832 		break;
1833 	}
1834 
1835 	/*
1836 	 * Create the register property by saving the current
1837 	 * value of the base register. Write 0xffffffff to the
1838 	 * base register.  Read the value back to determine the
1839 	 * required size of the address space.  Restore the base
1840 	 * register contents.
1841 	 *
1842 	 * Do not disable I/O and memory access; this isn't necessary
1843 	 * since no driver is yet attached to this device, and disabling
1844 	 * I/O and memory access has the side-effect of disabling PCI-PCI
1845 	 * bridge mappings, which makes the bridge transparent to secondary-
1846 	 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge
1847 	 * Spec V1.2).
1848 	 */
1849 	end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t);
1850 	for (j = 0, offset = PCI_CONF_BASE0; offset < end;
1851 	    j++, offset += bar_sz) {
1852 		int hard_decode = 0;
1853 
1854 		/* determine the size of the address space */
1855 		base = pci_getl(bus, dev, func, offset);
1856 		pci_putl(bus, dev, func, offset, 0xffffffff);
1857 		value = pci_getl(bus, dev, func, offset);
1858 		pci_putl(bus, dev, func, offset, base);
1859 
1860 		/* construct phys hi,med.lo, size hi, lo */
1861 		if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) {
1862 			/* i/o space */
1863 			bar_sz = PCI_BAR_SZ_32;
1864 			value &= PCI_BASE_IO_ADDR_M;
1865 			len = ((value ^ (value-1)) + 1) >> 1;
1866 
1867 			/* XXX Adjust first 4 IDE registers */
1868 			if (pciide) {
1869 				if (subclass != PCI_MASS_IDE)
1870 					progclass = (PCI_IDE_IF_NATIVE_PRI |
1871 					    PCI_IDE_IF_NATIVE_SEC);
1872 				hard_decode = pciIdeAdjustBAR(progclass, j,
1873 				    &base, &len);
1874 			} else if (value == 0) {
1875 				/* skip base regs with size of 0 */
1876 				continue;
1877 			}
1878 
1879 			regs[nreg].pci_size_low =
1880 			    assigned[nasgn].pci_size_low = len;
1881 			if (!hard_decode) {
1882 				regs[nreg].pci_phys_hi =
1883 				    (PCI_ADDR_IO | devloc) + offset;
1884 			} else {
1885 				regs[nreg].pci_phys_hi =
1886 				    (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) +
1887 				    offset;
1888 				regs[nreg].pci_phys_low =
1889 				    base & PCI_BASE_IO_ADDR_M;
1890 			}
1891 			assigned[nasgn].pci_phys_hi =
1892 			    (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset;
1893 			type = base & (~PCI_BASE_IO_ADDR_M);
1894 			base &= PCI_BASE_IO_ADDR_M;
1895 			/*
1896 			 * A device under a subtractive PPB can allocate
1897 			 * resources from its parent bus if there is no resource
1898 			 * available on its own bus.
1899 			 */
1900 			if ((config_op == CONFIG_NEW) && (*io_res == NULL)) {
1901 				res_bus = bus;
1902 				while (pci_bus_res[res_bus].subtractive) {
1903 					res_bus = pci_bus_res[res_bus].par_bus;
1904 					if (res_bus == (uchar_t)-1)
1905 						break; /* root bus already */
1906 					if (pci_bus_res[res_bus].io_ports) {
1907 						io_res = &pci_bus_res
1908 						    [res_bus].io_ports;
1909 						break;
1910 					}
1911 				}
1912 			}
1913 
1914 			/*
1915 			 * first pass - gather what's there
1916 			 * update/second pass - adjust/allocate regions
1917 			 *	config - allocate regions
1918 			 */
1919 			if (config_op == CONFIG_INFO) {	/* first pass */
1920 				/* take out of the resource map of the bus */
1921 				if (base != 0) {
1922 					if (*io_res)
1923 						(void) memlist_remove(io_res,
1924 						    base, len);
1925 					memlist_insert(io_res_used, base, len);
1926 				} else
1927 					reprogram = 1;
1928 			} else if ((*io_res && base == 0) ||
1929 			    pci_bus_res[bus].io_reprogram) {
1930 				base = (uint_t)memlist_find(io_res, len, len);
1931 				if (base != 0) {
1932 					memlist_insert(io_res_used, base, len);
1933 					/* XXX need to worry about 64-bit? */
1934 					pci_putl(bus, dev, func, offset,
1935 					    base | type);
1936 					base = pci_getl(bus, dev, func, offset);
1937 					base &= PCI_BASE_IO_ADDR_M;
1938 				}
1939 				if (base == 0) {
1940 					cmn_err(CE_WARN, "failed to program"
1941 					    " IO space [%d/%d/%d] BAR@0x%x"
1942 					    " length 0x%x",
1943 					    bus, dev, func, offset, len);
1944 				}
1945 			}
1946 			assigned[nasgn].pci_phys_low = base;
1947 			nreg++, nasgn++;
1948 
1949 		} else {
1950 			/* memory space */
1951 			if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) {
1952 				bar_sz = PCI_BAR_SZ_64;
1953 				base_hi = pci_getl(bus, dev, func, offset + 4);
1954 				phys_hi = PCI_ADDR_MEM64;
1955 			} else {
1956 				bar_sz = PCI_BAR_SZ_32;
1957 				base_hi = 0;
1958 				phys_hi = PCI_ADDR_MEM32;
1959 			}
1960 
1961 			/* skip base regs with size of 0 */
1962 			value &= PCI_BASE_M_ADDR_M;
1963 
1964 			if (value == 0) {
1965 				continue;
1966 			}
1967 			len = ((value ^ (value-1)) + 1) >> 1;
1968 			regs[nreg].pci_size_low =
1969 			    assigned[nasgn].pci_size_low = len;
1970 
1971 			phys_hi |= (devloc | offset);
1972 			if (base & PCI_BASE_PREF_M) {
1973 				mres = pmem_res;
1974 				mres_used = pmem_res_used;
1975 				phys_hi |= PCI_PREFETCH_B;
1976 			} else {
1977 				mres = mem_res;
1978 				mres_used = mem_res_used;
1979 			}
1980 			/*
1981 			 * A device under a subtractive PPB can allocate
1982 			 * resources from its parent bus if there is no resource
1983 			 * available on its own bus.
1984 			 */
1985 			if ((config_op == CONFIG_NEW) && (*mres == NULL)) {
1986 				res_bus = bus;
1987 				while (pci_bus_res[res_bus].subtractive) {
1988 					res_bus = pci_bus_res[res_bus].par_bus;
1989 					if (res_bus == (uchar_t)-1)
1990 						break; /* root bus already */
1991 					if ((phys_hi & PCI_PREFETCH_B) &&
1992 					    (res_bus != 0))
1993 						mres = &pci_bus_res
1994 						    [res_bus].pmem_space;
1995 					else
1996 						mres = &pci_bus_res
1997 						    [res_bus].mem_space;
1998 					if (*mres)
1999 						break;
2000 				}
2001 			}
2002 
2003 			regs[nreg].pci_phys_hi =
2004 			    assigned[nasgn].pci_phys_hi = phys_hi;
2005 			assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B;
2006 			assigned[nasgn].pci_phys_mid = base_hi;
2007 			type = base & ~PCI_BASE_M_ADDR_M;
2008 			base &= PCI_BASE_M_ADDR_M;
2009 
2010 			if (config_op == CONFIG_INFO) {
2011 				/* take out of the resource map of the bus */
2012 				if (base != 0) {
2013 					if (*mres)
2014 						(void) memlist_remove(mres,
2015 						    base, len);
2016 					memlist_insert(mres_used, base, len);
2017 				} else
2018 					reprogram = 1;
2019 			} else if ((*mres && base == 0) ||
2020 			    pci_bus_res[bus].mem_reprogram) {
2021 				base = (uint_t)memlist_find(mres, len, len);
2022 				if (base != NULL) {
2023 					memlist_insert(mres_used, base, len);
2024 					pci_putl(bus, dev, func, offset,
2025 					    base | type);
2026 					base = pci_getl(bus, dev, func, offset);
2027 					base &= PCI_BASE_M_ADDR_M;
2028 				}
2029 
2030 				if (base == 0) {
2031 					cmn_err(CE_WARN, "failed to program "
2032 					    "mem space [%d/%d/%d] BAR@0x%x"
2033 					    " length 0x%x",
2034 					    bus, dev, func, offset, len);
2035 				}
2036 			}
2037 			assigned[nasgn].pci_phys_low = base;
2038 			nreg++, nasgn++;
2039 		}
2040 	}
2041 	switch (header) {
2042 	case PCI_HEADER_ZERO:
2043 		offset = PCI_CONF_ROM;
2044 		break;
2045 	case PCI_HEADER_PPB:
2046 		offset = PCI_BCNF_ROM;
2047 		break;
2048 	default: /* including PCI_HEADER_CARDBUS */
2049 		goto done;
2050 	}
2051 
2052 	/*
2053 	 * Add the expansion rom memory space
2054 	 * Determine the size of the ROM base reg; don't write reserved bits
2055 	 * ROM isn't in the PCI memory space.
2056 	 */
2057 	base = pci_getl(bus, dev, func, offset);
2058 	pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M);
2059 	value = pci_getl(bus, dev, func, offset);
2060 	pci_putl(bus, dev, func, offset, base);
2061 	if (value & PCI_BASE_ROM_ENABLE)
2062 		value &= PCI_BASE_ROM_ADDR_M;
2063 	else
2064 		value = 0;
2065 
2066 	if (value != 0) {
2067 		regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset;
2068 		assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B |
2069 		    PCI_ADDR_MEM32 | devloc) + offset;
2070 		base &= PCI_BASE_ROM_ADDR_M;
2071 		assigned[nasgn].pci_phys_low = base;
2072 		len = ((value ^ (value-1)) + 1) >> 1;
2073 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len;
2074 		nreg++, nasgn++;
2075 		/* take it out of the memory resource */
2076 		if (*mem_res && base != 0)
2077 			(void) memlist_remove(mem_res, base, len);
2078 		if (base != 0)
2079 			memlist_insert(mem_res, base, len);
2080 	}
2081 
2082 	/*
2083 	 * The following are ISA resources. There are not part
2084 	 * of the PCI local bus resources. So don't attempt to
2085 	 * do resource accounting against PCI.
2086 	 */
2087 
2088 	/* add the three hard-decode, aliased address spaces for VGA */
2089 	if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) ||
2090 	    (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) {
2091 
2092 		/* VGA hard decode 0x3b0-0x3bb */
2093 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2094 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2095 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0;
2096 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc;
2097 		nreg++, nasgn++;
2098 
2099 		/* VGA hard decode 0x3c0-0x3df */
2100 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2101 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2102 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0;
2103 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20;
2104 		nreg++, nasgn++;
2105 
2106 		/* Video memory */
2107 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2108 		    (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc);
2109 		regs[nreg].pci_phys_low =
2110 		    assigned[nasgn].pci_phys_low = 0xa0000;
2111 		regs[nreg].pci_size_low =
2112 		    assigned[nasgn].pci_size_low = 0x20000;
2113 		nreg++, nasgn++;
2114 	}
2115 
2116 	/* add the hard-decode, aliased address spaces for 8514 */
2117 	if ((baseclass == PCI_CLASS_DISPLAY) &&
2118 	    (subclass == PCI_DISPLAY_VGA) &&
2119 	    (progclass & PCI_DISPLAY_IF_8514)) {
2120 
2121 		/* hard decode 0x2e8 */
2122 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2123 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2124 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8;
2125 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1;
2126 		nreg++, nasgn++;
2127 
2128 		/* hard decode 0x2ea-0x2ef */
2129 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2130 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2131 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea;
2132 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6;
2133 		nreg++, nasgn++;
2134 	}
2135 
2136 done:
2137 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg",
2138 	    (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int));
2139 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
2140 	    "assigned-addresses",
2141 	    (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int));
2142 
2143 	return (reprogram);
2144 }
2145 
2146 static void
2147 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
2148     int pciex)
2149 {
2150 	char *dev_type;
2151 	int i;
2152 	uint_t val, io_range[2], mem_range[2], pmem_range[2];
2153 	uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
2154 	uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
2155 	uchar_t progclass;
2156 
2157 	ASSERT(secbus <= subbus);
2158 
2159 	/*
2160 	 * Check if it's a subtractive PPB.
2161 	 */
2162 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
2163 	if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE)
2164 		pci_bus_res[secbus].subtractive = B_TRUE;
2165 
2166 	/*
2167 	 * Some BIOSes lie about max pci busses, we allow for
2168 	 * such mistakes here
2169 	 */
2170 	if (subbus > pci_bios_nbus) {
2171 		pci_bios_nbus = subbus;
2172 		alloc_res_array();
2173 	}
2174 
2175 	ASSERT(pci_bus_res[secbus].dip == NULL);
2176 	pci_bus_res[secbus].dip = dip;
2177 	pci_bus_res[secbus].par_bus = bus;
2178 
2179 	dev_type = pciex ? "pciex" : "pci";
2180 
2181 	/* setup bus number hierarchy */
2182 	pci_bus_res[secbus].sub_bus = subbus;
2183 	/*
2184 	 * Keep track of the largest subordinate bus number (this is essential
2185 	 * for peer busses because there is no other way of determining its
2186 	 * subordinate bus number).
2187 	 */
2188 	if (subbus > pci_bus_res[bus].sub_bus)
2189 		pci_bus_res[bus].sub_bus = subbus;
2190 	/*
2191 	 * Loop through subordinate busses, initializing their parent bus
2192 	 * field to this bridge's parent.  The subordinate busses' parent
2193 	 * fields may very well be further refined later, as child bridges
2194 	 * are enumerated.  (The value is to note that the subordinate busses
2195 	 * are not peer busses by changing their par_bus fields to anything
2196 	 * other than -1.)
2197 	 */
2198 	for (i = secbus + 1; i <= subbus; i++)
2199 		pci_bus_res[i].par_bus = bus;
2200 
2201 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
2202 	    "device_type", dev_type);
2203 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2204 	    "#address-cells", 3);
2205 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2206 	    "#size-cells", 2);
2207 
2208 	/*
2209 	 * According to PPB spec, the base register should be programmed
2210 	 * with a value bigger than the limit register when there are
2211 	 * no resources available. This applies to io, memory, and
2212 	 * prefetchable memory.
2213 	 */
2214 
2215 	/*
2216 	 * io range
2217 	 * We determine i/o windows that are left unconfigured by BIOS
2218 	 * through its i/o enable bit as Microsoft recommends OEMs to do.
2219 	 * If it is unset, we disable i/o and mark it for reconfiguration in
2220 	 * later passes by setting the base > limit
2221 	 */
2222 	val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM);
2223 	if (val & PCI_COMM_IO) {
2224 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
2225 		io_range[0] = ((val & 0xf0) << 8);
2226 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
2227 		io_range[1]  = ((val & 0xf0) << 8) | 0xFFF;
2228 	} else {
2229 		io_range[0] = 0x9fff;
2230 		io_range[1] = 0x1000;
2231 		pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
2232 		    (uint8_t)((io_range[0] >> 8) & 0xf0));
2233 		pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
2234 		    (uint8_t)((io_range[1] >> 8) & 0xf0));
2235 		pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
2236 		pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
2237 	}
2238 
2239 	if (io_range[0] != 0 && io_range[0] < io_range[1]) {
2240 		memlist_insert(&pci_bus_res[secbus].io_ports,
2241 		    (uint64_t)io_range[0],
2242 		    (uint64_t)(io_range[1] - io_range[0] + 1));
2243 		memlist_insert(&pci_bus_res[bus].io_ports_used,
2244 		    (uint64_t)io_range[0],
2245 		    (uint64_t)(io_range[1] - io_range[0] + 1));
2246 		if (pci_bus_res[bus].io_ports != NULL) {
2247 			(void) memlist_remove(&pci_bus_res[bus].io_ports,
2248 			    (uint64_t)io_range[0],
2249 			    (uint64_t)(io_range[1] - io_range[0] + 1));
2250 		}
2251 		dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x",
2252 		    secbus, io_range[0], io_range[1]);
2253 		/* if 32-bit supported, make sure upper bits are not set */
2254 		if ((val & 0xf) == 1 &&
2255 		    pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) {
2256 			cmn_err(CE_NOTE, "unsupported 32-bit IO address on"
2257 			    " pci-pci bridge [%d/%d/%d]", bus, dev, func);
2258 		}
2259 	}
2260 
2261 	/* mem range */
2262 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
2263 	mem_range[0] = ((val & 0xFFF0) << 16);
2264 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
2265 	mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF;
2266 	if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) {
2267 		memlist_insert(&pci_bus_res[secbus].mem_space,
2268 		    (uint64_t)mem_range[0],
2269 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2270 		memlist_insert(&pci_bus_res[bus].mem_space_used,
2271 		    (uint64_t)mem_range[0],
2272 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2273 		/* remove from parent resouce list */
2274 		if (pci_bus_res[bus].mem_space != NULL) {
2275 			(void) memlist_remove(&pci_bus_res[bus].mem_space,
2276 			    (uint64_t)mem_range[0],
2277 			    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2278 		}
2279 		dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x",
2280 		    secbus, mem_range[0], mem_range[1]);
2281 	}
2282 
2283 	/* prefetchable memory range */
2284 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW);
2285 	pmem_range[0] = ((val & 0xFFF0) << 16);
2286 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW);
2287 	pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF;
2288 	if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) {
2289 		memlist_insert(&pci_bus_res[secbus].pmem_space,
2290 		    (uint64_t)pmem_range[0],
2291 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2292 		memlist_insert(&pci_bus_res[bus].pmem_space_used,
2293 		    (uint64_t)pmem_range[0],
2294 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2295 		if (pci_bus_res[bus].pmem_space != NULL) {
2296 			(void) memlist_remove(&pci_bus_res[bus].pmem_space,
2297 			    (uint64_t)pmem_range[0],
2298 			    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2299 		}
2300 		dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x",
2301 		    secbus, pmem_range[0], pmem_range[1]);
2302 		/* if 64-bit supported, make sure upper bits are not set */
2303 		if ((val & 0xf) == 1 &&
2304 		    pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) {
2305 			cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on"
2306 			    " pci-pci bridge [%d/%d/%d]", bus, dev, func);
2307 		}
2308 	}
2309 
2310 	add_bus_range_prop(secbus);
2311 	add_ppb_ranges_prop(secbus);
2312 }
2313 
2314 extern const struct pci_class_strings_s class_pci[];
2315 extern int class_pci_items;
2316 
2317 static void
2318 add_model_prop(dev_info_t *dip, uint_t classcode)
2319 {
2320 	const char *desc;
2321 	int i;
2322 	uchar_t baseclass = classcode >> 16;
2323 	uchar_t subclass = (classcode >> 8) & 0xff;
2324 	uchar_t progclass = classcode & 0xff;
2325 
2326 	if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) {
2327 		desc = "IDE controller";
2328 	} else {
2329 		for (desc = 0, i = 0; i < class_pci_items; i++) {
2330 			if ((baseclass == class_pci[i].base_class) &&
2331 			    (subclass == class_pci[i].sub_class) &&
2332 			    (progclass == class_pci[i].prog_class)) {
2333 				desc = class_pci[i].actual_desc;
2334 				break;
2335 			}
2336 		}
2337 		if (i == class_pci_items)
2338 			desc = "Unknown class of pci/pnpbios device";
2339 	}
2340 
2341 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
2342 	    (char *)desc);
2343 }
2344 
2345 static void
2346 add_bus_range_prop(int bus)
2347 {
2348 	int bus_range[2];
2349 
2350 	if (pci_bus_res[bus].dip == NULL)
2351 		return;
2352 	bus_range[0] = bus;
2353 	bus_range[1] = pci_bus_res[bus].sub_bus;
2354 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
2355 	    "bus-range", (int *)bus_range, 2);
2356 }
2357 
2358 /*
2359  * Add slot-names property for any named pci hot-plug slots
2360  */
2361 static void
2362 add_bus_slot_names_prop(int bus)
2363 {
2364 	char slotprop[256];
2365 	int len;
2366 
2367 	if (pci_bus_res[bus].dip != NULL) {
2368 		/* simply return if the property is already defined */
2369 		if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip,
2370 		    DDI_PROP_DONTPASS, "slot-names"))
2371 			return;
2372 	}
2373 
2374 	len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop));
2375 	if (len > 0) {
2376 		/*
2377 		 * Only create a peer bus node if this bus may be a peer bus.
2378 		 * It may be a peer bus if the dip is NULL and if par_bus is
2379 		 * -1 (par_bus is -1 if this bus was not found to be
2380 		 * subordinate to any PCI-PCI bridge).
2381 		 * If it's not a peer bus, then the ACPI BBN-handling code
2382 		 * will remove it later.
2383 		 */
2384 		if (pci_bus_res[bus].par_bus == (uchar_t)-1 &&
2385 		    pci_bus_res[bus].dip == NULL) {
2386 
2387 			create_root_bus_dip(bus);
2388 		}
2389 		if (pci_bus_res[bus].dip != NULL) {
2390 			ASSERT((len % sizeof (int)) == 0);
2391 			(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
2392 			    pci_bus_res[bus].dip, "slot-names",
2393 			    (int *)slotprop, len / sizeof (int));
2394 		} else {
2395 			cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI "
2396 			    "IRQ routing table; Not adding slot-names "
2397 			    "property for incorrect bus %d", bus);
2398 		}
2399 	}
2400 }
2401 
2402 static int
2403 memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type)
2404 {
2405 	if (entry == NULL)
2406 		return (0);
2407 
2408 	/* assume 32-bit addresses */
2409 	rp->child_high = rp->parent_high = type;
2410 	rp->child_mid = rp->parent_mid = 0;
2411 	rp->child_low = rp->parent_low = (uint32_t)entry->address;
2412 	rp->size_high = 0;
2413 	rp->size_low = (uint32_t)entry->size;
2414 	return (1);
2415 }
2416 
2417 static void
2418 add_ppb_ranges_prop(int bus)
2419 {
2420 	int i = 0;
2421 	ppb_ranges_t *rp;
2422 
2423 	rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP);
2424 
2425 	i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports,
2426 	    PCI_ADDR_IO | PCI_REG_REL_M);
2427 	i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space,
2428 	    PCI_ADDR_MEM32 | PCI_REG_REL_M);
2429 	i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space,
2430 	    PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M);
2431 
2432 	if (i != 0)
2433 		(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
2434 		    pci_bus_res[bus].dip, "ranges", (int *)rp,
2435 		    i * sizeof (ppb_ranges_t) / sizeof (int));
2436 	kmem_free(rp, 3 * sizeof (*rp));
2437 }
2438 
2439 static int
2440 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type)
2441 {
2442 	int i = 0;
2443 
2444 	while (list) {
2445 		/* assume 32-bit addresses */
2446 		sp->pci_phys_hi = type;
2447 		sp->pci_phys_mid = 0;
2448 		sp->pci_phys_low = (uint32_t)list->address;
2449 		sp->pci_size_hi = 0;
2450 		sp->pci_size_low = (uint32_t)list->size;
2451 
2452 		list = list->next;
2453 		sp++, i++;
2454 	}
2455 	return (i);
2456 }
2457 
2458 static void
2459 add_bus_available_prop(int bus)
2460 {
2461 	int i, count;
2462 	struct pci_phys_spec *sp;
2463 
2464 	count = memlist_count(pci_bus_res[bus].io_ports) +
2465 	    memlist_count(pci_bus_res[bus].mem_space) +
2466 	    memlist_count(pci_bus_res[bus].pmem_space);
2467 
2468 	if (count == 0)		/* nothing available */
2469 		return;
2470 
2471 	sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP);
2472 	i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports,
2473 	    PCI_ADDR_IO | PCI_REG_REL_M);
2474 	i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space,
2475 	    PCI_ADDR_MEM32 | PCI_REG_REL_M);
2476 	i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space,
2477 	    PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M);
2478 	ASSERT(i == count);
2479 
2480 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
2481 	    "available", (int *)sp,
2482 	    i * sizeof (struct pci_phys_spec) / sizeof (int));
2483 	kmem_free(sp, count * sizeof (*sp));
2484 }
2485 
2486 static void
2487 alloc_res_array(void)
2488 {
2489 	static int array_max = 0;
2490 	int old_max;
2491 	void *old_res;
2492 
2493 	if (array_max > pci_bios_nbus + 1)
2494 		return;	/* array is big enough */
2495 
2496 	old_max = array_max;
2497 	old_res = pci_bus_res;
2498 
2499 	if (array_max == 0)
2500 		array_max = 16;	/* start with a reasonable number */
2501 
2502 	while (array_max < pci_bios_nbus + 1)
2503 		array_max <<= 1;
2504 	pci_bus_res = (struct pci_bus_resource *)kmem_zalloc(
2505 	    array_max * sizeof (struct pci_bus_resource), KM_SLEEP);
2506 
2507 	if (old_res) {	/* copy content and free old array */
2508 		bcopy(old_res, pci_bus_res,
2509 		    old_max * sizeof (struct pci_bus_resource));
2510 		kmem_free(old_res, old_max * sizeof (struct pci_bus_resource));
2511 	}
2512 }
2513 
2514 static void
2515 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
2516     ushort_t deviceid)
2517 {
2518 	static dev_info_t *ioapicsnode = NULL;
2519 	static int numioapics = 0;
2520 	dev_info_t *ioapic_node;
2521 	uint64_t physaddr;
2522 	uint32_t lobase, hibase = 0;
2523 
2524 	/* BAR 0 contains the IOAPIC's memory-mapped I/O address */
2525 	lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0);
2526 
2527 	/* We (and the rest of the world) only support memory-mapped IOAPICs */
2528 	if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM)
2529 		return;
2530 
2531 	if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL)
2532 		hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4);
2533 
2534 	lobase &= PCI_BASE_M_ADDR_M;
2535 
2536 	physaddr = (((uint64_t)hibase) << 32) | lobase;
2537 
2538 	/*
2539 	 * Create a nexus node for all IOAPICs under the root node.
2540 	 */
2541 	if (ioapicsnode == NULL) {
2542 		if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME,
2543 		    (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) {
2544 			return;
2545 		}
2546 		(void) ndi_devi_online(ioapicsnode, 0);
2547 	}
2548 
2549 	/*
2550 	 * Create a child node for this IOAPIC
2551 	 */
2552 	ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME,
2553 	    DEVI_SID_NODEID, numioapics++);
2554 	if (ioapic_node == NULL) {
2555 		return;
2556 	}
2557 
2558 	/* Vendor and Device ID */
2559 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node,
2560 	    IOAPICS_PROP_VENID, vendorid);
2561 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node,
2562 	    IOAPICS_PROP_DEVID, deviceid);
2563 
2564 	/* device_type */
2565 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node,
2566 	    "device_type", IOAPICS_DEV_TYPE);
2567 
2568 	/* reg */
2569 	(void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node,
2570 	    "reg", physaddr);
2571 }
2572 
2573 /*
2574  * NOTE: For PCIe slots, the name is generated from the slot number
2575  * information obtained from Slot Capabilities register.
2576  * For non-PCIe slots, it is generated based on the slot number
2577  * information in the PCI IRQ table.
2578  */
2579 static void
2580 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num)
2581 {
2582 	char slotprop[256];
2583 	int len;
2584 
2585 	bzero(slotprop, sizeof (slotprop));
2586 
2587 	/* set mask to 1 as there is only one slot (i.e dev 0) */
2588 	*(uint32_t *)slotprop = 1;
2589 	len = 4;
2590 	(void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d",
2591 	    slot_num);
2592 	len += strlen(slotprop + len) + 1;
2593 	len += len % 4;
2594 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names",
2595 	    (int *)slotprop, len / sizeof (int));
2596 }
2597