1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _NB5000_H 28 #define _NB5000_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/cpu_module.h> 35 36 #define NB_5000_MAX_MEM_CONTROLLERS 2 37 #define NB_MAX_DIMMS_PER_CHANNEL (nb_chipset == INTEL_NB_5100 ? 3 : \ 38 (nb_chipset == INTEL_NB_7300 ? 8 : 4)) 39 #define NB_MAX_CHANNELS_PER_BRANCH 2 40 #define NB_5100_RANKS_PER_CHANNEL 6 41 #define NB_MEM_BRANCH_SELECT \ 42 (nb_chipset == INTEL_NB_5400 || nb_chipset == INTEL_NB_5100 ? 2 : 3) 43 #define NB_MAX_MEM_BRANCH_SELECT 3 44 #define NB_MEM_RANK_SELECT (nb_chipset == INTEL_NB_7300 ? 7 : 5) 45 #define NB_MAX_MEM_RANK_SELECT 7 46 #define NB_RANKS_IN_SELECT 4 47 #define NB_PCI_DEV 10 48 49 #define NB_PCI_NFUNC 4 50 51 #define DOCMD_PEX_MASK 0x00 52 #define DOCMD_5400_PEX_MASK 0x000 53 #define DOCMD_PEX 0xf0 54 #define DOCMD_5400_PEX 0xff0 55 56 #define SPD_BUSY 0x1000 57 #define SPD_BUS_ERROR 0x2000 58 #define SPD_READ_DATA_VALID 0x8000 59 #define SPD_EEPROM_WRITE 0xa8000000 60 #define SPD_ADDR(slave, addr) ((((slave) & 7) << 24) | (((addr) & 0xff) << 16)) 61 62 #define MC_MIRROR 0x10000 63 #define MC_PATROL_SCRUB 0x80 64 #define MC_DEMAND_SCRUB 0x40 65 66 #define MCA_SCHDIMM 0x4000 67 68 #define TLOW_MAX 0x100000000ULL 69 70 #define MTR_PRESENT(mtr) \ 71 (((mtr) & (nb_chipset == INTEL_NB_5400 || nb_chipset == INTEL_NB_5100) \ 72 ? 0x0400 : 0x0100) != 0) 73 #define MTR_ETHROTTLE(mtr) \ 74 ((mtr) & (nb_chipset == INTEL_NB_5400 || nb_chipset == INTEL_NB_5100 ? \ 75 ? 0x0200 : 0x0080)) 76 #define MTR_WIDTH(mtr) \ 77 ((mtr) & (nb_chipset == INTEL_NB_5400 || nb_chipset == INTEL_NB_5100 ? \ 78 0x0100 : 0x0040) ? 8 : 4) 79 #define MTR_NUMBANK(mtr) \ 80 ((mtr) & (nb_chipset == INTEL_NB_5400 || nb_chipset == INTEL_NB_5100 ? \ 81 0x0040 : 0x0020) ? 8 : 4) 82 #define MTR_NUMRANK(mtr) (nb_chipset == INTEL_NB_5100 ? 1 : \ 83 (((mtr) & (nb_chipset == INTEL_NB_5400 ? 0x0020 : 0x0010)) ? 2 : 1)) 84 #define MTR_NUMROW(mtr) ((((mtr) >> 2) & 3) + 13) 85 #define MTR_NUMCOL(mtr) (((mtr) & 3) + 10) 86 87 #define MTR_DIMMSIZE(mtr) ((1ULL << (MTR_NUMCOL(mtr) + MTR_NUMROW(mtr))) \ 88 * MTR_NUMRANK(mtr) * MTR_NUMBANK(mtr) * MTR_WIDTH(mtr)) 89 #define DIMMSIZE(nrow, ncol, nrank, nbank, width) \ 90 ((1ULL << ((ncol) + (nrow))) * (nrank) * (nbank) * (width)) 91 #define MTR_DDR2_DIMMSIZE(mtr, nrank) \ 92 ((1ULL << (MTR_NUMCOL(mtr) + MTR_NUMROW(mtr))) \ 93 * (nrank) * MTR_NUMBANK(mtr) * MTR_WIDTH(mtr)) 94 95 /* FERR_GLOBAL and NERR_GLOBAL */ 96 #define GE_FERR_FSB3_FATAL 0x800000000ULL /* FSB3 Fatal Error */ 97 #define GE_FERR_FSB2_FATAL 0x400000000ULL /* FSB2 Fatal Error */ 98 #define GE_FERR_FSB3_NF 0x200000000ULL /* FSB3 Non-Fatal Error */ 99 #define GE_FERR_FSB2_NF 0x100000000ULL /* FSB2 Non-Fatal Error */ 100 101 #define GE_INT_FATAL 0x80000000 /* North Bridge Internal Error */ 102 #define GE_DMA_FATAL 0x40000000 /* DMA engine Fatal Error */ 103 #define GE_FSB1_FATAL 0x20000000 /* FSB1 Fatal Error */ 104 #define GE_FSB0_FATAL 0x10000000 /* FSB0 Fatal Error */ 105 #define GE_FERR_FBD_FATAL 0x08000000 /* FBD channel Fatal Error */ 106 #define GE_FERR_FBD3_FATAL 0x08000000 /* FBD3 channel Fatal Error */ 107 #define GE_FERR_FBD2_FATAL 0x04000000 /* FBD2 channel Fatal Error */ 108 #define GE_FERR_FBD1_FATAL 0x02000000 /* FBD1 channel Fatal Error */ 109 #define GE_FERR_FBD0_FATAL 0x01000000 /* FBD0 channel Fatal Error */ 110 #define GE_FERR_THERMAL_FATAL 0x04000000 /* Thermal Fatal Error */ 111 #define GE_PCIEX9_FATAL 0x02000000 /* PCI Express device 9 Fatal Error */ 112 #define GE_PCIEX8_FATAL 0x01000000 /* PCI Express device 8 Fatal Error */ 113 #define GE_PCIEX7_FATAL 0x00800000 /* PCI Express device 7 Fatal Error */ 114 #define GE_PCIEX6_FATAL 0x00400000 /* PCI Express device 6 Fatal Error */ 115 #define GE_PCIEX5_FATAL 0x00200000 /* PCI Express device 5 Fatal Error */ 116 #define GE_PCIEX4_FATAL 0x00100000 /* PCI Express device 4 Fatal Error */ 117 #define GE_PCIEX3_FATAL 0x00080000 /* PCI Express device 3 Fatal Error */ 118 #define GE_PCIEX2_FATAL 0x00040000 /* PCI Express device 2 Fatal Error */ 119 #define GE_PCIEX1_FATAL 0x00020000 /* PCI Express device 1 Fatal Error */ 120 #define GE_ESI_FATAL 0x00010000 /* ESI Fatal Error */ 121 #define GE_INT_NF 0x00008000 /* North Bridge Internal Error */ 122 #define GE_DMA_NF 0x00004000 /* DMA engine Non-Fatal Error */ 123 #define GE_FSB1_NF 0x00002000 /* FSB1 Non-Fatal Error */ 124 #define GE_FSB0_NF 0x00001000 /* FSB0 Non-Fatal Error */ 125 #define GE_FERR_FBD3_NF 0x00000800 /* FBD channel 3 Non-Fatal Error */ 126 #define GE_FERR_FBD2_NF 0x00000400 /* FBD channel 2 Non-Fatal Error */ 127 #define GE_FERR_FBD1_NF 0x00000200 /* FBD channel 1 Non-Fatal Error */ 128 #define GE_FERR_FBD0_NF 0x00000100 /* FBD channel 0 Non-Fatal Error */ 129 #define GE_FERR_FBD_NF 0x00000800 /* FBD channel Non-Fatal Error */ 130 #define GE_FERR_MEM1_NF 0x00000200 /* DDR channel 1 Non-Fatal Error */ 131 #define GE_FERR_MEM0_NF 0x00000100 /* DDR channel 0 Non-Fatal Error */ 132 #define GE_FERR_THERMAL_NF 0x00000400 /* Thermal Non-Fatal Error */ 133 #define GE_PCIEX9_NF 0x00000200 /* PCI Express dev 9 Non-Fatal Error */ 134 #define GE_PCIEX8_NF 0x00000100 /* PCI Express dev 8 Non-Fatal Error */ 135 #define GE_PCIEX7_NF 0x00000080 /* PCI Express dev 7 Non-Fatal Error */ 136 #define GE_PCIEX6_NF 0x00000040 /* PCI Express dev 6 Non-Fatal Error */ 137 #define GE_PCIEX5_NF 0x00000020 /* PCI Express dev 5 Non-Fatal Error */ 138 #define GE_PCIEX4_NF 0x00000010 /* PCI Express dev 4 Non-Fatal Error */ 139 #define GE_PCIEX3_NF 0x00000008 /* PCI Express dev 3 Non-Fatal Error */ 140 #define GE_PCIEX2_NF 0x00000004 /* PCI Express dev 2 Non-Fatal Error */ 141 #define GE_PCIEX1_NF 0x00000002 /* PCI Express dev 1 Non-Fatal Error */ 142 #define GE_ESI_NF 0x00000001 /* ESI Non-Fatal Error */ 143 144 #define GE_NERR_FSB2_FATAL 0x08000000 /* FSB2 Fatal Error */ 145 #define GE_NERR_FSB3_FATAL 0x04000000 /* FSB3 Fatal Error */ 146 #define GE_NERR_FBD_FATAL (nb_chipset == INTEL_NB_5100 ? 0 : 0x01000000) 147 /* FBD channel Fatal Error */ 148 #define GE_NERR_FSB2_NF 0x00000800 /* FSB2 Non-Fatal Error */ 149 #define GE_NERR_FSB3_NF 0x00000400 /* FSB3 Non-Fatal Error */ 150 #define GE_NERR_FBD_NF (nb_chipset == INTEL_NB_5100 ? 0 : 0x00000100) 151 /* FBD channel Non-Fatal Error */ 152 #define GE_NERR_MEM_NF (nb_chipset == INTEL_NB_5100 ? 0x00000100 : 0) 153 /* DDR channel0,1 Non-Fatal Error */ 154 #define ERR_FAT_FSB_F9 0x20 /* F9Msk FSB Protocol */ 155 #define ERR_FAT_FSB_F2 0x08 /* F2Msk Unsupported Bus Transaction */ 156 #define ERR_FAT_FSB_F1 0x01 /* F1Msk Request/Address Parity */ 157 158 #define ERR_NF_FSB_F7 0x04 /* F7Msk Detected MCERR */ 159 #define ERR_NF_FSB_F8 0x02 /* F8Msk B-INIT */ 160 #define ERR_NF_FSB_F6 0x01 /* F6Msk Data Parity */ 161 162 #define EMASK_FSB_F1 0x0001 /* F1Msk Request/Address Parity */ 163 #define EMASK_FSB_F2 0x0002 /* F2Msk Unsupported Bus Transaction */ 164 #define EMASK_FSB_F6 0x0020 /* F6Msk Data Parity */ 165 #define EMASK_FSB_F7 0x0040 /* F7Msk Detected MCERR */ 166 #define EMASK_FSB_F8 0x0080 /* F8Msk B-INIT */ 167 #define EMASK_FSB_F9 0x0100 /* F9Msk FSB Protocol */ 168 169 #define EMASK_FSB_FATAL (EMASK_FSB_F1 | EMASK_FSB_F2 | EMASK_FSB_F9) 170 #define EMASK_FSB_NF (EMASK_FSB_F6 | EMASK_FSB_F7 | EMASK_FSB_F8) 171 172 #define ERR_FBD_CH_SHIFT 28 /* channel index in fat_fbd and nf_fbd */ 173 174 #define ERR_FAT_FBD_M23 0x00400000 /* M23Err Non-Redundant Fast Reset */ 175 /* Timeout */ 176 #define ERR_FAT_FBD_M3 0x00000004 /* M3Err >Tmid thermal event with */ 177 /* intelligent throttling disabled */ 178 #define ERR_FAT_FBD_M2 0x00000002 /* M2Err memory or FBD configuration */ 179 /* CRC read error */ 180 #define ERR_FAT_FBD_M1 0x00000001 /* M1Err memory write error on */ 181 /* non-redundant retry or FBD */ 182 /* configuration write error on retry */ 183 #define ERR_FAT_FBD_MASK 0x007fffff 184 185 #define ERR_NF_FBD_M29 0x02000000 /* M29Err DIMM-Isolation Completed */ 186 #define ERR_NF_FBD_M28 0x01000000 /* M28Err DIMM-Spare Copy Completed */ 187 #define ERR_NF_FBD_M27 0x00800000 /* M27Err DIMM-Spare Copy Initiated */ 188 #define ERR_NF_FBD_M26 0x00400000 /* M26Err Redundant Fast Reset */ 189 /* Timeout */ 190 #define ERR_NF_FBD_M25 0x00200000 /* M25Err Memory write error on */ 191 #define ERR_NF_FBD_M24 0x00100000 /* M24Err refresh error */ 192 /* redundant retry */ 193 #define ERR_NF_FBD_M22 0x00040000 /* M22Err SPD protocol */ 194 #define ERR_NF_FBD_M21 0x00020000 /* M21Err FBD Northbound parity on */ 195 /* FBD sync status */ 196 #define ERR_NF_FBD_M20 0x00010000 /* M20Err Correctable patrol data ECC */ 197 #define ERR_NF_FBD_M19 0x00008000 /* M19Err Correctasble resilver or */ 198 /* spare-copy data ECC */ 199 #define ERR_NF_FBD_M18 0x00004000 /* M18Err Correctable Mirrored demand */ 200 /* data ECC */ 201 #define ERR_NF_FBD_M17 0x00002000 /* M17Err Correctable Non-mirrored */ 202 /* demand data ECC */ 203 #define ERR_NF_FBD_M16 0x00001000 /* M16Err channel failed over */ 204 #define ERR_NF_FBD_M15 0x00000800 /* M15Err Memory or FBD configuration */ 205 /* CRC read error */ 206 #define ERR_NF_FBD_M14 0x00000400 /* M14Err FBD configuration write */ 207 /* error on first attempt */ 208 #define ERR_NF_FBD_M13 0x00000200 /* M13Err Memory write error on first */ 209 /* attempt */ 210 #define ERR_NF_FBD_M12 0x00000100 /* M12Err Non-Aliased uncorrectable */ 211 /* patrol data ECC */ 212 #define ERR_NF_FBD_M11 0x00000080 /* M11Err Non-Aliased uncorrectable */ 213 /* resilver or spare copy data ECC */ 214 #define ERR_NF_FBD_M10 0x00000040 /* M10Err Non-Aliased uncorrectable */ 215 /* mirrored demand data ECC */ 216 #define ERR_NF_FBD_M9 0x00000020 /* M9Err Non-Aliased uncorrectable */ 217 /* non-mirrored demand data ECC */ 218 #define ERR_NF_FBD_M8 0x00000010 /* M8Err Aliased uncorrectable */ 219 /* patrol data ECC */ 220 #define ERR_NF_FBD_M7 0x00000008 /* M7Err Aliased uncorrectable */ 221 /* resilver or spare copy data ECC */ 222 #define ERR_NF_FBD_M6 0x00000004 /* M6Err Aliased uncorrectable */ 223 /* mirrored demand data ECC */ 224 #define ERR_NF_FBD_M5 0x00000002 /* M5Err Aliased uncorrectable */ 225 /* non-mirrored demand data ECC */ 226 #define ERR_NF_FBD_M4 0x00000001 /* M4Err uncorrectable data ECC on */ 227 /* replay */ 228 229 #define ERR_DEFAULT_NF_FBD_MASK 0x01ffffff 230 #define ERR_5000_NF_FBD_MASK (ERR_NF_FBD_M28|ERR_NF_FBD_M27|ERR_NF_FBD_M22| \ 231 ERR_NF_FBD_M21|ERR_NF_FBD_M20|ERR_NF_FBD_M19|ERR_NF_FBD_M18| \ 232 ERR_NF_FBD_M17|ERR_NF_FBD_M15|ERR_NF_FBD_M14|ERR_NF_FBD_M13| \ 233 ERR_NF_FBD_M12|ERR_NF_FBD_M11|ERR_NF_FBD_M10|ERR_NF_FBD_M9|ERR_NF_FBD_M8| \ 234 ERR_NF_FBD_M7|ERR_NF_FBD_M6|ERR_NF_FBD_M5|ERR_NF_FBD_M4) 235 #define ERR_5400_NF_FBD_MASK (ERR_NF_FBD_M29|ERR_NF_FBD_M28|ERR_NF_FBD_M27| \ 236 ERR_NF_FBD_M26|ERR_NF_FBD_M25|ERR_NF_FBD_M24|ERR_NF_FBD_M22| \ 237 ERR_NF_FBD_M21|ERR_NF_FBD_M20|ERR_NF_FBD_M19|ERR_NF_FBD_M18| \ 238 ERR_NF_FBD_M17|ERR_NF_FBD_M16|ERR_NF_FBD_M15|ERR_NF_FBD_M14| \ 239 ERR_NF_FBD_M13|ERR_NF_FBD_M12|ERR_NF_FBD_M11|ERR_NF_FBD_M10| \ 240 ERR_NF_FBD_M9|ERR_NF_FBD_M8|ERR_NF_FBD_M7|ERR_NF_FBD_M6|ERR_NF_FBD_M5| \ 241 ERR_NF_FBD_M4) 242 #define ERR_7300_NF_FBD_MASK (ERR_NF_FBD_M28|ERR_NF_FBD_M27|ERR_NF_FBD_M26| \ 243 ERR_NF_FBD_M25|ERR_NF_FBD_M22|ERR_NF_FBD_M21|ERR_NF_FBD_M20| \ 244 ERR_NF_FBD_M19|ERR_NF_FBD_M18|ERR_NF_FBD_M17|ERR_NF_FBD_M15| \ 245 ERR_NF_FBD_M14|ERR_NF_FBD_M13|ERR_NF_FBD_M12|ERR_NF_FBD_M11| \ 246 ERR_NF_FBD_M10|ERR_NF_FBD_M9|ERR_NF_FBD_M8|ERR_NF_FBD_M7|ERR_NF_FBD_M6| \ 247 ERR_NF_FBD_M5|ERR_NF_FBD_M4) 248 249 /* Bitmask of the FB-DIMM non-fatal errors */ 250 #define ERR_NF_FBD_MASK ( \ 251 (nb_chipset == INTEL_NB_5000P || nb_chipset == INTEL_NB_5000V || \ 252 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000Z) ? \ 253 ERR_5000_NF_FBD_MASK : \ 254 nb_chipset == INTEL_NB_5400 ? ERR_5400_NF_FBD_MASK : \ 255 nb_chipset == INTEL_NB_7300 ? ERR_7300_NF_FBD_MASK : \ 256 ERR_DEFAULT_NF_FBD_MASK) 257 258 #define ERR_NF_FBD_ECC_UE (ERR_NF_FBD_M12|ERR_NF_FBD_M11|ERR_NF_FBD_M10| \ 259 ERR_NF_FBD_M9|ERR_NF_FBD_M8|ERR_NF_FBD_M7|ERR_NF_FBD_M6|ERR_NF_FBD_M5| \ 260 ERR_NF_FBD_M4) 261 #define ERR_NF_FBD_MA (ERR_NF_FBD_M14) 262 #define ERR_NF_FBD_ECC_CE (ERR_NF_FBD_M20|ERR_NF_FBD_M19|ERR_NF_FBD_M18| \ 263 ERR_NF_FBD_M17|ERR_NF_FBD_M15|ERR_NF_FBD_M21) 264 #define ERR_NF_FBD_SPARE (ERR_NF_FBD_M28|ERR_NF_FBD_M27) 265 266 #define EMASK_FBD_M29 0x10000000 /* M29Err DIMM-Isolation Completed */ 267 #define EMASK_FBD_M28 0x08000000 /* M28Err DIMM-Spare Copy Completed */ 268 #define EMASK_FBD_M27 0x04000000 /* M27Err DIMM-Spare Copy Initiated */ 269 #define EMASK_FBD_M26 0x02000000 /* M26Err Redundant Fast Reset */ 270 /* Timeout */ 271 #define EMASK_FBD_M25 0x01000000 /* M25Err Memory write error on */ 272 /* redundant retry */ 273 #define EMASK_FBD_M24 0x00800000 /* M24Err refresh error */ 274 #define EMASK_FBD_M23 0x00400000 /* M23Err Non-Redundant Fast Reset */ 275 /* Timeout */ 276 #define EMASK_FBD_M22 0x00200000 /* M22Err SPD protocol */ 277 #define EMASK_FBD_M21 0x00100000 /* M21Err FBD Northbound parity on */ 278 /* FBD sync status */ 279 #define EMASK_FBD_M20 0x00080000 /* M20Err Correctable patrol data ECC */ 280 #define EMASK_FBD_M19 0x00040000 /* M19Err Correctasble resilver or */ 281 /* spare-copy data ECC */ 282 #define EMASK_FBD_M18 0x00020000 /* M18Err Correctable Mirrored demand */ 283 /* data ECC */ 284 #define EMASK_FBD_M17 0x00010000 /* M17Err Correctable Non-mirrored */ 285 /* demand data ECC */ 286 #define EMASK_FBD_M16 0x00008000 /* M16Err channel failed over */ 287 #define EMASK_FBD_M15 0x00004000 /* M15Err Memory or FBD configuration */ 288 /* CRC read error */ 289 #define EMASK_FBD_M14 0x00002000 /* M14Err FBD configuration write */ 290 /* error on first attempt */ 291 #define EMASK_FBD_M13 0x00001000 /* M13Err Memory write error on first */ 292 /* attempt */ 293 #define EMASK_FBD_M12 0x00000800 /* M12Err Non-Aliased uncorrectable */ 294 /* patrol data ECC */ 295 #define EMASK_FBD_M11 0x00000400 /* M11Err Non-Aliased uncorrectable */ 296 /* resilver or spare copy data ECC */ 297 #define EMASK_FBD_M10 0x00000200 /* M10Err Non-Aliased uncorrectable */ 298 /* mirrored demand data ECC */ 299 #define EMASK_FBD_M9 0x00000100 /* M9Err Non-Aliased uncorrectable */ 300 /* non-mirrored demand data ECC */ 301 #define EMASK_FBD_M8 0x00000080 /* M8Err Aliased uncorrectable */ 302 /* patrol data ECC */ 303 #define EMASK_FBD_M7 0x00000040 /* M7Err Aliased uncorrectable */ 304 /* resilver or spare copy data ECC */ 305 #define EMASK_FBD_M6 0x00000020 /* M6Err Aliased uncorrectable */ 306 /* mirrored demand data ECC */ 307 #define EMASK_FBD_M5 0x00000010 /* M5Err Aliased uncorrectable */ 308 /* non-mirrored demand data ECC */ 309 #define EMASK_FBD_M4 0x00000008 /* M4Err uncorrectable data ECC on */ 310 /* replay */ 311 #define EMASK_FBD_M3 0x00000004 /* M3Err >Tmid thermal event with */ 312 /* intelligent throttling disabled */ 313 #define EMASK_FBD_M2 0x00000002 /* M2Err memory or FBD configuration */ 314 /* CRC read error */ 315 #define EMASK_FBD_M1 0x00000001 /* M1Err memory write error on */ 316 /* non-redundant retry or FBD */ 317 /* configuration write error on retry */ 318 /* MCH 7300 errata 34 (reserved mask bits) */ 319 #define EMASK_5000_FBD_RES (EMASK_FBD_M24|EMASK_FBD_M16) 320 #define EMASK_FBD_RES (nb_chipset == INTEL_NB_5400 ? 0 : EMASK_5000_FBD_RES) 321 322 #define EMASK_FBD_FATAL (EMASK_FBD_M3|EMASK_FBD_M2|EMASK_FBD_M1) 323 #define EMASK_FBD_NF (EMASK_FBD_M28|EMASK_FBD_M27|EMASK_FBD_M26|EMASK_FBD_M25| \ 324 EMASK_FBD_M22|EMASK_FBD_M21|EMASK_FBD_M20|EMASK_FBD_M19|EMASK_FBD_M18| \ 325 EMASK_FBD_M17|EMASK_FBD_M15|EMASK_FBD_M14|EMASK_FBD_M13|EMASK_FBD_M12| \ 326 EMASK_FBD_M11|EMASK_FBD_M10|EMASK_FBD_M9|EMASK_FBD_M8|EMASK_FBD_M7| \ 327 EMASK_FBD_M6|EMASK_FBD_M5|EMASK_FBD_M4) 328 #define EMASK_5400_FBD_FATAL (EMASK_FBD_M23|EMASK_FBD_M2|EMASK_FBD_M1) 329 #define EMASK_5400_FBD_NF (EMASK_FBD_M29|EMASK_FBD_M28|EMASK_FBD_M27| \ 330 EMASK_FBD_M26|EMASK_FBD_M25|EMASK_FBD_M24|EMASK_FBD_M22|EMASK_FBD_M21| \ 331 EMASK_FBD_M20|EMASK_FBD_M19|EMASK_FBD_M18|EMASK_FBD_M17|EMASK_FBD_M16| \ 332 EMASK_FBD_M15|EMASK_FBD_M14|EMASK_FBD_M13|EMASK_FBD_M12| \ 333 EMASK_FBD_M11|EMASK_FBD_M10|EMASK_FBD_M9|EMASK_FBD_M8|EMASK_FBD_M7| \ 334 EMASK_FBD_M6|EMASK_FBD_M5|EMASK_FBD_M4) 335 #define EMASK_7300_FBD_FATAL (EMASK_FBD_M23|EMASK_FBD_M3|EMASK_FBD_M2| \ 336 EMASK_FBD_M1) 337 #define EMASK_7300_FBD_NF EMASK_FBD_NF 338 339 /* FERR_NF_MEM: MC First non-fatal errors */ 340 #define ERR_MEM_CH_SHIFT 28 /* channel index in nf_mem */ 341 342 #define ERR_NF_MEM_M21 0x00200000 /* M21Err Spare Copy Completed */ 343 #define ERR_NF_MEM_M20 0x00100000 /* M20Err Spare Copy Initiated */ 344 #define ERR_NF_MEM_M18 0x00040000 /* M18Err SPD protocal */ 345 #define ERR_NF_MEM_M16 0x00010000 /* M16Err Correctable Patrol Data ECC */ 346 #define ERR_NF_MEM_M15 0x00008000 /* M15Err Correctable Spare-copy ECC */ 347 #define ERR_NF_MEM_M14 0x00004000 /* M14Err Correctable demand data ECC */ 348 #define ERR_NF_MEM_M12 0x00001000 /* M12Err non-aliased ue Patrol ECC */ 349 #define ERR_NF_MEM_M11 0x00000800 /* M11Err non-aliased ue Spare-copy */ 350 #define ERR_NF_MEM_M10 0x00000400 /* M10Err non-aliased ue demand data */ 351 #define ERR_NF_MEM_M6 0x00000040 /* M6Err aliased ue Patrol Data ECC */ 352 #define ERR_NF_MEM_M5 0x00000020 /* M5Err aliased ue Spare-copy ECC */ 353 #define ERR_NF_MEM_M4 0x00000010 /* M4Err aliased ue demand data ECC */ 354 #define ERR_NF_MEM_M1 0x00000002 /* M1Err ue data ECC on replay */ 355 356 #define ERR_NF_MEM_MASK 0x0003fffff 357 #define ERR_NF_MEM_ECC_UE (ERR_NF_MEM_M12|ERR_NF_MEM_M11|ERR_NF_MEM_M10| \ 358 ERR_NF_MEM_M6|ERR_NF_MEM_M5|ERR_NF_MEM_M4|ERR_NF_MEM_M1) 359 #define ERR_NF_MEM_ECC_CE (ERR_NF_MEM_M16|ERR_NF_MEM_M15|ERR_NF_MEM_M14) 360 #define ERR_NF_MEM_SPARE (ERR_NF_MEM_M21|ERR_NF_MEM_M20) 361 362 #define EMASK_MEM_M21 ERR_NF_MEM_M21 363 #define EMASK_MEM_M20 ERR_NF_MEM_M20 364 #define EMASK_MEM_M18 ERR_NF_MEM_M18 365 #define EMASK_MEM_M16 ERR_NF_MEM_M16 366 #define EMASK_MEM_M15 ERR_NF_MEM_M15 367 #define EMASK_MEM_M14 ERR_NF_MEM_M14 368 #define EMASK_MEM_M12 ERR_NF_MEM_M12 369 #define EMASK_MEM_M11 ERR_NF_MEM_M11 370 #define EMASK_MEM_M10 ERR_NF_MEM_M10 371 #define EMASK_MEM_M6 ERR_NF_MEM_M6 372 #define EMASK_MEM_M5 ERR_NF_MEM_M5 373 #define EMASK_MEM_M4 ERR_NF_MEM_M4 374 #define EMASK_MEM_M1 ERR_NF_MEM_M1 375 376 #define EMASK_MEM_NF (EMASK_FBD_M21|EMASK_FBD_M20|EMASK_FBD_M18|EMASK_FBD_M16| \ 377 EMASK_FBD_M15|EMASK_FBD_M14|EMASK_FBD_M12|EMASK_FBD_M11|EMASK_FBD_M10| \ 378 EMASK_MEM_M6|EMASK_MEM_M5|EMASK_MEM_M4|EMASK_MEM_M1) 379 380 #define ERR_INT_ALL (nb_chipset == INTEL_NB_5400 ? 0xffffffff : 0xff) 381 382 #define ERR_FAT_INT_B14 0x0400 /* B14Msk SF Scrub DBE */ 383 #define ERR_FAT_INT_B12 0x0100 /* B12Msk Parity Protected register */ 384 #define ERR_FAT_INT_B25 0x0080 /* B25Msk illegal HISMM/TSEG access */ 385 #define ERR_FAT_INT_B23 0x0040 /* B23Msk Vt Unaffiliated port error */ 386 #define ERR_FAT_INT_B21 0x0020 /* B21Msk illegal way */ 387 #define ERR_FAT_INT_B7 0x0010 /* B7Msk Multiple ECC error in any of */ 388 /* the ways during SF lookup */ 389 #define ERR_FAT_INT_B4 0x08 /* B4Msk Virtual pin port error */ 390 #define ERR_FAT_INT_B3 0x04 /* B3Msk Coherency violation error for EWB */ 391 #define ERR_FAT_INT_B2 0x02 /* B2Msk Multi-tag hit SF */ 392 #define ERR_FAT_INT_B1 0x01 /* B1Msk DM parity error */ 393 394 #define ERR_NF_INT_B27 0x4000 /* B27Msk Request received when in S1 */ 395 #define ERR_NF_INT_B24 0x2000 /* B24Msk DFXERR */ 396 #define ERR_NF_INT_B19 0x1000 /* B19Msk scrub SBE (SF) */ 397 #define ERR_NF_INT_B18 0x0800 /* B18Msk perfmon task completion */ 398 #define ERR_NF_INT_B17 0x0400 /* B17Msk JTAG/TAP error status */ 399 #define ERR_NF_INT_B16 0x0200 /* B16Msk SMBus error status */ 400 #define ERR_NF_INT_B22 0x0080 /* B22Msk Victim ROM parity */ 401 #define ERR_NF_INT_B20 0x0040 /* B20Msk Configuration write abort */ 402 #define ERR_NF_INT_B11 0x0020 /* B11Msk Victim Ram parity error */ 403 #define ERR_NF_INT_B10 0x0010 /* B10Msk DM Parity */ 404 #define ERR_NF_INT_B9 0x0008 /* B9Msk illeagl access */ 405 #define ERR_NF_INT_B8 0x0004 /* B8Msk SF Coherency Error for BIL */ 406 #define ERR_NF_INT_B6 0x0002 /* B6Msk Single ECC error on SF lookup */ 407 #define ERR_NF_INT_B5 0x0001 /* B5Msk Address Map error */ 408 409 #define NERR_NF_5400_INT_B26 0x0004 /* B26Msk Illeagl Access to */ 410 /* non-coherent address space */ 411 412 #define EMASK_INT_RES 0x02000000 /* Do not change */ 413 #define EMASK_INT_B25 0x01000000 /* B25Msk illegal HISMM/TSEG access */ 414 #define EMASK_INT_B23 0x00400000 /* B23Msk Vt Unaffiliated port error */ 415 #define EMASK_INT_B22 0x00200000 /* B22Msk Victim ROM parity */ 416 #define EMASK_INT_B21 0x00100000 /* B21Msk illegal way */ 417 #define EMASK_INT_B20 0x00080000 /* B20Msk Configuration write abort */ 418 #define EMASK_INT_B19 0x00040000 /* B19Msk Scrub SBE */ 419 #define EMASK_INT_B14 0x00002000 /* B14Msk Scrub DBE */ 420 #define EMASK_INT_B12 0x00000800 /* B12Msk Parity Protected */ 421 #define EMASK_INT_B11 0x00000400 /* B11Msk Victim Ram parity error */ 422 #define EMASK_INT_B10 0x00000200 /* B10Msk DM Parity */ 423 #define EMASK_INT_B9 0x00000100 /* B9Msk Illegal Accesss */ 424 425 #define EMASK_INT_B8 0x80 /* B8Msk SF Coherency Error for BIL */ 426 #define EMASK_INT_B7 0x40 /* B7Msk Multiple ECC error in any of */ 427 /* the ways during SF lookup */ 428 #define EMASK_INT_B6 0x20 /* B6Msk Single ECC error on SF lookup */ 429 #define EMASK_INT_B5 0x10 /* B5Msk Address Map error */ 430 #define EMASK_INT_B4 0x08 /* B4Msk Virtual pin port error */ 431 #define EMASK_INT_B3 0x04 /* B3Msk Coherency violation error for EWB */ 432 #define EMASK_INT_B2 0x02 /* B2Msk Multi-tag hit SF */ 433 #define EMASK_INT_B1 0x01 /* B1Msk DM parity error */ 434 435 /* MCH 5000 errata 2: disable B1 */ 436 #define EMASK_INT_5000 EMASK_INT_B1 437 /* MCH 5100: mask all except B3 and B5 */ 438 #define EMASK_INT_5100 (~(EMASK_INT_B5|EMASK_INT_B3) & 0xff) 439 /* MCH 7300 errata 17 & 20 */ 440 #define EMASK_INT_7300 (EMASK_INT_B3|EMASK_INT_B1) 441 /* MCH 7300 errata 17,20 & 21 */ 442 #define EMASK_INT_7300_STEP_0 (EMASK_INT_B7|EMASK_INT_B3|EMASK_INT_B1) 443 #define EMASK_INT_5400 0 444 445 #define EMASK_INT_FATAL (EMASK_INT_B7|EMASK_INT_B4|EMASK_INT_B3|EMASK_INT_B2| \ 446 EMASK_INT_B1) 447 #define EMASK_INT_NF (EMASK_INT_B8|EMASK_INT_B6|EMASK_INT_B5) 448 #define EMASK_INT_5100_FATAL (EMASK_INT_B3|EMASK_INT_B1) 449 #define EMASK_INT_5100_NF (EMASK_INT_B5) 450 451 #define GE_FBD_FATAL ((nb_chipset == INTEL_NB_5400) ? GE_FERR_FBD_FATAL : \ 452 (nb_chipset == INTEL_NB_5100) ? 0 : \ 453 (GE_FERR_FBD0_FATAL|GE_FERR_FBD1_FATAL|GE_FERR_FBD2_FATAL| \ 454 GE_FERR_FBD3_FATAL)) 455 #define GE_FBD_NF ((nb_chipset == INTEL_NB_5400) ? GE_FERR_FBD_NF : \ 456 (nb_chipset == INTEL_NB_5100) ? 0 : \ 457 (GE_FERR_FBD0_NF|GE_FERR_FBD1_NF|GE_FERR_FBD2_NF|GE_FERR_FBD3_NF)) 458 #define GE_MEM_NF ((nb_chipset == INTEL_NB_5100) ? \ 459 (GE_FERR_MEM0_NF|GE_FERR_MEM1_NF) : 0) 460 461 #define EMASK_UNCOR_PEX_IO18 0x00200000 /* ESI Reset timeout */ 462 #define EMASK_UNCOR_PEX_IO2 0x00100000 /* Received an unsupported */ 463 /* request */ 464 #define EMASK_UNCOR_PEX_IO9 0x00040000 /* Malformed TLP Status */ 465 #define EMASK_UNCOR_PEX_IO10 0x00020000 /* Received buffer overflow */ 466 #define EMASK_UNCOR_PEX_IO8 0x00010000 /* unexpected completion */ 467 #define EMASK_UNCOR_PEX_IO7 0x00008000 /* completion abort */ 468 #define EMASK_UNCOR_PEX_IO6 0x00004000 /* completion timeout */ 469 #define EMASK_UNCOR_PEX_IO5 0x00002000 /* flow control protocol */ 470 #define EMASK_UNCOR_PEX_IO4 0x00001000 /* poisoned TLP */ 471 #define EMASK_UNCOR_PEX_IO19 0x00000020 /* surprise link down */ 472 #define EMASK_UNCOR_PEX_IO0 0x00000010 /* data link protocol */ 473 #define EMASK_UNCOR_PEX_IO3 0x00000001 /* training error */ 474 475 #define EMASK_COR_PEX_IO20 0x00002000 /* Advisory Non Fatal */ 476 #define EMASK_COR_PEX_IO16 0x00001000 /* replay timer timeout */ 477 #define EMASK_COR_PEX_IO15 0x00000100 /* replay num pollover */ 478 #define EMASK_COR_PEX_IO14 0x00000080 /* bad DLLP */ 479 #define EMASK_COR_PEX_IO13 0x00000040 /* bad TLP */ 480 #define EMASK_COR_PEX_IO12 0x00000001 /* receiver error mask */ 481 482 #define EMASK_RP_PEX_IO1 0x00000004 /* fatal message detect */ 483 #define EMASK_RP_PEX_IO11 0x00000002 /* uncorrectable message */ 484 #define EMASK_RP_PEX_IO17 0x00000001 /* correctable message */ 485 486 #define EMASK_UNIT_PEX_IO33 0x00002000 /* Link autonomous BW change */ 487 #define EMASK_UNIT_PEX_IO32 0x00001000 /* Received CA Posted Req */ 488 #define EMASK_UNIT_PEX_IO31 0x00000800 /* Received UR Posted Req */ 489 #define EMASK_UNIT_PEX_IO30 0x00000400 /* VT-d internal HW */ 490 #define EMASK_UNIT_PEX_IO29 0x00000200 /* MSI address */ 491 #define EMASK_UNIT_PEX_IO28 0x00000100 /* Link BW change */ 492 #define EMASK_UNIT_PEX_IO27 0x00000080 /* stop & scream */ 493 #define EMASK_UNIT_PEX_IO26 0x00000040 /* Received CA response */ 494 #define EMASK_UNIT_PEX_IO25 0x00000020 /* Received UR response */ 495 #define EMASK_UNIT_PEX_IO24 0x00000010 /* Outbound poisoned data */ 496 #define EMASK_UNIT_PEX_IO23 0x00000008 /* VTd fault */ 497 #define EMASK_UNIT_PEX_IO22 0x00000004 /* internal header/ctl parity */ 498 #define EMASK_UNIT_PEX_IO18 0x00000002 /* ESI reset timeout */ 499 #define EMASK_UNIT_PEX_VPP 0x00000001 /* correctable message detect */ 500 501 #define PEX_5400_FAT_IO32 0x00800000 /* Received CA Posted Request */ 502 #define PEX_5400_FAT_IO31 0x00400000 /* Received UR Posted Request */ 503 #define PEX_5400_FAT_IO30 0x00200000 /* VT-d Internal HW */ 504 #define PEX_5400_FAT_IO29 0x00100000 /* MSI Address */ 505 #define PEX_5400_FAT_IO27 0x00040000 /* Stop & Scream */ 506 #define PEX_5400_FAT_IO26 0x00020000 /* Received CA Response */ 507 #define PEX_5400_FAT_IO25 0x00010000 /* Received UR Response */ 508 #define PEX_5400_FAT_IO24 0x00008000 /* Outbound poisoned TLP */ 509 #define PEX_5400_FAT_IO23 0x00004000 /* VT-d Fault */ 510 #define PEX_5400_FAT_IO22 0x00002000 /* Internal Header/Control */ 511 /* Parity */ 512 #define PEX_5400_FAT_IO18 0x00001000 /* ESI reset timeout */ 513 #define PEX_5400_FAT_IO1 0x00000400 /* received fatal error msg */ 514 #define PEX_5400_FAT_IO2 0x00000200 /* received unsupported req */ 515 #define PEX_5400_FAT_IO9 0x00000100 /* malformed TLP */ 516 #define PEX_5400_FAT_IO10 0x00000080 /* receiver buffer overflow */ 517 #define PEX_5400_FAT_IO8 0x00000040 /* unexpected completion */ 518 #define PEX_5400_FAT_IO7 0x00000020 /* completer abort */ 519 #define PEX_5400_FAT_IO6 0x00000010 /* completion timeout */ 520 #define PEX_5400_FAT_IO5 0x00000008 /* flow control protocol */ 521 #define PEX_5400_FAT_IO4 0x00000004 /* poisoned TLP */ 522 #define PEX_5400_FAT_IO19 0x00000002 /* surprise link down */ 523 #define PEX_5400_FAT_IO0 0x00000001 /* data link layer protocol */ 524 #define PEX_FAT_IO19 0x00001000 /* surprise link down */ 525 #define PEX_FAT_IO18 0x00000800 /* ESI reset timeout */ 526 #define PEX_FAT_IO9 0x00000400 /* malformed TLP */ 527 #define PEX_FAT_IO10 0x00000200 /* receiver buffer overflow */ 528 #define PEX_FAT_IO8 0x00000100 /* unexpected completion */ 529 #define PEX_FAT_IO7 0x00000080 /* completer abort */ 530 #define PEX_FAT_IO6 0x00000040 /* completion timeout */ 531 #define PEX_FAT_IO5 0x00000020 /* flow control protocol */ 532 #define PEX_FAT_IO4 0x00000010 /* poisoned TLP */ 533 #define PEX_FAT_IO3 0x00000008 /* training error */ 534 #define PEX_FAT_IO2 0x00000004 /* received unsupported req */ 535 #define PEX_FAT_IO1 0x00000002 /* received fatal error message */ 536 #define PEX_FAT_IO0 0x00000001 /* data link layer protocol */ 537 538 #define PEX_5400_NF_IO33 0x20000000 /* link autonomous bandwidth */ 539 /* change (correctable) */ 540 #define PEX_5400_NF_IO32 0x10000000 /* Received CA Posted Request */ 541 #define PEX_5400_NF_IO31 0x08000000 /* Received UR Posted Request */ 542 #define PEX_5400_NF_IO30 0x04000000 /* VT-d Internal HW */ 543 #define PEX_5400_NF_IO29 0x02000000 /* MSI Address */ 544 #define PEX_5400_NF_IO28 0x01000000 /* Link bandwidth change */ 545 #define PEX_5400_NF_IO27 0x00800000 /* Stop & Scream */ 546 #define PEX_5400_NF_IO26 0x00400000 /* Received CA Response */ 547 #define PEX_5400_NF_IO25 0x00200000 /* Received UR Response */ 548 #define PEX_5400_NF_IO24 0x00100000 /* Outbound poisoned TLP */ 549 #define PEX_5400_NF_IO23 0x00080000 /* VT-d Fault */ 550 #define PEX_5400_NF_IO11 0x00040000 /* received non fatal err msg */ 551 #define PEX_5400_NF_IO17 0x00020000 /* rec correctable error msg */ 552 #define PEX_5400_NF_IO2 0x00008000 /* Received unsupported req */ 553 #define PEX_5400_NF_IO9 0x00004000 /* Malformed TLP */ 554 #define PEX_5400_NF_IO10 0x00002000 /* Received buffer overflow */ 555 #define PEX_5400_NF_IO8 0x00001000 /* unexpected completion err */ 556 #define PEX_5400_NF_IO7 0x00000800 /* completion abort */ 557 #define PEX_5400_NF_IO6 0x00000400 /* completion timeout */ 558 #define PEX_5400_NF_IO5 0x00000200 /* flow control protocol */ 559 #define PEX_5400_NF_IO4 0x00000100 /* poisoned TLP */ 560 #define PEX_5400_NF_IO19 0x00000080 /* surprise link down */ 561 #define PEX_5400_NF_IO0 0x00000040 /* data link layer protocol */ 562 #define PEX_5400_NF_IO20 0x00000020 /* Advisory Non Fatel */ 563 #define PEX_5400_NF_IO16 0x00000010 /* replay timer timeout */ 564 #define PEX_5400_NF_IO15 0x00000008 /* replay num pollover */ 565 #define PEX_5400_NF_IO14 0x00000004 /* bad DLLP */ 566 #define PEX_5400_NF_IO13 0x00000002 /* bad TLP */ 567 #define PEX_5400_NF_IO12 0x00000001 /* receiver error mask */ 568 #define PEX_NF_IO19 0x00020000 /* surprise link down */ 569 #define PEX_NF_IO17 0x00010000 /* received correctable error message */ 570 #define PEX_NF_IO16 0x00008000 /* replay timer timeout */ 571 #define PEX_NF_IO15 0x00004000 /* replay num pollover */ 572 #define PEX_NF_IO14 0x00002000 /* bad DLLP */ 573 #define PEX_NF_IO13 0x00001000 /* bad TLP */ 574 #define PEX_NF_IO12 0x00000800 /* receiver error mask */ 575 #define PEX_NF_IO11 0x00000400 /* received non fatal error message */ 576 #define PEX_NF_IO10 0x00000200 /* Received buffer overflow */ 577 #define PEX_NF_IO9 0x00000100 /* Malformed TLP */ 578 #define PEX_NF_IO8 0x00000080 579 #define PEX_NF_IO7 0x00000040 580 #define PEX_NF_IO6 0x00000020 /* completion timeout */ 581 #define PEX_NF_IO5 0x00000010 /* flow control protocol */ 582 #define PEX_NF_IO4 0x00000008 /* poisoned TLP */ 583 #define PEX_NF_IO3 0x00000004 584 #define PEX_NF_IO2 0x00000002 585 #define PEX_NF_IO0 0x00000001 /* data link layer protocol */ 586 587 #define ERR_FAT_TH2 0x02 /* >tmid thermal event */ 588 #define ERR_FAT_TH1 0x01 /* Catastrophic on-die thermal event */ 589 590 #define ERR_NF_TH5 0x10 /* timeout on cooling update */ 591 #define ERR_NF_TH4 0x08 /* TSMAX update */ 592 #define ERR_NF_TH3 0x04 /* on-die throttling event */ 593 594 #define EMASK_TH5 0x0010 /* TH5Msk timeout on cooling update */ 595 #define EMASK_TH4 0x0008 /* TH4Msk TSMAX update */ 596 #define EMASK_TH3 0x0004 /* TH3Msk on-die throttling event */ 597 #define EMASK_TH2 0x0002 /* TH2Msk >tmid thermal event */ 598 #define EMASK_TH1 0x0001 /* TH1Msk Catastrophic on-die thermal event */ 599 600 #define GE_FERR_FSB(ferr) ( \ 601 ((ferr) & (GE_FSB0_FATAL|GE_FSB0_NF)) ? 0 : \ 602 ((ferr) & (GE_FSB1_FATAL|GE_FSB1_NF)) ? 1 : \ 603 (nb_chipset == INTEL_NB_7300) && \ 604 ((ferr) & (GE_FERR_FSB2_FATAL|GE_FERR_FSB2_NF)) ? 2 : \ 605 (nb_chipset == INTEL_NB_7300) && \ 606 ((ferr) & (GE_FERR_FSB3_FATAL|GE_FERR_FSB3_NF)) ? 3 : \ 607 -1) 608 609 #define GE_NERR_TO_FERR_FSB(nerr) \ 610 ((((nerr) & GE_NERR_FSB3_FATAL) ? GE_FERR_FSB3_FATAL : 0) | \ 611 (((nerr) & GE_NERR_FSB2_FATAL) ? GE_FERR_FSB2_FATAL : 0) | \ 612 (((nerr) & GE_FSB1_FATAL) ? GE_FSB1_FATAL : 0) | \ 613 (((nerr) & GE_FSB0_FATAL) ? GE_FSB0_FATAL : 0) | \ 614 (((nerr) & GE_NERR_FSB3_NF) ? GE_FERR_FSB3_NF : 0) | \ 615 (((nerr) & GE_NERR_FSB2_NF) ? GE_FERR_FSB2_NF : 0) | \ 616 (((nerr) & GE_FSB1_NF) ? GE_FSB1_NF : 0) | \ 617 (((nerr) & GE_FSB0_NF) ? GE_FSB0_NF : 0)) 618 619 #define GE_ERR_PEX(ferr) ( \ 620 ((ferr) & (GE_ESI_FATAL|GE_ESI_NF)) ? 0 : \ 621 ((nb_chipset == INTEL_NB_7300 || nb_chipset == INTEL_NB_5400) && \ 622 ((ferr) & (GE_PCIEX1_FATAL|GE_PCIEX1_NF))) ? 1 : \ 623 ((ferr) & (GE_PCIEX2_FATAL|GE_PCIEX2_NF)) ? 2 : \ 624 ((ferr) & (GE_PCIEX3_FATAL|GE_PCIEX3_NF)) ? 3 : \ 625 ((ferr) & (GE_PCIEX4_FATAL|GE_PCIEX4_NF)) ? 4 : \ 626 ((ferr) & (GE_PCIEX5_FATAL|GE_PCIEX5_NF)) ? 5 : \ 627 ((ferr) & (GE_PCIEX6_FATAL|GE_PCIEX6_NF)) ? 6 : \ 628 ((ferr) & (GE_PCIEX7_FATAL|GE_PCIEX7_NF)) ? 7 : \ 629 (nb_chipset == INTEL_NB_5400) && \ 630 ((ferr) & (GE_PCIEX8_FATAL|GE_PCIEX8_NF)) ? 8 : \ 631 ((ferr) & (GE_PCIEX9_FATAL|GE_PCIEX9_NF)) ? 9 : \ 632 -1) 633 634 #define GE_FERR_FATAL ((nb_chipset == INTEL_NB_7300) ? \ 635 (GE_INT_FATAL|GE_DMA_FATAL|GE_FERR_FSB3_FATAL|GE_FERR_FSB2_FATAL| \ 636 GE_FSB1_FATAL|GE_FSB0_FATAL|GE_FBD_FATAL|GE_PCIEX7_FATAL| \ 637 GE_PCIEX6_FATAL| GE_PCIEX5_FATAL|GE_PCIEX4_FATAL|GE_PCIEX3_FATAL| \ 638 GE_PCIEX2_FATAL| GE_ESI_FATAL) : \ 639 (GE_INT_FATAL|GE_DMA_FATAL|GE_FSB1_FATAL|GE_FSB0_FATAL|GE_FBD_FATAL| \ 640 GE_PCIEX7_FATAL|GE_PCIEX6_FATAL|GE_PCIEX5_FATAL|GE_PCIEX4_FATAL| \ 641 GE_PCIEX3_FATAL|GE_PCIEX2_FATAL|GE_ESI_FATAL)) 642 643 #define GE_NERR_FATAL ((nb_chipset == INTEL_NB_7300) ? \ 644 (GE_INT_FATAL|GE_DMA_FATAL|GE_NERR_FSB3_FATAL|GE_NERR_FSB2_FATAL| \ 645 GE_FSB1_FATAL|GE_FSB0_FATAL|GE_FBD_FATAL|GE_PCIEX7_FATAL| \ 646 GE_PCIEX6_FATAL|GE_PCIEX5_FATAL|GE_PCIEX4_FATAL|GE_PCIEX3_FATAL| \ 647 GE_PCIEX2_FATALGE_ESI_FATAL) : \ 648 (GE_INT_FATAL|GE_DMA_FATAL|GE_FSB1_FATAL|GE_FSB0_FATAL|GE_FBD_FATAL| \ 649 GE_PCIEX7_FATAL|GE_PCIEX6_FATAL|GE_PCIEX5_FATAL|GE_PCIEX4_FATAL| \ 650 GE_PCIEX3_FATAL|GE_PCIEX2_FATAL|GE_ESI_FATAL)) 651 652 #define GE_PCIEX_FATAL (GE_ESI_FATAL|GE_PCIEX1_FATAL|GE_PCIEX2_FATAL| \ 653 GE_PCIEX3_FATAL|GE_PCIEX4_FATAL|GE_PCIEX5_FATAL|GE_PCIEX6_FATAL| \ 654 GE_PCIEX7_FATAL) 655 #define GE_PCIEX_NF (GE_ESI_NF|GE_PCIEX1_NF|GE_PCIEX2_NF|GE_PCIEX3_NF| \ 656 GE_PCIEX4_NF|GE_PCIEX5_NF|GE_PCIEX6_NF|GE_PCIEX7_NF) 657 #define GE_FERR_FSB_FATAL ((nb_chipset == INTEL_NB_7300) ? \ 658 (GE_FSB0_FATAL|GE_FSB1_FATAL|GE_FERR_FSB2_FATAL|GE_FERR_FSB3_FATAL) : \ 659 (GE_FSB0_FATAL|GE_FSB1_FATAL)) 660 #define GE_NERR_FSB_FATAL ((nb_chipset == INTEL_NB_7300) ? \ 661 (GE_FSB0_FATAL|GE_FSB1_FATAL|GE_NERR_FSB2_FATAL|GE_NERR_FSB3_FATAL) : \ 662 (GE_FSB0_FATAL|GE_FSB1_FATAL)) 663 #define GE_FERR_FSB_NF ((nb_chipset == INTEL_NB_7300) ? \ 664 (GE_FSB0_NF|GE_FSB1_NF|GE_FERR_FSB2_NF|GE_FERR_FSB3_NF) : \ 665 (GE_FSB0_NF|GE_FSB1_NF)) 666 #define GE_NERR_FSB_NF ((nb_chipset == INTEL_NB_7300) ? \ 667 (GE_FSB0_NF|GE_FSB1_NF|GE_NERR_FSB2_NF|GE_NERR_FSB3_NF) : \ 668 (GE_FSB0_NF|GE_FSB1_NF)) 669 670 #define FERR_FBD_CHANNEL(reg) ((reg)>>28 & 3) 671 672 #define NB5000_STEPPING() nb_pci_getw(0, 0, 0, 8, 0) 673 674 #define FERR_GLOBAL_RD() ((nb_chipset == INTEL_NB_7300) ? \ 675 ((uint64_t)nb_pci_getl(0, 16, 2, \ 676 0x48, 0) << 32) | nb_pci_getl(0, 16, 2, \ 677 0x40, 0) : \ 678 (uint64_t)nb_pci_getl(0, 16, 2, 0x40, 0)) 679 #define NERR_GLOBAL_RD() nb_pci_getl(0, 16, 2, 0x44, 0) 680 #define FERR_FAT_FSB_RD(fsb, ip) ((nb_chipset == INTEL_NB_7300) ? \ 681 nb_pci_getb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc0 : 0x40, ip) : \ 682 nb_pci_getb(0, 16, 0, fsb ? 0x480 : 0x180, ip)) 683 #define FERR_NF_FSB_RD(fsb, ip) ((nb_chipset == INTEL_NB_7300) ? \ 684 nb_pci_getb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc1 : 0x41, ip) : \ 685 nb_pci_getb(0, 16, 0, fsb ? 0x481 : 0x181, ip)) 686 #define NERR_FAT_FSB_RD(fsb, ip) ((nb_chipset == INTEL_NB_7300) ? \ 687 nb_pci_getb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc2 : 0x42, ip) : \ 688 nb_pci_getb(0, 16, 0, fsb ? 0x482 : 0x182, ip)) 689 #define NERR_NF_FSB_RD(fsb, ip) ((nb_chipset == INTEL_NB_7300) ? \ 690 nb_pci_getb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc3 : 0x43, ip) : \ 691 nb_pci_getb(0, 16, 0, fsb ? 0x483 : 0x183, ip)) 692 693 #define NRECFSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 694 nb_pci_getl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc4 : 0x44, 0) : \ 695 nb_pci_getl(0, 16, 0, fsb ? 0x484 : 0x184, 0)) 696 #define NRECFSB_WR(fsb) \ 697 if (nb_chipset == INTEL_NB_7300) { \ 698 nb_pci_putl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc4 : 0x44, \ 699 0); \ 700 } else { \ 701 nb_pci_putl(0, 16, 0, fsb ? 0x484 : 0x184, 0); \ 702 } 703 #define RECFSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 704 nb_pci_getl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc8 : 0x48, 0) : \ 705 nb_pci_getl(0, 16, 0, fsb ? 0x488 : 0x188, 0)) 706 #define RECFSB_WR(fsb) \ 707 if (nb_chipset == INTEL_NB_7300) { \ 708 nb_pci_putl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc8 : 0x48, \ 709 0); \ 710 } else { \ 711 nb_pci_putl(0, 16, 0, fsb ? 0x488 : 0x188, 0); \ 712 } 713 #define NRECADDR_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 714 ((uint64_t)(nb_pci_getb(0, 17, (fsb & 2) ? 3 : 0, \ 715 (fsb & 1) ? 0xd0 : 0x50, 0)) << 32) | \ 716 nb_pci_getl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xcc : 0x4c, 0) : \ 717 ((uint64_t)(nb_pci_getb(0, 16, 0, fsb ? 0x490 : 0x190, 0)) << 32) | \ 718 nb_pci_getl(0, 16, 0, fsb ? 0x48c : 0x18c, 0)) 719 #define NRECADDR_WR(fsb) \ 720 if (nb_chipset == INTEL_NB_7300) { \ 721 nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd0 : 0x50, \ 722 0); \ 723 nb_pci_putl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xcc : 0x4c, \ 724 0); \ 725 } else { \ 726 nb_pci_putb(0, 16, 0, fsb ? 0x490 : 0x190, 0); \ 727 nb_pci_putl(0, 16, 0, fsb ? 0x48c : 0x18c, 0); \ 728 } 729 #define EMASK_FSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 730 nb_pci_getw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd2 : 0x52, 0) : \ 731 nb_pci_getw(0, 16, 0, fsb ? 0x492 : 0x192, 0)) 732 #define ERR0_FSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 733 nb_pci_getw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd4 : 0x54, 0) : \ 734 nb_pci_getw(0, 16, 0, fsb ? 0x494 : 0x194, 0)) 735 #define ERR1_FSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 736 nb_pci_getw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd6 : 0x56, 0) : \ 737 nb_pci_getw(0, 16, 0, fsb ? 0x496 : 0x196, 0)) 738 #define ERR2_FSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 739 nb_pci_getw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd8 : 0x58, 0) : \ 740 nb_pci_getw(0, 16, 0, fsb ? 0x498 : 0x198, 0)) 741 #define MCERR_FSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 742 nb_pci_getw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xda : 0x5a, 0) : \ 743 nb_pci_getw(0, 16, 0, fsb ? 0x49a : 0x19a, 0)) 744 745 #define FERR_GLOBAL_WR(val) \ 746 if (nb_chipset == INTEL_NB_7300) \ 747 { \ 748 nb_pci_putl(0, 16, 2, 0x48, (uint32_t)(val >> 32)); \ 749 nb_pci_putl(0, 16, 2, 0x40, (uint32_t)val); \ 750 } else { \ 751 nb_pci_putl(0, 16, 2, 0x40, (uint32_t)val); \ 752 } 753 #define NERR_GLOBAL_WR(val) nb_pci_putl(0, 16, 2, 0x44, val) 754 #define FERR_FAT_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ 755 nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc0 : 0x40, val) : \ 756 nb_pci_putb(0, 16, 0, fsb ? 0x480 : 0x180, val)) 757 #define FERR_NF_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ 758 nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc1 : 0x41, val) : \ 759 nb_pci_putb(0, 16, 0, fsb ? 0x481 : 0x181, val)) 760 #define NERR_FAT_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ 761 nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc2 : 0x42, val) : \ 762 nb_pci_putb(0, 16, 0, fsb ? 0x482 : 0x182, val)) 763 #define NERR_NF_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ 764 nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc3 : 0x43, val) : \ 765 nb_pci_putb(0, 16, 0, fsb ? 0x483 : 0x183, val)) 766 #define EMASK_FSB_WR(fsb, val) \ 767 { \ 768 if (nb_chipset == INTEL_NB_7300) \ 769 nb_pci_putw(0, 17, ((fsb) & 2) ? 3 : 0, \ 770 ((fsb) & 1) ? 0xd2 : 0x52, val); \ 771 else \ 772 nb_pci_putw(0, 16, 0, fsb ? 0x492 : 0x192, val); \ 773 } 774 #define ERR0_FSB_WR(fsb, val) \ 775 { \ 776 if (nb_chipset == INTEL_NB_7300) \ 777 nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \ 778 (fsb & 1) ? 0xd4 : 0x54, val); \ 779 else \ 780 nb_pci_putw(0, 16, 0, fsb ? 0x494 : 0x194, val); \ 781 } 782 #define ERR1_FSB_WR(fsb, val) \ 783 { \ 784 if (nb_chipset == INTEL_NB_7300) \ 785 nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \ 786 (fsb & 1) ? 0xd6 : 0x56, val); \ 787 else \ 788 nb_pci_putw(0, 16, 0, fsb ? 0x496 : 0x196, val); \ 789 } 790 #define ERR2_FSB_WR(fsb, val) \ 791 { \ 792 if (nb_chipset == INTEL_NB_7300) \ 793 nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \ 794 (fsb & 1) ? 0xd8 : 0x58, val); \ 795 else \ 796 nb_pci_putw(0, 16, 0, fsb ? 0x498 : 0x198, val); \ 797 } 798 #define MCERR_FSB_WR(fsb, val) \ 799 { \ 800 if (nb_chipset == INTEL_NB_7300) \ 801 nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \ 802 (fsb & 1) ? 0xda : 0x5a, val); \ 803 else \ 804 nb_pci_putw(0, 16, 0, fsb ? 0x49a : 0x19a, val); \ 805 } 806 807 #define NRECSF_RD() (nb_chipset == INTEL_NB_5000X || \ 808 nb_chipset == INTEL_NB_7300) ? ((uint64_t)( \ 809 nb_pci_getl(0, 16, 2, 0xb4, 0)) << 32) | \ 810 nb_pci_getl(0, 16, 2, 0xb0, 0) : 0LL 811 #define RECSF_RD() (nb_chipset == INTEL_NB_5000X || \ 812 nb_chipset == INTEL_NB_7300) ? ((uint64_t)( \ 813 nb_pci_getl(0, 16, 2, 0xbc, 0)) << 32) | \ 814 nb_pci_getl(0, 16, 2, 0xb8, 0) : 0LL 815 816 #define NRECSF_WR() if (nb_chipset == INTEL_NB_5000X || \ 817 nb_chipset == INTEL_NB_7300) { \ 818 nb_pci_putl(0, 16, 2, 0xbc, 0); \ 819 nb_pci_putl(0, 16, 2, 0xb0, 0); \ 820 } 821 #define RECSF_WR() if (nb_chipset == INTEL_NB_5000X || \ 822 nb_chipset == INTEL_NB_7300) { \ 823 nb_pci_putl(0, 16, 2, 0xbc, 0); \ 824 nb_pci_putl(0, 16, 2, 0xb8, 0); \ 825 } 826 827 #define FERR_FAT_INT_RD(ip) (((nb_chipset == INTEL_NB_5400) ? \ 828 ((uint16_t)nb_pci_getb(0, 16, 2, 0xc1, ip) << 8) : (uint16_t)0) | \ 829 nb_pci_getb(0, 16, 2, 0xc0, ip)) 830 #define FERR_NF_INT_RD(ip) ((nb_chipset == INTEL_NB_5400) ? \ 831 ((uint16_t)nb_pci_getb(0, 16, 2, 0xc3, ip) << 8) | \ 832 nb_pci_getb(0, 16, 2, 0xc2, ip) : \ 833 (uint16_t)nb_pci_getb(0, 16, 2, 0xc1, ip)) 834 #define NERR_FAT_INT_RD(ip) ((nb_chipset == INTEL_NB_5400) ? \ 835 ((uint16_t)nb_pci_getb(0, 16, 2, 0xc5, ip) << 8) | \ 836 nb_pci_getb(0, 16, 2, 0xc4, ip) : \ 837 (uint16_t)nb_pci_getb(0, 16, 2, 0xc2, ip)) 838 #define NERR_NF_INT_RD(ip) ((nb_chipset == INTEL_NB_5400) ? \ 839 ((uint16_t)nb_pci_getb(0, 16, 2, 0xc7, ip) << 8) | \ 840 nb_pci_getb(0, 16, 2, 0xc6, ip) : \ 841 (uint16_t)nb_pci_getb(0, 16, 2, 0xc3, ip)) 842 #define EMASK_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \ 843 nb_pci_getl(0, 16, 2, 0xd0, 0) : nb_pci_getb(0, 16, 2, 0xcc, 0)) 844 #define ERR0_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \ 845 nb_pci_getl(0, 16, 2, 0xd4, 0) : nb_pci_getb(0, 16, 2, 0xd0, 0)) 846 #define ERR1_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \ 847 nb_pci_getl(0, 16, 2, 0xd8, 0) : nb_pci_getb(0, 16, 2, 0xd1, 0)) 848 #define ERR2_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \ 849 nb_pci_getl(0, 16, 2, 0xdc, 0) : nb_pci_getb(0, 16, 2, 0xd2, 0)) 850 #define MCERR_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \ 851 nb_pci_getl(0, 16, 2, 0xe0, 0) : nb_pci_getb(0, 16, 2, 0xd3, 0)) 852 853 #define FERR_FAT_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 854 nb_pci_putb(0, 16, 2, 0xc0, \ 855 val & 0xff); \ 856 nb_pci_putb(0, 16, 2, 0xc1, val >> 8); \ 857 } else { \ 858 nb_pci_putb(0, 16, 2, 0xc0, val); \ 859 } 860 #define FERR_NF_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 861 nb_pci_putb(0, 16, 2, 0xc2, \ 862 val & 0xff); \ 863 nb_pci_putb(0, 16, 2, 0xc3, val >> 8); \ 864 } else { \ 865 nb_pci_putb(0, 16, 2, 0xc1, val); \ 866 } 867 #define NERR_FAT_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 868 nb_pci_putb(0, 16, 2, 0xc4, \ 869 val & 0xff); \ 870 nb_pci_putb(0, 16, 2, 0xc5, val >> 8); \ 871 } else { \ 872 nb_pci_putb(0, 16, 2, 0xc2, val); \ 873 } 874 #define NERR_NF_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 875 nb_pci_putb(0, 16, 2, 0xc6, \ 876 val & 0xff); \ 877 nb_pci_putb(0, 16, 2, 0xc7, val >> 8); \ 878 } else { \ 879 nb_pci_putb(0, 16, 2, 0xc3, val); \ 880 } 881 #define EMASK_5000_INT_WR(val) nb_pci_putb(0, 16, 2, 0xcc, val) 882 #define EMASK_5400_INT_WR(val) nb_pci_putl(0, 16, 2, 0xd0, val) 883 #define EMASK_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 884 EMASK_5400_INT_WR(val); \ 885 } else { \ 886 EMASK_5000_INT_WR(val); \ 887 } 888 #define ERR0_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 889 nb_pci_putl(0, 16, 2, 0xd4, val); \ 890 } else { \ 891 nb_pci_putb(0, 16, 2, 0xd0, val); \ 892 } 893 #define ERR1_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 894 nb_pci_putl(0, 16, 2, 0xd8, val); \ 895 } else { \ 896 nb_pci_putb(0, 16, 2, 0xd1, val); \ 897 } 898 #define ERR2_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 899 nb_pci_putl(0, 16, 2, 0xdc, val); \ 900 } else { \ 901 nb_pci_putb(0, 16, 2, 0xd2, val); \ 902 } 903 #define MCERR_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 904 nb_pci_putl(0, 16, 2, 0xe0, val); \ 905 } else { \ 906 nb_pci_putb(0, 16, 2, 0xd3, val); \ 907 } 908 909 #define NRECINT_RD() nb_pci_getl(0, 16, 2, \ 910 nb_chipset == INTEL_NB_5400 ? 0xc8 : 0xc4, 0) 911 #define RECINT_RD() nb_pci_getl(0, 16, 2, \ 912 nb_chipset == INTEL_NB_5400 ? 0xcc : 0xc8, 0) 913 914 #define NRECINT_WR() nb_pci_putl(0, 16, 2, \ 915 nb_chipset == INTEL_NB_5400 ? 0xc8 : 0xc4, 0) 916 #define RECINT_WR() nb_pci_putl(0, 16, 2, \ 917 nb_chipset == INTEL_NB_5400 ? 0xcc : 0xc8, 0) 918 919 920 #define FERR_FAT_FBD_RD(ip) nb_pci_getl(0, 16, 1, 0x98, ip) 921 #define NERR_FAT_FBD_RD(ip) nb_pci_getl(0, 16, 1, 0x9c, ip) 922 #define FERR_NF_FBD_RD(ip) nb_pci_getl(0, 16, 1, 0xa0, ip) 923 #define NERR_NF_FBD_RD(ip) nb_pci_getl(0, 16, 1, 0xa4, ip) 924 #define EMASK_FBD_RD() nb_pci_getl(0, 16, 1, 0xa8, 0) 925 #define ERR0_FBD_RD() nb_pci_getl(0, 16, 1, 0xac, 0) 926 #define ERR1_FBD_RD() nb_pci_getl(0, 16, 1, 0xb0, 0) 927 #define ERR2_FBD_RD() nb_pci_getl(0, 16, 1, 0xb4, 0) 928 #define MCERR_FBD_RD() nb_pci_getl(0, 16, 1, 0xb8, 0) 929 930 #define FERR_FAT_FBD_WR(val) nb_pci_putl(0, 16, 1, 0x98, val) 931 #define NERR_FAT_FBD_WR(val) nb_pci_putl(0, 16, 1, 0x9c, val) 932 #define FERR_NF_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xa0, val) 933 #define NERR_NF_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xa4, val) 934 #define EMASK_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xa8, val) 935 #define ERR0_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xac, val) 936 #define ERR1_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb0, val) 937 #define ERR2_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb4, val) 938 #define MCERR_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb8, val) 939 940 #define NRECMEMA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 941 nb_pci_getw(0, (branch) ? 22 : 21, 1, 0xbe, 0) : \ 942 nb_pci_getw(0, 16, 1, 0xbe, 0)) 943 #define NRECMEMB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 944 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xc0, 0) : \ 945 nb_pci_getl(0, 16, 1, 0xc0, 0)) 946 #define NRECFGLOG_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 947 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0x74, 0) : \ 948 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0x74 : 0xc4, 0)) 949 #define NRECFBDA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 950 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xc4, 0) : \ 951 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xc4 : 0xc8, 0)) 952 #define NRECFBDB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 953 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xc8, 0) : \ 954 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xc8 : 0xcc, 0)) 955 #define NRECFBDC_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 956 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xcc, 0) : \ 957 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xcc : 0xd0, 0)) 958 #define NRECFBDD_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 959 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xd0, 0) : \ 960 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xd0 : 0xd4, 0)) 961 #define NRECFBDE_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 962 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xd4, 0) : \ 963 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xd4 : 0xd8, 0)) 964 #define NRECFBDF_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 965 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xd8, 0) : \ 966 nb_chipset == INTEL_NB_7300 ? nb_pci_getw(0, 16, 1, 0xd8, 0) : 0) 967 #define REDMEMB_RD() (nb_chipset == INTEL_NB_5400 ? \ 968 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0x7c, 0) : \ 969 nb_pci_getl(0, 16, 1, 0x7c, 0)) 970 #define RECMEMA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 971 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xe0, 0) & 0xffffff : \ 972 nb_pci_getw(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe0 : 0xe2, 0)) 973 #define RECMEMB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 974 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xe4, 0) : \ 975 nb_pci_getl(0, 16, 1, 0xe4, 0)) 976 #define RECFGLOG_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 977 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0x78, 0) : \ 978 nb_chipset == INTEL_NB_7300 ? nb_pci_getl(0, 16, 1, 0x78, 0) : \ 979 nb_pci_getl(0, 16, 1, 0xe8, 0)) 980 #define RECFBDA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 981 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xe8, 0) : \ 982 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe8 : 0xec, 0)) 983 #define RECFBDB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 984 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xec, 0) : \ 985 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xec : 0xf0, 0)) 986 #define RECFBDC_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 987 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xf0, 0) : \ 988 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf0 : 0xf4, 0)) 989 #define RECFBDD_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 990 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xf4, 0) : \ 991 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf4 : 0xf8, 0)) 992 #define RECFBDE_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 993 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xf8, 0) : \ 994 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf8 : 0xfc, 0)) 995 #define RECFBDF_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 996 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xfc, 0) : \ 997 nb_chipset == INTEL_NB_7300 ? nb_pci_getw(0, 16, 1, 0xfc, 0) : 0) 998 #define NRECMEMA_WR(branch) (nb_chipset == INTEL_NB_5400 ? \ 999 nb_pci_putw(0, (branch) ? 22 : 21, 1, 0xbe, 0) : \ 1000 nb_pci_putw(0, 16, 1, 0xbe, 0)) 1001 #define NRECMEMB_WR(branch) (nb_chipset == INTEL_NB_5400 ? \ 1002 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xc0, 0) : \ 1003 nb_pci_putl(0, 16, 1, 0xc0, 0)) 1004 #define NRECFGLOG_WR(branch) \ 1005 if (nb_chipset == INTEL_NB_5400) \ 1006 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0x74, 0); \ 1007 else if (nb_chipset == INTEL_NB_7300) \ 1008 nb_pci_putl(0, 16, 1, 0x74, 0); \ 1009 else \ 1010 nb_pci_putl(0, 16, 1, 0xc4, 0) 1011 #define NRECFBDA_WR(branch) \ 1012 if (nb_chipset == INTEL_NB_5400) \ 1013 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xc4, 0); \ 1014 else if (nb_chipset == INTEL_NB_7300) \ 1015 nb_pci_putl(0, 16, 1, 0xc4, 0); \ 1016 else \ 1017 nb_pci_putl(0, 16, 1, 0xc8, 0) 1018 #define NRECFBDB_WR(branch) \ 1019 if (nb_chipset == INTEL_NB_5400) \ 1020 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xc8, 0); \ 1021 else if (nb_chipset == INTEL_NB_7300) \ 1022 nb_pci_putl(0, 16, 1, 0xc8, 0); \ 1023 else \ 1024 nb_pci_putl(0, 16, 1, 0xcc, 0) 1025 #define NRECFBDC_WR(branch) \ 1026 if (nb_chipset == INTEL_NB_5400) \ 1027 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xcc, 0); \ 1028 else if (nb_chipset == INTEL_NB_7300) \ 1029 nb_pci_putl(0, 16, 1, 0xcc, 0); \ 1030 else \ 1031 nb_pci_putl(0, 16, 1, 0xd0, 0) 1032 #define NRECFBDD_WR(branch) \ 1033 if (nb_chipset == INTEL_NB_5400) \ 1034 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xd0, 0); \ 1035 else if (nb_chipset == INTEL_NB_7300) \ 1036 nb_pci_putl(0, 16, 1, 0xd0, 0); \ 1037 else \ 1038 nb_pci_putl(0, 16, 1, 0xd4, 0) 1039 #define NRECFBDE_WR(branch) \ 1040 if (nb_chipset == INTEL_NB_5400) \ 1041 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xd4, 0); \ 1042 else if (nb_chipset == INTEL_NB_7300) \ 1043 nb_pci_putl(0, 16, 1, 0xd4, 0); \ 1044 else \ 1045 nb_pci_putl(0, 16, 1, 0xd8, 0) 1046 #define NRECFBDF_WR(branch) \ 1047 if (nb_chipset == INTEL_NB_5400) \ 1048 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xd8, 0); \ 1049 else if (nb_chipset == INTEL_NB_7300) \ 1050 nb_pci_putw(0, 16, 1, 0xd8, 0); 1051 #define REDMEMB_WR(branch) \ 1052 if (nb_chipset == INTEL_NB_5400) \ 1053 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0x7c, 0); \ 1054 else \ 1055 nb_pci_putl(0, 16, 1, 0x7c, 0) 1056 #define RECMEMA_WR(branch) \ 1057 if (nb_chipset == INTEL_NB_5400) \ 1058 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xe0, 0); \ 1059 else \ 1060 nb_pci_putw(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe0 : \ 1061 0xe2, 0) 1062 #define RECMEMB_WR(branch) \ 1063 if (nb_chipset == INTEL_NB_5400) \ 1064 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xe4, 0); \ 1065 else \ 1066 nb_pci_putl(0, 16, 1, 0xe4, 0) 1067 #define RECFGLOG_WR(branch) \ 1068 if (nb_chipset == INTEL_NB_5400) \ 1069 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0x78, 0); \ 1070 else if (nb_chipset == INTEL_NB_7300) \ 1071 nb_pci_putl(0, 16, 1, 0x78, 0); \ 1072 else \ 1073 nb_pci_putl(0, 16, 1, 0xe8, 0) 1074 #define RECFBDA_WR(branch) \ 1075 if (nb_chipset == INTEL_NB_5400) \ 1076 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xe8, 0); \ 1077 else if (nb_chipset == INTEL_NB_7300) \ 1078 nb_pci_putl(0, 16, 1, 0xe8, 0); \ 1079 else \ 1080 nb_pci_putl(0, 16, 1, 0xec, 0) 1081 #define RECFBDB_WR(branch) \ 1082 if (nb_chipset == INTEL_NB_5400) \ 1083 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xec, 0); \ 1084 else if (nb_chipset == INTEL_NB_7300) \ 1085 nb_pci_putl(0, 16, 1, 0xec, 0); \ 1086 else \ 1087 nb_pci_putl(0, 16, 1, 0xf0, 0) 1088 #define RECFBDC_WR(branch) \ 1089 if (nb_chipset == INTEL_NB_5400) \ 1090 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xf0, 0); \ 1091 else if (nb_chipset == INTEL_NB_7300) \ 1092 nb_pci_putl(0, 16, 1, 0xf0, 0); \ 1093 else \ 1094 nb_pci_putl(0, 16, 1, 0xf4, 0) 1095 #define RECFBDD_WR(branch) \ 1096 if (nb_chipset == INTEL_NB_5400) \ 1097 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xf4, 0); \ 1098 else if (nb_chipset == INTEL_NB_7300) \ 1099 nb_pci_putl(0, 16, 1, 0xf4, 0); \ 1100 else \ 1101 nb_pci_putl(0, 16, 1, 0xf8, 0) 1102 #define RECFBDE_WR(branch) \ 1103 if (nb_chipset == INTEL_NB_5400) \ 1104 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xf8, 0); \ 1105 else if (nb_chipset == INTEL_NB_7300) \ 1106 nb_pci_putl(0, 16, 1, 0xf8, 0); \ 1107 else \ 1108 nb_pci_putl(0, 16, 1, 0xfc, 0) 1109 #define RECFBDF_WR(branch) \ 1110 if (nb_chipset == INTEL_NB_5400) \ 1111 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xfc, 0); \ 1112 else if (nb_chipset == INTEL_NB_7300) \ 1113 nb_pci_putw(0, 16, 1, 0xf8, 0); \ 1114 1115 #define FERR_NF_MEM_RD(ip) nb_pci_getl(0, 16, 1, 0xa0, ip) 1116 #define NERR_NF_MEM_RD(ip) nb_pci_getl(0, 16, 1, 0xa4, ip) 1117 #define EMASK_MEM_RD() nb_pci_getl(0, 16, 1, 0xa8, 0) 1118 #define ERR0_MEM_RD() nb_pci_getl(0, 16, 1, 0xac, 0) 1119 #define ERR1_MEM_RD() nb_pci_getl(0, 16, 1, 0xb0, 0) 1120 #define ERR2_MEM_RD() nb_pci_getl(0, 16, 1, 0xb4, 0) 1121 #define MCERR_MEM_RD() nb_pci_getl(0, 16, 1, 0xb8, 0) 1122 #define FERR_NF_MEM_WR(val) \ 1123 nb_pci_putl(0, 16, 1, 0xa0, (val)) 1124 #define NERR_NF_MEM_WR(val) \ 1125 nb_pci_putl(0, 16, 1, 0xa4, (val)) 1126 #define EMASK_MEM_WR(val) \ 1127 nb_pci_putl(0, 16, 1, 0xa8, (val)) 1128 #define ERR0_MEM_WR(val) \ 1129 nb_pci_putl(0, 16, 1, 0xac, (val)) 1130 #define ERR1_MEM_WR(val) \ 1131 nb_pci_putl(0, 16, 1, 0xb0, (val)) 1132 #define ERR2_MEM_WR(val) \ 1133 nb_pci_putl(0, 16, 1, 0xb4, (val)) 1134 #define MCERR_MEM_WR(val) \ 1135 nb_pci_putl(0, 16, 1, 0xb8, (val)) 1136 #define VALIDLOG_RD(branch) \ 1137 nb_pci_getl(0, (branch) ? 22 : 21, 0, 0x18c, 0) 1138 #define MEM_NRECMEMA_RD(branch) \ 1139 nb_pci_getl(0, (branch) ? 22 : 21, 0, 0x190, 0) 1140 #define MEM_NRECMEMB_RD(branch) \ 1141 nb_pci_getl(0, (branch) ? 22 : 21, 0, 0x194, 0) 1142 #define MEM_REDMEMA_RD(branch) \ 1143 nb_pci_getl(0, (branch) ? 22 : 21, 0, 0x198, 0) 1144 #define MEM_REDMEMB_RD(branch) \ 1145 nb_pci_getl(0, (branch) ? 22 : 21, 0, 0x19c, 0) 1146 #define MEM_RECMEMA_RD(branch) \ 1147 nb_pci_getl(0, (branch) ? 22 : 21, 0, 0x1a0, 0) 1148 #define MEM_RECMEMB_RD(branch) \ 1149 nb_pci_getl(0, (branch) ? 22 : 21, 0, 0x1a4, 0) 1150 #define MEM_CERRCNT_RD(branch) nb_pci_getl(0, 21, 0, 0x180, 0) 1151 #define MEM_CERRCNT_EXT_RD(branch) nb_pci_getw(0, 21, 0, 0x184, 0) 1152 #define MEM_NRECMEMA_WR(branch) \ 1153 nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x190, 0) 1154 #define MEM_NRECMEMB_WR(branch) \ 1155 nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x194, 0) 1156 #define MEM_REDMEMA_WR(branch) \ 1157 nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x198, 0) 1158 #define MEM_REDMEMB_WR(branch) \ 1159 nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x19c, 0) 1160 #define MEM_RECMEMA_WR(branch) \ 1161 nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x1a0, 0) 1162 #define MEM_RECMEMB_WR(branch) \ 1163 nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x1a4, 0) 1164 1165 #define MC_RD() nb_pci_getl(0, 16, 1, 0x40, 0) 1166 #define MC_WR(val) nb_pci_putl(0, 16, 1, 0x40, val) 1167 #define MCA_RD() nb_pci_getl(0, 16, 1, 0x58, 0) 1168 #define TOLM_RD() nb_pci_getw(0, 16, 1, 0x6c, 0) 1169 1170 #define MTR_5100_RD(channel, rank) ((rank) < 4 ? \ 1171 nb_pci_getw(0, (channel) == 0 ? 21 : 22, 0, 0x154 + ((rank) * 2), 0) : \ 1172 nb_pci_getw(0, (channel) == 0 ? 21 : 22, 0, 0x1b0 + (((rank) & 3) * 2),\ 1173 0)) 1174 1175 #define MTR_RD(branch, dimm) (nb_chipset == INTEL_NB_5100 ? \ 1176 MTR_5100_RD(branch, dimm) : \ 1177 nb_chipset == INTEL_NB_5400 ? \ 1178 nb_pci_getw(0, (branch) == 0 ? 21 : 22, 0, 0x80 + dimm * 2, 0) : \ 1179 ((branch) == 0) ? \ 1180 nb_pci_getw(0, 21, 0, \ 1181 dimm >= 4 ? 0x82 + (dimm & 3) * 4 : 0x80 + dimm * 4, 0) : \ 1182 (nb_number_memory_controllers == 2) ? \ 1183 nb_pci_getw(0, 22, 0, \ 1184 dimm >= 4 ? 0x82 + (dimm & 3) * 4 : 0x80 + dimm * 4, 0) : 0) 1185 #define MIR_RD(reg) nb_pci_getw(0, 16, 1, 0x80 + ((reg)*4), 0) 1186 1187 #define DMIR_RD(branch, reg) \ 1188 nb_chipset == INTEL_NB_5100 ? \ 1189 nb_pci_getl(0, ((branch) == 0) ? 21 : 22, 0, 0x15c + ((reg)*4), 0) : \ 1190 ((branch) == 0) ? nb_pci_getl(0, 21, 0, 0x90 + ((reg)*4), 0) : \ 1191 (nb_number_memory_controllers == 2) ? \ 1192 nb_pci_getl(0, 22, 0, 0x90 + ((reg)*4), 0) : 0 1193 1194 #define SPCPC_RD(branch) (nb_chipset == INTEL_NB_5000P || \ 1195 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1196 nb_chipset == INTEL_NB_5000Z ? \ 1197 (((branch) == 0) ? \ 1198 (uint32_t)nb_pci_getb(0, 21, 0, 0x40, 0) : \ 1199 (nb_number_memory_controllers == 2) ? \ 1200 (uint32_t)nb_pci_getb(0, 22, 0, 0x40, 0) : 0) : \ 1201 nb_pci_getl(0, ((branch) == 0) ? 21 : 22, 0, 0x40, 0)) 1202 1203 #define SPCPC_SPARE_ENABLE (nb_chipset == INTEL_NB_5000P || \ 1204 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1205 nb_chipset == INTEL_NB_5000Z ? 1 : 0x20) 1206 #define SPCPC_SPRANK(spcpc) (nb_chipset == INTEL_NB_5000P || \ 1207 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1208 nb_chipset == INTEL_NB_5000Z ? \ 1209 (((spcpc) >> 1) & 7) : ((spcpc) & 0xf)) 1210 1211 #define SPCPS_RD(branch) ((branch) == 0) ? \ 1212 nb_pci_getb(0, 21, 0, nb_chipset == INTEL_NB_5000P || \ 1213 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1214 nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0) : \ 1215 (nb_number_memory_controllers == 2) ? \ 1216 nb_pci_getb(0, 22, 0, nb_chipset == INTEL_NB_5000P || \ 1217 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1218 nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0) : 0 1219 1220 #define SPCPS_WR(branch) \ 1221 if ((branch) == 0) { \ 1222 nb_pci_putb(0, 21, 0, nb_chipset == INTEL_NB_5000P || \ 1223 nb_chipset == INTEL_NB_5000X || \ 1224 nb_chipset == INTEL_NB_5000V || \ 1225 nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0); \ 1226 } else if (nb_number_memory_controllers == 2) { \ 1227 nb_pci_putb(0, 22, 0, nb_chipset == INTEL_NB_5000P || \ 1228 nb_chipset == INTEL_NB_5000X || \ 1229 nb_chipset == INTEL_NB_5000V || \ 1230 nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0); \ 1231 } 1232 1233 #define SPCPS_SPARE_DEPLOYED (nb_chipset == INTEL_NB_5000P || \ 1234 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1235 nb_chipset == INTEL_NB_5000Z ? 0x11 : 0x60) 1236 #define SPCPS_FAILED_RANK(spcps) (nb_chipset == INTEL_NB_5000P || \ 1237 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1238 nb_chipset == INTEL_NB_5000Z ? (((spcps) >> 1) & 7) : ((spcps) & 0xf)) 1239 1240 #define UERRCNT_RD(branch) ((branch) == 0) ? \ 1241 nb_pci_getl(0, 21, 0, 0xa4, 0) : \ 1242 (nb_number_memory_controllers == 2) ? \ 1243 nb_pci_getl(0, 22, 0, 0xa4, 0) : 0 1244 #define CERRCNT_RD(branch) ((branch) == 0) ? \ 1245 nb_pci_getl(0, 21, 0, 0xa8, 0) : \ 1246 (nb_number_memory_controllers == 2) ? \ 1247 nb_pci_getl(0, 22, 0, 0xa8, 0) : 0 1248 #define CERRCNTA_RD(branch, channel) \ 1249 nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \ 1250 (channel & 1) == 0 ? 0xe0 : 0xf0, 0) 1251 #define CERRCNTB_RD(branch, channel) \ 1252 nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \ 1253 (channel & 1) == 0 ? 0xe4 : 0xf4, 0) 1254 #define CERRCNTC_RD(branch, channel) \ 1255 (nb_chipset == INTEL_NB_7300 ? \ 1256 nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \ 1257 (channel & 1) == 0 ? 0xe8 : 0xf8, 0) : 0) 1258 #define CERRCNTD_RD(branch, channel) \ 1259 (nb_chipset == INTEL_NB_7300 ? \ 1260 nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \ 1261 (channel & 1) == 0 ? 0xec : 0xfc, 0) : 0) 1262 #define BADRAMA_RD(branch) ((branch) == 0) ? \ 1263 nb_pci_getl(0, 21, 0, 0xac, 0) : \ 1264 (nb_number_memory_controllers == 2) ? \ 1265 nb_pci_getl(0, 22, 0, 0xac, 0) : 0 1266 #define BADRAMB_RD(branch) ((branch) == 0) ? \ 1267 nb_pci_getw(0, 21, 0, 0xb0, 0) : \ 1268 (nb_number_memory_controllers == 2) ? \ 1269 nb_pci_getw(0, 22, 0, 0xb0, 0) : 0 1270 #define BADCNT_RD(branch) ((branch) == 0) ? \ 1271 nb_pci_getl(0, 21, 0, 0xb4, 0) : \ 1272 (nb_number_memory_controllers == 2) ? \ 1273 nb_pci_getl(0, 22, 0, 0xb4, 0) : 0 1274 1275 #define UERRCNT_WR(branch, val) ((branch) == 0) ? \ 1276 nb_pci_putl(0, 21, 0, 0xa4, val) : \ 1277 (nb_number_memory_controllers == 2) ? \ 1278 nb_pci_putl(0, 22, 0, 0xa4, val) \ 1279 : 0 1280 #define CERRCNT_WR(branch, val) ((branch) == 0) ? \ 1281 nb_pci_putl(0, 21, 0, 0xa8, val) : \ 1282 (nb_number_memory_controllers == 2) ? \ 1283 nb_pci_putl(0, 22, 0, 0xa8, val) : 0 1284 #define BADRAMA_WR(branch, val) ((branch) == 0) ? \ 1285 nb_pci_putl(0, 21, 0, 0xac, val) : \ 1286 (nb_number_memory_controllers == 2) ? \ 1287 nb_pci_putl(0, 22, 0, 0xac, val) : 0 1288 #define BADRAMB_WR(branch, val) ((branch) == 0) ? \ 1289 nb_pci_putw(0, 21, 0, 0xb0, val) : \ 1290 (nb_number_memory_controllers == 2) ? \ 1291 nb_pci_putw(0, 22, 0, 0xb0) : 0 1292 #define BADCNT_WR(branch, val) ((branch) == 0) ? \ 1293 nb_pci_putl(0, 21, 0, 0xb4, val) : \ 1294 (nb_number_memory_controllers == 2) ? \ 1295 nb_pci_putl(0, 22, 0, 0xb4, val) : 0 1296 1297 #define SPD_RD(branch, channel) \ 1298 nb_chipset == INTEL_NB_5100 ? nb_pci_getw(0, 16, 1, 0x48, 0) : \ 1299 ((branch) == 0) ? \ 1300 nb_pci_getw(0, 21, 0, 0x74 + ((channel) * 2), 0) : \ 1301 (nb_number_memory_controllers == 2) ? \ 1302 nb_pci_getw(0, 22, 0, 0x74 + ((channel) * 2), 0) : 0 1303 #define SPDCMDRD(branch, channel) ((branch) == 0) ? \ 1304 nb_pci_getl(0, 21, 0, 0x78 + ((channel) * 4), 0) : \ 1305 (nb_number_memory_controllers == 2) ? \ 1306 nb_pci_getl(0, 22, 0, 0x78 + ((channel) * 4), 0) : 0 1307 1308 #define SPDCMD1_1_WR(val) nb_pci_putl(0, 21, 0, 0x7c, val) 1309 #define SPDCMD_WR(branch, channel, val) \ 1310 if (nb_chipset == INTEL_NB_5100) \ 1311 nb_pci_putl(0, 16, 1, 0x4c, val); \ 1312 else if ((branch) == 0) \ 1313 nb_pci_putl(0, 21, 0, 0x78 + ((channel) * 4), val); \ 1314 else if (nb_number_memory_controllers == 2) \ 1315 nb_pci_putl(0, 22, 0, 0x78 + ((channel) * 4), val) 1316 1317 #define UNCERRSTS_RD(pex) nb_pci_getl(0, pex, 0, 0x104, 0) 1318 #define UNCERRMSK_RD(pex) nb_pci_getl(0, pex, 0, 0x108, 0) 1319 #define PEX_FAT_FERR_ESI_RD() nb_pci_getl(0, 0, 0, 0x154, 0) 1320 #define PEX_FAT_NERR_ESI_RD() nb_pci_getl(0, 0, 0, 0x15c, 0) 1321 #define PEX_NF_FERR_ESI_RD() nb_pci_getl(0, 0, 0, 0x158, 0) 1322 #define PEX_NF_NERR_ESI_RD() nb_pci_getl(0, 0, 0, 0x160, 0) 1323 #define PEX_ERR_DOCMD_RD(pex) ((nb_chipset == INTEL_NB_5400) ? \ 1324 nb_pci_getw(0, pex, 0, 0x144, 0) : nb_pci_getl(0, pex, 0, 0x144, 0)) 1325 #define PEX_ERR_PIN_MASK_RD(pex) nb_pci_getw(0, pex, 0, 0x146, 0) 1326 #define EMASK_UNCOR_PEX_RD(pex) nb_pci_getl(0, pex, 0, 0x148, 0) 1327 #define EMASK_COR_PEX_RD(pex) nb_pci_getl(0, pex, 0, 0x14c, 0) 1328 #define EMASK_RP_PEX_RD(pex) nb_pci_getl(0, pex, 0, 0x150, 0) 1329 1330 #define UNCERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x104, val) 1331 #define UNCERRMSK_WR(pex, val) nb_pci_putl(0, pex, 0, 0x108, val) 1332 #define PEX_FAT_FERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x154, val) 1333 #define PEX_FAT_NERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x15c, val) 1334 #define PEX_NF_FERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x158, val) 1335 #define PEX_NF_NERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x160, val) 1336 #define PEX_ERR_DOCMD_WR(pex, val) ((nb_chipset == INTEL_NB_5400) ? \ 1337 nb_pci_putw(0, pex, 0, 0x144, val) : nb_pci_putl(0, pex, 0, 0x144, val)) 1338 #define PEX_ERR_PIN_MASK_WR(pex, val) nb_pci_putw(0, pex, 0, 0x146, val) 1339 #define EMASK_UNCOR_PEX_WR(pex, val) nb_pci_putl(0, pex, 0, 0x148, val) 1340 #define EMASK_COR_PEX_WR(pex, val) nb_pci_putl(0, pex, 0, 0x14c, val) 1341 #define EMASK_RP_PEX_WR(pex, val) nb_pci_putl(0, pex, 0, 0x150, val) 1342 1343 #define PEX_FAT_FERR_RD(pex, ip) nb_pci_getl(0, pex, 0, 0x154, ip) 1344 #define PEX_FAT_NERR_RD(pex, ip) nb_pci_getl(0, pex, 0, 0x15c, ip) 1345 #define PEX_NF_FERR_RD(pex, ip) nb_pci_getl(0, pex, 0, 0x158, ip) 1346 #define PEX_NF_NERR_RD(pex, ip) nb_pci_getl(0, pex, 0, 0x160, ip) 1347 #define UNCERRSEV_RD(pex) nb_pci_getl(0, pex, 0, 0x10c, 0) 1348 #define CORERRSTS_RD(pex) nb_pci_getl(0, pex, 0, 0x110, 0) 1349 #define RPERRSTS_RD(pex) nb_pci_getl(0, pex, 0, 0x130, 0) 1350 #define RPERRSID_RD(pex) nb_pci_getl(0, pex, 0, 0x134, 0) 1351 #define AERRCAPCTRL_RD(pex) nb_pci_getl(0, pex, 0, 0x118, 0) 1352 #define PEXDEVSTS_RD(pex) nb_pci_getw(0, pex, 0, 0x76, 0) 1353 #define PEXROOTCTL_RD(pex) nb_pci_getw(0, pex, 0, 0x88, 0) 1354 1355 #define PEX_FAT_FERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x154, val) 1356 #define PEX_FAT_NERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x15c, val) 1357 #define PEX_NF_FERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x158, val) 1358 #define PEX_NF_NERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x160, val) 1359 #define CORERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x110, val) 1360 #define UNCERRSEV_WR(pex, val) nb_pci_putl(0, pex, 0, 0x10c, val) 1361 #define RPERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x130, val) 1362 #define PEXDEVSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x76, val) 1363 #define PEXROOTCTL_WR(pex, val) nb_pci_putw(0, pex, 0, 0x88, val) 1364 1365 #define PCISTS_RD(ip) nb_pci_getw(0, 8, 0, 0x6, ip) 1366 #define PCIDEVSTS_RD() nb_pci_getw(0, 8, 0, 0x76, 0) 1367 #define PCISTS_WR(val) nb_pci_putw(0, 8, 0, 0x6, val) 1368 #define PCIDEVSTS_WR(val) nb_pci_putw(0, 8, 0, 0x76, val) 1369 1370 #define RANK_MASK (nb_chipset != INTEL_NB_7300 ? 7 : 0xf) 1371 #define CAS_MASK (nb_chipset == INTEL_NB_5000P || \ 1372 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1373 nb_chipset == INTEL_NB_5000Z ? 0xfff : 0x1fff) 1374 #define RAS_MASK (nb_chipset == INTEL_NB_5000P || \ 1375 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1376 nb_chipset == INTEL_NB_5000Z ? 0x7fff : 0xffff) 1377 #define BANK_MASK 7 1378 1379 #define DMIR_RANKS(dmir, rank0, rank1, rank2, rank3) \ 1380 if (nb_chipset == INTEL_NB_5000P || nb_chipset == INTEL_NB_5000X || \ 1381 nb_chipset == INTEL_NB_5000V || nb_chipset == INTEL_NB_5000Z) { \ 1382 rank0 = (dmir) & 0x7; \ 1383 rank1 = ((dmir) >> 3) & 0x7; \ 1384 rank2 = ((dmir) >> 6) & 0x7; \ 1385 rank3 = ((dmir) >> 9) & 0x7; \ 1386 } else if (nb_chipset == INTEL_NB_5100) { \ 1387 rank0 = (dmir) & 0x7; \ 1388 rank1 = ((dmir) >> 4) & 0x7; \ 1389 rank2 = ((dmir) >> 8) & 0x7; \ 1390 rank3 = ((dmir) >> 12) & 0x7; \ 1391 } else { \ 1392 rank0 = (dmir) & 0xf; \ 1393 rank1 = ((dmir) >> 4) & 0xf; \ 1394 rank2 = ((dmir) >> 8) & 0xf; \ 1395 rank3 = ((dmir) >> 12) & 0xf; \ 1396 } 1397 1398 #define FERR_FAT_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf0, ip) 1399 #define FERR_NF_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf1, ip) 1400 #define NERR_FAT_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf2, ip) 1401 #define NERR_NF_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf3, ip) 1402 #define EMASK_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xf6, ip) 1403 #define ERR0_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xf8, ip) 1404 #define ERR1_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xfa, ip) 1405 #define ERR2_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xfc, ip) 1406 #define MCERR_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xfe, ip) 1407 #define CTSTS_RD() nb_pci_getb(0, 16, 4, 0xee, 0) 1408 #define THRTSTS_RD() nb_pci_getw(0, 16, 3, 0x68, 0) 1409 1410 #define FERR_FAT_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf0, val) 1411 #define FERR_NF_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf1, val) 1412 #define NERR_FAT_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf2, val) 1413 #define NERR_NF_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf3, val) 1414 #define EMASK_THR_WR(val) nb_pci_putw(0, 16, 2, 0xf6, val) 1415 #define ERR0_THR_WR(val) nb_pci_putw(0, 16, 2, 0xf8, val) 1416 #define ERR1_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfa, val) 1417 #define ERR2_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfc, val) 1418 #define MCERR_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfe, val) 1419 #define CTSTS_WR(val) nb_pci_putb(0, 16, 4, 0xee, val) 1420 #define THRTSTS_WR(val) nb_pci_putw(0, 16, 3, 0x68, val) 1421 1422 #define ERR_FAT_THR_F2 0x02 /* >tnid thermal event with intelligent */ 1423 /* throttling disabled */ 1424 #define ERR_FAT_THR_F1 0x01 /* catastrophic on-die thermal event */ 1425 1426 #define ERR_NF_THR_F5 0x10 /* deadman timeout on cooling update */ 1427 #define ERR_NF_THR_F4 0x08 /* TSMAX Updated */ 1428 #define ERR_NF_THR_F3 0x04 /* On-die throttling event */ 1429 1430 #define EMASK_THR_FATAL (ERR_FAT_THR_F2|ERR_FAT_THR_F1) 1431 #define EMASK_THR_NF (ERR_NF_THR_F5|ERR_NF_THR_F4|ERR_NF_THR_F3) 1432 1433 #define EMASK_THR_F5 0x0010 /* deadman timeout on cooling update */ 1434 #define EMASK_THR_F4 0x0008 /* TSMAX Updated */ 1435 #define EMASK_THR_F3 0x0004 /* On-die throttling event */ 1436 #define EMASK_THR_F2 0x0002 /* >tnid thermal event with intelligent */ 1437 /* throttling disabled */ 1438 #define EMASK_THR_F1 0x0001 /* catastrophic on-die thermal event */ 1439 1440 /* dimm type */ 1441 #define SPD_MEM_TYPE 2 1442 #define SPD_DDR2 8 1443 #define SPD_FBDIMM 9 1444 1445 #ifdef __cplusplus 1446 } 1447 #endif 1448 1449 #endif /* _NB5000_H */ 1450