1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * VM - Hardware Address Translation management for i386 and amd64 30 * 31 * Implementation of the interfaces described in <common/vm/hat.h> 32 * 33 * Nearly all the details of how the hardware is managed should not be 34 * visible outside this layer except for misc. machine specific functions 35 * that work in conjunction with this code. 36 * 37 * Routines used only inside of i86pc/vm start with hati_ for HAT Internal. 38 */ 39 40 #include <sys/machparam.h> 41 #include <sys/machsystm.h> 42 #include <sys/mman.h> 43 #include <sys/types.h> 44 #include <sys/systm.h> 45 #include <sys/cpuvar.h> 46 #include <sys/thread.h> 47 #include <sys/proc.h> 48 #include <sys/cpu.h> 49 #include <sys/kmem.h> 50 #include <sys/disp.h> 51 #include <sys/shm.h> 52 #include <sys/sysmacros.h> 53 #include <sys/machparam.h> 54 #include <sys/vmem.h> 55 #include <sys/vmsystm.h> 56 #include <sys/promif.h> 57 #include <sys/var.h> 58 #include <sys/x86_archext.h> 59 #include <sys/atomic.h> 60 #include <sys/bitmap.h> 61 #include <sys/controlregs.h> 62 #include <sys/bootconf.h> 63 #include <sys/bootsvcs.h> 64 #include <sys/bootinfo.h> 65 #include <sys/archsystm.h> 66 67 #include <vm/seg_kmem.h> 68 #include <vm/hat_i86.h> 69 #include <vm/as.h> 70 #include <vm/seg.h> 71 #include <vm/page.h> 72 #include <vm/seg_kp.h> 73 #include <vm/seg_kpm.h> 74 #include <vm/vm_dep.h> 75 #include <vm/kboot_mmu.h> 76 #include <vm/seg_spt.h> 77 78 #include <sys/cmn_err.h> 79 80 /* 81 * Basic parameters for hat operation. 82 */ 83 struct hat_mmu_info mmu; 84 85 /* 86 * The page that is the kernel's top level pagetable. 87 * 88 * For 32 bit VLP support, the kernel hat will use the 1st 4 entries 89 * on this 4K page for its top level page table. The remaining groups of 90 * 4 entries are used for per processor copies of user VLP pagetables for 91 * running threads. See hat_switch() and reload_pae32() for details. 92 * 93 * vlp_page[0] - 0th level==2 PTE for kernel HAT (will be zero) 94 * vlp_page[1] - 1st level==2 PTE for kernel HAT (will be zero) 95 * vlp_page[2] - 2nd level==2 PTE for kernel HAT (zero for small memory) 96 * vlp_page[3] - 3rd level==2 PTE for kernel 97 * 98 * vlp_page[4] - 0th level==2 PTE for user thread on cpu 0 99 * vlp_page[5] - 1st level==2 PTE for user thread on cpu 0 100 * vlp_page[6] - 2nd level==2 PTE for user thread on cpu 0 101 * vlp_page[7] - probably copy of kernel PTE 102 * 103 * vlp_page[8] - 0th level==2 PTE for user thread on cpu 1 104 * vlp_page[9] - 1st level==2 PTE for user thread on cpu 1 105 * vlp_page[10] - 2nd level==2 PTE for user thread on cpu 1 106 * vlp_page[11] - probably copy of kernel PTE 107 * ... 108 * 109 * when / where the kernel PTE's are (entry 2 or 3 or none) depends 110 * on kernelbase. 111 */ 112 static x86pte_t *vlp_page; 113 114 /* 115 * forward declaration of internal utility routines 116 */ 117 static x86pte_t hati_update_pte(htable_t *ht, uint_t entry, x86pte_t expected, 118 x86pte_t new); 119 120 /* 121 * The kernel address space exists in all HATs. To implement this the 122 * kernel reserves a fixed number of entries in every topmost level page 123 * table. The values are setup in hat_init() and then copied to every hat 124 * created by hat_alloc(). This means that kernelbase must be: 125 * 126 * 4Meg aligned for 32 bit kernels 127 * 512Gig aligned for x86_64 64 bit kernel 128 * 129 * The PAE 32 bit hat is handled as a special case. Otherwise requiring 1Gig 130 * alignment would use too much VA for the kernel. 131 * 132 */ 133 static uint_t khat_start; /* index of 1st entry in kernel's top ptable */ 134 static uint_t khat_entries; /* number of entries in kernel's top ptable */ 135 136 #if defined(__i386) 137 138 static htable_t *khat_pae32_htable = NULL; 139 static uint_t khat_pae32_start; 140 static uint_t khat_pae32_entries; 141 142 #endif 143 144 uint_t use_boot_reserve = 1; /* cleared after early boot process */ 145 uint_t can_steal_post_boot = 0; /* set late in boot to enable stealing */ 146 147 /* 148 * A cpuset for all cpus. This is used for kernel address cross calls, since 149 * the kernel addresses apply to all cpus. 150 */ 151 cpuset_t khat_cpuset; 152 153 /* 154 * management stuff for hat structures 155 */ 156 kmutex_t hat_list_lock; 157 kcondvar_t hat_list_cv; 158 kmem_cache_t *hat_cache; 159 kmem_cache_t *hat_hash_cache; 160 kmem_cache_t *vlp_hash_cache; 161 162 /* 163 * Simple statistics 164 */ 165 struct hatstats hatstat; 166 167 /* 168 * useful stuff for atomic access/clearing/setting REF/MOD/RO bits in page_t's. 169 */ 170 extern void atomic_orb(uchar_t *addr, uchar_t val); 171 extern void atomic_andb(uchar_t *addr, uchar_t val); 172 173 #define PP_GETRM(pp, rmmask) (pp->p_nrm & rmmask) 174 #define PP_ISMOD(pp) PP_GETRM(pp, P_MOD) 175 #define PP_ISREF(pp) PP_GETRM(pp, P_REF) 176 #define PP_ISRO(pp) PP_GETRM(pp, P_RO) 177 178 #define PP_SETRM(pp, rm) atomic_orb(&(pp->p_nrm), rm) 179 #define PP_SETMOD(pp) PP_SETRM(pp, P_MOD) 180 #define PP_SETREF(pp) PP_SETRM(pp, P_REF) 181 #define PP_SETRO(pp) PP_SETRM(pp, P_RO) 182 183 #define PP_CLRRM(pp, rm) atomic_andb(&(pp->p_nrm), ~(rm)) 184 #define PP_CLRMOD(pp) PP_CLRRM(pp, P_MOD) 185 #define PP_CLRREF(pp) PP_CLRRM(pp, P_REF) 186 #define PP_CLRRO(pp) PP_CLRRM(pp, P_RO) 187 #define PP_CLRALL(pp) PP_CLRRM(pp, P_MOD | P_REF | P_RO) 188 189 /* 190 * kmem cache constructor for struct hat 191 */ 192 /*ARGSUSED*/ 193 static int 194 hati_constructor(void *buf, void *handle, int kmflags) 195 { 196 hat_t *hat = buf; 197 198 mutex_init(&hat->hat_mutex, NULL, MUTEX_DEFAULT, NULL); 199 bzero(hat->hat_pages_mapped, 200 sizeof (pgcnt_t) * (mmu.max_page_level + 1)); 201 hat->hat_ism_pgcnt = 0; 202 hat->hat_stats = 0; 203 hat->hat_flags = 0; 204 CPUSET_ZERO(hat->hat_cpus); 205 hat->hat_htable = NULL; 206 hat->hat_ht_hash = NULL; 207 return (0); 208 } 209 210 /* 211 * Allocate a hat structure for as. We also create the top level 212 * htable and initialize it to contain the kernel hat entries. 213 */ 214 hat_t * 215 hat_alloc(struct as *as) 216 { 217 hat_t *hat; 218 htable_t *ht; /* top level htable */ 219 uint_t use_vlp; 220 221 /* 222 * Once we start creating user process HATs we can enable 223 * the htable_steal() code. 224 */ 225 if (can_steal_post_boot == 0) 226 can_steal_post_boot = 1; 227 228 ASSERT(AS_WRITE_HELD(as, &as->a_lock)); 229 hat = kmem_cache_alloc(hat_cache, KM_SLEEP); 230 hat->hat_as = as; 231 mutex_init(&hat->hat_mutex, NULL, MUTEX_DEFAULT, NULL); 232 ASSERT(hat->hat_flags == 0); 233 234 /* 235 * a 32 bit process uses a VLP style hat when using PAE 236 */ 237 #if defined(__amd64) 238 use_vlp = (ttoproc(curthread)->p_model == DATAMODEL_ILP32); 239 #elif defined(__i386) 240 use_vlp = mmu.pae_hat; 241 #endif 242 if (use_vlp) { 243 hat->hat_flags = HAT_VLP; 244 bzero(hat->hat_vlp_ptes, VLP_SIZE); 245 } 246 247 /* 248 * Allocate the htable hash 249 */ 250 if ((hat->hat_flags & HAT_VLP)) { 251 hat->hat_num_hash = mmu.vlp_hash_cnt; 252 hat->hat_ht_hash = kmem_cache_alloc(vlp_hash_cache, KM_SLEEP); 253 } else { 254 hat->hat_num_hash = mmu.hash_cnt; 255 hat->hat_ht_hash = kmem_cache_alloc(hat_hash_cache, KM_SLEEP); 256 } 257 bzero(hat->hat_ht_hash, hat->hat_num_hash * sizeof (htable_t *)); 258 259 /* 260 * Initialize Kernel HAT entries at the top of the top level page 261 * table for the new hat. 262 * 263 * Note that we don't call htable_release() for the top level, that 264 * happens when the hat is destroyed in hat_free_end() 265 */ 266 hat->hat_htable = NULL; 267 hat->hat_ht_cached = NULL; 268 ht = htable_create(hat, (uintptr_t)0, TOP_LEVEL(hat), NULL); 269 270 if (!(hat->hat_flags & HAT_VLP)) 271 x86pte_copy(kas.a_hat->hat_htable, ht, khat_start, 272 khat_entries); 273 #if defined(__i386) 274 else if (khat_entries > 0) 275 bcopy(vlp_page + khat_start, hat->hat_vlp_ptes + khat_start, 276 khat_entries * sizeof (x86pte_t)); 277 #endif 278 hat->hat_htable = ht; 279 280 #if defined(__i386) 281 /* 282 * PAE32 HAT alignment is less restrictive than the others to keep 283 * the kernel from using too much VA. Because of this we may need 284 * one layer further down when kernelbase isn't 1Gig aligned. 285 * See hat_free_end() for the htable_release() that goes with this 286 * htable_create() 287 */ 288 if (khat_pae32_htable != NULL) { 289 ht = htable_create(hat, kernelbase, 290 khat_pae32_htable->ht_level, NULL); 291 x86pte_copy(khat_pae32_htable, ht, khat_pae32_start, 292 khat_pae32_entries); 293 ht->ht_valid_cnt = khat_pae32_entries; 294 } 295 #endif 296 297 /* 298 * Put it at the start of the global list of all hats (used by stealing) 299 * 300 * kas.a_hat is not in the list but is instead used to find the 301 * first and last items in the list. 302 * 303 * - kas.a_hat->hat_next points to the start of the user hats. 304 * The list ends where hat->hat_next == NULL 305 * 306 * - kas.a_hat->hat_prev points to the last of the user hats. 307 * The list begins where hat->hat_prev == NULL 308 */ 309 mutex_enter(&hat_list_lock); 310 hat->hat_prev = NULL; 311 hat->hat_next = kas.a_hat->hat_next; 312 if (hat->hat_next) 313 hat->hat_next->hat_prev = hat; 314 else 315 kas.a_hat->hat_prev = hat; 316 kas.a_hat->hat_next = hat; 317 mutex_exit(&hat_list_lock); 318 319 return (hat); 320 } 321 322 /* 323 * process has finished executing but as has not been cleaned up yet. 324 */ 325 /*ARGSUSED*/ 326 void 327 hat_free_start(hat_t *hat) 328 { 329 ASSERT(AS_WRITE_HELD(hat->hat_as, &hat->hat_as->a_lock)); 330 331 /* 332 * If the hat is currently a stealing victim, wait for the stealing 333 * to finish. Once we mark it as HAT_FREEING, htable_steal() 334 * won't look at its pagetables anymore. 335 */ 336 mutex_enter(&hat_list_lock); 337 while (hat->hat_flags & HAT_VICTIM) 338 cv_wait(&hat_list_cv, &hat_list_lock); 339 hat->hat_flags |= HAT_FREEING; 340 mutex_exit(&hat_list_lock); 341 } 342 343 /* 344 * An address space is being destroyed, so we destroy the associated hat. 345 */ 346 void 347 hat_free_end(hat_t *hat) 348 { 349 int i; 350 kmem_cache_t *cache; 351 352 #ifdef DEBUG 353 for (i = 0; i <= mmu.max_page_level; i++) 354 ASSERT(hat->hat_pages_mapped[i] == 0); 355 #endif 356 ASSERT(hat->hat_flags & HAT_FREEING); 357 358 /* 359 * must not be running on the given hat 360 */ 361 ASSERT(CPU->cpu_current_hat != hat); 362 363 /* 364 * Remove it from the list of HATs 365 */ 366 mutex_enter(&hat_list_lock); 367 if (hat->hat_prev) 368 hat->hat_prev->hat_next = hat->hat_next; 369 else 370 kas.a_hat->hat_next = hat->hat_next; 371 if (hat->hat_next) 372 hat->hat_next->hat_prev = hat->hat_prev; 373 else 374 kas.a_hat->hat_prev = hat->hat_prev; 375 mutex_exit(&hat_list_lock); 376 hat->hat_next = hat->hat_prev = NULL; 377 378 /* 379 * Make a pass through the htables freeing them all up. 380 */ 381 htable_purge_hat(hat); 382 383 /* 384 * Decide which kmem cache the hash table came from, then free it. 385 */ 386 if (hat->hat_flags & HAT_VLP) 387 cache = vlp_hash_cache; 388 else 389 cache = hat_hash_cache; 390 kmem_cache_free(cache, hat->hat_ht_hash); 391 hat->hat_ht_hash = NULL; 392 393 hat->hat_flags = 0; 394 kmem_cache_free(hat_cache, hat); 395 } 396 397 /* 398 * round kernelbase down to a supported value to use for _userlimit 399 * 400 * userlimit must be aligned down to an entry in the top level htable. 401 * The one exception is for 32 bit HAT's running PAE. 402 */ 403 uintptr_t 404 hat_kernelbase(uintptr_t va) 405 { 406 #if defined(__i386) 407 va &= LEVEL_MASK(1); 408 #endif 409 if (IN_VA_HOLE(va)) 410 panic("_userlimit %p will fall in VA hole\n", (void *)va); 411 return (va); 412 } 413 414 /* 415 * Initialize hat data structures based on processor MMU information. 416 */ 417 void 418 mmu_init(void) 419 { 420 uint_t max_htables; 421 uint_t pa_bits; 422 uint_t va_bits; 423 int i; 424 425 /* 426 * If CPU enabled the page table global bit, use it for the kernel 427 * This is bit 7 in CR4 (PGE - Page Global Enable). 428 */ 429 if ((x86_feature & X86_PGE) != 0 && (getcr4() & CR4_PGE) != 0) 430 mmu.pt_global = PT_GLOBAL; 431 432 /* 433 * Detect NX and PAE usage. 434 */ 435 mmu.pae_hat = kbm_pae_support; 436 if (kbm_nx_support) 437 mmu.pt_nx = PT_NX; 438 else 439 mmu.pt_nx = 0; 440 441 /* 442 * Use CPU info to set various MMU parameters 443 */ 444 cpuid_get_addrsize(CPU, &pa_bits, &va_bits); 445 446 if (va_bits < sizeof (void *) * NBBY) { 447 mmu.hole_start = (1ul << (va_bits - 1)); 448 mmu.hole_end = 0ul - mmu.hole_start - 1; 449 } else { 450 mmu.hole_end = 0; 451 mmu.hole_start = mmu.hole_end - 1; 452 } 453 #if defined(OPTERON_ERRATUM_121) 454 /* 455 * If erratum 121 has already been detected at this time, hole_start 456 * contains the value to be subtracted from mmu.hole_start. 457 */ 458 ASSERT(hole_start == 0 || opteron_erratum_121 != 0); 459 hole_start = mmu.hole_start - hole_start; 460 #else 461 hole_start = mmu.hole_start; 462 #endif 463 hole_end = mmu.hole_end; 464 465 mmu.highest_pfn = mmu_btop((1ull << pa_bits) - 1); 466 if (mmu.pae_hat == 0 && pa_bits > 32) 467 mmu.highest_pfn = PFN_4G - 1; 468 469 if (mmu.pae_hat) { 470 mmu.pte_size = 8; /* 8 byte PTEs */ 471 mmu.pte_size_shift = 3; 472 } else { 473 mmu.pte_size = 4; /* 4 byte PTEs */ 474 mmu.pte_size_shift = 2; 475 } 476 477 if (mmu.pae_hat && (x86_feature & X86_PAE) == 0) 478 panic("Processor does not support PAE"); 479 480 if ((x86_feature & X86_CX8) == 0) 481 panic("Processor does not support cmpxchg8b instruction"); 482 483 /* 484 * Initialize parameters based on the 64 or 32 bit kernels and 485 * for the 32 bit kernel decide if we should use PAE. 486 */ 487 if (kbm_largepage_support) 488 mmu.max_page_level = 1; 489 else 490 mmu.max_page_level = 0; 491 mmu_page_sizes = mmu.max_page_level + 1; 492 mmu_exported_page_sizes = mmu_page_sizes; 493 494 #if defined(__amd64) 495 496 mmu.num_level = 4; 497 mmu.max_level = 3; 498 mmu.ptes_per_table = 512; 499 mmu.top_level_count = 512; 500 501 mmu.level_shift[0] = 12; 502 mmu.level_shift[1] = 21; 503 mmu.level_shift[2] = 30; 504 mmu.level_shift[3] = 39; 505 506 #elif defined(__i386) 507 508 if (mmu.pae_hat) { 509 mmu.num_level = 3; 510 mmu.max_level = 2; 511 mmu.ptes_per_table = 512; 512 mmu.top_level_count = 4; 513 514 mmu.level_shift[0] = 12; 515 mmu.level_shift[1] = 21; 516 mmu.level_shift[2] = 30; 517 518 } else { 519 mmu.num_level = 2; 520 mmu.max_level = 1; 521 mmu.ptes_per_table = 1024; 522 mmu.top_level_count = 1024; 523 524 mmu.level_shift[0] = 12; 525 mmu.level_shift[1] = 22; 526 } 527 528 #endif /* __i386 */ 529 530 for (i = 0; i < mmu.num_level; ++i) { 531 mmu.level_size[i] = 1UL << mmu.level_shift[i]; 532 mmu.level_offset[i] = mmu.level_size[i] - 1; 533 mmu.level_mask[i] = ~mmu.level_offset[i]; 534 } 535 536 for (i = 0; i <= mmu.max_page_level; ++i) { 537 mmu.pte_bits[i] = PT_VALID; 538 if (i > 0) 539 mmu.pte_bits[i] |= PT_PAGESIZE; 540 } 541 542 /* 543 * NOTE Legacy 32 bit PAE mode only has the P_VALID bit at top level. 544 */ 545 for (i = 1; i < mmu.num_level; ++i) 546 mmu.ptp_bits[i] = PT_PTPBITS; 547 548 #if defined(__i386) 549 mmu.ptp_bits[2] = PT_VALID; 550 #endif 551 552 /* 553 * Compute how many hash table entries to have per process for htables. 554 * We start with 1 page's worth of entries. 555 * 556 * If physical memory is small, reduce the amount need to cover it. 557 */ 558 max_htables = physmax / mmu.ptes_per_table; 559 mmu.hash_cnt = MMU_PAGESIZE / sizeof (htable_t *); 560 while (mmu.hash_cnt > 16 && mmu.hash_cnt >= max_htables) 561 mmu.hash_cnt >>= 1; 562 mmu.vlp_hash_cnt = mmu.hash_cnt; 563 564 #if defined(__amd64) 565 /* 566 * If running in 64 bits and physical memory is large, 567 * increase the size of the cache to cover all of memory for 568 * a 64 bit process. 569 */ 570 #define HASH_MAX_LENGTH 4 571 while (mmu.hash_cnt * HASH_MAX_LENGTH < max_htables) 572 mmu.hash_cnt <<= 1; 573 #endif 574 } 575 576 577 /* 578 * initialize hat data structures 579 */ 580 void 581 hat_init() 582 { 583 #if defined(__i386) 584 /* 585 * _userlimit must be aligned correctly 586 */ 587 if ((_userlimit & LEVEL_MASK(1)) != _userlimit) { 588 prom_printf("hat_init(): _userlimit=%p, not aligned at %p\n", 589 (void *)_userlimit, (void *)LEVEL_SIZE(1)); 590 halt("hat_init(): Unable to continue"); 591 } 592 #endif 593 594 cv_init(&hat_list_cv, NULL, CV_DEFAULT, NULL); 595 596 /* 597 * initialize kmem caches 598 */ 599 htable_init(); 600 hment_init(); 601 602 hat_cache = kmem_cache_create("hat_t", 603 sizeof (hat_t), 0, hati_constructor, NULL, NULL, 604 NULL, 0, 0); 605 606 hat_hash_cache = kmem_cache_create("HatHash", 607 mmu.hash_cnt * sizeof (htable_t *), 0, NULL, NULL, NULL, 608 NULL, 0, 0); 609 610 /* 611 * VLP hats can use a smaller hash table size on large memroy machines 612 */ 613 if (mmu.hash_cnt == mmu.vlp_hash_cnt) { 614 vlp_hash_cache = hat_hash_cache; 615 } else { 616 vlp_hash_cache = kmem_cache_create("HatVlpHash", 617 mmu.vlp_hash_cnt * sizeof (htable_t *), 0, NULL, NULL, NULL, 618 NULL, 0, 0); 619 } 620 621 /* 622 * Set up the kernel's hat 623 */ 624 AS_LOCK_ENTER(&kas, &kas.a_lock, RW_WRITER); 625 kas.a_hat = kmem_cache_alloc(hat_cache, KM_NOSLEEP); 626 mutex_init(&kas.a_hat->hat_mutex, NULL, MUTEX_DEFAULT, NULL); 627 kas.a_hat->hat_as = &kas; 628 kas.a_hat->hat_flags = 0; 629 AS_LOCK_EXIT(&kas, &kas.a_lock); 630 631 CPUSET_ZERO(khat_cpuset); 632 CPUSET_ADD(khat_cpuset, CPU->cpu_id); 633 634 /* 635 * The kernel hat's next pointer serves as the head of the hat list . 636 * The kernel hat's prev pointer tracks the last hat on the list for 637 * htable_steal() to use. 638 */ 639 kas.a_hat->hat_next = NULL; 640 kas.a_hat->hat_prev = NULL; 641 642 /* 643 * Allocate an htable hash bucket for the kernel 644 * XX64 - tune for 64 bit procs 645 */ 646 kas.a_hat->hat_num_hash = mmu.hash_cnt; 647 kas.a_hat->hat_ht_hash = kmem_cache_alloc(hat_hash_cache, KM_NOSLEEP); 648 bzero(kas.a_hat->hat_ht_hash, mmu.hash_cnt * sizeof (htable_t *)); 649 650 /* 651 * zero out the top level and cached htable pointers 652 */ 653 kas.a_hat->hat_ht_cached = NULL; 654 kas.a_hat->hat_htable = NULL; 655 656 /* 657 * Pre-allocate hrm_hashtab before enabling the collection of 658 * refmod statistics. Allocating on the fly would mean us 659 * running the risk of suffering recursive mutex enters or 660 * deadlocks. 661 */ 662 hrm_hashtab = kmem_zalloc(HRM_HASHSIZE * sizeof (struct hrmstat *), 663 KM_SLEEP); 664 } 665 666 /* 667 * Prepare CPU specific pagetables for VLP processes on 64 bit kernels. 668 * 669 * Each CPU has a set of 2 pagetables that are reused for any 32 bit 670 * process it runs. They are the top level pagetable, hci_vlp_l3ptes, and 671 * the next to top level table for the bottom 512 Gig, hci_vlp_l2ptes. 672 */ 673 /*ARGSUSED*/ 674 static void 675 hat_vlp_setup(struct cpu *cpu) 676 { 677 #if defined(__amd64) 678 struct hat_cpu_info *hci = cpu->cpu_hat_info; 679 pfn_t pfn; 680 681 /* 682 * allocate the level==2 page table for the bottom most 683 * 512Gig of address space (this is where 32 bit apps live) 684 */ 685 ASSERT(hci != NULL); 686 hci->hci_vlp_l2ptes = kmem_zalloc(MMU_PAGESIZE, KM_SLEEP); 687 688 /* 689 * Allocate a top level pagetable and copy the kernel's 690 * entries into it. Then link in hci_vlp_l2ptes in the 1st entry. 691 */ 692 hci->hci_vlp_l3ptes = kmem_zalloc(MMU_PAGESIZE, KM_SLEEP); 693 hci->hci_vlp_pfn = 694 hat_getpfnum(kas.a_hat, (caddr_t)hci->hci_vlp_l3ptes); 695 ASSERT(hci->hci_vlp_pfn != PFN_INVALID); 696 bcopy(vlp_page + khat_start, hci->hci_vlp_l3ptes + khat_start, 697 khat_entries * sizeof (x86pte_t)); 698 699 pfn = hat_getpfnum(kas.a_hat, (caddr_t)hci->hci_vlp_l2ptes); 700 ASSERT(pfn != PFN_INVALID); 701 hci->hci_vlp_l3ptes[0] = MAKEPTP(pfn, 2); 702 #endif /* __amd64 */ 703 } 704 705 /*ARGSUSED*/ 706 static void 707 hat_vlp_teardown(cpu_t *cpu) 708 { 709 #if defined(__amd64) 710 struct hat_cpu_info *hci; 711 712 if ((hci = cpu->cpu_hat_info) == NULL) 713 return; 714 if (hci->hci_vlp_l2ptes) 715 kmem_free(hci->hci_vlp_l2ptes, MMU_PAGESIZE); 716 if (hci->hci_vlp_l3ptes) 717 kmem_free(hci->hci_vlp_l3ptes, MMU_PAGESIZE); 718 #endif /* __amd64 */ 719 } 720 721 /* 722 * Finish filling in the kernel hat. 723 * Pre fill in all top level kernel page table entries for the kernel's 724 * part of the address range. From this point on we can't use any new 725 * kernel large pages if they need PTE's at max_level 726 * 727 * create the kmap mappings. 728 */ 729 void 730 hat_init_finish(void) 731 { 732 htable_t *top = kas.a_hat->hat_htable; 733 htable_t *ht; 734 uint_t e; 735 x86pte_t pte; 736 uintptr_t va = kernelbase; 737 size_t size; 738 739 740 #if defined(__i386) 741 ASSERT((va & LEVEL_MASK(1)) == va); 742 743 /* 744 * Deal with kernelbase not 1Gig aligned for 32 bit PAE hats. 745 */ 746 if (!mmu.pae_hat || (va & LEVEL_OFFSET(mmu.max_level)) == 0) { 747 khat_pae32_htable = NULL; 748 } else { 749 ASSERT(mmu.max_level == 2); 750 ASSERT((va & LEVEL_OFFSET(mmu.max_level - 1)) == 0); 751 khat_pae32_htable = 752 htable_create(kas.a_hat, va, mmu.max_level - 1, NULL); 753 khat_pae32_start = htable_va2entry(va, khat_pae32_htable); 754 khat_pae32_entries = mmu.ptes_per_table - khat_pae32_start; 755 for (e = khat_pae32_start; e < mmu.ptes_per_table; 756 ++e, va += LEVEL_SIZE(mmu.max_level - 1)) { 757 pte = x86pte_get(khat_pae32_htable, e); 758 if (PTE_ISVALID(pte)) 759 continue; 760 ht = htable_create(kas.a_hat, va, mmu.max_level - 2, 761 NULL); 762 ASSERT(ht != NULL); 763 } 764 } 765 #endif 766 767 /* 768 * The kernel hat will need fixed values in the highest level 769 * ptable for copying to all other hat's. This implies 770 * alignment restrictions on _userlimit. 771 * 772 * Note we don't htable_release() these htables. This keeps them 773 * from ever being stolen or free'd. 774 * 775 * top_level_count is used instead of ptes_per_table, since 776 * on 32-bit PAE we only have 4 usable entries at the top level ptable. 777 */ 778 if (va == 0) 779 khat_start = mmu.top_level_count; 780 else 781 khat_start = htable_va2entry(va, kas.a_hat->hat_htable); 782 khat_entries = mmu.top_level_count - khat_start; 783 for (e = khat_start; e < mmu.top_level_count; 784 ++e, va += LEVEL_SIZE(mmu.max_level)) { 785 if (IN_HYPERVISOR_VA(va)) 786 continue; 787 pte = x86pte_get(top, e); 788 if (PTE_ISVALID(pte)) 789 continue; 790 ht = htable_create(kas.a_hat, va, mmu.max_level - 1, NULL); 791 ASSERT(ht != NULL); 792 } 793 794 /* 795 * We are now effectively running on the kernel hat. 796 * Clearing use_boot_reserve shuts off using the pre-allocated boot 797 * reserve for all HAT allocations. From here on, the reserves are 798 * only used when mapping in memory for the hat's own allocations. 799 */ 800 use_boot_reserve = 0; 801 htable_adjust_reserve(); 802 803 /* 804 * 32 bit kernels use only 4 of the 512 entries in its top level 805 * pagetable. We'll use the remainder for the "per CPU" page tables 806 * for VLP processes. 807 * 808 * We also map the top level kernel pagetable into the kernel to make 809 * it easy to use bcopy to initialize new address spaces. 810 */ 811 if (mmu.pae_hat) { 812 vlp_page = vmem_alloc(heap_arena, MMU_PAGESIZE, VM_SLEEP); 813 hat_devload(kas.a_hat, (caddr_t)vlp_page, MMU_PAGESIZE, 814 kas.a_hat->hat_htable->ht_pfn, 815 PROT_WRITE | 816 PROT_READ | HAT_NOSYNC | HAT_UNORDERED_OK, 817 HAT_LOAD | HAT_LOAD_NOCONSIST); 818 } 819 hat_vlp_setup(CPU); 820 821 /* 822 * Create kmap (cached mappings of kernel PTEs) 823 * for 32 bit we map from segmap_start .. ekernelheap 824 * for 64 bit we map from segmap_start .. segmap_start + segmapsize; 825 */ 826 #if defined(__i386) 827 size = (uintptr_t)ekernelheap - segmap_start; 828 #elif defined(__amd64) 829 size = segmapsize; 830 #endif 831 hat_kmap_init((uintptr_t)segmap_start, size); 832 } 833 834 /* 835 * On 32 bit PAE mode, PTE's are 64 bits, but ordinary atomic memory references 836 * are 32 bit, so for safety we must use cas64() to install these. 837 */ 838 #ifdef __i386 839 static void 840 reload_pae32(hat_t *hat, cpu_t *cpu) 841 { 842 x86pte_t *src; 843 x86pte_t *dest; 844 x86pte_t pte; 845 int i; 846 847 /* 848 * Load the 4 entries of the level 2 page table into this 849 * cpu's range of the vlp_page and point cr3 at them. 850 */ 851 ASSERT(mmu.pae_hat); 852 src = hat->hat_vlp_ptes; 853 dest = vlp_page + (cpu->cpu_id + 1) * VLP_NUM_PTES; 854 for (i = 0; i < VLP_NUM_PTES; ++i) { 855 for (;;) { 856 pte = dest[i]; 857 if (pte == src[i]) 858 break; 859 if (cas64(dest + i, pte, src[i]) != src[i]) 860 break; 861 } 862 } 863 } 864 #endif 865 866 /* 867 * Switch to a new active hat, maintaining bit masks to track active CPUs. 868 */ 869 void 870 hat_switch(hat_t *hat) 871 { 872 uintptr_t newcr3; 873 cpu_t *cpu = CPU; 874 hat_t *old = cpu->cpu_current_hat; 875 876 /* 877 * set up this information first, so we don't miss any cross calls 878 */ 879 if (old != NULL) { 880 if (old == hat) 881 return; 882 if (old != kas.a_hat) 883 CPUSET_ATOMIC_DEL(old->hat_cpus, cpu->cpu_id); 884 } 885 886 /* 887 * Add this CPU to the active set for this HAT. 888 */ 889 if (hat != kas.a_hat) { 890 CPUSET_ATOMIC_ADD(hat->hat_cpus, cpu->cpu_id); 891 } 892 cpu->cpu_current_hat = hat; 893 894 /* 895 * now go ahead and load cr3 896 */ 897 if (hat->hat_flags & HAT_VLP) { 898 #if defined(__amd64) 899 x86pte_t *vlpptep = cpu->cpu_hat_info->hci_vlp_l2ptes; 900 901 VLP_COPY(hat->hat_vlp_ptes, vlpptep); 902 newcr3 = MAKECR3(cpu->cpu_hat_info->hci_vlp_pfn); 903 #elif defined(__i386) 904 reload_pae32(hat, cpu); 905 newcr3 = MAKECR3(kas.a_hat->hat_htable->ht_pfn) + 906 (cpu->cpu_id + 1) * VLP_SIZE; 907 #endif 908 } else { 909 newcr3 = MAKECR3(hat->hat_htable->ht_pfn); 910 } 911 setcr3(newcr3); 912 ASSERT(cpu == CPU); 913 } 914 915 /* 916 * Utility to return a valid x86pte_t from protections, pfn, and level number 917 */ 918 static x86pte_t 919 hati_mkpte(pfn_t pfn, uint_t attr, level_t level, uint_t flags) 920 { 921 x86pte_t pte; 922 uint_t cache_attr = attr & HAT_ORDER_MASK; 923 924 pte = MAKEPTE(pfn, level); 925 926 if (attr & PROT_WRITE) 927 PTE_SET(pte, PT_WRITABLE); 928 929 if (attr & PROT_USER) 930 PTE_SET(pte, PT_USER); 931 932 if (!(attr & PROT_EXEC)) 933 PTE_SET(pte, mmu.pt_nx); 934 935 /* 936 * Set the software bits used track ref/mod sync's and hments. 937 * If not using REF/MOD, set them to avoid h/w rewriting PTEs. 938 */ 939 if (flags & HAT_LOAD_NOCONSIST) 940 PTE_SET(pte, PT_NOCONSIST | PT_REF | PT_MOD); 941 else if (attr & HAT_NOSYNC) 942 PTE_SET(pte, PT_NOSYNC | PT_REF | PT_MOD); 943 944 /* 945 * Set the caching attributes in the PTE. The combination 946 * of attributes are poorly defined, so we pay attention 947 * to them in the given order. 948 * 949 * The test for HAT_STRICTORDER is different because it's defined 950 * as "0" - which was a stupid thing to do, but is too late to change! 951 */ 952 if (cache_attr == HAT_STRICTORDER) { 953 PTE_SET(pte, PT_NOCACHE); 954 /*LINTED [Lint hates empty ifs, but it's the obvious way to do this] */ 955 } else if (cache_attr & (HAT_UNORDERED_OK | HAT_STORECACHING_OK)) { 956 /* nothing to set */; 957 } else if (cache_attr & (HAT_MERGING_OK | HAT_LOADCACHING_OK)) { 958 PTE_SET(pte, PT_NOCACHE); 959 if (x86_feature & X86_PAT) 960 PTE_SET(pte, (level == 0) ? PT_PAT_4K : PT_PAT_LARGE); 961 else 962 PTE_SET(pte, PT_WRITETHRU); 963 } else { 964 panic("hati_mkpte(): bad caching attributes: %x\n", cache_attr); 965 } 966 967 return (pte); 968 } 969 970 /* 971 * Duplicate address translations of the parent to the child. 972 * This function really isn't used anymore. 973 */ 974 /*ARGSUSED*/ 975 int 976 hat_dup(hat_t *old, hat_t *new, caddr_t addr, size_t len, uint_t flag) 977 { 978 ASSERT((uintptr_t)addr < kernelbase); 979 ASSERT(new != kas.a_hat); 980 ASSERT(old != kas.a_hat); 981 return (0); 982 } 983 984 /* 985 * Allocate any hat resources required for a process being swapped in. 986 */ 987 /*ARGSUSED*/ 988 void 989 hat_swapin(hat_t *hat) 990 { 991 /* do nothing - we let everything fault back in */ 992 } 993 994 /* 995 * Unload all translations associated with an address space of a process 996 * that is being swapped out. 997 */ 998 void 999 hat_swapout(hat_t *hat) 1000 { 1001 uintptr_t vaddr = (uintptr_t)0; 1002 uintptr_t eaddr = _userlimit; 1003 htable_t *ht = NULL; 1004 level_t l; 1005 1006 /* 1007 * We can't just call hat_unload(hat, 0, _userlimit...) here, because 1008 * seg_spt and shared pagetables can't be swapped out. 1009 * Take a look at segspt_shmswapout() - it's a big no-op. 1010 * 1011 * Instead we'll walk through all the address space and unload 1012 * any mappings which we are sure are not shared, not locked. 1013 */ 1014 ASSERT(IS_PAGEALIGNED(vaddr)); 1015 ASSERT(IS_PAGEALIGNED(eaddr)); 1016 ASSERT(AS_LOCK_HELD(hat->hat_as, &hat->hat_as->a_lock)); 1017 if ((uintptr_t)hat->hat_as->a_userlimit < eaddr) 1018 eaddr = (uintptr_t)hat->hat_as->a_userlimit; 1019 1020 while (vaddr < eaddr) { 1021 (void) htable_walk(hat, &ht, &vaddr, eaddr); 1022 if (ht == NULL) 1023 break; 1024 1025 ASSERT(!IN_VA_HOLE(vaddr)); 1026 1027 /* 1028 * If the page table is shared skip its entire range. 1029 * This code knows that only level 0 page tables are shared 1030 */ 1031 l = ht->ht_level; 1032 if (ht->ht_flags & HTABLE_SHARED_PFN) { 1033 ASSERT(l == 0); 1034 vaddr = ht->ht_vaddr + LEVEL_SIZE(1); 1035 htable_release(ht); 1036 ht = NULL; 1037 continue; 1038 } 1039 1040 /* 1041 * If the page table has no locked entries, unload this one. 1042 */ 1043 if (ht->ht_lock_cnt == 0) 1044 hat_unload(hat, (caddr_t)vaddr, LEVEL_SIZE(l), 1045 HAT_UNLOAD_UNMAP); 1046 1047 /* 1048 * If we have a level 0 page table with locked entries, 1049 * skip the entire page table, otherwise skip just one entry. 1050 */ 1051 if (ht->ht_lock_cnt > 0 && l == 0) 1052 vaddr = ht->ht_vaddr + LEVEL_SIZE(1); 1053 else 1054 vaddr += LEVEL_SIZE(l); 1055 } 1056 if (ht) 1057 htable_release(ht); 1058 1059 /* 1060 * We're in swapout because the system is low on memory, so 1061 * go back and flush all the htables off the cached list. 1062 */ 1063 htable_purge_hat(hat); 1064 } 1065 1066 /* 1067 * returns number of bytes that have valid mappings in hat. 1068 */ 1069 size_t 1070 hat_get_mapped_size(hat_t *hat) 1071 { 1072 size_t total = 0; 1073 int l; 1074 1075 for (l = 0; l <= mmu.max_page_level; l++) 1076 total += (hat->hat_pages_mapped[l] << LEVEL_SHIFT(l)); 1077 total += hat->hat_ism_pgcnt; 1078 1079 return (total); 1080 } 1081 1082 /* 1083 * enable/disable collection of stats for hat. 1084 */ 1085 int 1086 hat_stats_enable(hat_t *hat) 1087 { 1088 atomic_add_32(&hat->hat_stats, 1); 1089 return (1); 1090 } 1091 1092 void 1093 hat_stats_disable(hat_t *hat) 1094 { 1095 atomic_add_32(&hat->hat_stats, -1); 1096 } 1097 1098 /* 1099 * Utility to sync the ref/mod bits from a page table entry to the page_t 1100 * We must be holding the mapping list lock when this is called. 1101 */ 1102 static void 1103 hati_sync_pte_to_page(page_t *pp, x86pte_t pte, level_t level) 1104 { 1105 uint_t rm = 0; 1106 pgcnt_t pgcnt; 1107 1108 if (PTE_GET(pte, PT_SOFTWARE) >= PT_NOSYNC) 1109 return; 1110 1111 if (PTE_GET(pte, PT_REF)) 1112 rm |= P_REF; 1113 1114 if (PTE_GET(pte, PT_MOD)) 1115 rm |= P_MOD; 1116 1117 if (rm == 0) 1118 return; 1119 1120 /* 1121 * sync to all constituent pages of a large page 1122 */ 1123 ASSERT(x86_hm_held(pp)); 1124 pgcnt = page_get_pagecnt(level); 1125 ASSERT(IS_P2ALIGNED(pp->p_pagenum, pgcnt)); 1126 for (; pgcnt > 0; --pgcnt) { 1127 /* 1128 * hat_page_demote() can't decrease 1129 * pszc below this mapping size 1130 * since this large mapping existed after we 1131 * took mlist lock. 1132 */ 1133 ASSERT(pp->p_szc >= level); 1134 hat_page_setattr(pp, rm); 1135 ++pp; 1136 } 1137 } 1138 1139 /* 1140 * This the set of PTE bits for PFN, permissions and caching 1141 * that require a TLB flush (hat_tlb_inval) if changed on a HAT_LOAD_REMAP 1142 */ 1143 #define PT_REMAP_BITS \ 1144 (PT_PADDR | PT_NX | PT_WRITABLE | PT_WRITETHRU | \ 1145 PT_NOCACHE | PT_PAT_4K | PT_PAT_LARGE) 1146 1147 #define REMAPASSERT(EX) if (!(EX)) panic("hati_pte_map: " #EX) 1148 /* 1149 * Do the low-level work to get a mapping entered into a HAT's pagetables 1150 * and in the mapping list of the associated page_t. 1151 */ 1152 static int 1153 hati_pte_map( 1154 htable_t *ht, 1155 uint_t entry, 1156 page_t *pp, 1157 x86pte_t pte, 1158 int flags, 1159 void *pte_ptr) 1160 { 1161 hat_t *hat = ht->ht_hat; 1162 x86pte_t old_pte; 1163 level_t l = ht->ht_level; 1164 hment_t *hm; 1165 uint_t is_consist; 1166 int rv = 0; 1167 1168 /* 1169 * Is this a consistant (ie. need mapping list lock) mapping? 1170 */ 1171 is_consist = (pp != NULL && (flags & HAT_LOAD_NOCONSIST) == 0); 1172 1173 /* 1174 * Track locked mapping count in the htable. Do this first, 1175 * as we track locking even if there already is a mapping present. 1176 */ 1177 if ((flags & HAT_LOAD_LOCK) != 0 && hat != kas.a_hat) 1178 HTABLE_LOCK_INC(ht); 1179 1180 /* 1181 * Acquire the page's mapping list lock and get an hment to use. 1182 * Note that hment_prepare() might return NULL. 1183 */ 1184 if (is_consist) { 1185 x86_hm_enter(pp); 1186 hm = hment_prepare(ht, entry, pp); 1187 } 1188 1189 /* 1190 * Set the new pte, retrieving the old one at the same time. 1191 */ 1192 old_pte = x86pte_set(ht, entry, pte, pte_ptr); 1193 1194 /* 1195 * did we get a large page / page table collision? 1196 */ 1197 if (old_pte == LPAGE_ERROR) { 1198 rv = -1; 1199 goto done; 1200 } 1201 1202 /* 1203 * If the mapping didn't change there is nothing more to do. 1204 */ 1205 if (PTE_EQUIV(pte, old_pte)) 1206 goto done; 1207 1208 /* 1209 * Install a new mapping in the page's mapping list 1210 */ 1211 if (!PTE_ISVALID(old_pte)) { 1212 if (is_consist) { 1213 hment_assign(ht, entry, pp, hm); 1214 x86_hm_exit(pp); 1215 } else { 1216 ASSERT(flags & HAT_LOAD_NOCONSIST); 1217 } 1218 HTABLE_INC(ht->ht_valid_cnt); 1219 PGCNT_INC(hat, l); 1220 return (rv); 1221 } 1222 1223 /* 1224 * Remap's are more complicated: 1225 * - HAT_LOAD_REMAP must be specified if changing the pfn. 1226 * We also require that NOCONSIST be specified. 1227 * - Otherwise only permission or caching bits may change. 1228 */ 1229 if (!PTE_ISPAGE(old_pte, l)) 1230 panic("non-null/page mapping pte=" FMT_PTE, old_pte); 1231 1232 if (PTE2PFN(old_pte, l) != PTE2PFN(pte, l)) { 1233 REMAPASSERT(flags & HAT_LOAD_REMAP); 1234 REMAPASSERT(flags & HAT_LOAD_NOCONSIST); 1235 REMAPASSERT(PTE_GET(old_pte, PT_SOFTWARE) >= PT_NOCONSIST); 1236 REMAPASSERT(pf_is_memory(PTE2PFN(old_pte, l)) == 1237 pf_is_memory(PTE2PFN(pte, l))); 1238 REMAPASSERT(!is_consist); 1239 } 1240 1241 /* 1242 * We only let remaps change the bits for PFNs, permissions 1243 * or caching type. 1244 */ 1245 ASSERT(PTE_GET(old_pte, ~(PT_REMAP_BITS | PT_REF | PT_MOD)) == 1246 PTE_GET(pte, ~PT_REMAP_BITS)); 1247 1248 /* 1249 * We don't create any mapping list entries on a remap, so release 1250 * any allocated hment after we drop the mapping list lock. 1251 */ 1252 done: 1253 if (is_consist) { 1254 x86_hm_exit(pp); 1255 if (hm != NULL) 1256 hment_free(hm); 1257 } 1258 return (rv); 1259 } 1260 1261 /* 1262 * Internal routine to load a single page table entry. This only fails if 1263 * we attempt to overwrite a page table link with a large page. 1264 */ 1265 static int 1266 hati_load_common( 1267 hat_t *hat, 1268 uintptr_t va, 1269 page_t *pp, 1270 uint_t attr, 1271 uint_t flags, 1272 level_t level, 1273 pfn_t pfn) 1274 { 1275 htable_t *ht; 1276 uint_t entry; 1277 x86pte_t pte; 1278 int rv = 0; 1279 1280 /* 1281 * The number 16 is arbitrary and here to catch a recursion problem 1282 * early before we blow out the kernel stack. 1283 */ 1284 ++curthread->t_hatdepth; 1285 ASSERT(curthread->t_hatdepth < 16); 1286 1287 ASSERT(hat == kas.a_hat || 1288 AS_LOCK_HELD(hat->hat_as, &hat->hat_as->a_lock)); 1289 1290 if (flags & HAT_LOAD_SHARE) 1291 hat->hat_flags |= HAT_SHARED; 1292 1293 /* 1294 * Find the page table that maps this page if it already exists. 1295 */ 1296 ht = htable_lookup(hat, va, level); 1297 1298 /* 1299 * We must have HAT_LOAD_NOCONSIST if page_t is NULL. 1300 */ 1301 if (pp == NULL) 1302 flags |= HAT_LOAD_NOCONSIST; 1303 1304 if (ht == NULL) { 1305 ht = htable_create(hat, va, level, NULL); 1306 ASSERT(ht != NULL); 1307 } 1308 entry = htable_va2entry(va, ht); 1309 1310 /* 1311 * a bunch of paranoid error checking 1312 */ 1313 ASSERT(ht->ht_busy > 0); 1314 if (ht->ht_vaddr > va || va > HTABLE_LAST_PAGE(ht)) 1315 panic("hati_load_common: bad htable %p, va %p", ht, (void *)va); 1316 ASSERT(ht->ht_level == level); 1317 1318 /* 1319 * construct the new PTE 1320 */ 1321 if (hat == kas.a_hat) 1322 attr &= ~PROT_USER; 1323 pte = hati_mkpte(pfn, attr, level, flags); 1324 if (hat == kas.a_hat && va >= kernelbase) 1325 PTE_SET(pte, mmu.pt_global); 1326 1327 /* 1328 * establish the mapping 1329 */ 1330 rv = hati_pte_map(ht, entry, pp, pte, flags, NULL); 1331 1332 /* 1333 * release the htable and any reserves 1334 */ 1335 htable_release(ht); 1336 --curthread->t_hatdepth; 1337 return (rv); 1338 } 1339 1340 /* 1341 * special case of hat_memload to deal with some kernel addrs for performance 1342 */ 1343 static void 1344 hat_kmap_load( 1345 caddr_t addr, 1346 page_t *pp, 1347 uint_t attr, 1348 uint_t flags) 1349 { 1350 uintptr_t va = (uintptr_t)addr; 1351 x86pte_t pte; 1352 pfn_t pfn = page_pptonum(pp); 1353 pgcnt_t pg_off = mmu_btop(va - mmu.kmap_addr); 1354 htable_t *ht; 1355 uint_t entry; 1356 void *pte_ptr; 1357 1358 /* 1359 * construct the requested PTE 1360 */ 1361 attr &= ~PROT_USER; 1362 attr |= HAT_STORECACHING_OK; 1363 pte = hati_mkpte(pfn, attr, 0, flags); 1364 PTE_SET(pte, mmu.pt_global); 1365 1366 /* 1367 * Figure out the pte_ptr and htable and use common code to finish up 1368 */ 1369 if (mmu.pae_hat) 1370 pte_ptr = mmu.kmap_ptes + pg_off; 1371 else 1372 pte_ptr = (x86pte32_t *)mmu.kmap_ptes + pg_off; 1373 ht = mmu.kmap_htables[(va - mmu.kmap_htables[0]->ht_vaddr) >> 1374 LEVEL_SHIFT(1)]; 1375 entry = htable_va2entry(va, ht); 1376 ++curthread->t_hatdepth; 1377 ASSERT(curthread->t_hatdepth < 16); 1378 (void) hati_pte_map(ht, entry, pp, pte, flags, pte_ptr); 1379 --curthread->t_hatdepth; 1380 } 1381 1382 /* 1383 * hat_memload() - load a translation to the given page struct 1384 * 1385 * Flags for hat_memload/hat_devload/hat_*attr. 1386 * 1387 * HAT_LOAD Default flags to load a translation to the page. 1388 * 1389 * HAT_LOAD_LOCK Lock down mapping resources; hat_map(), hat_memload(), 1390 * and hat_devload(). 1391 * 1392 * HAT_LOAD_NOCONSIST Do not add mapping to page_t mapping list. 1393 * sets PT_NOCONSIST 1394 * 1395 * HAT_LOAD_SHARE A flag to hat_memload() to indicate h/w page tables 1396 * that map some user pages (not kas) is shared by more 1397 * than one process (eg. ISM). 1398 * 1399 * HAT_LOAD_REMAP Reload a valid pte with a different page frame. 1400 * 1401 * HAT_NO_KALLOC Do not kmem_alloc while creating the mapping; at this 1402 * point, it's setting up mapping to allocate internal 1403 * hat layer data structures. This flag forces hat layer 1404 * to tap its reserves in order to prevent infinite 1405 * recursion. 1406 * 1407 * The following is a protection attribute (like PROT_READ, etc.) 1408 * 1409 * HAT_NOSYNC set PT_NOSYNC - this mapping's ref/mod bits 1410 * are never cleared. 1411 * 1412 * Installing new valid PTE's and creation of the mapping list 1413 * entry are controlled under the same lock. It's derived from the 1414 * page_t being mapped. 1415 */ 1416 static uint_t supported_memload_flags = 1417 HAT_LOAD | HAT_LOAD_LOCK | HAT_LOAD_ADV | HAT_LOAD_NOCONSIST | 1418 HAT_LOAD_SHARE | HAT_NO_KALLOC | HAT_LOAD_REMAP | HAT_LOAD_TEXT; 1419 1420 void 1421 hat_memload( 1422 hat_t *hat, 1423 caddr_t addr, 1424 page_t *pp, 1425 uint_t attr, 1426 uint_t flags) 1427 { 1428 uintptr_t va = (uintptr_t)addr; 1429 level_t level = 0; 1430 pfn_t pfn = page_pptonum(pp); 1431 1432 ASSERT(IS_PAGEALIGNED(va)); 1433 ASSERT(hat == kas.a_hat || va < _userlimit); 1434 ASSERT(hat == kas.a_hat || 1435 AS_LOCK_HELD(hat->hat_as, &hat->hat_as->a_lock)); 1436 ASSERT((flags & supported_memload_flags) == flags); 1437 1438 ASSERT(!IN_VA_HOLE(va)); 1439 ASSERT(!PP_ISFREE(pp)); 1440 1441 /* 1442 * kernel address special case for performance. 1443 */ 1444 if (mmu.kmap_addr <= va && va < mmu.kmap_eaddr) { 1445 ASSERT(hat == kas.a_hat); 1446 hat_kmap_load(addr, pp, attr, flags); 1447 return; 1448 } 1449 1450 /* 1451 * This is used for memory with normal caching enabled, so 1452 * always set HAT_STORECACHING_OK. 1453 */ 1454 attr |= HAT_STORECACHING_OK; 1455 if (hati_load_common(hat, va, pp, attr, flags, level, pfn) != 0) 1456 panic("unexpected hati_load_common() failure"); 1457 } 1458 1459 /* ARGSUSED */ 1460 void 1461 hat_memload_region(struct hat *hat, caddr_t addr, struct page *pp, 1462 uint_t attr, uint_t flags, hat_region_cookie_t rcookie) 1463 { 1464 hat_memload(hat, addr, pp, attr, flags); 1465 } 1466 1467 /* 1468 * Load the given array of page structs using large pages when possible 1469 */ 1470 void 1471 hat_memload_array( 1472 hat_t *hat, 1473 caddr_t addr, 1474 size_t len, 1475 page_t **pages, 1476 uint_t attr, 1477 uint_t flags) 1478 { 1479 uintptr_t va = (uintptr_t)addr; 1480 uintptr_t eaddr = va + len; 1481 level_t level; 1482 size_t pgsize; 1483 pgcnt_t pgindx = 0; 1484 pfn_t pfn; 1485 pgcnt_t i; 1486 1487 ASSERT(IS_PAGEALIGNED(va)); 1488 ASSERT(hat == kas.a_hat || va + len <= _userlimit); 1489 ASSERT(hat == kas.a_hat || 1490 AS_LOCK_HELD(hat->hat_as, &hat->hat_as->a_lock)); 1491 ASSERT((flags & supported_memload_flags) == flags); 1492 1493 /* 1494 * memload is used for memory with full caching enabled, so 1495 * set HAT_STORECACHING_OK. 1496 */ 1497 attr |= HAT_STORECACHING_OK; 1498 1499 /* 1500 * handle all pages using largest possible pagesize 1501 */ 1502 while (va < eaddr) { 1503 /* 1504 * decide what level mapping to use (ie. pagesize) 1505 */ 1506 pfn = page_pptonum(pages[pgindx]); 1507 for (level = mmu.max_page_level; ; --level) { 1508 pgsize = LEVEL_SIZE(level); 1509 if (level == 0) 1510 break; 1511 1512 if (!IS_P2ALIGNED(va, pgsize) || 1513 (eaddr - va) < pgsize || 1514 !IS_P2ALIGNED(pfn_to_pa(pfn), pgsize)) 1515 continue; 1516 1517 /* 1518 * To use a large mapping of this size, all the 1519 * pages we are passed must be sequential subpages 1520 * of the large page. 1521 * hat_page_demote() can't change p_szc because 1522 * all pages are locked. 1523 */ 1524 if (pages[pgindx]->p_szc >= level) { 1525 for (i = 0; i < mmu_btop(pgsize); ++i) { 1526 if (pfn + i != 1527 page_pptonum(pages[pgindx + i])) 1528 break; 1529 ASSERT(pages[pgindx + i]->p_szc >= 1530 level); 1531 ASSERT(pages[pgindx] + i == 1532 pages[pgindx + i]); 1533 } 1534 if (i == mmu_btop(pgsize)) 1535 break; 1536 } 1537 } 1538 1539 /* 1540 * Load this page mapping. If the load fails, try a smaller 1541 * pagesize. 1542 */ 1543 ASSERT(!IN_VA_HOLE(va)); 1544 while (hati_load_common(hat, va, pages[pgindx], attr, 1545 flags, level, pfn) != 0) { 1546 if (level == 0) 1547 panic("unexpected hati_load_common() failure"); 1548 --level; 1549 pgsize = LEVEL_SIZE(level); 1550 } 1551 1552 /* 1553 * move to next page 1554 */ 1555 va += pgsize; 1556 pgindx += mmu_btop(pgsize); 1557 } 1558 } 1559 1560 /* ARGSUSED */ 1561 void 1562 hat_memload_array_region(struct hat *hat, caddr_t addr, size_t len, 1563 struct page **pps, uint_t attr, uint_t flags, 1564 hat_region_cookie_t rcookie) 1565 { 1566 hat_memload_array(hat, addr, len, pps, attr, flags); 1567 } 1568 1569 /* 1570 * void hat_devload(hat, addr, len, pf, attr, flags) 1571 * load/lock the given page frame number 1572 * 1573 * Advisory ordering attributes. Apply only to device mappings. 1574 * 1575 * HAT_STRICTORDER: the CPU must issue the references in order, as the 1576 * programmer specified. This is the default. 1577 * HAT_UNORDERED_OK: the CPU may reorder the references (this is all kinds 1578 * of reordering; store or load with store or load). 1579 * HAT_MERGING_OK: merging and batching: the CPU may merge individual stores 1580 * to consecutive locations (for example, turn two consecutive byte 1581 * stores into one halfword store), and it may batch individual loads 1582 * (for example, turn two consecutive byte loads into one halfword load). 1583 * This also implies re-ordering. 1584 * HAT_LOADCACHING_OK: the CPU may cache the data it fetches and reuse it 1585 * until another store occurs. The default is to fetch new data 1586 * on every load. This also implies merging. 1587 * HAT_STORECACHING_OK: the CPU may keep the data in the cache and push it to 1588 * the device (perhaps with other data) at a later time. The default is 1589 * to push the data right away. This also implies load caching. 1590 * 1591 * Equivalent of hat_memload(), but can be used for device memory where 1592 * there are no page_t's and we support additional flags (write merging, etc). 1593 * Note that we can have large page mappings with this interface. 1594 */ 1595 int supported_devload_flags = HAT_LOAD | HAT_LOAD_LOCK | 1596 HAT_LOAD_NOCONSIST | HAT_STRICTORDER | HAT_UNORDERED_OK | 1597 HAT_MERGING_OK | HAT_LOADCACHING_OK | HAT_STORECACHING_OK; 1598 1599 void 1600 hat_devload( 1601 hat_t *hat, 1602 caddr_t addr, 1603 size_t len, 1604 pfn_t pfn, 1605 uint_t attr, 1606 int flags) 1607 { 1608 uintptr_t va = ALIGN2PAGE(addr); 1609 uintptr_t eva = va + len; 1610 level_t level; 1611 size_t pgsize; 1612 page_t *pp; 1613 int f; /* per PTE copy of flags - maybe modified */ 1614 uint_t a; /* per PTE copy of attr */ 1615 1616 ASSERT(IS_PAGEALIGNED(va)); 1617 ASSERT(hat == kas.a_hat || eva <= _userlimit); 1618 ASSERT(hat == kas.a_hat || 1619 AS_LOCK_HELD(hat->hat_as, &hat->hat_as->a_lock)); 1620 ASSERT((flags & supported_devload_flags) == flags); 1621 1622 /* 1623 * handle all pages 1624 */ 1625 while (va < eva) { 1626 1627 /* 1628 * decide what level mapping to use (ie. pagesize) 1629 */ 1630 for (level = mmu.max_page_level; ; --level) { 1631 pgsize = LEVEL_SIZE(level); 1632 if (level == 0) 1633 break; 1634 if (IS_P2ALIGNED(va, pgsize) && 1635 (eva - va) >= pgsize && 1636 IS_P2ALIGNED(pfn, mmu_btop(pgsize))) 1637 break; 1638 } 1639 1640 /* 1641 * If this is just memory then allow caching (this happens 1642 * for the nucleus pages) - though HAT_PLAT_NOCACHE can be used 1643 * to override that. If we don't have a page_t then make sure 1644 * NOCONSIST is set. 1645 */ 1646 a = attr; 1647 f = flags; 1648 if (pf_is_memory(pfn)) { 1649 if (!(a & HAT_PLAT_NOCACHE)) 1650 a |= HAT_STORECACHING_OK; 1651 1652 if (f & HAT_LOAD_NOCONSIST) 1653 pp = NULL; 1654 else 1655 pp = page_numtopp_nolock(pfn); 1656 } else { 1657 pp = NULL; 1658 f |= HAT_LOAD_NOCONSIST; 1659 } 1660 1661 /* 1662 * load this page mapping 1663 */ 1664 ASSERT(!IN_VA_HOLE(va)); 1665 while (hati_load_common(hat, va, pp, a, f, level, pfn) != 0) { 1666 if (level == 0) 1667 panic("unexpected hati_load_common() failure"); 1668 --level; 1669 pgsize = LEVEL_SIZE(level); 1670 } 1671 1672 /* 1673 * move to next page 1674 */ 1675 va += pgsize; 1676 pfn += mmu_btop(pgsize); 1677 } 1678 } 1679 1680 /* 1681 * void hat_unlock(hat, addr, len) 1682 * unlock the mappings to a given range of addresses 1683 * 1684 * Locks are tracked by ht_lock_cnt in the htable. 1685 */ 1686 void 1687 hat_unlock(hat_t *hat, caddr_t addr, size_t len) 1688 { 1689 uintptr_t vaddr = (uintptr_t)addr; 1690 uintptr_t eaddr = vaddr + len; 1691 htable_t *ht = NULL; 1692 1693 /* 1694 * kernel entries are always locked, we don't track lock counts 1695 */ 1696 ASSERT(hat == kas.a_hat || eaddr <= _userlimit); 1697 ASSERT(IS_PAGEALIGNED(vaddr)); 1698 ASSERT(IS_PAGEALIGNED(eaddr)); 1699 if (hat == kas.a_hat) 1700 return; 1701 if (eaddr > _userlimit) 1702 panic("hat_unlock() address out of range - above _userlimit"); 1703 1704 ASSERT(AS_LOCK_HELD(hat->hat_as, &hat->hat_as->a_lock)); 1705 while (vaddr < eaddr) { 1706 (void) htable_walk(hat, &ht, &vaddr, eaddr); 1707 if (ht == NULL) 1708 break; 1709 1710 ASSERT(!IN_VA_HOLE(vaddr)); 1711 1712 if (ht->ht_lock_cnt < 1) 1713 panic("hat_unlock(): lock_cnt < 1, " 1714 "htable=%p, vaddr=%p\n", ht, (caddr_t)vaddr); 1715 HTABLE_LOCK_DEC(ht); 1716 1717 vaddr += LEVEL_SIZE(ht->ht_level); 1718 } 1719 if (ht) 1720 htable_release(ht); 1721 } 1722 1723 /* ARGSUSED */ 1724 void 1725 hat_unlock_region(struct hat *sfmmup, caddr_t addr, size_t len, 1726 hat_region_cookie_t rcookie) 1727 { 1728 panic("No shared region support on x86"); 1729 } 1730 1731 /* 1732 * Cross call service routine to demap a virtual page on 1733 * the current CPU or flush all mappings in TLB. 1734 */ 1735 /*ARGSUSED*/ 1736 static int 1737 hati_demap_func(xc_arg_t a1, xc_arg_t a2, xc_arg_t a3) 1738 { 1739 hat_t *hat = (hat_t *)a1; 1740 caddr_t addr = (caddr_t)a2; 1741 1742 /* 1743 * If the target hat isn't the kernel and this CPU isn't operating 1744 * in the target hat, we can ignore the cross call. 1745 */ 1746 if (hat != kas.a_hat && hat != CPU->cpu_current_hat) 1747 return (0); 1748 1749 /* 1750 * For a normal address, we just flush one page mapping 1751 */ 1752 if ((uintptr_t)addr != DEMAP_ALL_ADDR) { 1753 mmu_tlbflush_entry(addr); 1754 return (0); 1755 } 1756 1757 /* 1758 * Otherwise we reload cr3 to effect a complete TLB flush. 1759 * 1760 * A reload of cr3 on a VLP process also means we must also recopy in 1761 * the pte values from the struct hat 1762 */ 1763 if (hat->hat_flags & HAT_VLP) { 1764 #if defined(__amd64) 1765 x86pte_t *vlpptep = CPU->cpu_hat_info->hci_vlp_l2ptes; 1766 1767 VLP_COPY(hat->hat_vlp_ptes, vlpptep); 1768 #elif defined(__i386) 1769 reload_pae32(hat, CPU); 1770 #endif 1771 } 1772 reload_cr3(); 1773 return (0); 1774 } 1775 1776 /* 1777 * Flush all TLB entries, including global (ie. kernel) ones. 1778 */ 1779 static void 1780 flush_all_tlb_entries(void) 1781 { 1782 ulong_t cr4 = getcr4(); 1783 1784 if (cr4 & CR4_PGE) { 1785 setcr4(cr4 & ~(ulong_t)CR4_PGE); 1786 setcr4(cr4); 1787 1788 /* 1789 * 32 bit PAE also needs to always reload_cr3() 1790 */ 1791 if (mmu.max_level == 2) 1792 reload_cr3(); 1793 } else { 1794 reload_cr3(); 1795 } 1796 } 1797 1798 #define TLB_CPU_HALTED (01ul) 1799 #define TLB_INVAL_ALL (02ul) 1800 #define CAS_TLB_INFO(cpu, old, new) \ 1801 caslong((ulong_t *)&(cpu)->cpu_m.mcpu_tlb_info, (old), (new)) 1802 1803 /* 1804 * Record that a CPU is going idle 1805 */ 1806 void 1807 tlb_going_idle(void) 1808 { 1809 atomic_or_long((ulong_t *)&CPU->cpu_m.mcpu_tlb_info, TLB_CPU_HALTED); 1810 } 1811 1812 /* 1813 * Service a delayed TLB flush if coming out of being idle. 1814 */ 1815 void 1816 tlb_service(void) 1817 { 1818 ulong_t flags = getflags(); 1819 ulong_t tlb_info; 1820 ulong_t found; 1821 1822 /* 1823 * Be sure interrupts are off while doing this so that 1824 * higher level interrupts correctly wait for flushes to finish. 1825 */ 1826 if (flags & PS_IE) 1827 flags = intr_clear(); 1828 1829 /* 1830 * We only have to do something if coming out of being idle. 1831 */ 1832 tlb_info = CPU->cpu_m.mcpu_tlb_info; 1833 if (tlb_info & TLB_CPU_HALTED) { 1834 ASSERT(CPU->cpu_current_hat == kas.a_hat); 1835 1836 /* 1837 * Atomic clear and fetch of old state. 1838 */ 1839 while ((found = CAS_TLB_INFO(CPU, tlb_info, 0)) != tlb_info) { 1840 ASSERT(found & TLB_CPU_HALTED); 1841 tlb_info = found; 1842 SMT_PAUSE(); 1843 } 1844 if (tlb_info & TLB_INVAL_ALL) 1845 flush_all_tlb_entries(); 1846 } 1847 1848 /* 1849 * Restore interrupt enable control bit. 1850 */ 1851 if (flags & PS_IE) 1852 sti(); 1853 } 1854 1855 /* 1856 * Internal routine to do cross calls to invalidate a range of pages on 1857 * all CPUs using a given hat. 1858 */ 1859 void 1860 hat_tlb_inval(hat_t *hat, uintptr_t va) 1861 { 1862 extern int flushes_require_xcalls; /* from mp_startup.c */ 1863 cpuset_t justme; 1864 cpuset_t check_cpus; 1865 cpuset_t cpus_to_shootdown; 1866 cpu_t *cpup; 1867 int c; 1868 1869 /* 1870 * If the hat is being destroyed, there are no more users, so 1871 * demap need not do anything. 1872 */ 1873 if (hat->hat_flags & HAT_FREEING) 1874 return; 1875 1876 /* 1877 * If demapping from a shared pagetable, we best demap the 1878 * entire set of user TLBs, since we don't know what addresses 1879 * these were shared at. 1880 */ 1881 if (hat->hat_flags & HAT_SHARED) { 1882 hat = kas.a_hat; 1883 va = DEMAP_ALL_ADDR; 1884 } 1885 1886 /* 1887 * if not running with multiple CPUs, don't use cross calls 1888 */ 1889 if (panicstr || !flushes_require_xcalls) { 1890 (void) hati_demap_func((xc_arg_t)hat, (xc_arg_t)va, NULL); 1891 return; 1892 } 1893 1894 1895 /* 1896 * Determine CPUs to shootdown. Kernel changes always do all CPUs. 1897 * Otherwise it's just CPUs currently executing in this hat. 1898 */ 1899 kpreempt_disable(); 1900 CPUSET_ONLY(justme, CPU->cpu_id); 1901 if (hat == kas.a_hat) 1902 cpus_to_shootdown = khat_cpuset; 1903 else 1904 cpus_to_shootdown = hat->hat_cpus; 1905 1906 /* 1907 * If any CPUs in the set are idle, just request a delayed flush 1908 * and avoid waking them up. 1909 */ 1910 check_cpus = cpus_to_shootdown; 1911 for (c = 0; c < NCPU && !CPUSET_ISNULL(check_cpus); ++c) { 1912 ulong_t tlb_info; 1913 1914 if (!CPU_IN_SET(check_cpus, c)) 1915 continue; 1916 CPUSET_DEL(check_cpus, c); 1917 cpup = cpu[c]; 1918 if (cpup == NULL) 1919 continue; 1920 1921 tlb_info = cpup->cpu_m.mcpu_tlb_info; 1922 while (tlb_info == TLB_CPU_HALTED) { 1923 (void) CAS_TLB_INFO(cpup, TLB_CPU_HALTED, 1924 TLB_CPU_HALTED | TLB_INVAL_ALL); 1925 SMT_PAUSE(); 1926 tlb_info = cpup->cpu_m.mcpu_tlb_info; 1927 } 1928 if (tlb_info == (TLB_CPU_HALTED | TLB_INVAL_ALL)) { 1929 HATSTAT_INC(hs_tlb_inval_delayed); 1930 CPUSET_DEL(cpus_to_shootdown, c); 1931 } 1932 } 1933 1934 if (CPUSET_ISNULL(cpus_to_shootdown) || 1935 CPUSET_ISEQUAL(cpus_to_shootdown, justme)) { 1936 1937 (void) hati_demap_func((xc_arg_t)hat, (xc_arg_t)va, NULL); 1938 1939 } else { 1940 1941 CPUSET_ADD(cpus_to_shootdown, CPU->cpu_id); 1942 xc_call((xc_arg_t)hat, (xc_arg_t)va, NULL, X_CALL_HIPRI, 1943 cpus_to_shootdown, hati_demap_func); 1944 1945 } 1946 kpreempt_enable(); 1947 } 1948 1949 /* 1950 * Interior routine for HAT_UNLOADs from hat_unload_callback(), 1951 * hat_kmap_unload() OR from hat_steal() code. This routine doesn't 1952 * handle releasing of the htables. 1953 */ 1954 void 1955 hat_pte_unmap( 1956 htable_t *ht, 1957 uint_t entry, 1958 uint_t flags, 1959 x86pte_t old_pte, 1960 void *pte_ptr) 1961 { 1962 hat_t *hat = ht->ht_hat; 1963 hment_t *hm = NULL; 1964 page_t *pp = NULL; 1965 level_t l = ht->ht_level; 1966 pfn_t pfn; 1967 1968 /* 1969 * We always track the locking counts, even if nothing is unmapped 1970 */ 1971 if ((flags & HAT_UNLOAD_UNLOCK) != 0 && hat != kas.a_hat) { 1972 ASSERT(ht->ht_lock_cnt > 0); 1973 HTABLE_LOCK_DEC(ht); 1974 } 1975 1976 /* 1977 * Figure out which page's mapping list lock to acquire using the PFN 1978 * passed in "old" PTE. We then attempt to invalidate the PTE. 1979 * If another thread, probably a hat_pageunload, has asynchronously 1980 * unmapped/remapped this address we'll loop here. 1981 */ 1982 ASSERT(ht->ht_busy > 0); 1983 while (PTE_ISVALID(old_pte)) { 1984 pfn = PTE2PFN(old_pte, l); 1985 if (PTE_GET(old_pte, PT_SOFTWARE) >= PT_NOCONSIST) { 1986 pp = NULL; 1987 } else { 1988 pp = page_numtopp_nolock(pfn); 1989 if (pp == NULL) { 1990 panic("no page_t, not NOCONSIST: old_pte=" 1991 FMT_PTE " ht=%lx entry=0x%x pte_ptr=%lx", 1992 old_pte, (uintptr_t)ht, entry, 1993 (uintptr_t)pte_ptr); 1994 } 1995 x86_hm_enter(pp); 1996 } 1997 1998 /* 1999 * If freeing the address space, check that the PTE 2000 * hasn't changed, as the mappings are no longer in use by 2001 * any thread, invalidation is unnecessary. 2002 * If not freeing, do a full invalidate. 2003 */ 2004 if (hat->hat_flags & HAT_FREEING) 2005 old_pte = x86pte_get(ht, entry); 2006 else 2007 old_pte = x86pte_inval(ht, entry, old_pte, pte_ptr); 2008 2009 /* 2010 * If the page hadn't changed we've unmapped it and can proceed 2011 */ 2012 if (PTE_ISVALID(old_pte) && PTE2PFN(old_pte, l) == pfn) 2013 break; 2014 2015 /* 2016 * Otherwise, we'll have to retry with the current old_pte. 2017 * Drop the hment lock, since the pfn may have changed. 2018 */ 2019 if (pp != NULL) { 2020 x86_hm_exit(pp); 2021 pp = NULL; 2022 } else { 2023 ASSERT(PTE_GET(old_pte, PT_SOFTWARE) >= PT_NOCONSIST); 2024 } 2025 } 2026 2027 /* 2028 * If the old mapping wasn't valid, there's nothing more to do 2029 */ 2030 if (!PTE_ISVALID(old_pte)) { 2031 if (pp != NULL) 2032 x86_hm_exit(pp); 2033 return; 2034 } 2035 2036 /* 2037 * Take care of syncing any MOD/REF bits and removing the hment. 2038 */ 2039 if (pp != NULL) { 2040 if (!(flags & HAT_UNLOAD_NOSYNC)) 2041 hati_sync_pte_to_page(pp, old_pte, l); 2042 hm = hment_remove(pp, ht, entry); 2043 x86_hm_exit(pp); 2044 if (hm != NULL) 2045 hment_free(hm); 2046 } 2047 2048 /* 2049 * Handle book keeping in the htable and hat 2050 */ 2051 ASSERT(ht->ht_valid_cnt > 0); 2052 HTABLE_DEC(ht->ht_valid_cnt); 2053 PGCNT_DEC(hat, l); 2054 } 2055 2056 /* 2057 * very cheap unload implementation to special case some kernel addresses 2058 */ 2059 static void 2060 hat_kmap_unload(caddr_t addr, size_t len, uint_t flags) 2061 { 2062 uintptr_t va = (uintptr_t)addr; 2063 uintptr_t eva = va + len; 2064 pgcnt_t pg_index; 2065 htable_t *ht; 2066 uint_t entry; 2067 x86pte_t *pte_ptr; 2068 x86pte_t old_pte; 2069 2070 for (; va < eva; va += MMU_PAGESIZE) { 2071 /* 2072 * Get the PTE 2073 */ 2074 pg_index = mmu_btop(va - mmu.kmap_addr); 2075 pte_ptr = PT_INDEX_PTR(mmu.kmap_ptes, pg_index); 2076 old_pte = GET_PTE(pte_ptr); 2077 2078 /* 2079 * get the htable / entry 2080 */ 2081 ht = mmu.kmap_htables[(va - mmu.kmap_htables[0]->ht_vaddr) 2082 >> LEVEL_SHIFT(1)]; 2083 entry = htable_va2entry(va, ht); 2084 2085 /* 2086 * use mostly common code to unmap it. 2087 */ 2088 hat_pte_unmap(ht, entry, flags, old_pte, pte_ptr); 2089 } 2090 } 2091 2092 2093 /* 2094 * unload a range of virtual address space (no callback) 2095 */ 2096 void 2097 hat_unload(hat_t *hat, caddr_t addr, size_t len, uint_t flags) 2098 { 2099 uintptr_t va = (uintptr_t)addr; 2100 2101 ASSERT(hat == kas.a_hat || va + len <= _userlimit); 2102 2103 /* 2104 * special case for performance. 2105 */ 2106 if (mmu.kmap_addr <= va && va < mmu.kmap_eaddr) { 2107 ASSERT(hat == kas.a_hat); 2108 hat_kmap_unload(addr, len, flags); 2109 } else { 2110 hat_unload_callback(hat, addr, len, flags, NULL); 2111 } 2112 } 2113 2114 /* 2115 * Do the callbacks for ranges being unloaded. 2116 */ 2117 typedef struct range_info { 2118 uintptr_t rng_va; 2119 ulong_t rng_cnt; 2120 level_t rng_level; 2121 } range_info_t; 2122 2123 static void 2124 handle_ranges(hat_callback_t *cb, uint_t cnt, range_info_t *range) 2125 { 2126 /* 2127 * do callbacks to upper level VM system 2128 */ 2129 while (cb != NULL && cnt > 0) { 2130 --cnt; 2131 cb->hcb_start_addr = (caddr_t)range[cnt].rng_va; 2132 cb->hcb_end_addr = cb->hcb_start_addr; 2133 cb->hcb_end_addr += 2134 range[cnt].rng_cnt << LEVEL_SIZE(range[cnt].rng_level); 2135 cb->hcb_function(cb); 2136 } 2137 } 2138 2139 /* 2140 * Unload a given range of addresses (has optional callback) 2141 * 2142 * Flags: 2143 * define HAT_UNLOAD 0x00 2144 * define HAT_UNLOAD_NOSYNC 0x02 2145 * define HAT_UNLOAD_UNLOCK 0x04 2146 * define HAT_UNLOAD_OTHER 0x08 - not used 2147 * define HAT_UNLOAD_UNMAP 0x10 - same as HAT_UNLOAD 2148 */ 2149 #define MAX_UNLOAD_CNT (8) 2150 void 2151 hat_unload_callback( 2152 hat_t *hat, 2153 caddr_t addr, 2154 size_t len, 2155 uint_t flags, 2156 hat_callback_t *cb) 2157 { 2158 uintptr_t vaddr = (uintptr_t)addr; 2159 uintptr_t eaddr = vaddr + len; 2160 htable_t *ht = NULL; 2161 uint_t entry; 2162 uintptr_t contig_va = (uintptr_t)-1L; 2163 range_info_t r[MAX_UNLOAD_CNT]; 2164 uint_t r_cnt = 0; 2165 x86pte_t old_pte; 2166 2167 ASSERT(hat == kas.a_hat || eaddr <= _userlimit); 2168 ASSERT(IS_PAGEALIGNED(vaddr)); 2169 ASSERT(IS_PAGEALIGNED(eaddr)); 2170 2171 /* 2172 * Special case a single page being unloaded for speed. This happens 2173 * quite frequently, COW faults after a fork() for example. 2174 */ 2175 if (cb == NULL && len == MMU_PAGESIZE) { 2176 ht = htable_getpte(hat, vaddr, &entry, &old_pte, 0); 2177 if (ht != NULL) { 2178 if (PTE_ISVALID(old_pte)) 2179 hat_pte_unmap(ht, entry, flags, old_pte, NULL); 2180 htable_release(ht); 2181 } 2182 return; 2183 } 2184 2185 while (vaddr < eaddr) { 2186 old_pte = htable_walk(hat, &ht, &vaddr, eaddr); 2187 if (ht == NULL) 2188 break; 2189 2190 ASSERT(!IN_VA_HOLE(vaddr)); 2191 2192 if (vaddr < (uintptr_t)addr) 2193 panic("hat_unload_callback(): unmap inside large page"); 2194 2195 /* 2196 * We'll do the call backs for contiguous ranges 2197 */ 2198 if (vaddr != contig_va || 2199 (r_cnt > 0 && r[r_cnt - 1].rng_level != ht->ht_level)) { 2200 if (r_cnt == MAX_UNLOAD_CNT) { 2201 handle_ranges(cb, r_cnt, r); 2202 r_cnt = 0; 2203 } 2204 r[r_cnt].rng_va = vaddr; 2205 r[r_cnt].rng_cnt = 0; 2206 r[r_cnt].rng_level = ht->ht_level; 2207 ++r_cnt; 2208 } 2209 2210 /* 2211 * Unload one mapping from the page tables. 2212 */ 2213 entry = htable_va2entry(vaddr, ht); 2214 hat_pte_unmap(ht, entry, flags, old_pte, NULL); 2215 ASSERT(ht->ht_level <= mmu.max_page_level); 2216 vaddr += LEVEL_SIZE(ht->ht_level); 2217 contig_va = vaddr; 2218 ++r[r_cnt - 1].rng_cnt; 2219 } 2220 if (ht) 2221 htable_release(ht); 2222 2223 /* 2224 * handle last range for callbacks 2225 */ 2226 if (r_cnt > 0) 2227 handle_ranges(cb, r_cnt, r); 2228 } 2229 2230 /* 2231 * synchronize mapping with software data structures 2232 * 2233 * This interface is currently only used by the working set monitor 2234 * driver. 2235 */ 2236 /*ARGSUSED*/ 2237 void 2238 hat_sync(hat_t *hat, caddr_t addr, size_t len, uint_t flags) 2239 { 2240 uintptr_t vaddr = (uintptr_t)addr; 2241 uintptr_t eaddr = vaddr + len; 2242 htable_t *ht = NULL; 2243 uint_t entry; 2244 x86pte_t pte; 2245 x86pte_t save_pte; 2246 x86pte_t new; 2247 page_t *pp; 2248 2249 ASSERT(!IN_VA_HOLE(vaddr)); 2250 ASSERT(IS_PAGEALIGNED(vaddr)); 2251 ASSERT(IS_PAGEALIGNED(eaddr)); 2252 ASSERT(hat == kas.a_hat || eaddr <= _userlimit); 2253 2254 for (; vaddr < eaddr; vaddr += LEVEL_SIZE(ht->ht_level)) { 2255 try_again: 2256 pte = htable_walk(hat, &ht, &vaddr, eaddr); 2257 if (ht == NULL) 2258 break; 2259 entry = htable_va2entry(vaddr, ht); 2260 2261 if (PTE_GET(pte, PT_SOFTWARE) >= PT_NOSYNC || 2262 PTE_GET(pte, PT_REF | PT_MOD) == 0) 2263 continue; 2264 2265 /* 2266 * We need to acquire the mapping list lock to protect 2267 * against hat_pageunload(), hat_unload(), etc. 2268 */ 2269 pp = page_numtopp_nolock(PTE2PFN(pte, ht->ht_level)); 2270 if (pp == NULL) 2271 break; 2272 x86_hm_enter(pp); 2273 save_pte = pte; 2274 pte = x86pte_get(ht, entry); 2275 if (pte != save_pte) { 2276 x86_hm_exit(pp); 2277 goto try_again; 2278 } 2279 if (PTE_GET(pte, PT_SOFTWARE) >= PT_NOSYNC || 2280 PTE_GET(pte, PT_REF | PT_MOD) == 0) { 2281 x86_hm_exit(pp); 2282 continue; 2283 } 2284 2285 /* 2286 * Need to clear ref or mod bits. We may compete with 2287 * hardware updating the R/M bits and have to try again. 2288 */ 2289 if (flags == HAT_SYNC_ZERORM) { 2290 new = pte; 2291 PTE_CLR(new, PT_REF | PT_MOD); 2292 pte = hati_update_pte(ht, entry, pte, new); 2293 if (pte != 0) { 2294 x86_hm_exit(pp); 2295 goto try_again; 2296 } 2297 } else { 2298 /* 2299 * sync the PTE to the page_t 2300 */ 2301 hati_sync_pte_to_page(pp, save_pte, ht->ht_level); 2302 } 2303 x86_hm_exit(pp); 2304 } 2305 if (ht) 2306 htable_release(ht); 2307 } 2308 2309 /* 2310 * void hat_map(hat, addr, len, flags) 2311 */ 2312 /*ARGSUSED*/ 2313 void 2314 hat_map(hat_t *hat, caddr_t addr, size_t len, uint_t flags) 2315 { 2316 /* does nothing */ 2317 } 2318 2319 /* 2320 * uint_t hat_getattr(hat, addr, *attr) 2321 * returns attr for <hat,addr> in *attr. returns 0 if there was a 2322 * mapping and *attr is valid, nonzero if there was no mapping and 2323 * *attr is not valid. 2324 */ 2325 uint_t 2326 hat_getattr(hat_t *hat, caddr_t addr, uint_t *attr) 2327 { 2328 uintptr_t vaddr = ALIGN2PAGE(addr); 2329 htable_t *ht = NULL; 2330 x86pte_t pte; 2331 2332 ASSERT(hat == kas.a_hat || vaddr <= _userlimit); 2333 2334 if (IN_VA_HOLE(vaddr)) 2335 return ((uint_t)-1); 2336 2337 ht = htable_getpte(hat, vaddr, NULL, &pte, mmu.max_page_level); 2338 if (ht == NULL) 2339 return ((uint_t)-1); 2340 2341 if (!PTE_ISVALID(pte) || !PTE_ISPAGE(pte, ht->ht_level)) { 2342 htable_release(ht); 2343 return ((uint_t)-1); 2344 } 2345 2346 *attr = PROT_READ; 2347 if (PTE_GET(pte, PT_WRITABLE)) 2348 *attr |= PROT_WRITE; 2349 if (PTE_GET(pte, PT_USER)) 2350 *attr |= PROT_USER; 2351 if (!PTE_GET(pte, mmu.pt_nx)) 2352 *attr |= PROT_EXEC; 2353 if (PTE_GET(pte, PT_SOFTWARE) >= PT_NOSYNC) 2354 *attr |= HAT_NOSYNC; 2355 htable_release(ht); 2356 return (0); 2357 } 2358 2359 /* 2360 * hat_updateattr() applies the given attribute change to an existing mapping 2361 */ 2362 #define HAT_LOAD_ATTR 1 2363 #define HAT_SET_ATTR 2 2364 #define HAT_CLR_ATTR 3 2365 2366 static void 2367 hat_updateattr(hat_t *hat, caddr_t addr, size_t len, uint_t attr, int what) 2368 { 2369 uintptr_t vaddr = (uintptr_t)addr; 2370 uintptr_t eaddr = (uintptr_t)addr + len; 2371 htable_t *ht = NULL; 2372 uint_t entry; 2373 x86pte_t oldpte, newpte; 2374 page_t *pp; 2375 2376 ASSERT(IS_PAGEALIGNED(vaddr)); 2377 ASSERT(IS_PAGEALIGNED(eaddr)); 2378 ASSERT(hat == kas.a_hat || 2379 AS_LOCK_HELD(hat->hat_as, &hat->hat_as->a_lock)); 2380 for (; vaddr < eaddr; vaddr += LEVEL_SIZE(ht->ht_level)) { 2381 try_again: 2382 oldpte = htable_walk(hat, &ht, &vaddr, eaddr); 2383 if (ht == NULL) 2384 break; 2385 if (PTE_GET(oldpte, PT_SOFTWARE) >= PT_NOCONSIST) 2386 continue; 2387 2388 pp = page_numtopp_nolock(PTE2PFN(oldpte, ht->ht_level)); 2389 if (pp == NULL) 2390 continue; 2391 x86_hm_enter(pp); 2392 2393 newpte = oldpte; 2394 /* 2395 * We found a page table entry in the desired range, 2396 * figure out the new attributes. 2397 */ 2398 if (what == HAT_SET_ATTR || what == HAT_LOAD_ATTR) { 2399 if ((attr & PROT_WRITE) && 2400 !PTE_GET(oldpte, PT_WRITABLE)) 2401 newpte |= PT_WRITABLE; 2402 2403 if ((attr & HAT_NOSYNC) && 2404 PTE_GET(oldpte, PT_SOFTWARE) < PT_NOSYNC) 2405 newpte |= PT_NOSYNC; 2406 2407 if ((attr & PROT_EXEC) && PTE_GET(oldpte, mmu.pt_nx)) 2408 newpte &= ~mmu.pt_nx; 2409 } 2410 2411 if (what == HAT_LOAD_ATTR) { 2412 if (!(attr & PROT_WRITE) && 2413 PTE_GET(oldpte, PT_WRITABLE)) 2414 newpte &= ~PT_WRITABLE; 2415 2416 if (!(attr & HAT_NOSYNC) && 2417 PTE_GET(oldpte, PT_SOFTWARE) >= PT_NOSYNC) 2418 newpte &= ~PT_SOFTWARE; 2419 2420 if (!(attr & PROT_EXEC) && !PTE_GET(oldpte, mmu.pt_nx)) 2421 newpte |= mmu.pt_nx; 2422 } 2423 2424 if (what == HAT_CLR_ATTR) { 2425 if ((attr & PROT_WRITE) && PTE_GET(oldpte, PT_WRITABLE)) 2426 newpte &= ~PT_WRITABLE; 2427 2428 if ((attr & HAT_NOSYNC) && 2429 PTE_GET(oldpte, PT_SOFTWARE) >= PT_NOSYNC) 2430 newpte &= ~PT_SOFTWARE; 2431 2432 if ((attr & PROT_EXEC) && !PTE_GET(oldpte, mmu.pt_nx)) 2433 newpte |= mmu.pt_nx; 2434 } 2435 2436 /* 2437 * Ensure NOSYNC/NOCONSIST mappings have REF and MOD set. 2438 * x86pte_set() depends on this. 2439 */ 2440 if (PTE_GET(newpte, PT_SOFTWARE) >= PT_NOSYNC) 2441 newpte |= PT_REF | PT_MOD; 2442 2443 /* 2444 * what about PROT_READ or others? this code only handles: 2445 * EXEC, WRITE, NOSYNC 2446 */ 2447 2448 /* 2449 * If new PTE really changed, update the table. 2450 */ 2451 if (newpte != oldpte) { 2452 entry = htable_va2entry(vaddr, ht); 2453 oldpte = hati_update_pte(ht, entry, oldpte, newpte); 2454 if (oldpte != 0) { 2455 x86_hm_exit(pp); 2456 goto try_again; 2457 } 2458 } 2459 x86_hm_exit(pp); 2460 } 2461 if (ht) 2462 htable_release(ht); 2463 } 2464 2465 /* 2466 * Various wrappers for hat_updateattr() 2467 */ 2468 void 2469 hat_setattr(hat_t *hat, caddr_t addr, size_t len, uint_t attr) 2470 { 2471 ASSERT(hat == kas.a_hat || (uintptr_t)addr + len <= _userlimit); 2472 hat_updateattr(hat, addr, len, attr, HAT_SET_ATTR); 2473 } 2474 2475 void 2476 hat_clrattr(hat_t *hat, caddr_t addr, size_t len, uint_t attr) 2477 { 2478 ASSERT(hat == kas.a_hat || (uintptr_t)addr + len <= _userlimit); 2479 hat_updateattr(hat, addr, len, attr, HAT_CLR_ATTR); 2480 } 2481 2482 void 2483 hat_chgattr(hat_t *hat, caddr_t addr, size_t len, uint_t attr) 2484 { 2485 ASSERT(hat == kas.a_hat || (uintptr_t)addr + len <= _userlimit); 2486 hat_updateattr(hat, addr, len, attr, HAT_LOAD_ATTR); 2487 } 2488 2489 void 2490 hat_chgprot(hat_t *hat, caddr_t addr, size_t len, uint_t vprot) 2491 { 2492 ASSERT(hat == kas.a_hat || (uintptr_t)addr + len <= _userlimit); 2493 hat_updateattr(hat, addr, len, vprot & HAT_PROT_MASK, HAT_LOAD_ATTR); 2494 } 2495 2496 /* 2497 * size_t hat_getpagesize(hat, addr) 2498 * returns pagesize in bytes for <hat, addr>. returns -1 of there is 2499 * no mapping. This is an advisory call. 2500 */ 2501 ssize_t 2502 hat_getpagesize(hat_t *hat, caddr_t addr) 2503 { 2504 uintptr_t vaddr = ALIGN2PAGE(addr); 2505 htable_t *ht; 2506 size_t pagesize; 2507 2508 ASSERT(hat == kas.a_hat || vaddr <= _userlimit); 2509 if (IN_VA_HOLE(vaddr)) 2510 return (-1); 2511 ht = htable_getpage(hat, vaddr, NULL); 2512 if (ht == NULL) 2513 return (-1); 2514 pagesize = LEVEL_SIZE(ht->ht_level); 2515 htable_release(ht); 2516 return (pagesize); 2517 } 2518 2519 2520 2521 /* 2522 * pfn_t hat_getpfnum(hat, addr) 2523 * returns pfn for <hat, addr> or PFN_INVALID if mapping is invalid. 2524 */ 2525 pfn_t 2526 hat_getpfnum(hat_t *hat, caddr_t addr) 2527 { 2528 uintptr_t vaddr = ALIGN2PAGE(addr); 2529 htable_t *ht; 2530 uint_t entry; 2531 pfn_t pfn = PFN_INVALID; 2532 2533 ASSERT(hat == kas.a_hat || vaddr <= _userlimit); 2534 if (khat_running == 0) 2535 return (PFN_INVALID); 2536 2537 if (IN_VA_HOLE(vaddr)) 2538 return (PFN_INVALID); 2539 2540 /* 2541 * A very common use of hat_getpfnum() is from the DDI for kernel pages. 2542 * Use the kmap_ptes (which also covers the 32 bit heap) to speed 2543 * this up. 2544 */ 2545 if (mmu.kmap_addr <= vaddr && vaddr < mmu.kmap_eaddr) { 2546 x86pte_t pte; 2547 pgcnt_t pg_index; 2548 2549 pg_index = mmu_btop(vaddr - mmu.kmap_addr); 2550 pte = GET_PTE(PT_INDEX_PTR(mmu.kmap_ptes, pg_index)); 2551 if (!PTE_ISVALID(pte)) 2552 return (PFN_INVALID); 2553 /*LINTED [use of constant 0 causes a silly lint warning] */ 2554 return (PTE2PFN(pte, 0)); 2555 } 2556 2557 ht = htable_getpage(hat, vaddr, &entry); 2558 if (ht == NULL) 2559 return (PFN_INVALID); 2560 ASSERT(vaddr >= ht->ht_vaddr); 2561 ASSERT(vaddr <= HTABLE_LAST_PAGE(ht)); 2562 pfn = PTE2PFN(x86pte_get(ht, entry), ht->ht_level); 2563 if (ht->ht_level > 0) 2564 pfn += mmu_btop(vaddr & LEVEL_OFFSET(ht->ht_level)); 2565 htable_release(ht); 2566 return (pfn); 2567 } 2568 2569 /* 2570 * hat_getkpfnum() is an obsolete DDI routine, and its use is discouraged. 2571 * Use hat_getpfnum(kas.a_hat, ...) instead. 2572 * 2573 * We'd like to return PFN_INVALID if the mappings have underlying page_t's 2574 * but can't right now due to the fact that some software has grown to use 2575 * this interface incorrectly. So for now when the interface is misused, 2576 * return a warning to the user that in the future it won't work in the 2577 * way they're abusing it, and carry on. 2578 * 2579 * Note that hat_getkpfnum() is never supported on amd64. 2580 */ 2581 #if !defined(__amd64) 2582 pfn_t 2583 hat_getkpfnum(caddr_t addr) 2584 { 2585 pfn_t pfn; 2586 int badcaller = 0; 2587 2588 if (khat_running == 0) 2589 panic("hat_getkpfnum(): called too early\n"); 2590 if ((uintptr_t)addr < kernelbase) 2591 return (PFN_INVALID); 2592 2593 2594 if (segkpm && IS_KPM_ADDR(addr)) { 2595 badcaller = 1; 2596 pfn = hat_kpm_va2pfn(addr); 2597 } else { 2598 pfn = hat_getpfnum(kas.a_hat, addr); 2599 badcaller = pf_is_memory(pfn); 2600 } 2601 2602 if (badcaller) 2603 hat_getkpfnum_badcall(caller()); 2604 return (pfn); 2605 } 2606 #endif /* __amd64 */ 2607 2608 /* 2609 * int hat_probe(hat, addr) 2610 * return 0 if no valid mapping is present. Faster version 2611 * of hat_getattr in certain architectures. 2612 */ 2613 int 2614 hat_probe(hat_t *hat, caddr_t addr) 2615 { 2616 uintptr_t vaddr = ALIGN2PAGE(addr); 2617 uint_t entry; 2618 htable_t *ht; 2619 pgcnt_t pg_off; 2620 2621 ASSERT(hat == kas.a_hat || vaddr <= _userlimit); 2622 ASSERT(hat == kas.a_hat || 2623 AS_LOCK_HELD(hat->hat_as, &hat->hat_as->a_lock)); 2624 if (IN_VA_HOLE(vaddr)) 2625 return (0); 2626 2627 /* 2628 * Most common use of hat_probe is from segmap. We special case it 2629 * for performance. 2630 */ 2631 if (mmu.kmap_addr <= vaddr && vaddr < mmu.kmap_eaddr) { 2632 pg_off = mmu_btop(vaddr - mmu.kmap_addr); 2633 if (mmu.pae_hat) 2634 return (PTE_ISVALID(mmu.kmap_ptes[pg_off])); 2635 else 2636 return (PTE_ISVALID( 2637 ((x86pte32_t *)mmu.kmap_ptes)[pg_off])); 2638 } 2639 2640 ht = htable_getpage(hat, vaddr, &entry); 2641 if (ht == NULL) 2642 return (0); 2643 htable_release(ht); 2644 return (1); 2645 } 2646 2647 /* 2648 * Find out if the segment for hat_share()/hat_unshare() is DISM or locked ISM. 2649 */ 2650 static int 2651 is_it_dism(hat_t *hat, caddr_t va) 2652 { 2653 struct seg *seg; 2654 struct shm_data *shmd; 2655 struct spt_data *sptd; 2656 2657 seg = as_findseg(hat->hat_as, va, 0); 2658 ASSERT(seg != NULL); 2659 ASSERT(seg->s_base <= va); 2660 shmd = (struct shm_data *)seg->s_data; 2661 ASSERT(shmd != NULL); 2662 sptd = (struct spt_data *)shmd->shm_sptseg->s_data; 2663 ASSERT(sptd != NULL); 2664 if (sptd->spt_flags & SHM_PAGEABLE) 2665 return (1); 2666 return (0); 2667 } 2668 2669 /* 2670 * Simple implementation of ISM. hat_share() is similar to hat_memload_array(), 2671 * except that we use the ism_hat's existing mappings to determine the pages 2672 * and protections to use for this hat. If we find a full properly aligned 2673 * and sized pagetable, we will attempt to share the pagetable itself. 2674 */ 2675 /*ARGSUSED*/ 2676 int 2677 hat_share( 2678 hat_t *hat, 2679 caddr_t addr, 2680 hat_t *ism_hat, 2681 caddr_t src_addr, 2682 size_t len, /* almost useless value, see below.. */ 2683 uint_t ismszc) 2684 { 2685 uintptr_t vaddr_start = (uintptr_t)addr; 2686 uintptr_t vaddr; 2687 uintptr_t eaddr = vaddr_start + len; 2688 uintptr_t ism_addr_start = (uintptr_t)src_addr; 2689 uintptr_t ism_addr = ism_addr_start; 2690 uintptr_t e_ism_addr = ism_addr + len; 2691 htable_t *ism_ht = NULL; 2692 htable_t *ht; 2693 x86pte_t pte; 2694 page_t *pp; 2695 pfn_t pfn; 2696 level_t l; 2697 pgcnt_t pgcnt; 2698 uint_t prot; 2699 int is_dism; 2700 int flags; 2701 2702 /* 2703 * We might be asked to share an empty DISM hat by as_dup() 2704 */ 2705 ASSERT(hat != kas.a_hat); 2706 ASSERT(eaddr <= _userlimit); 2707 if (!(ism_hat->hat_flags & HAT_SHARED)) { 2708 ASSERT(hat_get_mapped_size(ism_hat) == 0); 2709 return (0); 2710 } 2711 2712 /* 2713 * The SPT segment driver often passes us a size larger than there are 2714 * valid mappings. That's because it rounds the segment size up to a 2715 * large pagesize, even if the actual memory mapped by ism_hat is less. 2716 */ 2717 ASSERT(IS_PAGEALIGNED(vaddr_start)); 2718 ASSERT(IS_PAGEALIGNED(ism_addr_start)); 2719 ASSERT(ism_hat->hat_flags & HAT_SHARED); 2720 is_dism = is_it_dism(hat, addr); 2721 while (ism_addr < e_ism_addr) { 2722 /* 2723 * use htable_walk to get the next valid ISM mapping 2724 */ 2725 pte = htable_walk(ism_hat, &ism_ht, &ism_addr, e_ism_addr); 2726 if (ism_ht == NULL) 2727 break; 2728 2729 /* 2730 * First check to see if we already share the page table. 2731 */ 2732 l = ism_ht->ht_level; 2733 vaddr = vaddr_start + (ism_addr - ism_addr_start); 2734 ht = htable_lookup(hat, vaddr, l); 2735 if (ht != NULL) { 2736 if (ht->ht_flags & HTABLE_SHARED_PFN) 2737 goto shared; 2738 htable_release(ht); 2739 goto not_shared; 2740 } 2741 2742 /* 2743 * Can't ever share top table. 2744 */ 2745 if (l == mmu.max_level) 2746 goto not_shared; 2747 2748 /* 2749 * Avoid level mismatches later due to DISM faults. 2750 */ 2751 if (is_dism && l > 0) 2752 goto not_shared; 2753 2754 /* 2755 * addresses and lengths must align 2756 * table must be fully populated 2757 * no lower level page tables 2758 */ 2759 if (ism_addr != ism_ht->ht_vaddr || 2760 (vaddr & LEVEL_OFFSET(l + 1)) != 0) 2761 goto not_shared; 2762 2763 /* 2764 * The range of address space must cover a full table. 2765 */ 2766 if (e_ism_addr - ism_addr < LEVEL_SIZE(1 + 1)) 2767 goto not_shared; 2768 2769 /* 2770 * All entries in the ISM page table must be leaf PTEs. 2771 */ 2772 if (l > 0) { 2773 int e; 2774 2775 /* 2776 * We know the 0th is from htable_walk() above. 2777 */ 2778 for (e = 1; e < HTABLE_NUM_PTES(ism_ht); ++e) { 2779 x86pte_t pte; 2780 pte = x86pte_get(ism_ht, e); 2781 if (!PTE_ISPAGE(pte, l)) 2782 goto not_shared; 2783 } 2784 } 2785 2786 /* 2787 * share the page table 2788 */ 2789 ht = htable_create(hat, vaddr, l, ism_ht); 2790 shared: 2791 ASSERT(ht->ht_flags & HTABLE_SHARED_PFN); 2792 ASSERT(ht->ht_shares == ism_ht); 2793 hat->hat_ism_pgcnt += 2794 (ism_ht->ht_valid_cnt - ht->ht_valid_cnt) << 2795 (LEVEL_SHIFT(ht->ht_level) - MMU_PAGESHIFT); 2796 ht->ht_valid_cnt = ism_ht->ht_valid_cnt; 2797 htable_release(ht); 2798 ism_addr = ism_ht->ht_vaddr + LEVEL_SIZE(l + 1); 2799 htable_release(ism_ht); 2800 ism_ht = NULL; 2801 continue; 2802 2803 not_shared: 2804 /* 2805 * Unable to share the page table. Instead we will 2806 * create new mappings from the values in the ISM mappings. 2807 * Figure out what level size mappings to use; 2808 */ 2809 for (l = ism_ht->ht_level; l > 0; --l) { 2810 if (LEVEL_SIZE(l) <= eaddr - vaddr && 2811 (vaddr & LEVEL_OFFSET(l)) == 0) 2812 break; 2813 } 2814 2815 /* 2816 * The ISM mapping might be larger than the share area, 2817 * be careful to truncate it if needed. 2818 */ 2819 if (eaddr - vaddr >= LEVEL_SIZE(ism_ht->ht_level)) { 2820 pgcnt = mmu_btop(LEVEL_SIZE(ism_ht->ht_level)); 2821 } else { 2822 pgcnt = mmu_btop(eaddr - vaddr); 2823 l = 0; 2824 } 2825 2826 pfn = PTE2PFN(pte, ism_ht->ht_level); 2827 ASSERT(pfn != PFN_INVALID); 2828 while (pgcnt > 0) { 2829 /* 2830 * Make a new pte for the PFN for this level. 2831 * Copy protections for the pte from the ISM pte. 2832 */ 2833 pp = page_numtopp_nolock(pfn); 2834 ASSERT(pp != NULL); 2835 2836 prot = PROT_USER | PROT_READ | HAT_UNORDERED_OK; 2837 if (PTE_GET(pte, PT_WRITABLE)) 2838 prot |= PROT_WRITE; 2839 if (!PTE_GET(pte, PT_NX)) 2840 prot |= PROT_EXEC; 2841 2842 flags = HAT_LOAD; 2843 if (!is_dism) 2844 flags |= HAT_LOAD_LOCK | HAT_LOAD_NOCONSIST; 2845 while (hati_load_common(hat, vaddr, pp, prot, flags, 2846 l, pfn) != 0) { 2847 if (l == 0) 2848 panic("hati_load_common() failure"); 2849 --l; 2850 } 2851 2852 vaddr += LEVEL_SIZE(l); 2853 ism_addr += LEVEL_SIZE(l); 2854 pfn += mmu_btop(LEVEL_SIZE(l)); 2855 pgcnt -= mmu_btop(LEVEL_SIZE(l)); 2856 } 2857 } 2858 if (ism_ht != NULL) 2859 htable_release(ism_ht); 2860 return (0); 2861 } 2862 2863 2864 /* 2865 * hat_unshare() is similar to hat_unload_callback(), but 2866 * we have to look for empty shared pagetables. Note that 2867 * hat_unshare() is always invoked against an entire segment. 2868 */ 2869 /*ARGSUSED*/ 2870 void 2871 hat_unshare(hat_t *hat, caddr_t addr, size_t len, uint_t ismszc) 2872 { 2873 uint64_t vaddr = (uintptr_t)addr; 2874 uintptr_t eaddr = vaddr + len; 2875 htable_t *ht = NULL; 2876 uint_t need_demaps = 0; 2877 int flags = HAT_UNLOAD_UNMAP; 2878 level_t l; 2879 2880 ASSERT(hat != kas.a_hat); 2881 ASSERT(eaddr <= _userlimit); 2882 ASSERT(IS_PAGEALIGNED(vaddr)); 2883 ASSERT(IS_PAGEALIGNED(eaddr)); 2884 2885 /* 2886 * First go through and remove any shared pagetables. 2887 * 2888 * Note that it's ok to delay the TLB shootdown till the entire range is 2889 * finished, because if hat_pageunload() were to unload a shared 2890 * pagetable page, its hat_tlb_inval() will do a global TLB invalidate. 2891 */ 2892 l = mmu.max_page_level; 2893 if (l == mmu.max_level) 2894 --l; 2895 for (; l >= 0; --l) { 2896 for (vaddr = (uintptr_t)addr; vaddr < eaddr; 2897 vaddr = (vaddr & LEVEL_MASK(l + 1)) + LEVEL_SIZE(l + 1)) { 2898 ASSERT(!IN_VA_HOLE(vaddr)); 2899 /* 2900 * find a pagetable that maps the current address 2901 */ 2902 ht = htable_lookup(hat, vaddr, l); 2903 if (ht == NULL) 2904 continue; 2905 if (ht->ht_flags & HTABLE_SHARED_PFN) { 2906 /* 2907 * clear page count, set valid_cnt to 0, 2908 * let htable_release() finish the job 2909 */ 2910 hat->hat_ism_pgcnt -= ht->ht_valid_cnt << 2911 (LEVEL_SHIFT(ht->ht_level) - MMU_PAGESHIFT); 2912 ht->ht_valid_cnt = 0; 2913 need_demaps = 1; 2914 } 2915 htable_release(ht); 2916 } 2917 } 2918 2919 /* 2920 * flush the TLBs - since we're probably dealing with MANY mappings 2921 * we do just one CR3 reload. 2922 */ 2923 if (!(hat->hat_flags & HAT_FREEING) && need_demaps) 2924 hat_tlb_inval(hat, DEMAP_ALL_ADDR); 2925 2926 /* 2927 * Now go back and clean up any unaligned mappings that 2928 * couldn't share pagetables. 2929 */ 2930 if (!is_it_dism(hat, addr)) 2931 flags |= HAT_UNLOAD_UNLOCK; 2932 hat_unload(hat, addr, len, flags); 2933 } 2934 2935 2936 /* 2937 * hat_reserve() does nothing 2938 */ 2939 /*ARGSUSED*/ 2940 void 2941 hat_reserve(struct as *as, caddr_t addr, size_t len) 2942 { 2943 } 2944 2945 2946 /* 2947 * Called when all mappings to a page should have write permission removed. 2948 * Mostly stolem from hat_pagesync() 2949 */ 2950 static void 2951 hati_page_clrwrt(struct page *pp) 2952 { 2953 hment_t *hm = NULL; 2954 htable_t *ht; 2955 uint_t entry; 2956 x86pte_t old; 2957 x86pte_t new; 2958 uint_t pszc = 0; 2959 2960 next_size: 2961 /* 2962 * walk thru the mapping list clearing write permission 2963 */ 2964 x86_hm_enter(pp); 2965 while ((hm = hment_walk(pp, &ht, &entry, hm)) != NULL) { 2966 if (ht->ht_level < pszc) 2967 continue; 2968 old = x86pte_get(ht, entry); 2969 2970 for (;;) { 2971 /* 2972 * Is this mapping of interest? 2973 */ 2974 if (PTE2PFN(old, ht->ht_level) != pp->p_pagenum || 2975 PTE_GET(old, PT_WRITABLE) == 0) 2976 break; 2977 2978 /* 2979 * Clear ref/mod writable bits. This requires cross 2980 * calls to ensure any executing TLBs see cleared bits. 2981 */ 2982 new = old; 2983 PTE_CLR(new, PT_REF | PT_MOD | PT_WRITABLE); 2984 old = hati_update_pte(ht, entry, old, new); 2985 if (old != 0) 2986 continue; 2987 2988 break; 2989 } 2990 } 2991 x86_hm_exit(pp); 2992 while (pszc < pp->p_szc) { 2993 page_t *tpp; 2994 pszc++; 2995 tpp = PP_GROUPLEADER(pp, pszc); 2996 if (pp != tpp) { 2997 pp = tpp; 2998 goto next_size; 2999 } 3000 } 3001 } 3002 3003 /* 3004 * void hat_page_setattr(pp, flag) 3005 * void hat_page_clrattr(pp, flag) 3006 * used to set/clr ref/mod bits. 3007 */ 3008 void 3009 hat_page_setattr(struct page *pp, uint_t flag) 3010 { 3011 vnode_t *vp = pp->p_vnode; 3012 kmutex_t *vphm = NULL; 3013 page_t **listp; 3014 int noshuffle; 3015 3016 noshuffle = flag & P_NSH; 3017 flag &= ~P_NSH; 3018 3019 if (PP_GETRM(pp, flag) == flag) 3020 return; 3021 3022 if ((flag & P_MOD) != 0 && vp != NULL && IS_VMODSORT(vp) && 3023 !noshuffle) { 3024 vphm = page_vnode_mutex(vp); 3025 mutex_enter(vphm); 3026 } 3027 3028 PP_SETRM(pp, flag); 3029 3030 if (vphm != NULL) { 3031 3032 /* 3033 * Some File Systems examine v_pages for NULL w/o 3034 * grabbing the vphm mutex. Must not let it become NULL when 3035 * pp is the only page on the list. 3036 */ 3037 if (pp->p_vpnext != pp) { 3038 page_vpsub(&vp->v_pages, pp); 3039 if (vp->v_pages != NULL) 3040 listp = &vp->v_pages->p_vpprev->p_vpnext; 3041 else 3042 listp = &vp->v_pages; 3043 page_vpadd(listp, pp); 3044 } 3045 mutex_exit(vphm); 3046 } 3047 } 3048 3049 void 3050 hat_page_clrattr(struct page *pp, uint_t flag) 3051 { 3052 vnode_t *vp = pp->p_vnode; 3053 ASSERT(!(flag & ~(P_MOD | P_REF | P_RO))); 3054 3055 /* 3056 * Caller is expected to hold page's io lock for VMODSORT to work 3057 * correctly with pvn_vplist_dirty() and pvn_getdirty() when mod 3058 * bit is cleared. 3059 * We don't have assert to avoid tripping some existing third party 3060 * code. The dirty page is moved back to top of the v_page list 3061 * after IO is done in pvn_write_done(). 3062 */ 3063 PP_CLRRM(pp, flag); 3064 3065 if ((flag & P_MOD) != 0 && vp != NULL && IS_VMODSORT(vp)) { 3066 3067 /* 3068 * VMODSORT works by removing write permissions and getting 3069 * a fault when a page is made dirty. At this point 3070 * we need to remove write permission from all mappings 3071 * to this page. 3072 */ 3073 hati_page_clrwrt(pp); 3074 } 3075 } 3076 3077 /* 3078 * If flag is specified, returns 0 if attribute is disabled 3079 * and non zero if enabled. If flag specifes multiple attributs 3080 * then returns 0 if ALL atriibutes are disabled. This is an advisory 3081 * call. 3082 */ 3083 uint_t 3084 hat_page_getattr(struct page *pp, uint_t flag) 3085 { 3086 return (PP_GETRM(pp, flag)); 3087 } 3088 3089 3090 /* 3091 * common code used by hat_pageunload() and hment_steal() 3092 */ 3093 hment_t * 3094 hati_page_unmap(page_t *pp, htable_t *ht, uint_t entry) 3095 { 3096 x86pte_t old_pte; 3097 pfn_t pfn = pp->p_pagenum; 3098 hment_t *hm; 3099 3100 /* 3101 * We need to acquire a hold on the htable in order to 3102 * do the invalidate. We know the htable must exist, since 3103 * unmap's don't release the htable until after removing any 3104 * hment. Having x86_hm_enter() keeps that from proceeding. 3105 */ 3106 htable_acquire(ht); 3107 3108 /* 3109 * Invalidate the PTE and remove the hment. 3110 */ 3111 old_pte = x86pte_inval(ht, entry, 0, NULL); 3112 if (PTE2PFN(old_pte, ht->ht_level) != pfn) { 3113 panic("x86pte_inval() failure found PTE = " FMT_PTE 3114 " pfn being unmapped is %lx ht=0x%lx entry=0x%x", 3115 old_pte, pfn, (uintptr_t)ht, entry); 3116 } 3117 3118 /* 3119 * Clean up all the htable information for this mapping 3120 */ 3121 ASSERT(ht->ht_valid_cnt > 0); 3122 HTABLE_DEC(ht->ht_valid_cnt); 3123 PGCNT_DEC(ht->ht_hat, ht->ht_level); 3124 3125 /* 3126 * sync ref/mod bits to the page_t 3127 */ 3128 if (PTE_GET(old_pte, PT_SOFTWARE) < PT_NOSYNC) 3129 hati_sync_pte_to_page(pp, old_pte, ht->ht_level); 3130 3131 /* 3132 * Remove the mapping list entry for this page. 3133 */ 3134 hm = hment_remove(pp, ht, entry); 3135 3136 /* 3137 * drop the mapping list lock so that we might free the 3138 * hment and htable. 3139 */ 3140 x86_hm_exit(pp); 3141 htable_release(ht); 3142 return (hm); 3143 } 3144 3145 extern int vpm_enable; 3146 /* 3147 * Unload all translations to a page. If the page is a subpage of a large 3148 * page, the large page mappings are also removed. 3149 * 3150 * The forceflags are unused. 3151 */ 3152 3153 /*ARGSUSED*/ 3154 static int 3155 hati_pageunload(struct page *pp, uint_t pg_szcd, uint_t forceflag) 3156 { 3157 page_t *cur_pp = pp; 3158 hment_t *hm; 3159 hment_t *prev; 3160 htable_t *ht; 3161 uint_t entry; 3162 level_t level; 3163 3164 #if defined(__amd64) 3165 /* 3166 * clear the vpm ref. 3167 */ 3168 if (vpm_enable) { 3169 pp->p_vpmref = 0; 3170 } 3171 #endif 3172 /* 3173 * The loop with next_size handles pages with multiple pagesize mappings 3174 */ 3175 next_size: 3176 for (;;) { 3177 3178 /* 3179 * Get a mapping list entry 3180 */ 3181 x86_hm_enter(cur_pp); 3182 for (prev = NULL; ; prev = hm) { 3183 hm = hment_walk(cur_pp, &ht, &entry, prev); 3184 if (hm == NULL) { 3185 x86_hm_exit(cur_pp); 3186 3187 /* 3188 * If not part of a larger page, we're done. 3189 */ 3190 if (cur_pp->p_szc <= pg_szcd) { 3191 return (0); 3192 } 3193 3194 /* 3195 * Else check the next larger page size. 3196 * hat_page_demote() may decrease p_szc 3197 * but that's ok we'll just take an extra 3198 * trip discover there're no larger mappings 3199 * and return. 3200 */ 3201 ++pg_szcd; 3202 cur_pp = PP_GROUPLEADER(cur_pp, pg_szcd); 3203 goto next_size; 3204 } 3205 3206 /* 3207 * If this mapping size matches, remove it. 3208 */ 3209 level = ht->ht_level; 3210 if (level == pg_szcd) 3211 break; 3212 } 3213 3214 /* 3215 * Remove the mapping list entry for this page. 3216 * Note this does the x86_hm_exit() for us. 3217 */ 3218 hm = hati_page_unmap(cur_pp, ht, entry); 3219 if (hm != NULL) 3220 hment_free(hm); 3221 } 3222 } 3223 3224 int 3225 hat_pageunload(struct page *pp, uint_t forceflag) 3226 { 3227 ASSERT(PAGE_EXCL(pp)); 3228 return (hati_pageunload(pp, 0, forceflag)); 3229 } 3230 3231 /* 3232 * Unload all large mappings to pp and reduce by 1 p_szc field of every large 3233 * page level that included pp. 3234 * 3235 * pp must be locked EXCL. Even though no other constituent pages are locked 3236 * it's legal to unload large mappings to pp because all constituent pages of 3237 * large locked mappings have to be locked SHARED. therefore if we have EXCL 3238 * lock on one of constituent pages none of the large mappings to pp are 3239 * locked. 3240 * 3241 * Change (always decrease) p_szc field starting from the last constituent 3242 * page and ending with root constituent page so that root's pszc always shows 3243 * the area where hat_page_demote() may be active. 3244 * 3245 * This mechanism is only used for file system pages where it's not always 3246 * possible to get EXCL locks on all constituent pages to demote the size code 3247 * (as is done for anonymous or kernel large pages). 3248 */ 3249 void 3250 hat_page_demote(page_t *pp) 3251 { 3252 uint_t pszc; 3253 uint_t rszc; 3254 uint_t szc; 3255 page_t *rootpp; 3256 page_t *firstpp; 3257 page_t *lastpp; 3258 pgcnt_t pgcnt; 3259 3260 ASSERT(PAGE_EXCL(pp)); 3261 ASSERT(!PP_ISFREE(pp)); 3262 ASSERT(page_szc_lock_assert(pp)); 3263 3264 if (pp->p_szc == 0) 3265 return; 3266 3267 rootpp = PP_GROUPLEADER(pp, 1); 3268 (void) hati_pageunload(rootpp, 1, HAT_FORCE_PGUNLOAD); 3269 3270 /* 3271 * all large mappings to pp are gone 3272 * and no new can be setup since pp is locked exclusively. 3273 * 3274 * Lock the root to make sure there's only one hat_page_demote() 3275 * outstanding within the area of this root's pszc. 3276 * 3277 * Second potential hat_page_demote() is already eliminated by upper 3278 * VM layer via page_szc_lock() but we don't rely on it and use our 3279 * own locking (so that upper layer locking can be changed without 3280 * assumptions that hat depends on upper layer VM to prevent multiple 3281 * hat_page_demote() to be issued simultaneously to the same large 3282 * page). 3283 */ 3284 again: 3285 pszc = pp->p_szc; 3286 if (pszc == 0) 3287 return; 3288 rootpp = PP_GROUPLEADER(pp, pszc); 3289 x86_hm_enter(rootpp); 3290 /* 3291 * If root's p_szc is different from pszc we raced with another 3292 * hat_page_demote(). Drop the lock and try to find the root again. 3293 * If root's p_szc is greater than pszc previous hat_page_demote() is 3294 * not done yet. Take and release mlist lock of root's root to wait 3295 * for previous hat_page_demote() to complete. 3296 */ 3297 if ((rszc = rootpp->p_szc) != pszc) { 3298 x86_hm_exit(rootpp); 3299 if (rszc > pszc) { 3300 /* p_szc of a locked non free page can't increase */ 3301 ASSERT(pp != rootpp); 3302 3303 rootpp = PP_GROUPLEADER(rootpp, rszc); 3304 x86_hm_enter(rootpp); 3305 x86_hm_exit(rootpp); 3306 } 3307 goto again; 3308 } 3309 ASSERT(pp->p_szc == pszc); 3310 3311 /* 3312 * Decrement by 1 p_szc of every constituent page of a region that 3313 * covered pp. For example if original szc is 3 it gets changed to 2 3314 * everywhere except in region 2 that covered pp. Region 2 that 3315 * covered pp gets demoted to 1 everywhere except in region 1 that 3316 * covered pp. The region 1 that covered pp is demoted to region 3317 * 0. It's done this way because from region 3 we removed level 3 3318 * mappings, from region 2 that covered pp we removed level 2 mappings 3319 * and from region 1 that covered pp we removed level 1 mappings. All 3320 * changes are done from from high pfn's to low pfn's so that roots 3321 * are changed last allowing one to know the largest region where 3322 * hat_page_demote() is stil active by only looking at the root page. 3323 * 3324 * This algorithm is implemented in 2 while loops. First loop changes 3325 * p_szc of pages to the right of pp's level 1 region and second 3326 * loop changes p_szc of pages of level 1 region that covers pp 3327 * and all pages to the left of level 1 region that covers pp. 3328 * In the first loop p_szc keeps dropping with every iteration 3329 * and in the second loop it keeps increasing with every iteration. 3330 * 3331 * First loop description: Demote pages to the right of pp outside of 3332 * level 1 region that covers pp. In every iteration of the while 3333 * loop below find the last page of szc region and the first page of 3334 * (szc - 1) region that is immediately to the right of (szc - 1) 3335 * region that covers pp. From last such page to first such page 3336 * change every page's szc to szc - 1. Decrement szc and continue 3337 * looping until szc is 1. If pp belongs to the last (szc - 1) region 3338 * of szc region skip to the next iteration. 3339 */ 3340 szc = pszc; 3341 while (szc > 1) { 3342 lastpp = PP_GROUPLEADER(pp, szc); 3343 pgcnt = page_get_pagecnt(szc); 3344 lastpp += pgcnt - 1; 3345 firstpp = PP_GROUPLEADER(pp, (szc - 1)); 3346 pgcnt = page_get_pagecnt(szc - 1); 3347 if (lastpp - firstpp < pgcnt) { 3348 szc--; 3349 continue; 3350 } 3351 firstpp += pgcnt; 3352 while (lastpp != firstpp) { 3353 ASSERT(lastpp->p_szc == pszc); 3354 lastpp->p_szc = szc - 1; 3355 lastpp--; 3356 } 3357 firstpp->p_szc = szc - 1; 3358 szc--; 3359 } 3360 3361 /* 3362 * Second loop description: 3363 * First iteration changes p_szc to 0 of every 3364 * page of level 1 region that covers pp. 3365 * Subsequent iterations find last page of szc region 3366 * immediately to the left of szc region that covered pp 3367 * and first page of (szc + 1) region that covers pp. 3368 * From last to first page change p_szc of every page to szc. 3369 * Increment szc and continue looping until szc is pszc. 3370 * If pp belongs to the fist szc region of (szc + 1) region 3371 * skip to the next iteration. 3372 * 3373 */ 3374 szc = 0; 3375 while (szc < pszc) { 3376 firstpp = PP_GROUPLEADER(pp, (szc + 1)); 3377 if (szc == 0) { 3378 pgcnt = page_get_pagecnt(1); 3379 lastpp = firstpp + (pgcnt - 1); 3380 } else { 3381 lastpp = PP_GROUPLEADER(pp, szc); 3382 if (firstpp == lastpp) { 3383 szc++; 3384 continue; 3385 } 3386 lastpp--; 3387 pgcnt = page_get_pagecnt(szc); 3388 } 3389 while (lastpp != firstpp) { 3390 ASSERT(lastpp->p_szc == pszc); 3391 lastpp->p_szc = szc; 3392 lastpp--; 3393 } 3394 firstpp->p_szc = szc; 3395 if (firstpp == rootpp) 3396 break; 3397 szc++; 3398 } 3399 x86_hm_exit(rootpp); 3400 } 3401 3402 /* 3403 * get hw stats from hardware into page struct and reset hw stats 3404 * returns attributes of page 3405 * Flags for hat_pagesync, hat_getstat, hat_sync 3406 * 3407 * define HAT_SYNC_ZERORM 0x01 3408 * 3409 * Additional flags for hat_pagesync 3410 * 3411 * define HAT_SYNC_STOPON_REF 0x02 3412 * define HAT_SYNC_STOPON_MOD 0x04 3413 * define HAT_SYNC_STOPON_RM 0x06 3414 * define HAT_SYNC_STOPON_SHARED 0x08 3415 */ 3416 uint_t 3417 hat_pagesync(struct page *pp, uint_t flags) 3418 { 3419 hment_t *hm = NULL; 3420 htable_t *ht; 3421 uint_t entry; 3422 x86pte_t old, save_old; 3423 x86pte_t new; 3424 uchar_t nrmbits = P_REF|P_MOD|P_RO; 3425 extern ulong_t po_share; 3426 page_t *save_pp = pp; 3427 uint_t pszc = 0; 3428 3429 ASSERT(PAGE_LOCKED(pp) || panicstr); 3430 3431 if (PP_ISRO(pp) && (flags & HAT_SYNC_STOPON_MOD)) 3432 return (pp->p_nrm & nrmbits); 3433 3434 if ((flags & HAT_SYNC_ZERORM) == 0) { 3435 3436 if ((flags & HAT_SYNC_STOPON_REF) != 0 && PP_ISREF(pp)) 3437 return (pp->p_nrm & nrmbits); 3438 3439 if ((flags & HAT_SYNC_STOPON_MOD) != 0 && PP_ISMOD(pp)) 3440 return (pp->p_nrm & nrmbits); 3441 3442 if ((flags & HAT_SYNC_STOPON_SHARED) != 0 && 3443 hat_page_getshare(pp) > po_share) { 3444 if (PP_ISRO(pp)) 3445 PP_SETREF(pp); 3446 return (pp->p_nrm & nrmbits); 3447 } 3448 } 3449 3450 next_size: 3451 /* 3452 * walk thru the mapping list syncing (and clearing) ref/mod bits. 3453 */ 3454 x86_hm_enter(pp); 3455 while ((hm = hment_walk(pp, &ht, &entry, hm)) != NULL) { 3456 if (ht->ht_level < pszc) 3457 continue; 3458 old = x86pte_get(ht, entry); 3459 try_again: 3460 3461 ASSERT(PTE2PFN(old, ht->ht_level) == pp->p_pagenum); 3462 3463 if (PTE_GET(old, PT_REF | PT_MOD) == 0) 3464 continue; 3465 3466 save_old = old; 3467 if ((flags & HAT_SYNC_ZERORM) != 0) { 3468 3469 /* 3470 * Need to clear ref or mod bits. Need to demap 3471 * to make sure any executing TLBs see cleared bits. 3472 */ 3473 new = old; 3474 PTE_CLR(new, PT_REF | PT_MOD); 3475 old = hati_update_pte(ht, entry, old, new); 3476 if (old != 0) 3477 goto try_again; 3478 3479 old = save_old; 3480 } 3481 3482 /* 3483 * Sync the PTE 3484 */ 3485 if (!(flags & HAT_SYNC_ZERORM) && 3486 PTE_GET(old, PT_SOFTWARE) <= PT_NOSYNC) 3487 hati_sync_pte_to_page(pp, old, ht->ht_level); 3488 3489 /* 3490 * can stop short if we found a ref'd or mod'd page 3491 */ 3492 if ((flags & HAT_SYNC_STOPON_MOD) && PP_ISMOD(save_pp) || 3493 (flags & HAT_SYNC_STOPON_REF) && PP_ISREF(save_pp)) { 3494 x86_hm_exit(pp); 3495 goto done; 3496 } 3497 } 3498 x86_hm_exit(pp); 3499 while (pszc < pp->p_szc) { 3500 page_t *tpp; 3501 pszc++; 3502 tpp = PP_GROUPLEADER(pp, pszc); 3503 if (pp != tpp) { 3504 pp = tpp; 3505 goto next_size; 3506 } 3507 } 3508 done: 3509 return (save_pp->p_nrm & nrmbits); 3510 } 3511 3512 /* 3513 * returns approx number of mappings to this pp. A return of 0 implies 3514 * there are no mappings to the page. 3515 */ 3516 ulong_t 3517 hat_page_getshare(page_t *pp) 3518 { 3519 uint_t cnt; 3520 cnt = hment_mapcnt(pp); 3521 #if defined(__amd64) 3522 if (vpm_enable && pp->p_vpmref) { 3523 cnt += 1; 3524 } 3525 #endif 3526 return (cnt); 3527 } 3528 3529 /* 3530 * Return 1 the number of mappings exceeds sh_thresh. Return 0 3531 * otherwise. 3532 */ 3533 int 3534 hat_page_checkshare(page_t *pp, ulong_t sh_thresh) 3535 { 3536 return (hat_page_getshare(pp) > sh_thresh); 3537 } 3538 3539 /* 3540 * hat_softlock isn't supported anymore 3541 */ 3542 /*ARGSUSED*/ 3543 faultcode_t 3544 hat_softlock( 3545 hat_t *hat, 3546 caddr_t addr, 3547 size_t *len, 3548 struct page **page_array, 3549 uint_t flags) 3550 { 3551 return (FC_NOSUPPORT); 3552 } 3553 3554 3555 3556 /* 3557 * Routine to expose supported HAT features to platform independent code. 3558 */ 3559 /*ARGSUSED*/ 3560 int 3561 hat_supported(enum hat_features feature, void *arg) 3562 { 3563 switch (feature) { 3564 3565 case HAT_SHARED_PT: /* this is really ISM */ 3566 return (1); 3567 3568 case HAT_DYNAMIC_ISM_UNMAP: 3569 return (0); 3570 3571 case HAT_VMODSORT: 3572 return (1); 3573 3574 case HAT_SHARED_REGIONS: 3575 return (0); 3576 3577 default: 3578 panic("hat_supported() - unknown feature"); 3579 } 3580 return (0); 3581 } 3582 3583 /* 3584 * Called when a thread is exiting and has been switched to the kernel AS 3585 */ 3586 void 3587 hat_thread_exit(kthread_t *thd) 3588 { 3589 ASSERT(thd->t_procp->p_as == &kas); 3590 hat_switch(thd->t_procp->p_as->a_hat); 3591 } 3592 3593 /* 3594 * Setup the given brand new hat structure as the new HAT on this cpu's mmu. 3595 */ 3596 /*ARGSUSED*/ 3597 void 3598 hat_setup(hat_t *hat, int flags) 3599 { 3600 kpreempt_disable(); 3601 3602 hat_switch(hat); 3603 3604 kpreempt_enable(); 3605 } 3606 3607 /* 3608 * Prepare for a CPU private mapping for the given address. 3609 * 3610 * The address can only be used from a single CPU and can be remapped 3611 * using hat_mempte_remap(). Return the address of the PTE. 3612 * 3613 * We do the htable_create() if necessary and increment the valid count so 3614 * the htable can't disappear. We also hat_devload() the page table into 3615 * kernel so that the PTE is quickly accessed. 3616 */ 3617 hat_mempte_t 3618 hat_mempte_setup(caddr_t addr) 3619 { 3620 uintptr_t va = (uintptr_t)addr; 3621 htable_t *ht; 3622 uint_t entry; 3623 x86pte_t oldpte; 3624 hat_mempte_t p; 3625 3626 ASSERT(IS_PAGEALIGNED(va)); 3627 ASSERT(!IN_VA_HOLE(va)); 3628 ++curthread->t_hatdepth; 3629 ht = htable_getpte(kas.a_hat, va, &entry, &oldpte, 0); 3630 if (ht == NULL) { 3631 ht = htable_create(kas.a_hat, va, 0, NULL); 3632 entry = htable_va2entry(va, ht); 3633 ASSERT(ht->ht_level == 0); 3634 oldpte = x86pte_get(ht, entry); 3635 } 3636 if (PTE_ISVALID(oldpte)) 3637 panic("hat_mempte_setup(): address already mapped" 3638 "ht=%p, entry=%d, pte=" FMT_PTE, ht, entry, oldpte); 3639 3640 /* 3641 * increment ht_valid_cnt so that the pagetable can't disappear 3642 */ 3643 HTABLE_INC(ht->ht_valid_cnt); 3644 3645 /* 3646 * return the PTE physical address to the caller. 3647 */ 3648 htable_release(ht); 3649 p = PT_INDEX_PHYSADDR(pfn_to_pa(ht->ht_pfn), entry); 3650 --curthread->t_hatdepth; 3651 return (p); 3652 } 3653 3654 /* 3655 * Release a CPU private mapping for the given address. 3656 * We decrement the htable valid count so it might be destroyed. 3657 */ 3658 /*ARGSUSED1*/ 3659 void 3660 hat_mempte_release(caddr_t addr, hat_mempte_t pte_pa) 3661 { 3662 htable_t *ht; 3663 3664 /* 3665 * invalidate any left over mapping and decrement the htable valid count 3666 */ 3667 { 3668 x86pte_t *pteptr; 3669 3670 pteptr = x86pte_mapin(mmu_btop(pte_pa), 3671 (pte_pa & MMU_PAGEOFFSET) >> mmu.pte_size_shift, NULL); 3672 if (mmu.pae_hat) 3673 *pteptr = 0; 3674 else 3675 *(x86pte32_t *)pteptr = 0; 3676 mmu_tlbflush_entry(addr); 3677 x86pte_mapout(); 3678 } 3679 3680 ht = htable_getpte(kas.a_hat, ALIGN2PAGE(addr), NULL, NULL, 0); 3681 if (ht == NULL) 3682 panic("hat_mempte_release(): invalid address"); 3683 ASSERT(ht->ht_level == 0); 3684 HTABLE_DEC(ht->ht_valid_cnt); 3685 htable_release(ht); 3686 } 3687 3688 /* 3689 * Apply a temporary CPU private mapping to a page. We flush the TLB only 3690 * on this CPU, so this ought to have been called with preemption disabled. 3691 */ 3692 void 3693 hat_mempte_remap( 3694 pfn_t pfn, 3695 caddr_t addr, 3696 hat_mempte_t pte_pa, 3697 uint_t attr, 3698 uint_t flags) 3699 { 3700 uintptr_t va = (uintptr_t)addr; 3701 x86pte_t pte; 3702 3703 /* 3704 * Remap the given PTE to the new page's PFN. Invalidate only 3705 * on this CPU. 3706 */ 3707 #ifdef DEBUG 3708 htable_t *ht; 3709 uint_t entry; 3710 3711 ASSERT(IS_PAGEALIGNED(va)); 3712 ASSERT(!IN_VA_HOLE(va)); 3713 ht = htable_getpte(kas.a_hat, va, &entry, NULL, 0); 3714 ASSERT(ht != NULL); 3715 ASSERT(ht->ht_level == 0); 3716 ASSERT(ht->ht_valid_cnt > 0); 3717 ASSERT(ht->ht_pfn == mmu_btop(pte_pa)); 3718 htable_release(ht); 3719 #endif 3720 pte = hati_mkpte(pfn, attr, 0, flags); 3721 { 3722 x86pte_t *pteptr; 3723 3724 pteptr = x86pte_mapin(mmu_btop(pte_pa), 3725 (pte_pa & MMU_PAGEOFFSET) >> mmu.pte_size_shift, NULL); 3726 if (mmu.pae_hat) 3727 *(x86pte_t *)pteptr = pte; 3728 else 3729 *(x86pte32_t *)pteptr = (x86pte32_t)pte; 3730 mmu_tlbflush_entry(addr); 3731 x86pte_mapout(); 3732 } 3733 } 3734 3735 3736 3737 /* 3738 * Hat locking functions 3739 * XXX - these two functions are currently being used by hatstats 3740 * they can be removed by using a per-as mutex for hatstats. 3741 */ 3742 void 3743 hat_enter(hat_t *hat) 3744 { 3745 mutex_enter(&hat->hat_mutex); 3746 } 3747 3748 void 3749 hat_exit(hat_t *hat) 3750 { 3751 mutex_exit(&hat->hat_mutex); 3752 } 3753 3754 /* 3755 * HAT part of cpu initialization. 3756 */ 3757 void 3758 hat_cpu_online(struct cpu *cpup) 3759 { 3760 if (cpup != CPU) { 3761 x86pte_cpu_init(cpup); 3762 hat_vlp_setup(cpup); 3763 } 3764 CPUSET_ATOMIC_ADD(khat_cpuset, cpup->cpu_id); 3765 } 3766 3767 /* 3768 * HAT part of cpu deletion. 3769 * (currently, we only call this after the cpu is safely passivated.) 3770 */ 3771 void 3772 hat_cpu_offline(struct cpu *cpup) 3773 { 3774 ASSERT(cpup != CPU); 3775 3776 CPUSET_ATOMIC_DEL(khat_cpuset, cpup->cpu_id); 3777 x86pte_cpu_fini(cpup); 3778 hat_vlp_teardown(cpup); 3779 } 3780 3781 /* 3782 * Function called after all CPUs are brought online. 3783 * Used to remove low address boot mappings. 3784 */ 3785 void 3786 clear_boot_mappings(uintptr_t low, uintptr_t high) 3787 { 3788 uintptr_t vaddr = low; 3789 htable_t *ht = NULL; 3790 level_t level; 3791 uint_t entry; 3792 x86pte_t pte; 3793 3794 /* 3795 * On 1st CPU we can unload the prom mappings, basically we blow away 3796 * all virtual mappings under _userlimit. 3797 */ 3798 while (vaddr < high) { 3799 pte = htable_walk(kas.a_hat, &ht, &vaddr, high); 3800 if (ht == NULL) 3801 break; 3802 3803 level = ht->ht_level; 3804 entry = htable_va2entry(vaddr, ht); 3805 ASSERT(level <= mmu.max_page_level); 3806 ASSERT(PTE_ISPAGE(pte, level)); 3807 3808 /* 3809 * Unload the mapping from the page tables. 3810 */ 3811 (void) x86pte_inval(ht, entry, 0, NULL); 3812 ASSERT(ht->ht_valid_cnt > 0); 3813 HTABLE_DEC(ht->ht_valid_cnt); 3814 PGCNT_DEC(ht->ht_hat, ht->ht_level); 3815 3816 vaddr += LEVEL_SIZE(ht->ht_level); 3817 } 3818 if (ht) 3819 htable_release(ht); 3820 } 3821 3822 /* 3823 * Atomically update a new translation for a single page. If the 3824 * currently installed PTE doesn't match the value we expect to find, 3825 * it's not updated and we return the PTE we found. 3826 * 3827 * If activating nosync or NOWRITE and the page was modified we need to sync 3828 * with the page_t. Also sync with page_t if clearing ref/mod bits. 3829 */ 3830 static x86pte_t 3831 hati_update_pte(htable_t *ht, uint_t entry, x86pte_t expected, x86pte_t new) 3832 { 3833 page_t *pp; 3834 uint_t rm = 0; 3835 x86pte_t replaced; 3836 3837 if (PTE_GET(expected, PT_SOFTWARE) < PT_NOSYNC && 3838 PTE_GET(expected, PT_MOD | PT_REF) && 3839 (PTE_GET(new, PT_NOSYNC) || !PTE_GET(new, PT_WRITABLE) || 3840 !PTE_GET(new, PT_MOD | PT_REF))) { 3841 3842 ASSERT(!pfn_is_foreign(PTE2PFN(expected, ht->ht_level))); 3843 pp = page_numtopp_nolock(PTE2PFN(expected, ht->ht_level)); 3844 ASSERT(pp != NULL); 3845 if (PTE_GET(expected, PT_MOD)) 3846 rm |= P_MOD; 3847 if (PTE_GET(expected, PT_REF)) 3848 rm |= P_REF; 3849 PTE_CLR(new, PT_MOD | PT_REF); 3850 } 3851 3852 replaced = x86pte_update(ht, entry, expected, new); 3853 if (replaced != expected) 3854 return (replaced); 3855 3856 if (rm) { 3857 /* 3858 * sync to all constituent pages of a large page 3859 */ 3860 pgcnt_t pgcnt = page_get_pagecnt(ht->ht_level); 3861 ASSERT(IS_P2ALIGNED(pp->p_pagenum, pgcnt)); 3862 while (pgcnt-- > 0) { 3863 /* 3864 * hat_page_demote() can't decrease 3865 * pszc below this mapping size 3866 * since large mapping existed after we 3867 * took mlist lock. 3868 */ 3869 ASSERT(pp->p_szc >= ht->ht_level); 3870 hat_page_setattr(pp, rm); 3871 ++pp; 3872 } 3873 } 3874 3875 return (0); 3876 } 3877 3878 /* ARGSUSED */ 3879 void 3880 hat_join_srd(struct hat *sfmmup, vnode_t *evp) 3881 { 3882 } 3883 3884 /* ARGSUSED */ 3885 hat_region_cookie_t 3886 hat_join_region(struct hat *sfmmup, 3887 caddr_t r_saddr, 3888 size_t r_size, 3889 void *r_obj, 3890 u_offset_t r_objoff, 3891 uchar_t r_perm, 3892 uchar_t r_pgszc, 3893 hat_rgn_cb_func_t r_cb_function, 3894 uint_t flags) 3895 { 3896 panic("No shared region support on x86"); 3897 return (HAT_INVALID_REGION_COOKIE); 3898 } 3899 3900 /* ARGSUSED */ 3901 void 3902 hat_leave_region(struct hat *sfmmup, hat_region_cookie_t rcookie, uint_t flags) 3903 { 3904 panic("No shared region support on x86"); 3905 } 3906 3907 /* ARGSUSED */ 3908 void 3909 hat_dup_region(struct hat *sfmmup, hat_region_cookie_t rcookie) 3910 { 3911 panic("No shared region support on x86"); 3912 } 3913 3914 3915 /* 3916 * Kernel Physical Mapping (kpm) facility 3917 * 3918 * Most of the routines needed to support segkpm are almost no-ops on the 3919 * x86 platform. We map in the entire segment when it is created and leave 3920 * it mapped in, so there is no additional work required to set up and tear 3921 * down individual mappings. All of these routines were created to support 3922 * SPARC platforms that have to avoid aliasing in their virtually indexed 3923 * caches. 3924 * 3925 * Most of the routines have sanity checks in them (e.g. verifying that the 3926 * passed-in page is locked). We don't actually care about most of these 3927 * checks on x86, but we leave them in place to identify problems in the 3928 * upper levels. 3929 */ 3930 3931 /* 3932 * Map in a locked page and return the vaddr. 3933 */ 3934 /*ARGSUSED*/ 3935 caddr_t 3936 hat_kpm_mapin(struct page *pp, struct kpme *kpme) 3937 { 3938 caddr_t vaddr; 3939 3940 #ifdef DEBUG 3941 if (kpm_enable == 0) { 3942 cmn_err(CE_WARN, "hat_kpm_mapin: kpm_enable not set\n"); 3943 return ((caddr_t)NULL); 3944 } 3945 3946 if (pp == NULL || PAGE_LOCKED(pp) == 0) { 3947 cmn_err(CE_WARN, "hat_kpm_mapin: pp zero or not locked\n"); 3948 return ((caddr_t)NULL); 3949 } 3950 #endif 3951 3952 vaddr = hat_kpm_page2va(pp, 1); 3953 3954 return (vaddr); 3955 } 3956 3957 /* 3958 * Mapout a locked page. 3959 */ 3960 /*ARGSUSED*/ 3961 void 3962 hat_kpm_mapout(struct page *pp, struct kpme *kpme, caddr_t vaddr) 3963 { 3964 #ifdef DEBUG 3965 if (kpm_enable == 0) { 3966 cmn_err(CE_WARN, "hat_kpm_mapout: kpm_enable not set\n"); 3967 return; 3968 } 3969 3970 if (IS_KPM_ADDR(vaddr) == 0) { 3971 cmn_err(CE_WARN, "hat_kpm_mapout: no kpm address\n"); 3972 return; 3973 } 3974 3975 if (pp == NULL || PAGE_LOCKED(pp) == 0) { 3976 cmn_err(CE_WARN, "hat_kpm_mapout: page zero or not locked\n"); 3977 return; 3978 } 3979 #endif 3980 } 3981 3982 /* 3983 * Return the kpm virtual address for a specific pfn 3984 */ 3985 caddr_t 3986 hat_kpm_pfn2va(pfn_t pfn) 3987 { 3988 uintptr_t vaddr = (uintptr_t)kpm_vbase + mmu_ptob(pfn); 3989 3990 return ((caddr_t)vaddr); 3991 } 3992 3993 /* 3994 * Return the kpm virtual address for the page at pp. 3995 */ 3996 /*ARGSUSED*/ 3997 caddr_t 3998 hat_kpm_page2va(struct page *pp, int checkswap) 3999 { 4000 return (hat_kpm_pfn2va(pp->p_pagenum)); 4001 } 4002 4003 /* 4004 * Return the page frame number for the kpm virtual address vaddr. 4005 */ 4006 pfn_t 4007 hat_kpm_va2pfn(caddr_t vaddr) 4008 { 4009 pfn_t pfn; 4010 4011 ASSERT(IS_KPM_ADDR(vaddr)); 4012 4013 pfn = (pfn_t)btop(vaddr - kpm_vbase); 4014 4015 return (pfn); 4016 } 4017 4018 4019 /* 4020 * Return the page for the kpm virtual address vaddr. 4021 */ 4022 page_t * 4023 hat_kpm_vaddr2page(caddr_t vaddr) 4024 { 4025 pfn_t pfn; 4026 4027 ASSERT(IS_KPM_ADDR(vaddr)); 4028 4029 pfn = hat_kpm_va2pfn(vaddr); 4030 4031 return (page_numtopp_nolock(pfn)); 4032 } 4033 4034 /* 4035 * hat_kpm_fault is called from segkpm_fault when we take a page fault on a 4036 * KPM page. This should never happen on x86 4037 */ 4038 int 4039 hat_kpm_fault(hat_t *hat, caddr_t vaddr) 4040 { 4041 panic("pagefault in seg_kpm. hat: 0x%p vaddr: 0x%p", hat, vaddr); 4042 4043 return (0); 4044 } 4045 4046 /*ARGSUSED*/ 4047 void 4048 hat_kpm_mseghash_clear(int nentries) 4049 {} 4050 4051 /*ARGSUSED*/ 4052 void 4053 hat_kpm_mseghash_update(pgcnt_t inx, struct memseg *msp) 4054 {} 4055