xref: /titanic_52/usr/src/uts/i86pc/sys/rm_platter.h (revision 45916cd2fec6e79bca5dee0421bd39e3c2910d1e)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_RM_PLATTER_H
27 #define	_SYS_RM_PLATTER_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #include <sys/types.h>
32 #include <sys/tss.h>
33 #include <sys/segments.h>
34 
35 #ifdef	__cplusplus
36 extern "C" {
37 #endif
38 
39 typedef	struct rm_platter {
40 	char		rm_code[1024];
41 #if defined(__amd64)
42 	/*
43 	 * The compiler will want to 64-bit align the 64-bit rm_gdt_base
44 	 * pointer, so we need to add an extra four bytes of padding here to
45 	 * make sure rm_gdt_lim and rm_gdt_base will align to create a proper
46 	 * ten byte GDT pseudo-descriptor.
47 	 */
48 	uint32_t	rm_gdt_pad;
49 #endif	/* __amd64 */
50 	ushort_t	rm_debug;
51 	ushort_t	rm_gdt_lim;	/* stuff for lgdt */
52 	user_desc_t	*rm_gdt_base;
53 #if defined(__amd64)
54 	/*
55 	 * The compiler will want to 64-bit align the 64-bit rm_idt_base
56 	 * pointer, so we need to add an extra four bytes of padding here to
57 	 * make sure rm_idt_lim and rm_idt_base will align to create a proper
58 	 * ten byte IDT pseudo-descriptor.
59 	 */
60 	uint32_t	rm_idt_pad;
61 #endif	/* __amd64 */
62 	ushort_t	rm_filler2;	/* till I am sure that pragma works */
63 	ushort_t	rm_idt_lim;	/* stuff for lidt */
64 	gate_desc_t	*rm_idt_base;
65 	uint_t		rm_pdbr;	/* cr3 value */
66 	uint_t		rm_cpu;		/* easy way to know which CPU we are */
67 	uint_t		rm_x86feature;	/* X86 supported features */
68 	uint_t		rm_cr4;		/* cr4 value on cpu0 */
69 #if defined(__amd64)
70 	/*
71 	 * Temporary GDT for the brief transition from real mode to protected
72 	 * mode before a CPU continues on into long mode.
73 	 *
74 	 * Putting it here assures it will be located in identity mapped memory
75 	 * (va == pa, 1:1).
76 	 *
77 	 * rm_temp_gdt is sized to hold only a null descriptor in slot zero
78 	 * and a 64-bit code descriptor in slot one.
79 	 *
80 	 * rm_temp_[gi]dt_lim and rm_temp_[gi]dt_base are the pseudo-descriptors
81 	 * for the temporary GDT and IDT, respectively.
82 	 */
83 	uint64_t	rm_temp_gdt[2];
84 	ushort_t	rm_temp_gdtdesc_pad;	/* filler to align GDT desc */
85 	ushort_t	rm_temp_gdt_lim;
86 	uint32_t	rm_temp_gdt_base;
87 	ushort_t	rm_temp_idtdesc_pad;	/* filler to align IDT desc */
88 	ushort_t	rm_temp_idt_lim;
89 	uint32_t	rm_temp_idt_base;
90 
91 	/*
92 	 * The code executing in the rm_platter needs the offset into the
93 	 * platter at which the 64-bit code starts, so have mp_startup
94 	 * calculate it and store it here.
95 	 */
96 	uint32_t	rm_longmode64_addr;
97 #endif	/* __amd64 */
98 } rm_platter_t;
99 
100 /*
101  * cpu tables put within a single structure all the tables which need to be
102  * allocated when a CPU starts up. Makes it more memory efficient and easier
103  * to allocate/release
104  *
105  * IMPORTANT: i86pc/ml/offsets.in depends upon ct_stack being DEFAULTSTKSZ
106  * bytes long, and followed immediately by ct_gdt. Yes, it's a hack. If
107  * changing cpu_tables, you must updates offsets.in so that it can
108  * continue to calculate the size of DEFAULTSTKSZ.
109  *
110  * Note: gdt and tss should be 16 byte aligned for best performance on
111  * amd64.  Since DEFAULTSTKSIZE is a multiple of pagesize gdt will be aligned.
112  * We test below that the tss is properly aligned.
113  */
114 
115 struct cpu_tables {
116 	char		ct_stack[DEFAULTSTKSZ];
117 	user_desc_t	*ct_gdt;
118 	struct tss	ct_tss;
119 };
120 
121 /*
122  * gdt entries are 8 bytes long, ensure that we have an even no. of them.
123  */
124 #if ((NGDT / 2) * 2 != NGDT)
125 #error "rm_platter.h: tss not properly aligned"
126 #endif
127 
128 #ifdef	__cplusplus
129 }
130 #endif
131 
132 #endif	/* _SYS_RM_PLATTER_H */
133