1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_CPUDRV_MACH_H 27 #define _SYS_CPUDRV_MACH_H 28 29 #include <sys/cpuvar.h> 30 #include <sys/cpupm.h> 31 #include <sys/cpu_acpi.h> 32 #include <sys/cpudrv.h> 33 #include <sys/ksynch.h> 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 /* 40 * We currently refuse to power manage if the CPU in not ready to 41 * take cross calls (cross calls fail silently if CPU is not ready 42 * for it). 43 */ 44 extern cpuset_t cpu_ready_set; 45 #define CPUDRV_PM_XCALL_IS_READY(cpuid) CPU_IN_SET(cpu_ready_set, (cpuid)) 46 47 /* 48 * An error attaching any of the devices results in disabling 49 * CPU power management. 50 */ 51 #define CPUDRV_PM_DISABLE() cpupm_disable(CPUPM_ALL_STATES) 52 53 /* 54 * If no power management states are enabled, then CPU power 55 * management is disabled. 56 */ 57 #define CPUDRV_PM_DISABLED() \ 58 (!cpupm_is_enabled(CPUPM_P_STATES) && !cpupm_is_enabled(CPUPM_T_STATES)) 59 60 /* 61 * Is P-state management enabled? 62 */ 63 #define CPUDRV_PM_POWER_ENABLED(cpudsp) \ 64 (((cpudrv_mach_state_t *)cpudsp->mach_state)->caps & CPUDRV_P_STATES) 65 66 /* 67 * We're about to exit the _PPC thread so reset tag. 68 */ 69 #define CPUDRV_PM_RESET_GOVERNOR_THREAD(cpupm) { \ 70 if (curthread == cpupm->pm_governor_thread) \ 71 cpupm->pm_governor_thread = NULL; \ 72 } 73 74 /* 75 * Install a _PPC/_TPC change notification handler. 76 */ 77 #define CPUDRV_PM_INSTALL_MAX_CHANGE_HANDLER(cpudsp, dip) \ 78 cpudrv_pm_install_notify_handler(cpudsp, dip); 79 80 /* 81 * Redefine the topspeed. 82 */ 83 #define CPUDRV_PM_REDEFINE_TOPSPEED(dip) cpudrv_pm_redefine_topspeed(dip) 84 85 /* 86 * Set callbacks so that PPM can callback into CPUDRV 87 */ 88 #define CPUDRV_PM_SET_PPM_CALLBACKS() { \ 89 cpupm_get_topspeed = cpudrv_pm_get_topspeed; \ 90 cpupm_set_topspeed = cpudrv_pm_set_topspeed; \ 91 } 92 93 /* 94 * ACPI provides the supported speeds. 95 */ 96 #define CPUDRV_PM_GET_SPEEDS(cpudsp, speeds, nspeeds) \ 97 nspeeds = cpudrv_pm_get_speeds(cpudsp, &speeds); 98 #define CPUDRV_PM_FREE_SPEEDS(speeds, nspeeds) \ 99 cpudrv_pm_free_speeds(speeds, nspeeds); 100 101 /* 102 * Convert speed to Hz. 103 */ 104 #define CPUDRV_PM_SPEED_HZ(unused, mhz) ((uint64_t)mhz * 1000000) 105 106 /* 107 * Compute the idle cnt percentage for a given speed. 108 */ 109 #define CPUDRV_PM_IDLE_CNT_PERCENT(hwm, speeds, i) \ 110 (100 - (((100 - hwm) * speeds[0]) / speeds[i])) 111 112 /* 113 * Compute the user cnt percentage for a given speed. 114 */ 115 #define CPUDRV_PM_USER_CNT_PERCENT(hwm, speeds, i) \ 116 ((hwm * speeds[i]) / speeds[i - 1]); 117 118 /* 119 * pm-components property defintions for this machine type. 120 * 121 * Fully constructed pm-components property should be an array of 122 * strings that look something like: 123 * 124 * pmc[0] = "NAME=CPU Speed" 125 * pmc[1] = "1=2800MHz" 126 * pmc[2] = "2=3200MHz" 127 * 128 * The amount of memory needed for each string is: 129 * digits for power level + '=' + digits for freq + 'MHz' + '\0' 130 */ 131 #define CPUDRV_PM_COMP_SIZE() \ 132 (CPUDRV_PM_COMP_MAX_DIG + 1 + CPUDRV_PM_COMP_MAX_DIG + 3 + 1); 133 #define CPUDRV_PM_COMP_SPEED(cpupm, cur_spd) cur_spd->speed; 134 #define CPUDRV_PM_COMP_SPRINT(pmc, cpupm, cur_spd, comp_spd) \ 135 (void) sprintf(pmc, "%d=%dMHz", cur_spd->pm_level, comp_spd); 136 137 /* 138 * T-State domain list 139 */ 140 typedef struct cpudrv_tstate_domain_node { 141 struct cpudrv_tstate_domain_node *tdn_next; 142 struct cpudrv_tstate_domain *tdn_domain; 143 cpudrv_devstate_t *tdn_cpudsp; 144 } cpudrv_tstate_domain_node_t; 145 146 typedef struct cpudrv_tstate_domain { 147 struct cpudrv_tstate_domain *td_next; 148 cpudrv_tstate_domain_node_t *td_node; 149 uint32_t td_domain; 150 uint32_t td_type; 151 kmutex_t td_lock; 152 } cpudrv_tstate_domain_t; 153 154 extern cpudrv_tstate_domain_t *cpudrv_tstate_domains; 155 156 /* 157 * Different processor families have their own technologies for supporting 158 * CPU power management (i.e., Intel has Enhanced SpeedStep for some of it's 159 * processors and AMD has PowerNow! for some of it's processors). We support 160 * these different technologies via modules that export the interfaces 161 * described below. 162 * 163 * If a module implements the technology that should be used to manage 164 * the current CPU device, then the cpups_init() module should return 165 * succesfully (i.e., return code of 0) and perform any initialization 166 * such that future power transistions can be performed by calling 167 * the cpups_power() interface(). And the cpups_fini() interface can be 168 * used to free any resources allocated by cpups_init(). 169 */ 170 typedef struct cpudrv_pstate_ops { 171 char *cpups_label; 172 int (*cpups_init)(cpudrv_devstate_t *); 173 void (*cpups_fini)(cpudrv_devstate_t *); 174 int (*cpups_power)(cpudrv_devstate_t *, uint32_t); 175 } cpudrv_pstate_ops_t; 176 177 /* 178 * T-state support. 179 */ 180 typedef struct cpudrv_tstate_ops { 181 char *cputs_label; 182 int (*cputs_init)(cpudrv_devstate_t *); 183 void (*cputs_fini)(cpudrv_devstate_t *); 184 int (*cputs_throttle)(cpudrv_devstate_t *, uint32_t); 185 } cpudrv_tstate_ops_t; 186 187 typedef struct cpudrv_mach_state { 188 void *acpi_handle; 189 cpudrv_pstate_ops_t *cpupm_pstate_ops; 190 cpudrv_tstate_ops_t *cpupm_tstate_ops; 191 cpudrv_tstate_domain_node_t *tstate_domain_node; 192 uint32_t pstate; 193 uint32_t tstate; 194 uint32_t caps; 195 } cpudrv_mach_state_t; 196 197 #define CPUDRV_NO_STATES 0x00 198 #define CPUDRV_P_STATES 0x01 199 #define CPUDRV_T_STATES 0x02 200 201 extern uint_t cpudrv_pm_get_speeds(cpudrv_devstate_t *, int **); 202 extern void cpudrv_pm_free_speeds(int *, uint_t); 203 extern void cpudrv_pm_set_topspeed(void *, int); 204 extern int cpudrv_pm_get_topspeed(void *); 205 extern void cpudrv_pm_redefine_topspeed(void *); 206 extern void cpudrv_pm_install_notify_handler(cpudrv_devstate_t *, dev_info_t *); 207 #ifdef __cplusplus 208 } 209 #endif 210 211 #endif /* _SYS_CPUDRV_MACH_H */ 212