1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include <sys/types.h> 28 #include <sys/thread.h> 29 #include <sys/cpuvar.h> 30 #include <sys/t_lock.h> 31 #include <sys/param.h> 32 #include <sys/proc.h> 33 #include <sys/disp.h> 34 #include <sys/class.h> 35 #include <sys/cmn_err.h> 36 #include <sys/debug.h> 37 #include <sys/asm_linkage.h> 38 #include <sys/x_call.h> 39 #include <sys/systm.h> 40 #include <sys/var.h> 41 #include <sys/vtrace.h> 42 #include <vm/hat.h> 43 #include <vm/as.h> 44 #include <vm/seg_kmem.h> 45 #include <vm/seg_kp.h> 46 #include <sys/segments.h> 47 #include <sys/kmem.h> 48 #include <sys/stack.h> 49 #include <sys/smp_impldefs.h> 50 #include <sys/x86_archext.h> 51 #include <sys/machsystm.h> 52 #include <sys/traptrace.h> 53 #include <sys/clock.h> 54 #include <sys/cpc_impl.h> 55 #include <sys/pg.h> 56 #include <sys/cmt.h> 57 #include <sys/dtrace.h> 58 #include <sys/archsystm.h> 59 #include <sys/fp.h> 60 #include <sys/reboot.h> 61 #include <sys/kdi_machimpl.h> 62 #include <vm/hat_i86.h> 63 #include <sys/memnode.h> 64 #include <sys/pci_cfgspace.h> 65 #include <sys/mach_mmu.h> 66 #include <sys/sysmacros.h> 67 #if defined(__xpv) 68 #include <sys/hypervisor.h> 69 #endif 70 #include <sys/cpu_module.h> 71 72 struct cpu cpus[1]; /* CPU data */ 73 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 74 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 75 76 /* 77 * Useful for disabling MP bring-up on a MP capable system. 78 */ 79 int use_mp = 1; 80 81 /* 82 * to be set by a PSM to indicate what cpus 83 * are sitting around on the system. 84 */ 85 cpuset_t mp_cpus; 86 87 /* 88 * This variable is used by the hat layer to decide whether or not 89 * critical sections are needed to prevent race conditions. For sun4m, 90 * this variable is set once enough MP initialization has been done in 91 * order to allow cross calls. 92 */ 93 int flushes_require_xcalls; 94 95 cpuset_t cpu_ready_set; /* initialized in startup() */ 96 97 static void mp_startup(void); 98 99 static void cpu_sep_enable(void); 100 static void cpu_sep_disable(void); 101 static void cpu_asysc_enable(void); 102 static void cpu_asysc_disable(void); 103 104 /* 105 * Init CPU info - get CPU type info for processor_info system call. 106 */ 107 void 108 init_cpu_info(struct cpu *cp) 109 { 110 processor_info_t *pi = &cp->cpu_type_info; 111 char buf[CPU_IDSTRLEN]; 112 113 /* 114 * Get clock-frequency property for the CPU. 115 */ 116 pi->pi_clock = cpu_freq; 117 118 /* 119 * Current frequency in Hz. 120 */ 121 cp->cpu_curr_clock = cpu_freq_hz; 122 123 /* 124 * Supported frequencies. 125 */ 126 if (cp->cpu_supp_freqs == NULL) { 127 cpu_set_supp_freqs(cp, NULL); 128 } 129 130 (void) strcpy(pi->pi_processor_type, "i386"); 131 if (fpu_exists) 132 (void) strcpy(pi->pi_fputypes, "i387 compatible"); 133 134 (void) cpuid_getidstr(cp, buf, sizeof (buf)); 135 136 cp->cpu_idstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 137 (void) strcpy(cp->cpu_idstr, buf); 138 139 (void) cpuid_getbrandstr(cp, buf, sizeof (buf)); 140 cp->cpu_brandstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 141 (void) strcpy(cp->cpu_brandstr, buf); 142 } 143 144 /* 145 * Configure syscall support on this CPU. 146 */ 147 /*ARGSUSED*/ 148 void 149 init_cpu_syscall(struct cpu *cp) 150 { 151 kpreempt_disable(); 152 153 #if defined(__amd64) 154 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) { 155 156 #if !defined(__lint) 157 /* 158 * The syscall instruction imposes a certain ordering on 159 * segment selectors, so we double-check that ordering 160 * here. 161 */ 162 ASSERT(KDS_SEL == KCS_SEL + 8); 163 ASSERT(UDS_SEL == U32CS_SEL + 8); 164 ASSERT(UCS_SEL == U32CS_SEL + 16); 165 #endif 166 /* 167 * Turn syscall/sysret extensions on. 168 */ 169 cpu_asysc_enable(); 170 171 /* 172 * Program the magic registers .. 173 */ 174 wrmsr(MSR_AMD_STAR, 175 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 176 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 177 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 178 179 /* 180 * This list of flags is masked off the incoming 181 * %rfl when we enter the kernel. 182 */ 183 wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); 184 } 185 #endif 186 187 /* 188 * On 32-bit kernels, we use sysenter/sysexit because it's too 189 * hard to use syscall/sysret, and it is more portable anyway. 190 * 191 * On 64-bit kernels on Nocona machines, the 32-bit syscall 192 * variant isn't available to 32-bit applications, but sysenter is. 193 */ 194 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) { 195 196 #if !defined(__lint) 197 /* 198 * The sysenter instruction imposes a certain ordering on 199 * segment selectors, so we double-check that ordering 200 * here. See "sysenter" in Intel document 245471-012, "IA-32 201 * Intel Architecture Software Developer's Manual Volume 2: 202 * Instruction Set Reference" 203 */ 204 ASSERT(KDS_SEL == KCS_SEL + 8); 205 206 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 207 ASSERT32(UDS_SEL == UCS_SEL + 8); 208 209 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 210 ASSERT64(UDS_SEL == U32CS_SEL + 8); 211 #endif 212 213 cpu_sep_enable(); 214 215 /* 216 * resume() sets this value to the base of the threads stack 217 * via a context handler. 218 */ 219 wrmsr(MSR_INTC_SEP_ESP, 0); 220 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 221 } 222 223 kpreempt_enable(); 224 } 225 226 /* 227 * Multiprocessor initialization. 228 * 229 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 230 * startup and idle threads for the specified CPU. 231 */ 232 struct cpu * 233 mp_startup_init(int cpun) 234 { 235 struct cpu *cp; 236 kthread_id_t tp; 237 caddr_t sp; 238 proc_t *procp; 239 #if !defined(__xpv) 240 extern int idle_cpu_prefer_mwait; 241 extern void cpu_idle_mwait(); 242 #endif 243 extern void idle(); 244 extern void cpu_idle(); 245 246 #ifdef TRAPTRACE 247 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 248 #endif 249 250 ASSERT(cpun < NCPU && cpu[cpun] == NULL); 251 252 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 253 #if !defined(__xpv) 254 if ((x86_feature & X86_MWAIT) && idle_cpu_prefer_mwait) { 255 cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(CPU); 256 cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait; 257 } else 258 #endif 259 cp->cpu_m.mcpu_idle_cpu = cpu_idle; 260 261 procp = curthread->t_procp; 262 263 mutex_enter(&cpu_lock); 264 /* 265 * Initialize the dispatcher first. 266 */ 267 disp_cpu_init(cp); 268 mutex_exit(&cpu_lock); 269 270 cpu_vm_data_init(cp); 271 272 /* 273 * Allocate and initialize the startup thread for this CPU. 274 * Interrupt and process switch stacks get allocated later 275 * when the CPU starts running. 276 */ 277 tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 278 TS_STOPPED, maxclsyspri); 279 280 /* 281 * Set state to TS_ONPROC since this thread will start running 282 * as soon as the CPU comes online. 283 * 284 * All the other fields of the thread structure are setup by 285 * thread_create(). 286 */ 287 THREAD_ONPROC(tp, cp); 288 tp->t_preempt = 1; 289 tp->t_bound_cpu = cp; 290 tp->t_affinitycnt = 1; 291 tp->t_cpu = cp; 292 tp->t_disp_queue = cp->cpu_disp; 293 294 /* 295 * Setup thread to start in mp_startup. 296 */ 297 sp = tp->t_stk; 298 tp->t_pc = (uintptr_t)mp_startup; 299 tp->t_sp = (uintptr_t)(sp - MINFRAME); 300 #if defined(__amd64) 301 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 302 #endif 303 304 cp->cpu_id = cpun; 305 cp->cpu_self = cp; 306 cp->cpu_thread = tp; 307 cp->cpu_lwp = NULL; 308 cp->cpu_dispthread = tp; 309 cp->cpu_dispatch_pri = DISP_PRIO(tp); 310 311 /* 312 * cpu_base_spl must be set explicitly here to prevent any blocking 313 * operations in mp_startup from causing the spl of the cpu to drop 314 * to 0 (allowing device interrupts before we're ready) in resume(). 315 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 316 * As an extra bit of security on DEBUG kernels, this is enforced with 317 * an assertion in mp_startup() -- before cpu_base_spl is set to its 318 * proper value. 319 */ 320 cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 321 322 /* 323 * Now, initialize per-CPU idle thread for this CPU. 324 */ 325 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 326 327 cp->cpu_idle_thread = tp; 328 329 tp->t_preempt = 1; 330 tp->t_bound_cpu = cp; 331 tp->t_affinitycnt = 1; 332 tp->t_cpu = cp; 333 tp->t_disp_queue = cp->cpu_disp; 334 335 /* 336 * Bootstrap the CPU's PG data 337 */ 338 pg_cpu_bootstrap(cp); 339 340 /* 341 * Perform CPC initialization on the new CPU. 342 */ 343 kcpc_hw_init(cp); 344 345 /* 346 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 347 * for each CPU. 348 */ 349 setup_vaddr_for_ppcopy(cp); 350 351 /* 352 * Allocate page for new GDT and initialize from current GDT. 353 */ 354 #if !defined(__lint) 355 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 356 #endif 357 cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 358 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT)); 359 360 #if defined(__i386) 361 /* 362 * setup kernel %gs. 363 */ 364 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 365 SEL_KPL, 0, 1); 366 #endif 367 368 /* 369 * If we have more than one node, each cpu gets a copy of IDT 370 * local to its node. If this is a Pentium box, we use cpu 0's 371 * IDT. cpu 0's IDT has been made read-only to workaround the 372 * cmpxchgl register bug 373 */ 374 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 375 #if !defined(__lint) 376 ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE); 377 #endif 378 cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP); 379 bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE); 380 } else { 381 cp->cpu_idt = CPU->cpu_idt; 382 } 383 384 /* 385 * Get interrupt priority data from cpu 0. 386 */ 387 cp->cpu_pri_data = CPU->cpu_pri_data; 388 389 /* 390 * alloc space for cpuid info 391 */ 392 cpuid_alloc_space(cp); 393 394 /* 395 * alloc space for ucode_info 396 */ 397 ucode_alloc_space(cp); 398 xc_init_cpu(cp); 399 hat_cpu_online(cp); 400 401 #ifdef TRAPTRACE 402 /* 403 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 404 */ 405 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 406 ttc->ttc_next = ttc->ttc_first; 407 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 408 #endif 409 /* 410 * Record that we have another CPU. 411 */ 412 mutex_enter(&cpu_lock); 413 /* 414 * Initialize the interrupt threads for this CPU 415 */ 416 cpu_intr_alloc(cp, NINTR_THREADS); 417 /* 418 * Add CPU to list of available CPUs. It'll be on the active list 419 * after mp_startup(). 420 */ 421 cpu_add_unit(cp); 422 mutex_exit(&cpu_lock); 423 424 return (cp); 425 } 426 427 /* 428 * Undo what was done in mp_startup_init 429 */ 430 static void 431 mp_startup_fini(struct cpu *cp, int error) 432 { 433 mutex_enter(&cpu_lock); 434 435 /* 436 * Remove the CPU from the list of available CPUs. 437 */ 438 cpu_del_unit(cp->cpu_id); 439 440 if (error == ETIMEDOUT) { 441 /* 442 * The cpu was started, but never *seemed* to run any 443 * code in the kernel; it's probably off spinning in its 444 * own private world, though with potential references to 445 * our kmem-allocated IDTs and GDTs (for example). 446 * 447 * Worse still, it may actually wake up some time later, 448 * so rather than guess what it might or might not do, we 449 * leave the fundamental data structures intact. 450 */ 451 cp->cpu_flags = 0; 452 mutex_exit(&cpu_lock); 453 return; 454 } 455 456 /* 457 * At this point, the only threads bound to this CPU should 458 * special per-cpu threads: it's idle thread, it's pause threads, 459 * and it's interrupt threads. Clean these up. 460 */ 461 cpu_destroy_bound_threads(cp); 462 cp->cpu_idle_thread = NULL; 463 464 /* 465 * Free the interrupt stack. 466 */ 467 segkp_release(segkp, 468 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 469 470 mutex_exit(&cpu_lock); 471 472 #ifdef TRAPTRACE 473 /* 474 * Discard the trap trace buffer 475 */ 476 { 477 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 478 479 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 480 ttc->ttc_first = NULL; 481 } 482 #endif 483 484 hat_cpu_offline(cp); 485 486 cpuid_free_space(cp); 487 488 ucode_free_space(cp); 489 490 if (cp->cpu_idt != CPU->cpu_idt) 491 kmem_free(cp->cpu_idt, PAGESIZE); 492 cp->cpu_idt = NULL; 493 494 kmem_free(cp->cpu_gdt, PAGESIZE); 495 cp->cpu_gdt = NULL; 496 497 teardown_vaddr_for_ppcopy(cp); 498 499 kcpc_hw_fini(cp); 500 501 cp->cpu_dispthread = NULL; 502 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 503 504 cpu_vm_data_destroy(cp); 505 506 mutex_enter(&cpu_lock); 507 disp_cpu_fini(cp); 508 mutex_exit(&cpu_lock); 509 510 #if !defined(__xpv) 511 if (cp->cpu_m.mcpu_mwait != NULL) 512 cpuid_mwait_free(cp); 513 #endif 514 kmem_free(cp, sizeof (*cp)); 515 } 516 517 /* 518 * Apply workarounds for known errata, and warn about those that are absent. 519 * 520 * System vendors occasionally create configurations which contain different 521 * revisions of the CPUs that are almost but not exactly the same. At the 522 * time of writing, this meant that their clock rates were the same, their 523 * feature sets were the same, but the required workaround were -not- 524 * necessarily the same. So, this routine is invoked on -every- CPU soon 525 * after starting to make sure that the resulting system contains the most 526 * pessimal set of workarounds needed to cope with *any* of the CPUs in the 527 * system. 528 * 529 * workaround_errata is invoked early in mlsetup() for CPU 0, and in 530 * mp_startup() for all slave CPUs. Slaves process workaround_errata prior 531 * to acknowledging their readiness to the master, so this routine will 532 * never be executed by multiple CPUs in parallel, thus making updates to 533 * global data safe. 534 * 535 * These workarounds are based on Rev 3.57 of the Revision Guide for 536 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 537 */ 538 539 #if defined(OPTERON_ERRATUM_88) 540 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 541 #endif 542 543 #if defined(OPTERON_ERRATUM_91) 544 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 545 #endif 546 547 #if defined(OPTERON_ERRATUM_93) 548 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 549 #endif 550 551 #if defined(OPTERON_ERRATUM_95) 552 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 553 #endif 554 555 #if defined(OPTERON_ERRATUM_100) 556 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 557 #endif 558 559 #if defined(OPTERON_ERRATUM_108) 560 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 561 #endif 562 563 #if defined(OPTERON_ERRATUM_109) 564 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 565 #endif 566 567 #if defined(OPTERON_ERRATUM_121) 568 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 569 #endif 570 571 #if defined(OPTERON_ERRATUM_122) 572 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 573 #endif 574 575 #if defined(OPTERON_ERRATUM_123) 576 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 577 #endif 578 579 #if defined(OPTERON_ERRATUM_131) 580 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 581 #endif 582 583 #if defined(OPTERON_WORKAROUND_6336786) 584 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 585 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 586 #endif 587 588 #if defined(OPTERON_WORKAROUND_6323525) 589 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 590 #endif 591 592 #if defined(OPTERON_ERRATUM_298) 593 int opteron_erratum_298; 594 #endif 595 596 static void 597 workaround_warning(cpu_t *cp, uint_t erratum) 598 { 599 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 600 cp->cpu_id, erratum); 601 } 602 603 static void 604 workaround_applied(uint_t erratum) 605 { 606 if (erratum > 1000000) 607 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 608 erratum); 609 else 610 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 611 erratum); 612 } 613 614 static void 615 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 616 { 617 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 618 cp->cpu_id, rw, msr, error); 619 } 620 621 /* 622 * Determine the number of nodes in a Hammer / Greyhound / Griffin family 623 * system. 624 */ 625 static uint_t 626 opteron_get_nnodes(void) 627 { 628 static uint_t nnodes = 0; 629 630 if (nnodes == 0) { 631 #ifdef DEBUG 632 uint_t family; 633 634 /* 635 * This routine uses a PCI config space based mechanism 636 * for retrieving the number of nodes in the system. 637 * Device 24, function 0, offset 0x60 as used here is not 638 * AMD processor architectural, and may not work on processor 639 * families other than those listed below. 640 * 641 * Callers of this routine must ensure that we're running on 642 * a processor which supports this mechanism. 643 * The assertion below is meant to catch calls on unsupported 644 * processors. 645 */ 646 family = cpuid_getfamily(CPU); 647 ASSERT(family == 0xf || family == 0x10 || family == 0x11); 648 #endif /* DEBUG */ 649 650 /* 651 * Obtain the number of nodes in the system from 652 * bits [6:4] of the Node ID register on node 0. 653 * 654 * The actual node count is NodeID[6:4] + 1 655 * 656 * The Node ID register is accessed via function 0, 657 * offset 0x60. Node 0 is device 24. 658 */ 659 nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1; 660 } 661 return (nnodes); 662 } 663 664 uint_t 665 do_erratum_298(struct cpu *cpu) 666 { 667 static int osvwrc = -3; 668 extern int osvw_opteron_erratum(cpu_t *, uint_t); 669 670 /* 671 * L2 Eviction May Occur During Processor Operation To Set 672 * Accessed or Dirty Bit. 673 */ 674 if (osvwrc == -3) { 675 osvwrc = osvw_opteron_erratum(cpu, 298); 676 } else { 677 /* osvw return codes should be consistent for all cpus */ 678 ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298)); 679 } 680 681 switch (osvwrc) { 682 case 0: /* erratum is not present: do nothing */ 683 break; 684 case 1: /* erratum is present: BIOS workaround applied */ 685 /* 686 * check if workaround is actually in place and issue warning 687 * if not. 688 */ 689 if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 690 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) { 691 #if defined(OPTERON_ERRATUM_298) 692 opteron_erratum_298++; 693 #else 694 workaround_warning(cpu, 298); 695 return (1); 696 #endif 697 } 698 break; 699 case -1: /* cannot determine via osvw: check cpuid */ 700 if ((cpuid_opteron_erratum(cpu, 298) > 0) && 701 (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 702 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) { 703 #if defined(OPTERON_ERRATUM_298) 704 opteron_erratum_298++; 705 #else 706 workaround_warning(cpu, 298); 707 return (1); 708 #endif 709 } 710 break; 711 } 712 return (0); 713 } 714 715 uint_t 716 workaround_errata(struct cpu *cpu) 717 { 718 uint_t missing = 0; 719 720 ASSERT(cpu == CPU); 721 722 /*LINTED*/ 723 if (cpuid_opteron_erratum(cpu, 88) > 0) { 724 /* 725 * SWAPGS May Fail To Read Correct GS Base 726 */ 727 #if defined(OPTERON_ERRATUM_88) 728 /* 729 * The workaround is an mfence in the relevant assembler code 730 */ 731 opteron_erratum_88++; 732 #else 733 workaround_warning(cpu, 88); 734 missing++; 735 #endif 736 } 737 738 if (cpuid_opteron_erratum(cpu, 91) > 0) { 739 /* 740 * Software Prefetches May Report A Page Fault 741 */ 742 #if defined(OPTERON_ERRATUM_91) 743 /* 744 * fix is in trap.c 745 */ 746 opteron_erratum_91++; 747 #else 748 workaround_warning(cpu, 91); 749 missing++; 750 #endif 751 } 752 753 if (cpuid_opteron_erratum(cpu, 93) > 0) { 754 /* 755 * RSM Auto-Halt Restart Returns to Incorrect RIP 756 */ 757 #if defined(OPTERON_ERRATUM_93) 758 /* 759 * fix is in trap.c 760 */ 761 opteron_erratum_93++; 762 #else 763 workaround_warning(cpu, 93); 764 missing++; 765 #endif 766 } 767 768 /*LINTED*/ 769 if (cpuid_opteron_erratum(cpu, 95) > 0) { 770 /* 771 * RET Instruction May Return to Incorrect EIP 772 */ 773 #if defined(OPTERON_ERRATUM_95) 774 #if defined(_LP64) 775 /* 776 * Workaround this by ensuring that 32-bit user code and 777 * 64-bit kernel code never occupy the same address 778 * range mod 4G. 779 */ 780 if (_userlimit32 > 0xc0000000ul) 781 *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 782 783 /*LINTED*/ 784 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 785 opteron_erratum_95++; 786 #endif /* _LP64 */ 787 #else 788 workaround_warning(cpu, 95); 789 missing++; 790 #endif 791 } 792 793 if (cpuid_opteron_erratum(cpu, 100) > 0) { 794 /* 795 * Compatibility Mode Branches Transfer to Illegal Address 796 */ 797 #if defined(OPTERON_ERRATUM_100) 798 /* 799 * fix is in trap.c 800 */ 801 opteron_erratum_100++; 802 #else 803 workaround_warning(cpu, 100); 804 missing++; 805 #endif 806 } 807 808 /*LINTED*/ 809 if (cpuid_opteron_erratum(cpu, 108) > 0) { 810 /* 811 * CPUID Instruction May Return Incorrect Model Number In 812 * Some Processors 813 */ 814 #if defined(OPTERON_ERRATUM_108) 815 /* 816 * (Our cpuid-handling code corrects the model number on 817 * those processors) 818 */ 819 #else 820 workaround_warning(cpu, 108); 821 missing++; 822 #endif 823 } 824 825 /*LINTED*/ 826 if (cpuid_opteron_erratum(cpu, 109) > 0) do { 827 /* 828 * Certain Reverse REP MOVS May Produce Unpredictable Behavior 829 */ 830 #if defined(OPTERON_ERRATUM_109) 831 /* 832 * The "workaround" is to print a warning to upgrade the BIOS 833 */ 834 uint64_t value; 835 const uint_t msr = MSR_AMD_PATCHLEVEL; 836 int err; 837 838 if ((err = checked_rdmsr(msr, &value)) != 0) { 839 msr_warning(cpu, "rd", msr, err); 840 workaround_warning(cpu, 109); 841 missing++; 842 } 843 if (value == 0) 844 opteron_erratum_109++; 845 #else 846 workaround_warning(cpu, 109); 847 missing++; 848 #endif 849 /*CONSTANTCONDITION*/ 850 } while (0); 851 852 /*LINTED*/ 853 if (cpuid_opteron_erratum(cpu, 121) > 0) { 854 /* 855 * Sequential Execution Across Non_Canonical Boundary Caused 856 * Processor Hang 857 */ 858 #if defined(OPTERON_ERRATUM_121) 859 #if defined(_LP64) 860 /* 861 * Erratum 121 is only present in long (64 bit) mode. 862 * Workaround is to include the page immediately before the 863 * va hole to eliminate the possibility of system hangs due to 864 * sequential execution across the va hole boundary. 865 */ 866 if (opteron_erratum_121) 867 opteron_erratum_121++; 868 else { 869 if (hole_start) { 870 hole_start -= PAGESIZE; 871 } else { 872 /* 873 * hole_start not yet initialized by 874 * mmu_init. Initialize hole_start 875 * with value to be subtracted. 876 */ 877 hole_start = PAGESIZE; 878 } 879 opteron_erratum_121++; 880 } 881 #endif /* _LP64 */ 882 #else 883 workaround_warning(cpu, 121); 884 missing++; 885 #endif 886 } 887 888 /*LINTED*/ 889 if (cpuid_opteron_erratum(cpu, 122) > 0) do { 890 /* 891 * TLB Flush Filter May Cause Coherency Problem in 892 * Multiprocessor Systems 893 */ 894 #if defined(OPTERON_ERRATUM_122) 895 uint64_t value; 896 const uint_t msr = MSR_AMD_HWCR; 897 int error; 898 899 /* 900 * Erratum 122 is only present in MP configurations (multi-core 901 * or multi-processor). 902 */ 903 #if defined(__xpv) 904 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 905 break; 906 if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1) 907 break; 908 #else 909 if (!opteron_erratum_122 && opteron_get_nnodes() == 1 && 910 cpuid_get_ncpu_per_chip(cpu) == 1) 911 break; 912 #endif 913 /* disable TLB Flush Filter */ 914 915 if ((error = checked_rdmsr(msr, &value)) != 0) { 916 msr_warning(cpu, "rd", msr, error); 917 workaround_warning(cpu, 122); 918 missing++; 919 } else { 920 value |= (uint64_t)AMD_HWCR_FFDIS; 921 if ((error = checked_wrmsr(msr, value)) != 0) { 922 msr_warning(cpu, "wr", msr, error); 923 workaround_warning(cpu, 122); 924 missing++; 925 } 926 } 927 opteron_erratum_122++; 928 #else 929 workaround_warning(cpu, 122); 930 missing++; 931 #endif 932 /*CONSTANTCONDITION*/ 933 } while (0); 934 935 /*LINTED*/ 936 if (cpuid_opteron_erratum(cpu, 123) > 0) do { 937 /* 938 * Bypassed Reads May Cause Data Corruption of System Hang in 939 * Dual Core Processors 940 */ 941 #if defined(OPTERON_ERRATUM_123) 942 uint64_t value; 943 const uint_t msr = MSR_AMD_PATCHLEVEL; 944 int err; 945 946 /* 947 * Erratum 123 applies only to multi-core cpus. 948 */ 949 if (cpuid_get_ncpu_per_chip(cpu) < 2) 950 break; 951 #if defined(__xpv) 952 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 953 break; 954 #endif 955 /* 956 * The "workaround" is to print a warning to upgrade the BIOS 957 */ 958 if ((err = checked_rdmsr(msr, &value)) != 0) { 959 msr_warning(cpu, "rd", msr, err); 960 workaround_warning(cpu, 123); 961 missing++; 962 } 963 if (value == 0) 964 opteron_erratum_123++; 965 #else 966 workaround_warning(cpu, 123); 967 missing++; 968 969 #endif 970 /*CONSTANTCONDITION*/ 971 } while (0); 972 973 /*LINTED*/ 974 if (cpuid_opteron_erratum(cpu, 131) > 0) do { 975 /* 976 * Multiprocessor Systems with Four or More Cores May Deadlock 977 * Waiting for a Probe Response 978 */ 979 #if defined(OPTERON_ERRATUM_131) 980 uint64_t nbcfg; 981 const uint_t msr = MSR_AMD_NB_CFG; 982 const uint64_t wabits = 983 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 984 int error; 985 986 /* 987 * Erratum 131 applies to any system with four or more cores. 988 */ 989 if (opteron_erratum_131) 990 break; 991 #if defined(__xpv) 992 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 993 break; 994 if (xpv_nr_phys_cpus() < 4) 995 break; 996 #else 997 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4) 998 break; 999 #endif 1000 /* 1001 * Print a warning if neither of the workarounds for 1002 * erratum 131 is present. 1003 */ 1004 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 1005 msr_warning(cpu, "rd", msr, error); 1006 workaround_warning(cpu, 131); 1007 missing++; 1008 } else if ((nbcfg & wabits) == 0) { 1009 opteron_erratum_131++; 1010 } else { 1011 /* cannot have both workarounds set */ 1012 ASSERT((nbcfg & wabits) != wabits); 1013 } 1014 #else 1015 workaround_warning(cpu, 131); 1016 missing++; 1017 #endif 1018 /*CONSTANTCONDITION*/ 1019 } while (0); 1020 1021 /* 1022 * This isn't really an erratum, but for convenience the 1023 * detection/workaround code lives here and in cpuid_opteron_erratum. 1024 */ 1025 if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 1026 #if defined(OPTERON_WORKAROUND_6336786) 1027 /* 1028 * Disable C1-Clock ramping on multi-core/multi-processor 1029 * K8 platforms to guard against TSC drift. 1030 */ 1031 if (opteron_workaround_6336786) { 1032 opteron_workaround_6336786++; 1033 #if defined(__xpv) 1034 } else if ((DOMAIN_IS_INITDOMAIN(xen_info) && 1035 xpv_nr_phys_cpus() > 1) || 1036 opteron_workaround_6336786_UP) { 1037 /* 1038 * XXPV Hmm. We can't walk the Northbridges on 1039 * the hypervisor; so just complain and drive 1040 * on. This probably needs to be fixed in 1041 * the hypervisor itself. 1042 */ 1043 opteron_workaround_6336786++; 1044 workaround_warning(cpu, 6336786); 1045 #else /* __xpv */ 1046 } else if ((opteron_get_nnodes() * 1047 cpuid_get_ncpu_per_chip(cpu) > 1) || 1048 opteron_workaround_6336786_UP) { 1049 1050 uint_t node, nnodes; 1051 uint8_t data; 1052 1053 nnodes = opteron_get_nnodes(); 1054 for (node = 0; node < nnodes; node++) { 1055 /* 1056 * Clear PMM7[1:0] (function 3, offset 0x87) 1057 * Northbridge device is the node id + 24. 1058 */ 1059 data = pci_getb_func(0, node + 24, 3, 0x87); 1060 data &= 0xFC; 1061 pci_putb_func(0, node + 24, 3, 0x87, data); 1062 } 1063 opteron_workaround_6336786++; 1064 #endif /* __xpv */ 1065 } 1066 #else 1067 workaround_warning(cpu, 6336786); 1068 missing++; 1069 #endif 1070 } 1071 1072 /*LINTED*/ 1073 /* 1074 * Mutex primitives don't work as expected. 1075 */ 1076 if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 1077 #if defined(OPTERON_WORKAROUND_6323525) 1078 /* 1079 * This problem only occurs with 2 or more cores. If bit in 1080 * MSR_AMD_BU_CFG set, then not applicable. The workaround 1081 * is to patch the semaphone routines with the lfence 1082 * instruction to provide necessary load memory barrier with 1083 * possible subsequent read-modify-write ops. 1084 * 1085 * It is too early in boot to call the patch routine so 1086 * set erratum variable to be done in startup_end(). 1087 */ 1088 if (opteron_workaround_6323525) { 1089 opteron_workaround_6323525++; 1090 #if defined(__xpv) 1091 } else if (x86_feature & X86_SSE2) { 1092 if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1093 /* 1094 * XXPV Use dom0_msr here when extended 1095 * operations are supported? 1096 */ 1097 if (xpv_nr_phys_cpus() > 1) 1098 opteron_workaround_6323525++; 1099 } else { 1100 /* 1101 * We have no way to tell how many physical 1102 * cpus there are, or even if this processor 1103 * has the problem, so enable the workaround 1104 * unconditionally (at some performance cost). 1105 */ 1106 opteron_workaround_6323525++; 1107 } 1108 #else /* __xpv */ 1109 } else if ((x86_feature & X86_SSE2) && ((opteron_get_nnodes() * 1110 cpuid_get_ncpu_per_chip(cpu)) > 1)) { 1111 if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0) 1112 opteron_workaround_6323525++; 1113 #endif /* __xpv */ 1114 } 1115 #else 1116 workaround_warning(cpu, 6323525); 1117 missing++; 1118 #endif 1119 } 1120 1121 missing += do_erratum_298(cpu); 1122 1123 #ifdef __xpv 1124 return (0); 1125 #else 1126 return (missing); 1127 #endif 1128 } 1129 1130 void 1131 workaround_errata_end() 1132 { 1133 #if defined(OPTERON_ERRATUM_88) 1134 if (opteron_erratum_88) 1135 workaround_applied(88); 1136 #endif 1137 #if defined(OPTERON_ERRATUM_91) 1138 if (opteron_erratum_91) 1139 workaround_applied(91); 1140 #endif 1141 #if defined(OPTERON_ERRATUM_93) 1142 if (opteron_erratum_93) 1143 workaround_applied(93); 1144 #endif 1145 #if defined(OPTERON_ERRATUM_95) 1146 if (opteron_erratum_95) 1147 workaround_applied(95); 1148 #endif 1149 #if defined(OPTERON_ERRATUM_100) 1150 if (opteron_erratum_100) 1151 workaround_applied(100); 1152 #endif 1153 #if defined(OPTERON_ERRATUM_108) 1154 if (opteron_erratum_108) 1155 workaround_applied(108); 1156 #endif 1157 #if defined(OPTERON_ERRATUM_109) 1158 if (opteron_erratum_109) { 1159 cmn_err(CE_WARN, 1160 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1161 " processor\nerratum 109 was not detected; updating your" 1162 " system's BIOS to a version\ncontaining this" 1163 " microcode patch is HIGHLY recommended or erroneous" 1164 " system\noperation may occur.\n"); 1165 } 1166 #endif 1167 #if defined(OPTERON_ERRATUM_121) 1168 if (opteron_erratum_121) 1169 workaround_applied(121); 1170 #endif 1171 #if defined(OPTERON_ERRATUM_122) 1172 if (opteron_erratum_122) 1173 workaround_applied(122); 1174 #endif 1175 #if defined(OPTERON_ERRATUM_123) 1176 if (opteron_erratum_123) { 1177 cmn_err(CE_WARN, 1178 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1179 " processor\nerratum 123 was not detected; updating your" 1180 " system's BIOS to a version\ncontaining this" 1181 " microcode patch is HIGHLY recommended or erroneous" 1182 " system\noperation may occur.\n"); 1183 } 1184 #endif 1185 #if defined(OPTERON_ERRATUM_131) 1186 if (opteron_erratum_131) { 1187 cmn_err(CE_WARN, 1188 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1189 " processor\nerratum 131 was not detected; updating your" 1190 " system's BIOS to a version\ncontaining this" 1191 " microcode patch is HIGHLY recommended or erroneous" 1192 " system\noperation may occur.\n"); 1193 } 1194 #endif 1195 #if defined(OPTERON_WORKAROUND_6336786) 1196 if (opteron_workaround_6336786) 1197 workaround_applied(6336786); 1198 #endif 1199 #if defined(OPTERON_WORKAROUND_6323525) 1200 if (opteron_workaround_6323525) 1201 workaround_applied(6323525); 1202 #endif 1203 #if defined(OPTERON_ERRATUM_298) 1204 if (opteron_erratum_298) { 1205 cmn_err(CE_WARN, 1206 "BIOS microcode patch for AMD 64/Opteron(tm)" 1207 " processor\nerratum 298 was not detected; updating your" 1208 " system's BIOS to a version\ncontaining this" 1209 " microcode patch is HIGHLY recommended or erroneous" 1210 " system\noperation may occur.\n"); 1211 } 1212 #endif 1213 } 1214 1215 static cpuset_t procset; 1216 1217 /* 1218 * Start a single cpu, assuming that the kernel context is available 1219 * to successfully start another cpu. 1220 * 1221 * (For example, real mode code is mapped into the right place 1222 * in memory and is ready to be run.) 1223 */ 1224 int 1225 start_cpu(processorid_t who) 1226 { 1227 void *ctx; 1228 cpu_t *cp; 1229 int delays; 1230 int error = 0; 1231 1232 ASSERT(who != 0); 1233 1234 /* 1235 * Check if there's at least a Mbyte of kmem available 1236 * before attempting to start the cpu. 1237 */ 1238 if (kmem_avail() < 1024 * 1024) { 1239 /* 1240 * Kick off a reap in case that helps us with 1241 * later attempts .. 1242 */ 1243 kmem_reap(); 1244 return (ENOMEM); 1245 } 1246 1247 cp = mp_startup_init(who); 1248 if ((ctx = mach_cpucontext_alloc(cp)) == NULL || 1249 (error = mach_cpu_start(cp, ctx)) != 0) { 1250 1251 /* 1252 * Something went wrong before we even started it 1253 */ 1254 if (ctx) 1255 cmn_err(CE_WARN, 1256 "cpu%d: failed to start error %d", 1257 cp->cpu_id, error); 1258 else 1259 cmn_err(CE_WARN, 1260 "cpu%d: failed to allocate context", cp->cpu_id); 1261 1262 if (ctx) 1263 mach_cpucontext_free(cp, ctx, error); 1264 else 1265 error = EAGAIN; /* hmm. */ 1266 mp_startup_fini(cp, error); 1267 return (error); 1268 } 1269 1270 for (delays = 0; !CPU_IN_SET(procset, who); delays++) { 1271 if (delays == 500) { 1272 /* 1273 * After five seconds, things are probably looking 1274 * a bit bleak - explain the hang. 1275 */ 1276 cmn_err(CE_NOTE, "cpu%d: started, " 1277 "but not running in the kernel yet", who); 1278 } else if (delays > 2000) { 1279 /* 1280 * We waited at least 20 seconds, bail .. 1281 */ 1282 error = ETIMEDOUT; 1283 cmn_err(CE_WARN, "cpu%d: timed out", who); 1284 mach_cpucontext_free(cp, ctx, error); 1285 mp_startup_fini(cp, error); 1286 return (error); 1287 } 1288 1289 /* 1290 * wait at least 10ms, then check again.. 1291 */ 1292 delay(USEC_TO_TICK_ROUNDUP(10000)); 1293 } 1294 1295 mach_cpucontext_free(cp, ctx, 0); 1296 1297 #ifndef __xpv 1298 if (tsc_gethrtime_enable) 1299 tsc_sync_master(who); 1300 #endif 1301 1302 if (dtrace_cpu_init != NULL) { 1303 /* 1304 * DTrace CPU initialization expects cpu_lock to be held. 1305 */ 1306 mutex_enter(&cpu_lock); 1307 (*dtrace_cpu_init)(who); 1308 mutex_exit(&cpu_lock); 1309 } 1310 1311 while (!CPU_IN_SET(cpu_ready_set, who)) 1312 delay(1); 1313 1314 return (0); 1315 } 1316 1317 1318 /*ARGSUSED*/ 1319 void 1320 start_other_cpus(int cprboot) 1321 { 1322 uint_t who; 1323 uint_t skipped = 0; 1324 uint_t bootcpuid = 0; 1325 1326 /* 1327 * Initialize our own cpu_info. 1328 */ 1329 init_cpu_info(CPU); 1330 1331 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr); 1332 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr); 1333 1334 /* 1335 * Initialize our syscall handlers 1336 */ 1337 init_cpu_syscall(CPU); 1338 1339 /* 1340 * Take the boot cpu out of the mp_cpus set because we know 1341 * it's already running. Add it to the cpu_ready_set for 1342 * precisely the same reason. 1343 */ 1344 CPUSET_DEL(mp_cpus, bootcpuid); 1345 CPUSET_ADD(cpu_ready_set, bootcpuid); 1346 1347 /* 1348 * if only 1 cpu or not using MP, skip the rest of this 1349 */ 1350 if (CPUSET_ISNULL(mp_cpus) || use_mp == 0) { 1351 if (use_mp == 0) 1352 cmn_err(CE_CONT, "?***** Not in MP mode\n"); 1353 goto done; 1354 } 1355 1356 /* 1357 * perform such initialization as is needed 1358 * to be able to take CPUs on- and off-line. 1359 */ 1360 cpu_pause_init(); 1361 1362 xc_init_cpu(CPU); /* initialize processor crosscalls */ 1363 1364 if (mach_cpucontext_init() != 0) 1365 goto done; 1366 1367 flushes_require_xcalls = 1; 1368 1369 /* 1370 * We lock our affinity to the master CPU to ensure that all slave CPUs 1371 * do their TSC syncs with the same CPU. 1372 */ 1373 affinity_set(CPU_CURRENT); 1374 1375 for (who = 0; who < NCPU; who++) { 1376 1377 if (!CPU_IN_SET(mp_cpus, who)) 1378 continue; 1379 ASSERT(who != bootcpuid); 1380 if (ncpus >= max_ncpus) { 1381 skipped = who; 1382 continue; 1383 } 1384 if (start_cpu(who) != 0) 1385 CPUSET_DEL(mp_cpus, who); 1386 1387 mutex_enter(&cpu_lock); 1388 cpu_state_change_notify(who, CPU_SETUP); 1389 mutex_exit(&cpu_lock); 1390 } 1391 1392 /* Free the space allocated to hold the microcode file */ 1393 ucode_cleanup(); 1394 1395 affinity_clear(); 1396 1397 if (skipped) { 1398 cmn_err(CE_NOTE, 1399 "System detected %d cpus, but " 1400 "only %d cpu(s) were enabled during boot.", 1401 skipped + 1, ncpus); 1402 cmn_err(CE_NOTE, 1403 "Use \"boot-ncpus\" parameter to enable more CPU(s). " 1404 "See eeprom(1M)."); 1405 } 1406 1407 done: 1408 if (get_hwenv() == HW_NATIVE) 1409 workaround_errata_end(); 1410 mach_cpucontext_fini(); 1411 1412 cmi_post_mpstartup(); 1413 } 1414 1415 /* 1416 * Dummy functions - no i86pc platforms support dynamic cpu allocation. 1417 */ 1418 /*ARGSUSED*/ 1419 int 1420 mp_cpu_configure(int cpuid) 1421 { 1422 return (ENOTSUP); /* not supported */ 1423 } 1424 1425 /*ARGSUSED*/ 1426 int 1427 mp_cpu_unconfigure(int cpuid) 1428 { 1429 return (ENOTSUP); /* not supported */ 1430 } 1431 1432 /* 1433 * Startup function for 'other' CPUs (besides boot cpu). 1434 * Called from real_mode_start. 1435 * 1436 * WARNING: until CPU_READY is set, mp_startup and routines called by 1437 * mp_startup should not call routines (e.g. kmem_free) that could call 1438 * hat_unload which requires CPU_READY to be set. 1439 */ 1440 void 1441 mp_startup(void) 1442 { 1443 struct cpu *cp = CPU; 1444 uint_t new_x86_feature; 1445 extern void cpu_event_init_cpu(cpu_t *); 1446 #ifndef __xpv 1447 extern void cpupm_init(cpu_t *); 1448 #endif 1449 const char *fmt = "?cpu%d: %b\n"; 1450 1451 /* 1452 * We need to get TSC on this proc synced (i.e., any delta 1453 * from cpu0 accounted for) as soon as we can, because many 1454 * many things use gethrtime/pc_gethrestime, including 1455 * interrupts, cmn_err, etc. 1456 */ 1457 1458 /* Let cpu0 continue into tsc_sync_master() */ 1459 CPUSET_ATOMIC_ADD(procset, cp->cpu_id); 1460 1461 #ifndef __xpv 1462 if (tsc_gethrtime_enable) 1463 tsc_sync_slave(); 1464 #endif 1465 1466 /* 1467 * Once this was done from assembly, but it's safer here; if 1468 * it blocks, we need to be able to swtch() to and from, and 1469 * since we get here by calling t_pc, we need to do that call 1470 * before swtch() overwrites it. 1471 */ 1472 (void) (*ap_mlsetup)(); 1473 1474 new_x86_feature = cpuid_pass1(cp); 1475 1476 #ifndef __xpv 1477 /* 1478 * Program this cpu's PAT 1479 */ 1480 if (x86_feature & X86_PAT) 1481 pat_sync(); 1482 #endif 1483 1484 /* 1485 * Set up TSC_AUX to contain the cpuid for this processor 1486 * for the rdtscp instruction. 1487 */ 1488 if (x86_feature & X86_TSCP) 1489 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1490 1491 /* 1492 * Initialize this CPU's syscall handlers 1493 */ 1494 init_cpu_syscall(cp); 1495 1496 /* 1497 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 1498 * highest level at which a routine is permitted to block on 1499 * an adaptive mutex (allows for cpu poke interrupt in case 1500 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 1501 * device interrupts that may end up in the hat layer issuing cross 1502 * calls before CPU_READY is set. 1503 */ 1504 splx(ipltospl(LOCK_LEVEL)); 1505 sti(); 1506 1507 /* 1508 * Do a sanity check to make sure this new CPU is a sane thing 1509 * to add to the collection of processors running this system. 1510 * 1511 * XXX Clearly this needs to get more sophisticated, if x86 1512 * systems start to get built out of heterogenous CPUs; as is 1513 * likely to happen once the number of processors in a configuration 1514 * gets large enough. 1515 */ 1516 if ((x86_feature & new_x86_feature) != x86_feature) { 1517 cmn_err(CE_CONT, fmt, cp->cpu_id, new_x86_feature, 1518 FMT_X86_FEATURE); 1519 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 1520 } 1521 1522 /* 1523 * We do not support cpus with mixed monitor/mwait support if the 1524 * boot cpu supports monitor/mwait. 1525 */ 1526 if ((x86_feature & ~new_x86_feature) & X86_MWAIT) 1527 panic("unsupported mixed cpu monitor/mwait support detected"); 1528 1529 /* 1530 * We could be more sophisticated here, and just mark the CPU 1531 * as "faulted" but at this point we'll opt for the easier 1532 * answer of dying horribly. Provided the boot cpu is ok, 1533 * the system can be recovered by booting with use_mp set to zero. 1534 */ 1535 if (workaround_errata(cp) != 0) 1536 panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 1537 1538 cpuid_pass2(cp); 1539 cpuid_pass3(cp); 1540 (void) cpuid_pass4(cp); 1541 1542 init_cpu_info(cp); 1543 1544 mutex_enter(&cpu_lock); 1545 1546 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS; 1547 1548 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 1549 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 1550 1551 if (dtrace_cpu_init != NULL) { 1552 (*dtrace_cpu_init)(cp->cpu_id); 1553 } 1554 1555 /* 1556 * Fill out cpu_ucode_info. Update microcode if necessary. 1557 */ 1558 ucode_check(cp); 1559 1560 mutex_exit(&cpu_lock); 1561 1562 post_startup_cpu_fixups(); 1563 1564 /* 1565 * Enable preemption here so that contention for any locks acquired 1566 * later in mp_startup may be preempted if the thread owning those 1567 * locks is continuously executing on other CPUs (for example, this 1568 * CPU must be preemptible to allow other CPUs to pause it during their 1569 * startup phases). It's safe to enable preemption here because the 1570 * CPU state is pretty-much fully constructed. 1571 */ 1572 curthread->t_preempt = 0; 1573 1574 /* The base spl should still be at LOCK LEVEL here */ 1575 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1576 set_base_spl(); /* Restore the spl to its proper value */ 1577 1578 cpu_event_init_cpu(cp); 1579 #ifndef __xpv 1580 cpupm_init(cp); 1581 #endif 1582 1583 /* 1584 * Processor group initialization for this CPU is dependent on the 1585 * cpuid probing, which must be done in the context of the current 1586 * CPU, as well as the CPU's device node initialization (for ACPI). 1587 */ 1588 mutex_enter(&cpu_lock); 1589 pghw_physid_create(cp); 1590 pg_cpu_init(cp); 1591 pg_cmt_cpu_startup(cp); 1592 mutex_exit(&cpu_lock); 1593 1594 /* Enable interrupts */ 1595 (void) spl0(); 1596 1597 mutex_enter(&cpu_lock); 1598 cpu_enable_intr(cp); 1599 cpu_add_active(cp); 1600 mutex_exit(&cpu_lock); 1601 1602 #ifndef __xpv 1603 { 1604 /* 1605 * Set up the CPU module for this CPU. This can't be done 1606 * before this CPU is made CPU_READY, because we may (in 1607 * heterogeneous systems) need to go load another CPU module. 1608 * The act of attempting to load a module may trigger a 1609 * cross-call, which will ASSERT unless this cpu is CPU_READY. 1610 */ 1611 cmi_hdl_t hdl; 1612 1613 if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), 1614 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) { 1615 if (x86_feature & X86_MCA) 1616 cmi_mca_init(hdl); 1617 } 1618 } 1619 #endif /* __xpv */ 1620 1621 if (boothowto & RB_DEBUG) 1622 kdi_cpu_init(); 1623 1624 /* 1625 * Setting the bit in cpu_ready_set must be the last operation in 1626 * processor initialization; the boot CPU will continue to boot once 1627 * it sees this bit set for all active CPUs. 1628 */ 1629 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 1630 1631 /* 1632 * Because mp_startup() gets fired off after init() starts, we 1633 * can't use the '?' trick to do 'boot -v' printing - so we 1634 * always direct the 'cpu .. online' messages to the log. 1635 */ 1636 cmn_err(CE_CONT, "!cpu%d initialization complete - online\n", 1637 cp->cpu_id); 1638 1639 (void) mach_cpu_create_device_node(cp, NULL); 1640 1641 /* 1642 * Now we are done with the startup thread, so free it up. 1643 */ 1644 thread_exit(); 1645 panic("mp_startup: cannot return"); 1646 /*NOTREACHED*/ 1647 } 1648 1649 1650 /* 1651 * Start CPU on user request. 1652 */ 1653 /* ARGSUSED */ 1654 int 1655 mp_cpu_start(struct cpu *cp) 1656 { 1657 ASSERT(MUTEX_HELD(&cpu_lock)); 1658 return (0); 1659 } 1660 1661 /* 1662 * Stop CPU on user request. 1663 */ 1664 /* ARGSUSED */ 1665 int 1666 mp_cpu_stop(struct cpu *cp) 1667 { 1668 extern int cbe_psm_timer_mode; 1669 ASSERT(MUTEX_HELD(&cpu_lock)); 1670 1671 #ifdef __xpv 1672 /* 1673 * We can't offline vcpu0. 1674 */ 1675 if (cp->cpu_id == 0) 1676 return (EBUSY); 1677 #endif 1678 1679 /* 1680 * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1681 * can't stop it. (This is true only for machines with no TSC.) 1682 */ 1683 1684 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1685 return (EBUSY); 1686 1687 return (0); 1688 } 1689 1690 /* 1691 * Take the specified CPU out of participation in interrupts. 1692 */ 1693 int 1694 cpu_disable_intr(struct cpu *cp) 1695 { 1696 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 1697 return (EBUSY); 1698 1699 cp->cpu_flags &= ~CPU_ENABLE; 1700 return (0); 1701 } 1702 1703 /* 1704 * Allow the specified CPU to participate in interrupts. 1705 */ 1706 void 1707 cpu_enable_intr(struct cpu *cp) 1708 { 1709 ASSERT(MUTEX_HELD(&cpu_lock)); 1710 cp->cpu_flags |= CPU_ENABLE; 1711 psm_enable_intr(cp->cpu_id); 1712 } 1713 1714 1715 /*ARGSUSED*/ 1716 void 1717 mp_cpu_faulted_enter(struct cpu *cp) 1718 { 1719 #ifndef __xpv 1720 cmi_hdl_t hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1721 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1722 1723 if (hdl != NULL) { 1724 cmi_faulted_enter(hdl); 1725 cmi_hdl_rele(hdl); 1726 } 1727 #endif 1728 } 1729 1730 /*ARGSUSED*/ 1731 void 1732 mp_cpu_faulted_exit(struct cpu *cp) 1733 { 1734 #ifndef __xpv 1735 cmi_hdl_t hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1736 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1737 1738 if (hdl != NULL) { 1739 cmi_faulted_exit(hdl); 1740 cmi_hdl_rele(hdl); 1741 } 1742 #endif 1743 } 1744 1745 /* 1746 * The following two routines are used as context operators on threads belonging 1747 * to processes with a private LDT (see sysi86). Due to the rarity of such 1748 * processes, these routines are currently written for best code readability and 1749 * organization rather than speed. We could avoid checking x86_feature at every 1750 * context switch by installing different context ops, depending on the 1751 * x86_feature flags, at LDT creation time -- one for each combination of fast 1752 * syscall feature flags. 1753 */ 1754 1755 /*ARGSUSED*/ 1756 void 1757 cpu_fast_syscall_disable(void *arg) 1758 { 1759 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1760 cpu_sep_disable(); 1761 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1762 cpu_asysc_disable(); 1763 } 1764 1765 /*ARGSUSED*/ 1766 void 1767 cpu_fast_syscall_enable(void *arg) 1768 { 1769 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1770 cpu_sep_enable(); 1771 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1772 cpu_asysc_enable(); 1773 } 1774 1775 static void 1776 cpu_sep_enable(void) 1777 { 1778 ASSERT(x86_feature & X86_SEP); 1779 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1780 1781 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 1782 } 1783 1784 static void 1785 cpu_sep_disable(void) 1786 { 1787 ASSERT(x86_feature & X86_SEP); 1788 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1789 1790 /* 1791 * Setting the SYSENTER_CS_MSR register to 0 causes software executing 1792 * the sysenter or sysexit instruction to trigger a #gp fault. 1793 */ 1794 wrmsr(MSR_INTC_SEP_CS, 0); 1795 } 1796 1797 static void 1798 cpu_asysc_enable(void) 1799 { 1800 ASSERT(x86_feature & X86_ASYSC); 1801 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1802 1803 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 1804 (uint64_t)(uintptr_t)AMD_EFER_SCE); 1805 } 1806 1807 static void 1808 cpu_asysc_disable(void) 1809 { 1810 ASSERT(x86_feature & X86_ASYSC); 1811 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1812 1813 /* 1814 * Turn off the SCE (syscall enable) bit in the EFER register. Software 1815 * executing syscall or sysret with this bit off will incur a #ud trap. 1816 */ 1817 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 1818 ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 1819 } 1820