1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include <sys/types.h> 28 #include <sys/thread.h> 29 #include <sys/cpuvar.h> 30 #include <sys/t_lock.h> 31 #include <sys/param.h> 32 #include <sys/proc.h> 33 #include <sys/disp.h> 34 #include <sys/class.h> 35 #include <sys/cmn_err.h> 36 #include <sys/debug.h> 37 #include <sys/asm_linkage.h> 38 #include <sys/x_call.h> 39 #include <sys/systm.h> 40 #include <sys/var.h> 41 #include <sys/vtrace.h> 42 #include <vm/hat.h> 43 #include <vm/as.h> 44 #include <vm/seg_kmem.h> 45 #include <vm/seg_kp.h> 46 #include <sys/segments.h> 47 #include <sys/kmem.h> 48 #include <sys/stack.h> 49 #include <sys/smp_impldefs.h> 50 #include <sys/x86_archext.h> 51 #include <sys/machsystm.h> 52 #include <sys/traptrace.h> 53 #include <sys/clock.h> 54 #include <sys/cpc_impl.h> 55 #include <sys/pg.h> 56 #include <sys/cmt.h> 57 #include <sys/dtrace.h> 58 #include <sys/archsystm.h> 59 #include <sys/fp.h> 60 #include <sys/reboot.h> 61 #include <sys/kdi_machimpl.h> 62 #include <vm/hat_i86.h> 63 #include <sys/memnode.h> 64 #include <sys/pci_cfgspace.h> 65 #include <sys/mach_mmu.h> 66 #include <sys/sysmacros.h> 67 #if defined(__xpv) 68 #include <sys/hypervisor.h> 69 #endif 70 #include <sys/cpu_module.h> 71 72 struct cpu cpus[1]; /* CPU data */ 73 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 74 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 75 76 /* 77 * Useful for disabling MP bring-up on a MP capable system. 78 */ 79 int use_mp = 1; 80 81 /* 82 * to be set by a PSM to indicate what cpus 83 * are sitting around on the system. 84 */ 85 cpuset_t mp_cpus; 86 87 /* 88 * This variable is used by the hat layer to decide whether or not 89 * critical sections are needed to prevent race conditions. For sun4m, 90 * this variable is set once enough MP initialization has been done in 91 * order to allow cross calls. 92 */ 93 int flushes_require_xcalls; 94 95 cpuset_t cpu_ready_set; /* initialized in startup() */ 96 97 static void mp_startup(void); 98 99 static void cpu_sep_enable(void); 100 static void cpu_sep_disable(void); 101 static void cpu_asysc_enable(void); 102 static void cpu_asysc_disable(void); 103 104 /* 105 * Init CPU info - get CPU type info for processor_info system call. 106 */ 107 void 108 init_cpu_info(struct cpu *cp) 109 { 110 processor_info_t *pi = &cp->cpu_type_info; 111 char buf[CPU_IDSTRLEN]; 112 113 /* 114 * Get clock-frequency property for the CPU. 115 */ 116 pi->pi_clock = cpu_freq; 117 118 /* 119 * Current frequency in Hz. 120 */ 121 cp->cpu_curr_clock = cpu_freq_hz; 122 123 /* 124 * Supported frequencies. 125 */ 126 if (cp->cpu_supp_freqs == NULL) { 127 cpu_set_supp_freqs(cp, NULL); 128 } 129 130 (void) strcpy(pi->pi_processor_type, "i386"); 131 if (fpu_exists) 132 (void) strcpy(pi->pi_fputypes, "i387 compatible"); 133 134 (void) cpuid_getidstr(cp, buf, sizeof (buf)); 135 136 cp->cpu_idstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 137 (void) strcpy(cp->cpu_idstr, buf); 138 139 (void) cpuid_getbrandstr(cp, buf, sizeof (buf)); 140 cp->cpu_brandstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 141 (void) strcpy(cp->cpu_brandstr, buf); 142 } 143 144 /* 145 * Configure syscall support on this CPU. 146 */ 147 /*ARGSUSED*/ 148 void 149 init_cpu_syscall(struct cpu *cp) 150 { 151 kpreempt_disable(); 152 153 #if defined(__amd64) 154 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) { 155 156 #if !defined(__lint) 157 /* 158 * The syscall instruction imposes a certain ordering on 159 * segment selectors, so we double-check that ordering 160 * here. 161 */ 162 ASSERT(KDS_SEL == KCS_SEL + 8); 163 ASSERT(UDS_SEL == U32CS_SEL + 8); 164 ASSERT(UCS_SEL == U32CS_SEL + 16); 165 #endif 166 /* 167 * Turn syscall/sysret extensions on. 168 */ 169 cpu_asysc_enable(); 170 171 /* 172 * Program the magic registers .. 173 */ 174 wrmsr(MSR_AMD_STAR, 175 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 176 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 177 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 178 179 /* 180 * This list of flags is masked off the incoming 181 * %rfl when we enter the kernel. 182 */ 183 wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); 184 } 185 #endif 186 187 /* 188 * On 32-bit kernels, we use sysenter/sysexit because it's too 189 * hard to use syscall/sysret, and it is more portable anyway. 190 * 191 * On 64-bit kernels on Nocona machines, the 32-bit syscall 192 * variant isn't available to 32-bit applications, but sysenter is. 193 */ 194 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) { 195 196 #if !defined(__lint) 197 /* 198 * The sysenter instruction imposes a certain ordering on 199 * segment selectors, so we double-check that ordering 200 * here. See "sysenter" in Intel document 245471-012, "IA-32 201 * Intel Architecture Software Developer's Manual Volume 2: 202 * Instruction Set Reference" 203 */ 204 ASSERT(KDS_SEL == KCS_SEL + 8); 205 206 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 207 ASSERT32(UDS_SEL == UCS_SEL + 8); 208 209 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 210 ASSERT64(UDS_SEL == U32CS_SEL + 8); 211 #endif 212 213 cpu_sep_enable(); 214 215 /* 216 * resume() sets this value to the base of the threads stack 217 * via a context handler. 218 */ 219 wrmsr(MSR_INTC_SEP_ESP, 0); 220 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 221 } 222 223 kpreempt_enable(); 224 } 225 226 /* 227 * Multiprocessor initialization. 228 * 229 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 230 * startup and idle threads for the specified CPU. 231 */ 232 struct cpu * 233 mp_startup_init(int cpun) 234 { 235 struct cpu *cp; 236 kthread_id_t tp; 237 caddr_t sp; 238 proc_t *procp; 239 #if !defined(__xpv) 240 extern int idle_cpu_prefer_mwait; 241 extern void cpu_idle_mwait(); 242 #endif 243 extern void idle(); 244 extern void cpu_idle(); 245 246 #ifdef TRAPTRACE 247 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 248 #endif 249 250 ASSERT(cpun < NCPU && cpu[cpun] == NULL); 251 252 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 253 #if !defined(__xpv) 254 if ((x86_feature & X86_MWAIT) && idle_cpu_prefer_mwait) { 255 cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(CPU); 256 cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait; 257 } else 258 #endif 259 cp->cpu_m.mcpu_idle_cpu = cpu_idle; 260 261 cp->cpu_m.mcpu_istamp = cpun << 16; 262 263 procp = curthread->t_procp; 264 265 mutex_enter(&cpu_lock); 266 /* 267 * Initialize the dispatcher first. 268 */ 269 disp_cpu_init(cp); 270 mutex_exit(&cpu_lock); 271 272 cpu_vm_data_init(cp); 273 274 /* 275 * Allocate and initialize the startup thread for this CPU. 276 * Interrupt and process switch stacks get allocated later 277 * when the CPU starts running. 278 */ 279 tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 280 TS_STOPPED, maxclsyspri); 281 282 /* 283 * Set state to TS_ONPROC since this thread will start running 284 * as soon as the CPU comes online. 285 * 286 * All the other fields of the thread structure are setup by 287 * thread_create(). 288 */ 289 THREAD_ONPROC(tp, cp); 290 tp->t_preempt = 1; 291 tp->t_bound_cpu = cp; 292 tp->t_affinitycnt = 1; 293 tp->t_cpu = cp; 294 tp->t_disp_queue = cp->cpu_disp; 295 296 /* 297 * Setup thread to start in mp_startup. 298 */ 299 sp = tp->t_stk; 300 tp->t_pc = (uintptr_t)mp_startup; 301 tp->t_sp = (uintptr_t)(sp - MINFRAME); 302 #if defined(__amd64) 303 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 304 #endif 305 306 cp->cpu_id = cpun; 307 cp->cpu_self = cp; 308 cp->cpu_thread = tp; 309 cp->cpu_lwp = NULL; 310 cp->cpu_dispthread = tp; 311 cp->cpu_dispatch_pri = DISP_PRIO(tp); 312 313 /* 314 * cpu_base_spl must be set explicitly here to prevent any blocking 315 * operations in mp_startup from causing the spl of the cpu to drop 316 * to 0 (allowing device interrupts before we're ready) in resume(). 317 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 318 * As an extra bit of security on DEBUG kernels, this is enforced with 319 * an assertion in mp_startup() -- before cpu_base_spl is set to its 320 * proper value. 321 */ 322 cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 323 324 /* 325 * Now, initialize per-CPU idle thread for this CPU. 326 */ 327 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 328 329 cp->cpu_idle_thread = tp; 330 331 tp->t_preempt = 1; 332 tp->t_bound_cpu = cp; 333 tp->t_affinitycnt = 1; 334 tp->t_cpu = cp; 335 tp->t_disp_queue = cp->cpu_disp; 336 337 /* 338 * Bootstrap the CPU's PG data 339 */ 340 pg_cpu_bootstrap(cp); 341 342 /* 343 * Perform CPC initialization on the new CPU. 344 */ 345 kcpc_hw_init(cp); 346 347 /* 348 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 349 * for each CPU. 350 */ 351 setup_vaddr_for_ppcopy(cp); 352 353 /* 354 * Allocate page for new GDT and initialize from current GDT. 355 */ 356 #if !defined(__lint) 357 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 358 #endif 359 cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 360 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT)); 361 362 #if defined(__i386) 363 /* 364 * setup kernel %gs. 365 */ 366 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 367 SEL_KPL, 0, 1); 368 #endif 369 370 /* 371 * If we have more than one node, each cpu gets a copy of IDT 372 * local to its node. If this is a Pentium box, we use cpu 0's 373 * IDT. cpu 0's IDT has been made read-only to workaround the 374 * cmpxchgl register bug 375 */ 376 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 377 #if !defined(__lint) 378 ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE); 379 #endif 380 cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP); 381 bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE); 382 } else { 383 cp->cpu_idt = CPU->cpu_idt; 384 } 385 386 /* 387 * Get interrupt priority data from cpu 0. 388 */ 389 cp->cpu_pri_data = CPU->cpu_pri_data; 390 391 /* 392 * alloc space for cpuid info 393 */ 394 cpuid_alloc_space(cp); 395 396 /* 397 * alloc space for ucode_info 398 */ 399 ucode_alloc_space(cp); 400 xc_init_cpu(cp); 401 hat_cpu_online(cp); 402 403 #ifdef TRAPTRACE 404 /* 405 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 406 */ 407 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 408 ttc->ttc_next = ttc->ttc_first; 409 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 410 #endif 411 /* 412 * Record that we have another CPU. 413 */ 414 mutex_enter(&cpu_lock); 415 /* 416 * Initialize the interrupt threads for this CPU 417 */ 418 cpu_intr_alloc(cp, NINTR_THREADS); 419 /* 420 * Add CPU to list of available CPUs. It'll be on the active list 421 * after mp_startup(). 422 */ 423 cpu_add_unit(cp); 424 mutex_exit(&cpu_lock); 425 426 return (cp); 427 } 428 429 /* 430 * Undo what was done in mp_startup_init 431 */ 432 static void 433 mp_startup_fini(struct cpu *cp, int error) 434 { 435 mutex_enter(&cpu_lock); 436 437 /* 438 * Remove the CPU from the list of available CPUs. 439 */ 440 cpu_del_unit(cp->cpu_id); 441 442 if (error == ETIMEDOUT) { 443 /* 444 * The cpu was started, but never *seemed* to run any 445 * code in the kernel; it's probably off spinning in its 446 * own private world, though with potential references to 447 * our kmem-allocated IDTs and GDTs (for example). 448 * 449 * Worse still, it may actually wake up some time later, 450 * so rather than guess what it might or might not do, we 451 * leave the fundamental data structures intact. 452 */ 453 cp->cpu_flags = 0; 454 mutex_exit(&cpu_lock); 455 return; 456 } 457 458 /* 459 * At this point, the only threads bound to this CPU should 460 * special per-cpu threads: it's idle thread, it's pause threads, 461 * and it's interrupt threads. Clean these up. 462 */ 463 cpu_destroy_bound_threads(cp); 464 cp->cpu_idle_thread = NULL; 465 466 /* 467 * Free the interrupt stack. 468 */ 469 segkp_release(segkp, 470 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 471 472 mutex_exit(&cpu_lock); 473 474 #ifdef TRAPTRACE 475 /* 476 * Discard the trap trace buffer 477 */ 478 { 479 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 480 481 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 482 ttc->ttc_first = NULL; 483 } 484 #endif 485 486 hat_cpu_offline(cp); 487 488 cpuid_free_space(cp); 489 490 ucode_free_space(cp); 491 492 if (cp->cpu_idt != CPU->cpu_idt) 493 kmem_free(cp->cpu_idt, PAGESIZE); 494 cp->cpu_idt = NULL; 495 496 kmem_free(cp->cpu_gdt, PAGESIZE); 497 cp->cpu_gdt = NULL; 498 499 teardown_vaddr_for_ppcopy(cp); 500 501 kcpc_hw_fini(cp); 502 503 cp->cpu_dispthread = NULL; 504 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 505 506 cpu_vm_data_destroy(cp); 507 508 mutex_enter(&cpu_lock); 509 disp_cpu_fini(cp); 510 mutex_exit(&cpu_lock); 511 512 #if !defined(__xpv) 513 if (cp->cpu_m.mcpu_mwait != NULL) 514 cpuid_mwait_free(cp); 515 #endif 516 kmem_free(cp, sizeof (*cp)); 517 } 518 519 /* 520 * Apply workarounds for known errata, and warn about those that are absent. 521 * 522 * System vendors occasionally create configurations which contain different 523 * revisions of the CPUs that are almost but not exactly the same. At the 524 * time of writing, this meant that their clock rates were the same, their 525 * feature sets were the same, but the required workaround were -not- 526 * necessarily the same. So, this routine is invoked on -every- CPU soon 527 * after starting to make sure that the resulting system contains the most 528 * pessimal set of workarounds needed to cope with *any* of the CPUs in the 529 * system. 530 * 531 * workaround_errata is invoked early in mlsetup() for CPU 0, and in 532 * mp_startup() for all slave CPUs. Slaves process workaround_errata prior 533 * to acknowledging their readiness to the master, so this routine will 534 * never be executed by multiple CPUs in parallel, thus making updates to 535 * global data safe. 536 * 537 * These workarounds are based on Rev 3.57 of the Revision Guide for 538 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 539 */ 540 541 #if defined(OPTERON_ERRATUM_88) 542 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 543 #endif 544 545 #if defined(OPTERON_ERRATUM_91) 546 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 547 #endif 548 549 #if defined(OPTERON_ERRATUM_93) 550 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 551 #endif 552 553 #if defined(OPTERON_ERRATUM_95) 554 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 555 #endif 556 557 #if defined(OPTERON_ERRATUM_100) 558 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 559 #endif 560 561 #if defined(OPTERON_ERRATUM_108) 562 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 563 #endif 564 565 #if defined(OPTERON_ERRATUM_109) 566 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 567 #endif 568 569 #if defined(OPTERON_ERRATUM_121) 570 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 571 #endif 572 573 #if defined(OPTERON_ERRATUM_122) 574 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 575 #endif 576 577 #if defined(OPTERON_ERRATUM_123) 578 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 579 #endif 580 581 #if defined(OPTERON_ERRATUM_131) 582 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 583 #endif 584 585 #if defined(OPTERON_WORKAROUND_6336786) 586 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 587 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 588 #endif 589 590 #if defined(OPTERON_WORKAROUND_6323525) 591 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 592 #endif 593 594 #if defined(OPTERON_ERRATUM_298) 595 int opteron_erratum_298; 596 #endif 597 598 static void 599 workaround_warning(cpu_t *cp, uint_t erratum) 600 { 601 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 602 cp->cpu_id, erratum); 603 } 604 605 static void 606 workaround_applied(uint_t erratum) 607 { 608 if (erratum > 1000000) 609 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 610 erratum); 611 else 612 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 613 erratum); 614 } 615 616 static void 617 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 618 { 619 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 620 cp->cpu_id, rw, msr, error); 621 } 622 623 /* 624 * Determine the number of nodes in a Hammer / Greyhound / Griffin family 625 * system. 626 */ 627 static uint_t 628 opteron_get_nnodes(void) 629 { 630 static uint_t nnodes = 0; 631 632 if (nnodes == 0) { 633 #ifdef DEBUG 634 uint_t family; 635 636 /* 637 * This routine uses a PCI config space based mechanism 638 * for retrieving the number of nodes in the system. 639 * Device 24, function 0, offset 0x60 as used here is not 640 * AMD processor architectural, and may not work on processor 641 * families other than those listed below. 642 * 643 * Callers of this routine must ensure that we're running on 644 * a processor which supports this mechanism. 645 * The assertion below is meant to catch calls on unsupported 646 * processors. 647 */ 648 family = cpuid_getfamily(CPU); 649 ASSERT(family == 0xf || family == 0x10 || family == 0x11); 650 #endif /* DEBUG */ 651 652 /* 653 * Obtain the number of nodes in the system from 654 * bits [6:4] of the Node ID register on node 0. 655 * 656 * The actual node count is NodeID[6:4] + 1 657 * 658 * The Node ID register is accessed via function 0, 659 * offset 0x60. Node 0 is device 24. 660 */ 661 nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1; 662 } 663 return (nnodes); 664 } 665 666 uint_t 667 do_erratum_298(struct cpu *cpu) 668 { 669 static int osvwrc = -3; 670 extern int osvw_opteron_erratum(cpu_t *, uint_t); 671 672 /* 673 * L2 Eviction May Occur During Processor Operation To Set 674 * Accessed or Dirty Bit. 675 */ 676 if (osvwrc == -3) { 677 osvwrc = osvw_opteron_erratum(cpu, 298); 678 } else { 679 /* osvw return codes should be consistent for all cpus */ 680 ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298)); 681 } 682 683 switch (osvwrc) { 684 case 0: /* erratum is not present: do nothing */ 685 break; 686 case 1: /* erratum is present: BIOS workaround applied */ 687 /* 688 * check if workaround is actually in place and issue warning 689 * if not. 690 */ 691 if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 692 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) { 693 #if defined(OPTERON_ERRATUM_298) 694 opteron_erratum_298++; 695 #else 696 workaround_warning(cpu, 298); 697 return (1); 698 #endif 699 } 700 break; 701 case -1: /* cannot determine via osvw: check cpuid */ 702 if ((cpuid_opteron_erratum(cpu, 298) > 0) && 703 (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 704 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) { 705 #if defined(OPTERON_ERRATUM_298) 706 opteron_erratum_298++; 707 #else 708 workaround_warning(cpu, 298); 709 return (1); 710 #endif 711 } 712 break; 713 } 714 return (0); 715 } 716 717 uint_t 718 workaround_errata(struct cpu *cpu) 719 { 720 uint_t missing = 0; 721 722 ASSERT(cpu == CPU); 723 724 /*LINTED*/ 725 if (cpuid_opteron_erratum(cpu, 88) > 0) { 726 /* 727 * SWAPGS May Fail To Read Correct GS Base 728 */ 729 #if defined(OPTERON_ERRATUM_88) 730 /* 731 * The workaround is an mfence in the relevant assembler code 732 */ 733 opteron_erratum_88++; 734 #else 735 workaround_warning(cpu, 88); 736 missing++; 737 #endif 738 } 739 740 if (cpuid_opteron_erratum(cpu, 91) > 0) { 741 /* 742 * Software Prefetches May Report A Page Fault 743 */ 744 #if defined(OPTERON_ERRATUM_91) 745 /* 746 * fix is in trap.c 747 */ 748 opteron_erratum_91++; 749 #else 750 workaround_warning(cpu, 91); 751 missing++; 752 #endif 753 } 754 755 if (cpuid_opteron_erratum(cpu, 93) > 0) { 756 /* 757 * RSM Auto-Halt Restart Returns to Incorrect RIP 758 */ 759 #if defined(OPTERON_ERRATUM_93) 760 /* 761 * fix is in trap.c 762 */ 763 opteron_erratum_93++; 764 #else 765 workaround_warning(cpu, 93); 766 missing++; 767 #endif 768 } 769 770 /*LINTED*/ 771 if (cpuid_opteron_erratum(cpu, 95) > 0) { 772 /* 773 * RET Instruction May Return to Incorrect EIP 774 */ 775 #if defined(OPTERON_ERRATUM_95) 776 #if defined(_LP64) 777 /* 778 * Workaround this by ensuring that 32-bit user code and 779 * 64-bit kernel code never occupy the same address 780 * range mod 4G. 781 */ 782 if (_userlimit32 > 0xc0000000ul) 783 *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 784 785 /*LINTED*/ 786 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 787 opteron_erratum_95++; 788 #endif /* _LP64 */ 789 #else 790 workaround_warning(cpu, 95); 791 missing++; 792 #endif 793 } 794 795 if (cpuid_opteron_erratum(cpu, 100) > 0) { 796 /* 797 * Compatibility Mode Branches Transfer to Illegal Address 798 */ 799 #if defined(OPTERON_ERRATUM_100) 800 /* 801 * fix is in trap.c 802 */ 803 opteron_erratum_100++; 804 #else 805 workaround_warning(cpu, 100); 806 missing++; 807 #endif 808 } 809 810 /*LINTED*/ 811 if (cpuid_opteron_erratum(cpu, 108) > 0) { 812 /* 813 * CPUID Instruction May Return Incorrect Model Number In 814 * Some Processors 815 */ 816 #if defined(OPTERON_ERRATUM_108) 817 /* 818 * (Our cpuid-handling code corrects the model number on 819 * those processors) 820 */ 821 #else 822 workaround_warning(cpu, 108); 823 missing++; 824 #endif 825 } 826 827 /*LINTED*/ 828 if (cpuid_opteron_erratum(cpu, 109) > 0) do { 829 /* 830 * Certain Reverse REP MOVS May Produce Unpredictable Behavior 831 */ 832 #if defined(OPTERON_ERRATUM_109) 833 /* 834 * The "workaround" is to print a warning to upgrade the BIOS 835 */ 836 uint64_t value; 837 const uint_t msr = MSR_AMD_PATCHLEVEL; 838 int err; 839 840 if ((err = checked_rdmsr(msr, &value)) != 0) { 841 msr_warning(cpu, "rd", msr, err); 842 workaround_warning(cpu, 109); 843 missing++; 844 } 845 if (value == 0) 846 opteron_erratum_109++; 847 #else 848 workaround_warning(cpu, 109); 849 missing++; 850 #endif 851 /*CONSTANTCONDITION*/ 852 } while (0); 853 854 /*LINTED*/ 855 if (cpuid_opteron_erratum(cpu, 121) > 0) { 856 /* 857 * Sequential Execution Across Non_Canonical Boundary Caused 858 * Processor Hang 859 */ 860 #if defined(OPTERON_ERRATUM_121) 861 #if defined(_LP64) 862 /* 863 * Erratum 121 is only present in long (64 bit) mode. 864 * Workaround is to include the page immediately before the 865 * va hole to eliminate the possibility of system hangs due to 866 * sequential execution across the va hole boundary. 867 */ 868 if (opteron_erratum_121) 869 opteron_erratum_121++; 870 else { 871 if (hole_start) { 872 hole_start -= PAGESIZE; 873 } else { 874 /* 875 * hole_start not yet initialized by 876 * mmu_init. Initialize hole_start 877 * with value to be subtracted. 878 */ 879 hole_start = PAGESIZE; 880 } 881 opteron_erratum_121++; 882 } 883 #endif /* _LP64 */ 884 #else 885 workaround_warning(cpu, 121); 886 missing++; 887 #endif 888 } 889 890 /*LINTED*/ 891 if (cpuid_opteron_erratum(cpu, 122) > 0) do { 892 /* 893 * TLB Flush Filter May Cause Coherency Problem in 894 * Multiprocessor Systems 895 */ 896 #if defined(OPTERON_ERRATUM_122) 897 uint64_t value; 898 const uint_t msr = MSR_AMD_HWCR; 899 int error; 900 901 /* 902 * Erratum 122 is only present in MP configurations (multi-core 903 * or multi-processor). 904 */ 905 #if defined(__xpv) 906 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 907 break; 908 if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1) 909 break; 910 #else 911 if (!opteron_erratum_122 && opteron_get_nnodes() == 1 && 912 cpuid_get_ncpu_per_chip(cpu) == 1) 913 break; 914 #endif 915 /* disable TLB Flush Filter */ 916 917 if ((error = checked_rdmsr(msr, &value)) != 0) { 918 msr_warning(cpu, "rd", msr, error); 919 workaround_warning(cpu, 122); 920 missing++; 921 } else { 922 value |= (uint64_t)AMD_HWCR_FFDIS; 923 if ((error = checked_wrmsr(msr, value)) != 0) { 924 msr_warning(cpu, "wr", msr, error); 925 workaround_warning(cpu, 122); 926 missing++; 927 } 928 } 929 opteron_erratum_122++; 930 #else 931 workaround_warning(cpu, 122); 932 missing++; 933 #endif 934 /*CONSTANTCONDITION*/ 935 } while (0); 936 937 /*LINTED*/ 938 if (cpuid_opteron_erratum(cpu, 123) > 0) do { 939 /* 940 * Bypassed Reads May Cause Data Corruption of System Hang in 941 * Dual Core Processors 942 */ 943 #if defined(OPTERON_ERRATUM_123) 944 uint64_t value; 945 const uint_t msr = MSR_AMD_PATCHLEVEL; 946 int err; 947 948 /* 949 * Erratum 123 applies only to multi-core cpus. 950 */ 951 if (cpuid_get_ncpu_per_chip(cpu) < 2) 952 break; 953 #if defined(__xpv) 954 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 955 break; 956 #endif 957 /* 958 * The "workaround" is to print a warning to upgrade the BIOS 959 */ 960 if ((err = checked_rdmsr(msr, &value)) != 0) { 961 msr_warning(cpu, "rd", msr, err); 962 workaround_warning(cpu, 123); 963 missing++; 964 } 965 if (value == 0) 966 opteron_erratum_123++; 967 #else 968 workaround_warning(cpu, 123); 969 missing++; 970 971 #endif 972 /*CONSTANTCONDITION*/ 973 } while (0); 974 975 /*LINTED*/ 976 if (cpuid_opteron_erratum(cpu, 131) > 0) do { 977 /* 978 * Multiprocessor Systems with Four or More Cores May Deadlock 979 * Waiting for a Probe Response 980 */ 981 #if defined(OPTERON_ERRATUM_131) 982 uint64_t nbcfg; 983 const uint_t msr = MSR_AMD_NB_CFG; 984 const uint64_t wabits = 985 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 986 int error; 987 988 /* 989 * Erratum 131 applies to any system with four or more cores. 990 */ 991 if (opteron_erratum_131) 992 break; 993 #if defined(__xpv) 994 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 995 break; 996 if (xpv_nr_phys_cpus() < 4) 997 break; 998 #else 999 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4) 1000 break; 1001 #endif 1002 /* 1003 * Print a warning if neither of the workarounds for 1004 * erratum 131 is present. 1005 */ 1006 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 1007 msr_warning(cpu, "rd", msr, error); 1008 workaround_warning(cpu, 131); 1009 missing++; 1010 } else if ((nbcfg & wabits) == 0) { 1011 opteron_erratum_131++; 1012 } else { 1013 /* cannot have both workarounds set */ 1014 ASSERT((nbcfg & wabits) != wabits); 1015 } 1016 #else 1017 workaround_warning(cpu, 131); 1018 missing++; 1019 #endif 1020 /*CONSTANTCONDITION*/ 1021 } while (0); 1022 1023 /* 1024 * This isn't really an erratum, but for convenience the 1025 * detection/workaround code lives here and in cpuid_opteron_erratum. 1026 */ 1027 if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 1028 #if defined(OPTERON_WORKAROUND_6336786) 1029 /* 1030 * Disable C1-Clock ramping on multi-core/multi-processor 1031 * K8 platforms to guard against TSC drift. 1032 */ 1033 if (opteron_workaround_6336786) { 1034 opteron_workaround_6336786++; 1035 #if defined(__xpv) 1036 } else if ((DOMAIN_IS_INITDOMAIN(xen_info) && 1037 xpv_nr_phys_cpus() > 1) || 1038 opteron_workaround_6336786_UP) { 1039 /* 1040 * XXPV Hmm. We can't walk the Northbridges on 1041 * the hypervisor; so just complain and drive 1042 * on. This probably needs to be fixed in 1043 * the hypervisor itself. 1044 */ 1045 opteron_workaround_6336786++; 1046 workaround_warning(cpu, 6336786); 1047 #else /* __xpv */ 1048 } else if ((opteron_get_nnodes() * 1049 cpuid_get_ncpu_per_chip(cpu) > 1) || 1050 opteron_workaround_6336786_UP) { 1051 1052 uint_t node, nnodes; 1053 uint8_t data; 1054 1055 nnodes = opteron_get_nnodes(); 1056 for (node = 0; node < nnodes; node++) { 1057 /* 1058 * Clear PMM7[1:0] (function 3, offset 0x87) 1059 * Northbridge device is the node id + 24. 1060 */ 1061 data = pci_getb_func(0, node + 24, 3, 0x87); 1062 data &= 0xFC; 1063 pci_putb_func(0, node + 24, 3, 0x87, data); 1064 } 1065 opteron_workaround_6336786++; 1066 #endif /* __xpv */ 1067 } 1068 #else 1069 workaround_warning(cpu, 6336786); 1070 missing++; 1071 #endif 1072 } 1073 1074 /*LINTED*/ 1075 /* 1076 * Mutex primitives don't work as expected. 1077 */ 1078 if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 1079 #if defined(OPTERON_WORKAROUND_6323525) 1080 /* 1081 * This problem only occurs with 2 or more cores. If bit in 1082 * MSR_AMD_BU_CFG set, then not applicable. The workaround 1083 * is to patch the semaphone routines with the lfence 1084 * instruction to provide necessary load memory barrier with 1085 * possible subsequent read-modify-write ops. 1086 * 1087 * It is too early in boot to call the patch routine so 1088 * set erratum variable to be done in startup_end(). 1089 */ 1090 if (opteron_workaround_6323525) { 1091 opteron_workaround_6323525++; 1092 #if defined(__xpv) 1093 } else if (x86_feature & X86_SSE2) { 1094 if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1095 /* 1096 * XXPV Use dom0_msr here when extended 1097 * operations are supported? 1098 */ 1099 if (xpv_nr_phys_cpus() > 1) 1100 opteron_workaround_6323525++; 1101 } else { 1102 /* 1103 * We have no way to tell how many physical 1104 * cpus there are, or even if this processor 1105 * has the problem, so enable the workaround 1106 * unconditionally (at some performance cost). 1107 */ 1108 opteron_workaround_6323525++; 1109 } 1110 #else /* __xpv */ 1111 } else if ((x86_feature & X86_SSE2) && ((opteron_get_nnodes() * 1112 cpuid_get_ncpu_per_chip(cpu)) > 1)) { 1113 if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0) 1114 opteron_workaround_6323525++; 1115 #endif /* __xpv */ 1116 } 1117 #else 1118 workaround_warning(cpu, 6323525); 1119 missing++; 1120 #endif 1121 } 1122 1123 missing += do_erratum_298(cpu); 1124 1125 #ifdef __xpv 1126 return (0); 1127 #else 1128 return (missing); 1129 #endif 1130 } 1131 1132 void 1133 workaround_errata_end() 1134 { 1135 #if defined(OPTERON_ERRATUM_88) 1136 if (opteron_erratum_88) 1137 workaround_applied(88); 1138 #endif 1139 #if defined(OPTERON_ERRATUM_91) 1140 if (opteron_erratum_91) 1141 workaround_applied(91); 1142 #endif 1143 #if defined(OPTERON_ERRATUM_93) 1144 if (opteron_erratum_93) 1145 workaround_applied(93); 1146 #endif 1147 #if defined(OPTERON_ERRATUM_95) 1148 if (opteron_erratum_95) 1149 workaround_applied(95); 1150 #endif 1151 #if defined(OPTERON_ERRATUM_100) 1152 if (opteron_erratum_100) 1153 workaround_applied(100); 1154 #endif 1155 #if defined(OPTERON_ERRATUM_108) 1156 if (opteron_erratum_108) 1157 workaround_applied(108); 1158 #endif 1159 #if defined(OPTERON_ERRATUM_109) 1160 if (opteron_erratum_109) { 1161 cmn_err(CE_WARN, 1162 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1163 " processor\nerratum 109 was not detected; updating your" 1164 " system's BIOS to a version\ncontaining this" 1165 " microcode patch is HIGHLY recommended or erroneous" 1166 " system\noperation may occur.\n"); 1167 } 1168 #endif 1169 #if defined(OPTERON_ERRATUM_121) 1170 if (opteron_erratum_121) 1171 workaround_applied(121); 1172 #endif 1173 #if defined(OPTERON_ERRATUM_122) 1174 if (opteron_erratum_122) 1175 workaround_applied(122); 1176 #endif 1177 #if defined(OPTERON_ERRATUM_123) 1178 if (opteron_erratum_123) { 1179 cmn_err(CE_WARN, 1180 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1181 " processor\nerratum 123 was not detected; updating your" 1182 " system's BIOS to a version\ncontaining this" 1183 " microcode patch is HIGHLY recommended or erroneous" 1184 " system\noperation may occur.\n"); 1185 } 1186 #endif 1187 #if defined(OPTERON_ERRATUM_131) 1188 if (opteron_erratum_131) { 1189 cmn_err(CE_WARN, 1190 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1191 " processor\nerratum 131 was not detected; updating your" 1192 " system's BIOS to a version\ncontaining this" 1193 " microcode patch is HIGHLY recommended or erroneous" 1194 " system\noperation may occur.\n"); 1195 } 1196 #endif 1197 #if defined(OPTERON_WORKAROUND_6336786) 1198 if (opteron_workaround_6336786) 1199 workaround_applied(6336786); 1200 #endif 1201 #if defined(OPTERON_WORKAROUND_6323525) 1202 if (opteron_workaround_6323525) 1203 workaround_applied(6323525); 1204 #endif 1205 #if defined(OPTERON_ERRATUM_298) 1206 if (opteron_erratum_298) { 1207 cmn_err(CE_WARN, 1208 "BIOS microcode patch for AMD 64/Opteron(tm)" 1209 " processor\nerratum 298 was not detected; updating your" 1210 " system's BIOS to a version\ncontaining this" 1211 " microcode patch is HIGHLY recommended or erroneous" 1212 " system\noperation may occur.\n"); 1213 } 1214 #endif 1215 } 1216 1217 static cpuset_t procset; 1218 1219 /* 1220 * Start a single cpu, assuming that the kernel context is available 1221 * to successfully start another cpu. 1222 * 1223 * (For example, real mode code is mapped into the right place 1224 * in memory and is ready to be run.) 1225 */ 1226 int 1227 start_cpu(processorid_t who) 1228 { 1229 void *ctx; 1230 cpu_t *cp; 1231 int delays; 1232 int error = 0; 1233 1234 ASSERT(who != 0); 1235 1236 /* 1237 * Check if there's at least a Mbyte of kmem available 1238 * before attempting to start the cpu. 1239 */ 1240 if (kmem_avail() < 1024 * 1024) { 1241 /* 1242 * Kick off a reap in case that helps us with 1243 * later attempts .. 1244 */ 1245 kmem_reap(); 1246 return (ENOMEM); 1247 } 1248 1249 cp = mp_startup_init(who); 1250 if ((ctx = mach_cpucontext_alloc(cp)) == NULL || 1251 (error = mach_cpu_start(cp, ctx)) != 0) { 1252 1253 /* 1254 * Something went wrong before we even started it 1255 */ 1256 if (ctx) 1257 cmn_err(CE_WARN, 1258 "cpu%d: failed to start error %d", 1259 cp->cpu_id, error); 1260 else 1261 cmn_err(CE_WARN, 1262 "cpu%d: failed to allocate context", cp->cpu_id); 1263 1264 if (ctx) 1265 mach_cpucontext_free(cp, ctx, error); 1266 else 1267 error = EAGAIN; /* hmm. */ 1268 mp_startup_fini(cp, error); 1269 return (error); 1270 } 1271 1272 for (delays = 0; !CPU_IN_SET(procset, who); delays++) { 1273 if (delays == 500) { 1274 /* 1275 * After five seconds, things are probably looking 1276 * a bit bleak - explain the hang. 1277 */ 1278 cmn_err(CE_NOTE, "cpu%d: started, " 1279 "but not running in the kernel yet", who); 1280 } else if (delays > 2000) { 1281 /* 1282 * We waited at least 20 seconds, bail .. 1283 */ 1284 error = ETIMEDOUT; 1285 cmn_err(CE_WARN, "cpu%d: timed out", who); 1286 mach_cpucontext_free(cp, ctx, error); 1287 mp_startup_fini(cp, error); 1288 return (error); 1289 } 1290 1291 /* 1292 * wait at least 10ms, then check again.. 1293 */ 1294 delay(USEC_TO_TICK_ROUNDUP(10000)); 1295 } 1296 1297 mach_cpucontext_free(cp, ctx, 0); 1298 1299 #ifndef __xpv 1300 if (tsc_gethrtime_enable) 1301 tsc_sync_master(who); 1302 #endif 1303 1304 if (dtrace_cpu_init != NULL) { 1305 /* 1306 * DTrace CPU initialization expects cpu_lock to be held. 1307 */ 1308 mutex_enter(&cpu_lock); 1309 (*dtrace_cpu_init)(who); 1310 mutex_exit(&cpu_lock); 1311 } 1312 1313 while (!CPU_IN_SET(cpu_ready_set, who)) 1314 delay(1); 1315 1316 return (0); 1317 } 1318 1319 1320 /*ARGSUSED*/ 1321 void 1322 start_other_cpus(int cprboot) 1323 { 1324 uint_t who; 1325 uint_t skipped = 0; 1326 uint_t bootcpuid = 0; 1327 1328 /* 1329 * Initialize our own cpu_info. 1330 */ 1331 init_cpu_info(CPU); 1332 1333 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr); 1334 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr); 1335 1336 /* 1337 * Initialize our syscall handlers 1338 */ 1339 init_cpu_syscall(CPU); 1340 1341 /* 1342 * Take the boot cpu out of the mp_cpus set because we know 1343 * it's already running. Add it to the cpu_ready_set for 1344 * precisely the same reason. 1345 */ 1346 CPUSET_DEL(mp_cpus, bootcpuid); 1347 CPUSET_ADD(cpu_ready_set, bootcpuid); 1348 1349 /* 1350 * if only 1 cpu or not using MP, skip the rest of this 1351 */ 1352 if (CPUSET_ISNULL(mp_cpus) || use_mp == 0) { 1353 if (use_mp == 0) 1354 cmn_err(CE_CONT, "?***** Not in MP mode\n"); 1355 goto done; 1356 } 1357 1358 /* 1359 * perform such initialization as is needed 1360 * to be able to take CPUs on- and off-line. 1361 */ 1362 cpu_pause_init(); 1363 1364 xc_init_cpu(CPU); /* initialize processor crosscalls */ 1365 1366 if (mach_cpucontext_init() != 0) 1367 goto done; 1368 1369 flushes_require_xcalls = 1; 1370 1371 /* 1372 * We lock our affinity to the master CPU to ensure that all slave CPUs 1373 * do their TSC syncs with the same CPU. 1374 */ 1375 affinity_set(CPU_CURRENT); 1376 1377 for (who = 0; who < NCPU; who++) { 1378 1379 if (!CPU_IN_SET(mp_cpus, who)) 1380 continue; 1381 ASSERT(who != bootcpuid); 1382 if (ncpus >= max_ncpus) { 1383 skipped = who; 1384 continue; 1385 } 1386 if (start_cpu(who) != 0) 1387 CPUSET_DEL(mp_cpus, who); 1388 1389 mutex_enter(&cpu_lock); 1390 cpu_state_change_notify(who, CPU_SETUP); 1391 mutex_exit(&cpu_lock); 1392 } 1393 1394 /* Free the space allocated to hold the microcode file */ 1395 ucode_cleanup(); 1396 1397 affinity_clear(); 1398 1399 if (skipped) { 1400 cmn_err(CE_NOTE, 1401 "System detected %d cpus, but " 1402 "only %d cpu(s) were enabled during boot.", 1403 skipped + 1, ncpus); 1404 cmn_err(CE_NOTE, 1405 "Use \"boot-ncpus\" parameter to enable more CPU(s). " 1406 "See eeprom(1M)."); 1407 } 1408 1409 done: 1410 if (get_hwenv() == HW_NATIVE) 1411 workaround_errata_end(); 1412 mach_cpucontext_fini(); 1413 1414 cmi_post_mpstartup(); 1415 } 1416 1417 /* 1418 * Dummy functions - no i86pc platforms support dynamic cpu allocation. 1419 */ 1420 /*ARGSUSED*/ 1421 int 1422 mp_cpu_configure(int cpuid) 1423 { 1424 return (ENOTSUP); /* not supported */ 1425 } 1426 1427 /*ARGSUSED*/ 1428 int 1429 mp_cpu_unconfigure(int cpuid) 1430 { 1431 return (ENOTSUP); /* not supported */ 1432 } 1433 1434 /* 1435 * Startup function for 'other' CPUs (besides boot cpu). 1436 * Called from real_mode_start. 1437 * 1438 * WARNING: until CPU_READY is set, mp_startup and routines called by 1439 * mp_startup should not call routines (e.g. kmem_free) that could call 1440 * hat_unload which requires CPU_READY to be set. 1441 */ 1442 void 1443 mp_startup(void) 1444 { 1445 struct cpu *cp = CPU; 1446 uint_t new_x86_feature; 1447 extern void cpu_event_init_cpu(cpu_t *); 1448 #ifndef __xpv 1449 extern void cpupm_init(cpu_t *); 1450 #endif 1451 const char *fmt = "?cpu%d: %b\n"; 1452 1453 /* 1454 * We need to get TSC on this proc synced (i.e., any delta 1455 * from cpu0 accounted for) as soon as we can, because many 1456 * many things use gethrtime/pc_gethrestime, including 1457 * interrupts, cmn_err, etc. 1458 */ 1459 1460 /* Let cpu0 continue into tsc_sync_master() */ 1461 CPUSET_ATOMIC_ADD(procset, cp->cpu_id); 1462 1463 #ifndef __xpv 1464 if (tsc_gethrtime_enable) 1465 tsc_sync_slave(); 1466 #endif 1467 1468 /* 1469 * Once this was done from assembly, but it's safer here; if 1470 * it blocks, we need to be able to swtch() to and from, and 1471 * since we get here by calling t_pc, we need to do that call 1472 * before swtch() overwrites it. 1473 */ 1474 (void) (*ap_mlsetup)(); 1475 1476 new_x86_feature = cpuid_pass1(cp); 1477 1478 #ifndef __xpv 1479 /* 1480 * Program this cpu's PAT 1481 */ 1482 if (x86_feature & X86_PAT) 1483 pat_sync(); 1484 #endif 1485 1486 /* 1487 * Set up TSC_AUX to contain the cpuid for this processor 1488 * for the rdtscp instruction. 1489 */ 1490 if (x86_feature & X86_TSCP) 1491 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1492 1493 /* 1494 * Initialize this CPU's syscall handlers 1495 */ 1496 init_cpu_syscall(cp); 1497 1498 /* 1499 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 1500 * highest level at which a routine is permitted to block on 1501 * an adaptive mutex (allows for cpu poke interrupt in case 1502 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 1503 * device interrupts that may end up in the hat layer issuing cross 1504 * calls before CPU_READY is set. 1505 */ 1506 splx(ipltospl(LOCK_LEVEL)); 1507 sti(); 1508 1509 /* 1510 * Do a sanity check to make sure this new CPU is a sane thing 1511 * to add to the collection of processors running this system. 1512 * 1513 * XXX Clearly this needs to get more sophisticated, if x86 1514 * systems start to get built out of heterogenous CPUs; as is 1515 * likely to happen once the number of processors in a configuration 1516 * gets large enough. 1517 */ 1518 if ((x86_feature & new_x86_feature) != x86_feature) { 1519 cmn_err(CE_CONT, fmt, cp->cpu_id, new_x86_feature, 1520 FMT_X86_FEATURE); 1521 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 1522 } 1523 1524 /* 1525 * We do not support cpus with mixed monitor/mwait support if the 1526 * boot cpu supports monitor/mwait. 1527 */ 1528 if ((x86_feature & ~new_x86_feature) & X86_MWAIT) 1529 panic("unsupported mixed cpu monitor/mwait support detected"); 1530 1531 /* 1532 * We could be more sophisticated here, and just mark the CPU 1533 * as "faulted" but at this point we'll opt for the easier 1534 * answer of dying horribly. Provided the boot cpu is ok, 1535 * the system can be recovered by booting with use_mp set to zero. 1536 */ 1537 if (workaround_errata(cp) != 0) 1538 panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 1539 1540 cpuid_pass2(cp); 1541 cpuid_pass3(cp); 1542 (void) cpuid_pass4(cp); 1543 1544 init_cpu_info(cp); 1545 1546 mutex_enter(&cpu_lock); 1547 1548 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS; 1549 1550 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 1551 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 1552 1553 if (dtrace_cpu_init != NULL) { 1554 (*dtrace_cpu_init)(cp->cpu_id); 1555 } 1556 1557 /* 1558 * Fill out cpu_ucode_info. Update microcode if necessary. 1559 */ 1560 ucode_check(cp); 1561 1562 mutex_exit(&cpu_lock); 1563 1564 post_startup_cpu_fixups(); 1565 1566 /* 1567 * Enable preemption here so that contention for any locks acquired 1568 * later in mp_startup may be preempted if the thread owning those 1569 * locks is continuously executing on other CPUs (for example, this 1570 * CPU must be preemptible to allow other CPUs to pause it during their 1571 * startup phases). It's safe to enable preemption here because the 1572 * CPU state is pretty-much fully constructed. 1573 */ 1574 curthread->t_preempt = 0; 1575 1576 /* The base spl should still be at LOCK LEVEL here */ 1577 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1578 set_base_spl(); /* Restore the spl to its proper value */ 1579 1580 cpu_event_init_cpu(cp); 1581 #ifndef __xpv 1582 cpupm_init(cp); 1583 #endif 1584 1585 /* 1586 * Processor group initialization for this CPU is dependent on the 1587 * cpuid probing, which must be done in the context of the current 1588 * CPU, as well as the CPU's device node initialization (for ACPI). 1589 */ 1590 mutex_enter(&cpu_lock); 1591 pghw_physid_create(cp); 1592 (void) pg_cpu_init(cp, B_FALSE); 1593 pg_cmt_cpu_startup(cp); 1594 mutex_exit(&cpu_lock); 1595 1596 /* Enable interrupts */ 1597 (void) spl0(); 1598 1599 mutex_enter(&cpu_lock); 1600 cpu_enable_intr(cp); 1601 cpu_add_active(cp); 1602 mutex_exit(&cpu_lock); 1603 1604 #ifndef __xpv 1605 { 1606 /* 1607 * Set up the CPU module for this CPU. This can't be done 1608 * before this CPU is made CPU_READY, because we may (in 1609 * heterogeneous systems) need to go load another CPU module. 1610 * The act of attempting to load a module may trigger a 1611 * cross-call, which will ASSERT unless this cpu is CPU_READY. 1612 */ 1613 cmi_hdl_t hdl; 1614 1615 if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), 1616 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) { 1617 if (x86_feature & X86_MCA) 1618 cmi_mca_init(hdl); 1619 } 1620 } 1621 #endif /* __xpv */ 1622 1623 if (boothowto & RB_DEBUG) 1624 kdi_cpu_init(); 1625 1626 /* 1627 * Setting the bit in cpu_ready_set must be the last operation in 1628 * processor initialization; the boot CPU will continue to boot once 1629 * it sees this bit set for all active CPUs. 1630 */ 1631 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 1632 1633 /* 1634 * Because mp_startup() gets fired off after init() starts, we 1635 * can't use the '?' trick to do 'boot -v' printing - so we 1636 * always direct the 'cpu .. online' messages to the log. 1637 */ 1638 cmn_err(CE_CONT, "!cpu%d initialization complete - online\n", 1639 cp->cpu_id); 1640 1641 (void) mach_cpu_create_device_node(cp, NULL); 1642 1643 /* 1644 * Now we are done with the startup thread, so free it up. 1645 */ 1646 thread_exit(); 1647 panic("mp_startup: cannot return"); 1648 /*NOTREACHED*/ 1649 } 1650 1651 1652 /* 1653 * Start CPU on user request. 1654 */ 1655 /* ARGSUSED */ 1656 int 1657 mp_cpu_start(struct cpu *cp) 1658 { 1659 ASSERT(MUTEX_HELD(&cpu_lock)); 1660 return (0); 1661 } 1662 1663 /* 1664 * Stop CPU on user request. 1665 */ 1666 /* ARGSUSED */ 1667 int 1668 mp_cpu_stop(struct cpu *cp) 1669 { 1670 extern int cbe_psm_timer_mode; 1671 ASSERT(MUTEX_HELD(&cpu_lock)); 1672 1673 #ifdef __xpv 1674 /* 1675 * We can't offline vcpu0. 1676 */ 1677 if (cp->cpu_id == 0) 1678 return (EBUSY); 1679 #endif 1680 1681 /* 1682 * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1683 * can't stop it. (This is true only for machines with no TSC.) 1684 */ 1685 1686 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1687 return (EBUSY); 1688 1689 return (0); 1690 } 1691 1692 /* 1693 * Take the specified CPU out of participation in interrupts. 1694 */ 1695 int 1696 cpu_disable_intr(struct cpu *cp) 1697 { 1698 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 1699 return (EBUSY); 1700 1701 cp->cpu_flags &= ~CPU_ENABLE; 1702 return (0); 1703 } 1704 1705 /* 1706 * Allow the specified CPU to participate in interrupts. 1707 */ 1708 void 1709 cpu_enable_intr(struct cpu *cp) 1710 { 1711 ASSERT(MUTEX_HELD(&cpu_lock)); 1712 cp->cpu_flags |= CPU_ENABLE; 1713 psm_enable_intr(cp->cpu_id); 1714 } 1715 1716 1717 /*ARGSUSED*/ 1718 void 1719 mp_cpu_faulted_enter(struct cpu *cp) 1720 { 1721 #ifndef __xpv 1722 cmi_hdl_t hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1723 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1724 1725 if (hdl != NULL) { 1726 cmi_faulted_enter(hdl); 1727 cmi_hdl_rele(hdl); 1728 } 1729 #endif 1730 } 1731 1732 /*ARGSUSED*/ 1733 void 1734 mp_cpu_faulted_exit(struct cpu *cp) 1735 { 1736 #ifndef __xpv 1737 cmi_hdl_t hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1738 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1739 1740 if (hdl != NULL) { 1741 cmi_faulted_exit(hdl); 1742 cmi_hdl_rele(hdl); 1743 } 1744 #endif 1745 } 1746 1747 /* 1748 * The following two routines are used as context operators on threads belonging 1749 * to processes with a private LDT (see sysi86). Due to the rarity of such 1750 * processes, these routines are currently written for best code readability and 1751 * organization rather than speed. We could avoid checking x86_feature at every 1752 * context switch by installing different context ops, depending on the 1753 * x86_feature flags, at LDT creation time -- one for each combination of fast 1754 * syscall feature flags. 1755 */ 1756 1757 /*ARGSUSED*/ 1758 void 1759 cpu_fast_syscall_disable(void *arg) 1760 { 1761 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1762 cpu_sep_disable(); 1763 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1764 cpu_asysc_disable(); 1765 } 1766 1767 /*ARGSUSED*/ 1768 void 1769 cpu_fast_syscall_enable(void *arg) 1770 { 1771 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1772 cpu_sep_enable(); 1773 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1774 cpu_asysc_enable(); 1775 } 1776 1777 static void 1778 cpu_sep_enable(void) 1779 { 1780 ASSERT(x86_feature & X86_SEP); 1781 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1782 1783 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 1784 } 1785 1786 static void 1787 cpu_sep_disable(void) 1788 { 1789 ASSERT(x86_feature & X86_SEP); 1790 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1791 1792 /* 1793 * Setting the SYSENTER_CS_MSR register to 0 causes software executing 1794 * the sysenter or sysexit instruction to trigger a #gp fault. 1795 */ 1796 wrmsr(MSR_INTC_SEP_CS, 0); 1797 } 1798 1799 static void 1800 cpu_asysc_enable(void) 1801 { 1802 ASSERT(x86_feature & X86_ASYSC); 1803 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1804 1805 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 1806 (uint64_t)(uintptr_t)AMD_EFER_SCE); 1807 } 1808 1809 static void 1810 cpu_asysc_disable(void) 1811 { 1812 ASSERT(x86_feature & X86_ASYSC); 1813 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1814 1815 /* 1816 * Turn off the SCE (syscall enable) bit in the EFER register. Software 1817 * executing syscall or sysret with this bit off will incur a #ud trap. 1818 */ 1819 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 1820 ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 1821 } 1822