1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 30 #include <sys/types.h> 31 #include <sys/sysmacros.h> 32 #include <sys/disp.h> 33 #include <sys/promif.h> 34 #include <sys/clock.h> 35 #include <sys/cpuvar.h> 36 #include <sys/stack.h> 37 #include <vm/as.h> 38 #include <vm/hat.h> 39 #include <sys/reboot.h> 40 #include <sys/avintr.h> 41 #include <sys/vtrace.h> 42 #include <sys/proc.h> 43 #include <sys/thread.h> 44 #include <sys/cpupart.h> 45 #include <sys/pset.h> 46 #include <sys/copyops.h> 47 #include <sys/pg.h> 48 #include <sys/disp.h> 49 #include <sys/debug.h> 50 #include <sys/sunddi.h> 51 #include <sys/x86_archext.h> 52 #include <sys/privregs.h> 53 #include <sys/machsystm.h> 54 #include <sys/ontrap.h> 55 #include <sys/bootconf.h> 56 #include <sys/boot_console.h> 57 #include <sys/kdi_machimpl.h> 58 #include <sys/archsystm.h> 59 #include <sys/promif.h> 60 #include <sys/pci_cfgspace.h> 61 #ifdef __xpv 62 #include <sys/hypervisor.h> 63 #else 64 #include <sys/xpv_support.h> 65 #endif 66 67 /* 68 * some globals for patching the result of cpuid 69 * to solve problems w/ creative cpu vendors 70 */ 71 72 extern uint32_t cpuid_feature_ecx_include; 73 extern uint32_t cpuid_feature_ecx_exclude; 74 extern uint32_t cpuid_feature_edx_include; 75 extern uint32_t cpuid_feature_edx_exclude; 76 77 /* 78 * Dummy spl priority masks 79 */ 80 static unsigned char dummy_cpu_pri[MAXIPL + 1] = { 81 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 82 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf 83 }; 84 85 /* 86 * Set console mode 87 */ 88 static void 89 set_console_mode(uint8_t val) 90 { 91 struct bop_regs rp = {0}; 92 93 rp.eax.byte.ah = 0x0; 94 rp.eax.byte.al = val; 95 rp.ebx.word.bx = 0x0; 96 97 BOP_DOINT(bootops, 0x10, &rp); 98 } 99 100 101 /* 102 * Setup routine called right before main(). Interposing this function 103 * before main() allows us to call it in a machine-independent fashion. 104 */ 105 void 106 mlsetup(struct regs *rp) 107 { 108 u_longlong_t prop_value; 109 extern struct classfuncs sys_classfuncs; 110 extern disp_t cpu0_disp; 111 extern char t0stack[]; 112 extern int post_fastreboot; 113 extern int console; 114 extern uint64_t plat_dr_options; 115 116 ASSERT_STACK_ALIGNED(); 117 118 /* 119 * initialize cpu_self 120 */ 121 cpu[0]->cpu_self = cpu[0]; 122 123 #if defined(__xpv) 124 /* 125 * Point at the hypervisor's virtual cpu structure 126 */ 127 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0]; 128 #endif 129 130 /* 131 * Set up dummy cpu_pri_data values till psm spl code is 132 * installed. This allows splx() to work on amd64. 133 */ 134 135 cpu[0]->cpu_pri_data = dummy_cpu_pri; 136 137 /* 138 * check if we've got special bits to clear or set 139 * when checking cpu features 140 */ 141 142 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0) 143 cpuid_feature_ecx_include = 0; 144 else 145 cpuid_feature_ecx_include = (uint32_t)prop_value; 146 147 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0) 148 cpuid_feature_ecx_exclude = 0; 149 else 150 cpuid_feature_ecx_exclude = (uint32_t)prop_value; 151 152 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0) 153 cpuid_feature_edx_include = 0; 154 else 155 cpuid_feature_edx_include = (uint32_t)prop_value; 156 157 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0) 158 cpuid_feature_edx_exclude = 0; 159 else 160 cpuid_feature_edx_exclude = (uint32_t)prop_value; 161 162 /* 163 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss. 164 */ 165 init_desctbls(); 166 167 /* 168 * lgrp_init() and possibly cpuid_pass1() need PCI config 169 * space access 170 */ 171 #if defined(__xpv) 172 if (DOMAIN_IS_INITDOMAIN(xen_info)) 173 pci_cfgspace_init(); 174 #else 175 pci_cfgspace_init(); 176 #endif 177 178 /* 179 * The first lightweight pass (pass0) through the cpuid data 180 * was done in locore before mlsetup was called. Do the next 181 * pass in C code. 182 * 183 * The x86_feature bits are set here on the basis of the capabilities 184 * of the boot CPU. Note that if we choose to support CPUs that have 185 * different feature sets (at which point we would almost certainly 186 * want to set the feature bits to correspond to the feature 187 * minimum) this value may be altered. 188 */ 189 x86_feature = cpuid_pass1(cpu[0]); 190 191 #if !defined(__xpv) 192 193 if (get_hwenv() == HW_XEN_HVM) 194 xen_hvm_init(); 195 196 /* 197 * Patch the tsc_read routine with appropriate set of instructions, 198 * depending on the processor family and architecure, to read the 199 * time-stamp counter while ensuring no out-of-order execution. 200 * Patch it while the kernel text is still writable. 201 * 202 * Note: tsc_read is not patched for intel processors whose family 203 * is >6 and for amd whose family >f (in case they don't support rdtscp 204 * instruction, unlikely). By default tsc_read will use cpuid for 205 * serialization in such cases. The following code needs to be 206 * revisited if intel processors of family >= f retains the 207 * instruction serialization nature of mfence instruction. 208 * Note: tsc_read is not patched for x86 processors which do 209 * not support "mfence". By default tsc_read will use cpuid for 210 * serialization in such cases. 211 * 212 * The Xen hypervisor does not correctly report whether rdtscp is 213 * supported or not, so we must assume that it is not. 214 */ 215 if (get_hwenv() != HW_XEN_HVM && (x86_feature & X86_TSCP)) 216 patch_tsc_read(X86_HAVE_TSCP); 217 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD && 218 cpuid_getfamily(CPU) <= 0xf && (x86_feature & X86_SSE2) != 0) 219 patch_tsc_read(X86_TSC_MFENCE); 220 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel && 221 cpuid_getfamily(CPU) <= 6 && (x86_feature & X86_SSE2) != 0) 222 patch_tsc_read(X86_TSC_LFENCE); 223 224 #endif /* !__xpv */ 225 226 #if defined(__i386) && !defined(__xpv) 227 /* 228 * Some i386 processors do not implement the rdtsc instruction, 229 * or at least they do not implement it correctly. Patch them to 230 * return 0. 231 */ 232 if ((x86_feature & X86_TSC) == 0) 233 patch_tsc_read(X86_NO_TSC); 234 #endif /* __i386 && !__xpv */ 235 236 #if defined(__amd64) && !defined(__xpv) 237 patch_memops(cpuid_getvendor(CPU)); 238 #endif /* __amd64 && !__xpv */ 239 240 #if !defined(__xpv) 241 /* XXPV what, if anything, should be dorked with here under xen? */ 242 243 /* 244 * While we're thinking about the TSC, let's set up %cr4 so that 245 * userland can issue rdtsc, and initialize the TSC_AUX value 246 * (the cpuid) for the rdtscp instruction on appropriately 247 * capable hardware. 248 */ 249 if (x86_feature & X86_TSC) 250 setcr4(getcr4() & ~CR4_TSD); 251 252 if (x86_feature & X86_TSCP) 253 (void) wrmsr(MSR_AMD_TSCAUX, 0); 254 255 if (x86_feature & X86_DE) 256 setcr4(getcr4() | CR4_DE); 257 #endif /* __xpv */ 258 259 /* 260 * initialize t0 261 */ 262 t0.t_stk = (caddr_t)rp - MINFRAME; 263 t0.t_stkbase = t0stack; 264 t0.t_pri = maxclsyspri - 3; 265 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP; 266 t0.t_procp = &p0; 267 t0.t_plockp = &p0lock.pl_lock; 268 t0.t_lwp = &lwp0; 269 t0.t_forw = &t0; 270 t0.t_back = &t0; 271 t0.t_next = &t0; 272 t0.t_prev = &t0; 273 t0.t_cpu = cpu[0]; 274 t0.t_disp_queue = &cpu0_disp; 275 t0.t_bind_cpu = PBIND_NONE; 276 t0.t_bind_pset = PS_NONE; 277 t0.t_bindflag = (uchar_t)default_binding_mode; 278 t0.t_cpupart = &cp_default; 279 t0.t_clfuncs = &sys_classfuncs.thread; 280 t0.t_copyops = NULL; 281 THREAD_ONPROC(&t0, CPU); 282 283 lwp0.lwp_thread = &t0; 284 lwp0.lwp_regs = (void *)rp; 285 lwp0.lwp_procp = &p0; 286 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1; 287 288 p0.p_exec = NULL; 289 p0.p_stat = SRUN; 290 p0.p_flag = SSYS; 291 p0.p_tlist = &t0; 292 p0.p_stksize = 2*PAGESIZE; 293 p0.p_stkpageszc = 0; 294 p0.p_as = &kas; 295 p0.p_lockp = &p0lock; 296 p0.p_brkpageszc = 0; 297 p0.p_t1_lgrpid = LGRP_NONE; 298 p0.p_tr_lgrpid = LGRP_NONE; 299 sigorset(&p0.p_ignore, &ignoredefault); 300 301 CPU->cpu_thread = &t0; 302 bzero(&cpu0_disp, sizeof (disp_t)); 303 CPU->cpu_disp = &cpu0_disp; 304 CPU->cpu_disp->disp_cpu = CPU; 305 CPU->cpu_dispthread = &t0; 306 CPU->cpu_idle_thread = &t0; 307 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE; 308 CPU->cpu_dispatch_pri = t0.t_pri; 309 310 CPU->cpu_id = 0; 311 312 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */ 313 314 /* 315 * The kernel doesn't use LDTs unless a process explicitly requests one. 316 */ 317 p0.p_ldt_desc = null_sdesc; 318 319 /* 320 * Initialize thread/cpu microstate accounting 321 */ 322 init_mstate(&t0, LMS_SYSTEM); 323 init_cpu_mstate(CPU, CMS_SYSTEM); 324 325 /* 326 * Initialize lists of available and active CPUs. 327 */ 328 cpu_list_init(CPU); 329 330 pg_cpu_bootstrap(CPU); 331 332 /* 333 * Now that we have taken over the GDT, IDT and have initialized 334 * active CPU list it's time to inform kmdb if present. 335 */ 336 if (boothowto & RB_DEBUG) 337 kdi_idt_sync(); 338 339 /* 340 * Explicitly set console to text mode (0x3) if this is a boot 341 * post Fast Reboot, and the console is set to CONS_SCREEN_TEXT. 342 */ 343 if (post_fastreboot && console == CONS_SCREEN_TEXT) 344 set_console_mode(0x3); 345 346 /* 347 * If requested (boot -d) drop into kmdb. 348 * 349 * This must be done after cpu_list_init() on the 64-bit kernel 350 * since taking a trap requires that we re-compute gsbase based 351 * on the cpu list. 352 */ 353 if (boothowto & RB_DEBUGENTER) 354 kmdb_enter(); 355 356 cpu_vm_data_init(CPU); 357 358 rp->r_fp = 0; /* terminate kernel stack traces! */ 359 360 prom_init("kernel", (void *)NULL); 361 362 /* User-set option overrides firmware value. */ 363 if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) { 364 plat_dr_options = (uint64_t)prop_value; 365 } 366 #if defined(__xpv) 367 /* No support of DR operations on xpv */ 368 plat_dr_options = 0; 369 #else /* __xpv */ 370 /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */ 371 plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED; 372 #ifndef __amd64 373 /* Only enable CPU/memory DR on 64 bits kernel. */ 374 plat_dr_options &= ~PLAT_DR_FEATURE_MEMORY; 375 plat_dr_options &= ~PLAT_DR_FEATURE_CPU; 376 #endif /* __amd64 */ 377 #endif /* __xpv */ 378 379 /* 380 * Get value of "plat_dr_physmax" boot option. 381 * It overrides values calculated from MSCT or SRAT table. 382 */ 383 if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) { 384 plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT; 385 } 386 387 /* Get value of boot_ncpus. */ 388 if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) { 389 boot_ncpus = NCPU; 390 } else { 391 boot_ncpus = (int)prop_value; 392 if (boot_ncpus <= 0 || boot_ncpus > NCPU) 393 boot_ncpus = NCPU; 394 } 395 396 /* 397 * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't 398 * support CPU DR operations. 399 */ 400 if (plat_dr_support_cpu() == 0) { 401 max_ncpus = boot_max_ncpus = boot_ncpus; 402 } else { 403 if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) { 404 max_ncpus = NCPU; 405 } else { 406 max_ncpus = (int)prop_value; 407 if (max_ncpus <= 0 || max_ncpus > NCPU) { 408 max_ncpus = NCPU; 409 } 410 if (boot_ncpus > max_ncpus) { 411 boot_ncpus = max_ncpus; 412 } 413 } 414 415 if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) { 416 boot_max_ncpus = boot_ncpus; 417 } else { 418 boot_max_ncpus = (int)prop_value; 419 if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) { 420 boot_max_ncpus = boot_ncpus; 421 } else if (boot_max_ncpus > max_ncpus) { 422 boot_max_ncpus = max_ncpus; 423 } 424 } 425 } 426 427 /* 428 * Initialize the lgrp framework 429 */ 430 lgrp_init(LGRP_INIT_STAGE1); 431 432 if (boothowto & RB_HALT) { 433 prom_printf("unix: kernel halted by -h flag\n"); 434 prom_enter_mon(); 435 } 436 437 ASSERT_STACK_ALIGNED(); 438 439 /* 440 * Fill out cpu_ucode_info. Update microcode if necessary. 441 */ 442 ucode_check(CPU); 443 444 if (workaround_errata(CPU) != 0) 445 panic("critical workaround(s) missing for boot cpu"); 446 } 447 448 449 void 450 mach_modpath(char *path, const char *filename) 451 { 452 /* 453 * Construct the directory path from the filename. 454 */ 455 456 int len; 457 char *p; 458 const char isastr[] = "/amd64"; 459 size_t isalen = strlen(isastr); 460 461 if ((p = strrchr(filename, '/')) == NULL) 462 return; 463 464 while (p > filename && *(p - 1) == '/') 465 p--; /* remove trailing '/' characters */ 466 if (p == filename) 467 p++; /* so "/" -is- the modpath in this case */ 468 469 /* 470 * Remove optional isa-dependent directory name - the module 471 * subsystem will put this back again (!) 472 */ 473 len = p - filename; 474 if (len > isalen && 475 strncmp(&filename[len - isalen], isastr, isalen) == 0) 476 p -= isalen; 477 478 /* 479 * "/platform/mumblefrotz" + " " + MOD_DEFPATH 480 */ 481 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1; 482 (void) strncpy(path, filename, p - filename); 483 } 484