1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/x86_archext.h> 27 #include <sys/machsystm.h> 28 #include <sys/x_call.h> 29 #include <sys/acpi/acpi.h> 30 #include <sys/acpica.h> 31 #include <sys/pwrnow.h> 32 #include <sys/cpu_acpi.h> 33 #include <sys/cpupm.h> 34 #include <sys/dtrace.h> 35 #include <sys/sdt.h> 36 37 static int pwrnow_init(cpu_t *); 38 static void pwrnow_fini(cpu_t *); 39 static void pwrnow_power(cpuset_t, uint32_t); 40 static void pwrnow_stop(cpu_t *); 41 42 /* 43 * Interfaces for modules implementing AMD's PowerNow!. 44 */ 45 cpupm_state_ops_t pwrnow_ops = { 46 "PowerNow! Technology", 47 pwrnow_init, 48 pwrnow_fini, 49 pwrnow_power, 50 pwrnow_stop 51 }; 52 53 /* 54 * Error returns 55 */ 56 #define PWRNOW_RET_SUCCESS 0x00 57 #define PWRNOW_RET_NO_PM 0x01 58 #define PWRNOW_RET_UNSUP_STATE 0x02 59 #define PWRNOW_RET_TRANS_INCOMPLETE 0x03 60 61 #define PWRNOW_LATENCY_WAIT 10 62 63 /* 64 * MSR registers for changing and reading processor power state. 65 */ 66 #define PWRNOW_PERF_CTL_MSR 0xC0010062 67 #define PWRNOW_PERF_STATUS_MSR 0xC0010063 68 69 #define AMD_CPUID_PSTATE_HARDWARE (1<<7) 70 #define AMD_CPUID_TSC_CONSTANT (1<<8) 71 72 /* 73 * Debugging support 74 */ 75 #ifdef DEBUG 76 volatile int pwrnow_debug = 0; 77 #define PWRNOW_DEBUG(arglist) if (pwrnow_debug) printf arglist; 78 #else 79 #define PWRNOW_DEBUG(arglist) 80 #endif 81 82 /* 83 * Write the ctrl register. 84 */ 85 static void 86 write_ctrl(cpu_acpi_handle_t handle, uint32_t ctrl) 87 { 88 cpu_acpi_pct_t *pct_ctrl; 89 uint64_t reg; 90 91 pct_ctrl = CPU_ACPI_PCT_CTRL(handle); 92 93 switch (pct_ctrl->cr_addrspace_id) { 94 case ACPI_ADR_SPACE_FIXED_HARDWARE: 95 reg = ctrl; 96 wrmsr(PWRNOW_PERF_CTL_MSR, reg); 97 break; 98 99 default: 100 DTRACE_PROBE1(pwrnow_ctrl_unsupported_type, uint8_t, 101 pct_ctrl->cr_addrspace_id); 102 return; 103 } 104 105 DTRACE_PROBE1(pwrnow_ctrl_write, uint32_t, ctrl); 106 } 107 108 /* 109 * Transition the current processor to the requested state. 110 */ 111 static void 112 pwrnow_pstate_transition(uint32_t req_state) 113 { 114 cpupm_mach_state_t *mach_state = 115 (cpupm_mach_state_t *)CPU->cpu_m.mcpu_pm_mach_state; 116 cpu_acpi_handle_t handle = mach_state->ms_acpi_handle; 117 cpu_acpi_pstate_t *req_pstate; 118 uint32_t ctrl; 119 120 req_pstate = (cpu_acpi_pstate_t *)CPU_ACPI_PSTATES(handle); 121 req_pstate += req_state; 122 123 DTRACE_PROBE1(pwrnow_transition_freq, uint32_t, 124 CPU_ACPI_FREQ(req_pstate)); 125 126 /* 127 * Initiate the processor p-state change. 128 */ 129 ctrl = CPU_ACPI_PSTATE_CTRL(req_pstate); 130 write_ctrl(handle, ctrl); 131 132 mach_state->ms_pstate.cma_state.pstate = req_state; 133 cpu_set_curr_clock((uint64_t)CPU_ACPI_FREQ(req_pstate) * 1000000); 134 } 135 136 static void 137 pwrnow_power(cpuset_t set, uint32_t req_state) 138 { 139 /* 140 * If thread is already running on target CPU then just 141 * make the transition request. Otherwise, we'll need to 142 * make a cross-call. 143 */ 144 kpreempt_disable(); 145 if (CPU_IN_SET(set, CPU->cpu_id)) { 146 pwrnow_pstate_transition(req_state); 147 CPUSET_DEL(set, CPU->cpu_id); 148 } 149 if (!CPUSET_ISNULL(set)) { 150 xc_call((xc_arg_t)req_state, NULL, NULL, 151 CPUSET2BV(set), (xc_func_t)pwrnow_pstate_transition); 152 } 153 kpreempt_enable(); 154 } 155 156 /* 157 * Validate that this processor supports PowerNow! and if so, 158 * get the P-state data from ACPI and cache it. 159 */ 160 static int 161 pwrnow_init(cpu_t *cp) 162 { 163 cpupm_mach_state_t *mach_state = 164 (cpupm_mach_state_t *)cp->cpu_m.mcpu_pm_mach_state; 165 cpu_acpi_handle_t handle = mach_state->ms_acpi_handle; 166 cpu_acpi_pct_t *pct_stat; 167 168 PWRNOW_DEBUG(("pwrnow_init: processor %d\n", cp->cpu_id)); 169 170 /* 171 * Cache the P-state specific ACPI data. 172 */ 173 if (cpu_acpi_cache_pstate_data(handle) != 0) { 174 cmn_err(CE_NOTE, "!PowerNow! support is being " 175 "disabled due to errors parsing ACPI P-state objects " 176 "exported by BIOS."); 177 pwrnow_fini(cp); 178 return (PWRNOW_RET_NO_PM); 179 } 180 181 pct_stat = CPU_ACPI_PCT_STATUS(handle); 182 switch (pct_stat->cr_addrspace_id) { 183 case ACPI_ADR_SPACE_FIXED_HARDWARE: 184 PWRNOW_DEBUG(("Transitions will use fixed hardware\n")); 185 break; 186 default: 187 cmn_err(CE_WARN, "!_PCT configured for unsupported " 188 "addrspace = %d.", pct_stat->cr_addrspace_id); 189 cmn_err(CE_NOTE, "!CPU power management will not function."); 190 pwrnow_fini(cp); 191 return (PWRNOW_RET_NO_PM); 192 } 193 194 cpupm_alloc_domains(cp, CPUPM_P_STATES); 195 196 PWRNOW_DEBUG(("Processor %d succeeded.\n", cp->cpu_id)) 197 return (PWRNOW_RET_SUCCESS); 198 } 199 200 /* 201 * Free resources allocated by pwrnow_init(). 202 */ 203 static void 204 pwrnow_fini(cpu_t *cp) 205 { 206 cpupm_mach_state_t *mach_state = 207 (cpupm_mach_state_t *)(cp->cpu_m.mcpu_pm_mach_state); 208 cpu_acpi_handle_t handle = mach_state->ms_acpi_handle; 209 210 cpupm_free_domains(&cpupm_pstate_domains); 211 cpu_acpi_free_pstate_data(handle); 212 } 213 214 boolean_t 215 pwrnow_supported() 216 { 217 struct cpuid_regs cpu_regs; 218 219 /* Required features */ 220 if (!(x86_feature & X86_CPUID) || 221 !(x86_feature & X86_MSR)) { 222 PWRNOW_DEBUG(("No CPUID or MSR support.")); 223 return (B_FALSE); 224 } 225 226 /* 227 * Get the Advanced Power Management Information. 228 */ 229 cpu_regs.cp_eax = 0x80000007; 230 (void) __cpuid_insn(&cpu_regs); 231 232 /* 233 * We currently only support CPU power management of 234 * processors that are P-state TSC invariant 235 */ 236 if (!(cpu_regs.cp_edx & AMD_CPUID_TSC_CONSTANT)) { 237 PWRNOW_DEBUG(("No support for CPUs that are not P-state " 238 "TSC invariant.\n")); 239 return (B_FALSE); 240 } 241 242 /* 243 * We only support the "Fire and Forget" style of PowerNow! (i.e., 244 * single MSR write to change speed). 245 */ 246 if (!(cpu_regs.cp_edx & AMD_CPUID_PSTATE_HARDWARE)) { 247 PWRNOW_DEBUG(("Hardware P-State control is not supported.\n")); 248 return (B_FALSE); 249 } 250 return (B_TRUE); 251 } 252 253 static void 254 pwrnow_stop(cpu_t *cp) 255 { 256 cpupm_mach_state_t *mach_state = 257 (cpupm_mach_state_t *)(cp->cpu_m.mcpu_pm_mach_state); 258 cpu_acpi_handle_t handle = mach_state->ms_acpi_handle; 259 260 cpupm_remove_domains(cp, CPUPM_P_STATES, &cpupm_pstate_domains); 261 cpu_acpi_free_pstate_data(handle); 262 } 263