1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Various routines to handle identification 30 * and classification of x86 processors. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/archsystm.h> 35 #include <sys/x86_archext.h> 36 #include <sys/kmem.h> 37 #include <sys/systm.h> 38 #include <sys/cmn_err.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/cpuvar.h> 42 #include <sys/processor.h> 43 #include <sys/sysmacros.h> 44 #include <sys/pg.h> 45 #include <sys/fp.h> 46 #include <sys/controlregs.h> 47 #include <sys/auxv_386.h> 48 #include <sys/bitmap.h> 49 #include <sys/memnode.h> 50 51 /* 52 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 53 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 54 * them accordingly. For most modern processors, feature detection occurs here 55 * in pass 1. 56 * 57 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 58 * for the boot CPU and does the basic analysis that the early kernel needs. 59 * x86_feature is set based on the return value of cpuid_pass1() of the boot 60 * CPU. 61 * 62 * Pass 1 includes: 63 * 64 * o Determining vendor/model/family/stepping and setting x86_type and 65 * x86_vendor accordingly. 66 * o Processing the feature flags returned by the cpuid instruction while 67 * applying any workarounds or tricks for the specific processor. 68 * o Mapping the feature flags into Solaris feature bits (X86_*). 69 * o Processing extended feature flags if supported by the processor, 70 * again while applying specific processor knowledge. 71 * o Determining the CMT characteristics of the system. 72 * 73 * Pass 1 is done on non-boot CPUs during their initialization and the results 74 * are used only as a meager attempt at ensuring that all processors within the 75 * system support the same features. 76 * 77 * Pass 2 of cpuid feature analysis happens just at the beginning 78 * of startup(). It just copies in and corrects the remainder 79 * of the cpuid data we depend on: standard cpuid functions that we didn't 80 * need for pass1 feature analysis, and extended cpuid functions beyond the 81 * simple feature processing done in pass1. 82 * 83 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 84 * particular kernel memory allocation has been made available. It creates a 85 * readable brand string based on the data collected in the first two passes. 86 * 87 * Pass 4 of cpuid analysis is invoked after post_startup() when all 88 * the support infrastructure for various hardware features has been 89 * initialized. It determines which processor features will be reported 90 * to userland via the aux vector. 91 * 92 * All passes are executed on all CPUs, but only the boot CPU determines what 93 * features the kernel will use. 94 * 95 * Much of the worst junk in this file is for the support of processors 96 * that didn't really implement the cpuid instruction properly. 97 * 98 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 99 * the pass numbers. Accordingly, changes to the pass code may require changes 100 * to the accessor code. 101 */ 102 103 uint_t x86_feature = 0; 104 uint_t x86_vendor = X86_VENDOR_IntelClone; 105 uint_t x86_type = X86_TYPE_OTHER; 106 107 uint_t pentiumpro_bug4046376; 108 uint_t pentiumpro_bug4064495; 109 110 uint_t enable486; 111 112 /* 113 * This set of strings are for processors rumored to support the cpuid 114 * instruction, and is used by locore.s to figure out how to set x86_vendor 115 */ 116 const char CyrixInstead[] = "CyrixInstead"; 117 118 /* 119 * monitor/mwait info. 120 * 121 * size_actual and buf_actual are the real address and size allocated to get 122 * proper mwait_buf alignement. buf_actual and size_actual should be passed 123 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use 124 * processor cache-line alignment, but this is not guarantied in the furture. 125 */ 126 struct mwait_info { 127 size_t mon_min; /* min size to avoid missed wakeups */ 128 size_t mon_max; /* size to avoid false wakeups */ 129 size_t size_actual; /* size actually allocated */ 130 void *buf_actual; /* memory actually allocated */ 131 uint32_t support; /* processor support of monitor/mwait */ 132 }; 133 134 /* 135 * These constants determine how many of the elements of the 136 * cpuid we cache in the cpuid_info data structure; the 137 * remaining elements are accessible via the cpuid instruction. 138 */ 139 140 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 141 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 142 143 struct cpuid_info { 144 uint_t cpi_pass; /* last pass completed */ 145 /* 146 * standard function information 147 */ 148 uint_t cpi_maxeax; /* fn 0: %eax */ 149 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 150 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 151 152 uint_t cpi_family; /* fn 1: extended family */ 153 uint_t cpi_model; /* fn 1: extended model */ 154 uint_t cpi_step; /* fn 1: stepping */ 155 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 156 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 157 int cpi_clogid; /* fn 1: %ebx: thread # */ 158 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 159 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 160 uint_t cpi_ncache; /* fn 2: number of elements */ 161 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 162 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 163 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 164 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 165 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 166 /* 167 * extended function information 168 */ 169 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 170 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 171 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 172 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 173 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 174 id_t cpi_coreid; 175 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 176 /* Intel: fn 4: %eax[31-26] */ 177 /* 178 * supported feature information 179 */ 180 uint32_t cpi_support[5]; 181 #define STD_EDX_FEATURES 0 182 #define AMD_EDX_FEATURES 1 183 #define TM_EDX_FEATURES 2 184 #define STD_ECX_FEATURES 3 185 #define AMD_ECX_FEATURES 4 186 /* 187 * Synthesized information, where known. 188 */ 189 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 190 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 191 uint32_t cpi_socket; /* Chip package/socket type */ 192 193 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 194 }; 195 196 197 static struct cpuid_info cpuid_info0; 198 199 /* 200 * These bit fields are defined by the Intel Application Note AP-485 201 * "Intel Processor Identification and the CPUID Instruction" 202 */ 203 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 204 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 205 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 206 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 207 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 208 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 209 210 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 211 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 212 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 213 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 214 215 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 216 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 217 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 218 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 219 220 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 221 #define CPI_XMAXEAX_MAX 0x80000100 222 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 223 224 /* 225 * Function 4 (Deterministic Cache Parameters) macros 226 * Defined by Intel Application Note AP-485 227 */ 228 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 229 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 230 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 231 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 232 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 233 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 234 235 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 236 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 237 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 238 239 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 240 241 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 242 243 244 /* 245 * A couple of shorthand macros to identify "later" P6-family chips 246 * like the Pentium M and Core. First, the "older" P6-based stuff 247 * (loosely defined as "pre-Pentium-4"): 248 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 249 */ 250 251 #define IS_LEGACY_P6(cpi) ( \ 252 cpi->cpi_family == 6 && \ 253 (cpi->cpi_model == 1 || \ 254 cpi->cpi_model == 3 || \ 255 cpi->cpi_model == 5 || \ 256 cpi->cpi_model == 6 || \ 257 cpi->cpi_model == 7 || \ 258 cpi->cpi_model == 8 || \ 259 cpi->cpi_model == 0xA || \ 260 cpi->cpi_model == 0xB) \ 261 ) 262 263 /* A "new F6" is everything with family 6 that's not the above */ 264 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 265 266 /* Extended family/model support */ 267 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ 268 cpi->cpi_family >= 0xf) 269 270 /* 271 * AMD family 0xf and family 0x10 socket types. 272 * First index : 273 * 0 for family 0xf, revs B thru E 274 * 1 for family 0xf, revs F and G 275 * 2 for family 0x10, rev B 276 * Second index by (model & 0x3) 277 */ 278 static uint32_t amd_skts[3][4] = { 279 /* 280 * Family 0xf revisions B through E 281 */ 282 #define A_SKTS_0 0 283 { 284 X86_SOCKET_754, /* 0b00 */ 285 X86_SOCKET_940, /* 0b01 */ 286 X86_SOCKET_754, /* 0b10 */ 287 X86_SOCKET_939 /* 0b11 */ 288 }, 289 /* 290 * Family 0xf revisions F and G 291 */ 292 #define A_SKTS_1 1 293 { 294 X86_SOCKET_S1g1, /* 0b00 */ 295 X86_SOCKET_F1207, /* 0b01 */ 296 X86_SOCKET_UNKNOWN, /* 0b10 */ 297 X86_SOCKET_AM2 /* 0b11 */ 298 }, 299 /* 300 * Family 0x10 revisions A and B 301 * It is not clear whether, as new sockets release, that 302 * model & 0x3 will id socket for this family 303 */ 304 #define A_SKTS_2 2 305 { 306 X86_SOCKET_F1207, /* 0b00 */ 307 X86_SOCKET_F1207, /* 0b01 */ 308 X86_SOCKET_F1207, /* 0b10 */ 309 X86_SOCKET_F1207, /* 0b11 */ 310 } 311 }; 312 313 /* 314 * Table for mapping AMD Family 0xf and AMD Family 0x10 model/stepping 315 * combination to chip "revision" and socket type. 316 * 317 * The first member of this array that matches a given family, extended model 318 * plus model range, and stepping range will be considered a match. 319 */ 320 static const struct amd_rev_mapent { 321 uint_t rm_family; 322 uint_t rm_modello; 323 uint_t rm_modelhi; 324 uint_t rm_steplo; 325 uint_t rm_stephi; 326 uint32_t rm_chiprev; 327 const char *rm_chiprevstr; 328 int rm_sktidx; 329 } amd_revmap[] = { 330 /* 331 * =============== AuthenticAMD Family 0xf =============== 332 */ 333 334 /* 335 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1. 336 */ 337 { 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 }, 338 { 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 }, 339 /* 340 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8 341 */ 342 { 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", A_SKTS_0 }, 343 /* 344 * Rev CG is the rest of extended model 0x0 - i.e., everything 345 * but the rev B and C0 combinations covered above. 346 */ 347 { 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", A_SKTS_0 }, 348 /* 349 * Rev D has extended model 0x1. 350 */ 351 { 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", A_SKTS_0 }, 352 /* 353 * Rev E has extended model 0x2. 354 * Extended model 0x3 is unused but available to grow into. 355 */ 356 { 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", A_SKTS_0 }, 357 /* 358 * Rev F has extended models 0x4 and 0x5. 359 */ 360 { 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", A_SKTS_1 }, 361 /* 362 * Rev G has extended model 0x6. 363 */ 364 { 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", A_SKTS_1 }, 365 366 /* 367 * =============== AuthenticAMD Family 0x10 =============== 368 */ 369 370 /* 371 * Rev A has model 0 and stepping 0/1/2 for DR-{A0,A1,A2}. 372 * Give all of model 0 stepping range to rev A. 373 */ 374 { 0x10, 0x00, 0x00, 0x0, 0x2, X86_CHIPREV_AMD_10_REV_A, "A", A_SKTS_2 }, 375 376 /* 377 * Rev B has model 2 and steppings 0/1/0xa/2 for DR-{B0,B1,BA,B2}. 378 * Give all of model 2 stepping range to rev B. 379 */ 380 { 0x10, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_10_REV_B, "B", A_SKTS_2 }, 381 }; 382 383 /* 384 * Info for monitor/mwait idle loop. 385 * 386 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 387 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 388 * 2006. 389 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 390 * Documentation Updates" #33633, Rev 2.05, December 2006. 391 */ 392 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 393 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 394 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 395 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 396 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 397 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 398 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 399 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 400 /* 401 * Number of sub-cstates for a given c-state. 402 */ 403 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 404 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 405 406 static void intel_cpuid_4_cache_info(void *, struct cpuid_info *); 407 408 static void 409 synth_amd_info(struct cpuid_info *cpi) 410 { 411 const struct amd_rev_mapent *rmp; 412 uint_t family, model, step; 413 int i; 414 415 /* 416 * Currently only AMD family 0xf and family 0x10 use these fields. 417 */ 418 if (cpi->cpi_family != 0xf && cpi->cpi_family != 0x10) 419 return; 420 421 family = cpi->cpi_family; 422 model = cpi->cpi_model; 423 step = cpi->cpi_step; 424 425 for (i = 0, rmp = amd_revmap; i < sizeof (amd_revmap) / sizeof (*rmp); 426 i++, rmp++) { 427 if (family == rmp->rm_family && 428 model >= rmp->rm_modello && model <= rmp->rm_modelhi && 429 step >= rmp->rm_steplo && step <= rmp->rm_stephi) { 430 cpi->cpi_chiprev = rmp->rm_chiprev; 431 cpi->cpi_chiprevstr = rmp->rm_chiprevstr; 432 cpi->cpi_socket = amd_skts[rmp->rm_sktidx][model & 0x3]; 433 return; 434 } 435 } 436 } 437 438 static void 439 synth_info(struct cpuid_info *cpi) 440 { 441 cpi->cpi_chiprev = X86_CHIPREV_UNKNOWN; 442 cpi->cpi_chiprevstr = "Unknown"; 443 cpi->cpi_socket = X86_SOCKET_UNKNOWN; 444 445 switch (cpi->cpi_vendor) { 446 case X86_VENDOR_AMD: 447 synth_amd_info(cpi); 448 break; 449 450 default: 451 break; 452 453 } 454 } 455 456 /* 457 * Apply up various platform-dependent restrictions where the 458 * underlying platform restrictions mean the CPU can be marked 459 * as less capable than its cpuid instruction would imply. 460 */ 461 #if defined(__xpv) 462 static void 463 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) 464 { 465 switch (eax) { 466 case 1: 467 cp->cp_edx &= 468 ~(CPUID_INTC_EDX_PSE | 469 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 470 CPUID_INTC_EDX_MCA | /* XXPV true on dom0? */ 471 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | 472 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | 473 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 474 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); 475 break; 476 477 case 0x80000001: 478 cp->cp_edx &= 479 ~(CPUID_AMD_EDX_PSE | 480 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 481 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | 482 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | 483 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 484 CPUID_AMD_EDX_TSCP); 485 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; 486 break; 487 default: 488 break; 489 } 490 491 switch (vendor) { 492 case X86_VENDOR_Intel: 493 switch (eax) { 494 case 4: 495 /* 496 * Zero out the (ncores-per-chip - 1) field 497 */ 498 cp->cp_eax &= 0x03fffffff; 499 break; 500 default: 501 break; 502 } 503 break; 504 case X86_VENDOR_AMD: 505 switch (eax) { 506 case 0x80000008: 507 /* 508 * Zero out the (ncores-per-chip - 1) field 509 */ 510 cp->cp_ecx &= 0xffffff00; 511 break; 512 default: 513 break; 514 } 515 break; 516 default: 517 break; 518 } 519 } 520 #else 521 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 522 #endif 523 524 /* 525 * Some undocumented ways of patching the results of the cpuid 526 * instruction to permit running Solaris 10 on future cpus that 527 * we don't currently support. Could be set to non-zero values 528 * via settings in eeprom. 529 */ 530 531 uint32_t cpuid_feature_ecx_include; 532 uint32_t cpuid_feature_ecx_exclude; 533 uint32_t cpuid_feature_edx_include; 534 uint32_t cpuid_feature_edx_exclude; 535 536 void 537 cpuid_alloc_space(cpu_t *cpu) 538 { 539 /* 540 * By convention, cpu0 is the boot cpu, which is set up 541 * before memory allocation is available. All other cpus get 542 * their cpuid_info struct allocated here. 543 */ 544 ASSERT(cpu->cpu_id != 0); 545 cpu->cpu_m.mcpu_cpi = 546 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 547 } 548 549 void 550 cpuid_free_space(cpu_t *cpu) 551 { 552 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 553 int i; 554 555 ASSERT(cpu->cpu_id != 0); 556 557 /* 558 * Free up any function 4 related dynamic storage 559 */ 560 for (i = 1; i < cpi->cpi_std_4_size; i++) 561 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 562 if (cpi->cpi_std_4_size > 0) 563 kmem_free(cpi->cpi_std_4, 564 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 565 566 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); 567 } 568 569 uint_t 570 cpuid_pass1(cpu_t *cpu) 571 { 572 uint32_t mask_ecx, mask_edx; 573 uint_t feature = X86_CPUID; 574 struct cpuid_info *cpi; 575 struct cpuid_regs *cp; 576 int xcpuid; 577 #if !defined(__xpv) 578 extern int idle_cpu_prefer_mwait; 579 #endif 580 581 /* 582 * Space statically allocated for cpu0, ensure pointer is set 583 */ 584 if (cpu->cpu_id == 0) 585 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 586 cpi = cpu->cpu_m.mcpu_cpi; 587 ASSERT(cpi != NULL); 588 cp = &cpi->cpi_std[0]; 589 cp->cp_eax = 0; 590 cpi->cpi_maxeax = __cpuid_insn(cp); 591 { 592 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 593 *iptr++ = cp->cp_ebx; 594 *iptr++ = cp->cp_edx; 595 *iptr++ = cp->cp_ecx; 596 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 597 } 598 599 /* 600 * Map the vendor string to a type code 601 */ 602 if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0) 603 cpi->cpi_vendor = X86_VENDOR_Intel; 604 else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0) 605 cpi->cpi_vendor = X86_VENDOR_AMD; 606 else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0) 607 cpi->cpi_vendor = X86_VENDOR_TM; 608 else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0) 609 /* 610 * CyrixInstead is a variable used by the Cyrix detection code 611 * in locore. 612 */ 613 cpi->cpi_vendor = X86_VENDOR_Cyrix; 614 else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0) 615 cpi->cpi_vendor = X86_VENDOR_UMC; 616 else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0) 617 cpi->cpi_vendor = X86_VENDOR_NexGen; 618 else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0) 619 cpi->cpi_vendor = X86_VENDOR_Centaur; 620 else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0) 621 cpi->cpi_vendor = X86_VENDOR_Rise; 622 else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0) 623 cpi->cpi_vendor = X86_VENDOR_SiS; 624 else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0) 625 cpi->cpi_vendor = X86_VENDOR_NSC; 626 else 627 cpi->cpi_vendor = X86_VENDOR_IntelClone; 628 629 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 630 631 /* 632 * Limit the range in case of weird hardware 633 */ 634 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 635 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 636 if (cpi->cpi_maxeax < 1) 637 goto pass1_done; 638 639 cp = &cpi->cpi_std[1]; 640 cp->cp_eax = 1; 641 (void) __cpuid_insn(cp); 642 643 /* 644 * Extract identifying constants for easy access. 645 */ 646 cpi->cpi_model = CPI_MODEL(cpi); 647 cpi->cpi_family = CPI_FAMILY(cpi); 648 649 if (cpi->cpi_family == 0xf) 650 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 651 652 /* 653 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 654 * Intel, and presumably everyone else, uses model == 0xf, as 655 * one would expect (max value means possible overflow). Sigh. 656 */ 657 658 switch (cpi->cpi_vendor) { 659 case X86_VENDOR_Intel: 660 if (IS_EXTENDED_MODEL_INTEL(cpi)) 661 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 662 break; 663 case X86_VENDOR_AMD: 664 if (CPI_FAMILY(cpi) == 0xf) 665 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 666 break; 667 default: 668 if (cpi->cpi_model == 0xf) 669 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 670 break; 671 } 672 673 cpi->cpi_step = CPI_STEP(cpi); 674 cpi->cpi_brandid = CPI_BRANDID(cpi); 675 676 /* 677 * *default* assumptions: 678 * - believe %edx feature word 679 * - ignore %ecx feature word 680 * - 32-bit virtual and physical addressing 681 */ 682 mask_edx = 0xffffffff; 683 mask_ecx = 0; 684 685 cpi->cpi_pabits = cpi->cpi_vabits = 32; 686 687 switch (cpi->cpi_vendor) { 688 case X86_VENDOR_Intel: 689 if (cpi->cpi_family == 5) 690 x86_type = X86_TYPE_P5; 691 else if (IS_LEGACY_P6(cpi)) { 692 x86_type = X86_TYPE_P6; 693 pentiumpro_bug4046376 = 1; 694 pentiumpro_bug4064495 = 1; 695 /* 696 * Clear the SEP bit when it was set erroneously 697 */ 698 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 699 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 700 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 701 x86_type = X86_TYPE_P4; 702 /* 703 * We don't currently depend on any of the %ecx 704 * features until Prescott, so we'll only check 705 * this from P4 onwards. We might want to revisit 706 * that idea later. 707 */ 708 mask_ecx = 0xffffffff; 709 } else if (cpi->cpi_family > 0xf) 710 mask_ecx = 0xffffffff; 711 /* 712 * We don't support MONITOR/MWAIT if leaf 5 is not available 713 * to obtain the monitor linesize. 714 */ 715 if (cpi->cpi_maxeax < 5) 716 mask_ecx &= ~CPUID_INTC_ECX_MON; 717 break; 718 case X86_VENDOR_IntelClone: 719 default: 720 break; 721 case X86_VENDOR_AMD: 722 #if defined(OPTERON_ERRATUM_108) 723 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 724 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 725 cpi->cpi_model = 0xc; 726 } else 727 #endif 728 if (cpi->cpi_family == 5) { 729 /* 730 * AMD K5 and K6 731 * 732 * These CPUs have an incomplete implementation 733 * of MCA/MCE which we mask away. 734 */ 735 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 736 737 /* 738 * Model 0 uses the wrong (APIC) bit 739 * to indicate PGE. Fix it here. 740 */ 741 if (cpi->cpi_model == 0) { 742 if (cp->cp_edx & 0x200) { 743 cp->cp_edx &= ~0x200; 744 cp->cp_edx |= CPUID_INTC_EDX_PGE; 745 } 746 } 747 748 /* 749 * Early models had problems w/ MMX; disable. 750 */ 751 if (cpi->cpi_model < 6) 752 mask_edx &= ~CPUID_INTC_EDX_MMX; 753 } 754 755 /* 756 * For newer families, SSE3 and CX16, at least, are valid; 757 * enable all 758 */ 759 if (cpi->cpi_family >= 0xf) 760 mask_ecx = 0xffffffff; 761 /* 762 * We don't support MONITOR/MWAIT if leaf 5 is not available 763 * to obtain the monitor linesize. 764 */ 765 if (cpi->cpi_maxeax < 5) 766 mask_ecx &= ~CPUID_INTC_ECX_MON; 767 768 #if !defined(__xpv) 769 /* 770 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD 771 * processors. AMD does not intend MWAIT to be used in the cpu 772 * idle loop on current and future processors. 10h and future 773 * AMD processors use more power in MWAIT than HLT. 774 * Pre-family-10h Opterons do not have the MWAIT instruction. 775 */ 776 idle_cpu_prefer_mwait = 0; 777 #endif 778 779 break; 780 case X86_VENDOR_TM: 781 /* 782 * workaround the NT workaround in CMS 4.1 783 */ 784 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 785 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 786 cp->cp_edx |= CPUID_INTC_EDX_CX8; 787 break; 788 case X86_VENDOR_Centaur: 789 /* 790 * workaround the NT workarounds again 791 */ 792 if (cpi->cpi_family == 6) 793 cp->cp_edx |= CPUID_INTC_EDX_CX8; 794 break; 795 case X86_VENDOR_Cyrix: 796 /* 797 * We rely heavily on the probing in locore 798 * to actually figure out what parts, if any, 799 * of the Cyrix cpuid instruction to believe. 800 */ 801 switch (x86_type) { 802 case X86_TYPE_CYRIX_486: 803 mask_edx = 0; 804 break; 805 case X86_TYPE_CYRIX_6x86: 806 mask_edx = 0; 807 break; 808 case X86_TYPE_CYRIX_6x86L: 809 mask_edx = 810 CPUID_INTC_EDX_DE | 811 CPUID_INTC_EDX_CX8; 812 break; 813 case X86_TYPE_CYRIX_6x86MX: 814 mask_edx = 815 CPUID_INTC_EDX_DE | 816 CPUID_INTC_EDX_MSR | 817 CPUID_INTC_EDX_CX8 | 818 CPUID_INTC_EDX_PGE | 819 CPUID_INTC_EDX_CMOV | 820 CPUID_INTC_EDX_MMX; 821 break; 822 case X86_TYPE_CYRIX_GXm: 823 mask_edx = 824 CPUID_INTC_EDX_MSR | 825 CPUID_INTC_EDX_CX8 | 826 CPUID_INTC_EDX_CMOV | 827 CPUID_INTC_EDX_MMX; 828 break; 829 case X86_TYPE_CYRIX_MediaGX: 830 break; 831 case X86_TYPE_CYRIX_MII: 832 case X86_TYPE_VIA_CYRIX_III: 833 mask_edx = 834 CPUID_INTC_EDX_DE | 835 CPUID_INTC_EDX_TSC | 836 CPUID_INTC_EDX_MSR | 837 CPUID_INTC_EDX_CX8 | 838 CPUID_INTC_EDX_PGE | 839 CPUID_INTC_EDX_CMOV | 840 CPUID_INTC_EDX_MMX; 841 break; 842 default: 843 break; 844 } 845 break; 846 } 847 848 #if defined(__xpv) 849 /* 850 * Do not support MONITOR/MWAIT under a hypervisor 851 */ 852 mask_ecx &= ~CPUID_INTC_ECX_MON; 853 #endif /* __xpv */ 854 855 /* 856 * Now we've figured out the masks that determine 857 * which bits we choose to believe, apply the masks 858 * to the feature words, then map the kernel's view 859 * of these feature words into its feature word. 860 */ 861 cp->cp_edx &= mask_edx; 862 cp->cp_ecx &= mask_ecx; 863 864 /* 865 * apply any platform restrictions (we don't call this 866 * immediately after __cpuid_insn here, because we need the 867 * workarounds applied above first) 868 */ 869 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 870 871 /* 872 * fold in overrides from the "eeprom" mechanism 873 */ 874 cp->cp_edx |= cpuid_feature_edx_include; 875 cp->cp_edx &= ~cpuid_feature_edx_exclude; 876 877 cp->cp_ecx |= cpuid_feature_ecx_include; 878 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 879 880 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 881 feature |= X86_LARGEPAGE; 882 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 883 feature |= X86_TSC; 884 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 885 feature |= X86_MSR; 886 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 887 feature |= X86_MTRR; 888 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 889 feature |= X86_PGE; 890 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 891 feature |= X86_CMOV; 892 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 893 feature |= X86_MMX; 894 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 895 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 896 feature |= X86_MCA; 897 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 898 feature |= X86_PAE; 899 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 900 feature |= X86_CX8; 901 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 902 feature |= X86_CX16; 903 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 904 feature |= X86_PAT; 905 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 906 feature |= X86_SEP; 907 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 908 /* 909 * In our implementation, fxsave/fxrstor 910 * are prerequisites before we'll even 911 * try and do SSE things. 912 */ 913 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 914 feature |= X86_SSE; 915 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 916 feature |= X86_SSE2; 917 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 918 feature |= X86_SSE3; 919 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 920 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) 921 feature |= X86_SSSE3; 922 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) 923 feature |= X86_SSE4_1; 924 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) 925 feature |= X86_SSE4_2; 926 } 927 } 928 if (cp->cp_edx & CPUID_INTC_EDX_DE) 929 feature |= X86_DE; 930 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 931 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 932 feature |= X86_MWAIT; 933 } 934 935 if (feature & X86_PAE) 936 cpi->cpi_pabits = 36; 937 938 /* 939 * Hyperthreading configuration is slightly tricky on Intel 940 * and pure clones, and even trickier on AMD. 941 * 942 * (AMD chose to set the HTT bit on their CMP processors, 943 * even though they're not actually hyperthreaded. Thus it 944 * takes a bit more work to figure out what's really going 945 * on ... see the handling of the CMP_LGCY bit below) 946 */ 947 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 948 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 949 if (cpi->cpi_ncpu_per_chip > 1) 950 feature |= X86_HTT; 951 } else { 952 cpi->cpi_ncpu_per_chip = 1; 953 } 954 955 /* 956 * Work on the "extended" feature information, doing 957 * some basic initialization for cpuid_pass2() 958 */ 959 xcpuid = 0; 960 switch (cpi->cpi_vendor) { 961 case X86_VENDOR_Intel: 962 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 963 xcpuid++; 964 break; 965 case X86_VENDOR_AMD: 966 if (cpi->cpi_family > 5 || 967 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 968 xcpuid++; 969 break; 970 case X86_VENDOR_Cyrix: 971 /* 972 * Only these Cyrix CPUs are -known- to support 973 * extended cpuid operations. 974 */ 975 if (x86_type == X86_TYPE_VIA_CYRIX_III || 976 x86_type == X86_TYPE_CYRIX_GXm) 977 xcpuid++; 978 break; 979 case X86_VENDOR_Centaur: 980 case X86_VENDOR_TM: 981 default: 982 xcpuid++; 983 break; 984 } 985 986 if (xcpuid) { 987 cp = &cpi->cpi_extd[0]; 988 cp->cp_eax = 0x80000000; 989 cpi->cpi_xmaxeax = __cpuid_insn(cp); 990 } 991 992 if (cpi->cpi_xmaxeax & 0x80000000) { 993 994 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 995 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 996 997 switch (cpi->cpi_vendor) { 998 case X86_VENDOR_Intel: 999 case X86_VENDOR_AMD: 1000 if (cpi->cpi_xmaxeax < 0x80000001) 1001 break; 1002 cp = &cpi->cpi_extd[1]; 1003 cp->cp_eax = 0x80000001; 1004 (void) __cpuid_insn(cp); 1005 1006 if (cpi->cpi_vendor == X86_VENDOR_AMD && 1007 cpi->cpi_family == 5 && 1008 cpi->cpi_model == 6 && 1009 cpi->cpi_step == 6) { 1010 /* 1011 * K6 model 6 uses bit 10 to indicate SYSC 1012 * Later models use bit 11. Fix it here. 1013 */ 1014 if (cp->cp_edx & 0x400) { 1015 cp->cp_edx &= ~0x400; 1016 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 1017 } 1018 } 1019 1020 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 1021 1022 /* 1023 * Compute the additions to the kernel's feature word. 1024 */ 1025 if (cp->cp_edx & CPUID_AMD_EDX_NX) 1026 feature |= X86_NX; 1027 1028 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 1029 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 1030 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) 1031 feature |= X86_SSE4A; 1032 1033 /* 1034 * If both the HTT and CMP_LGCY bits are set, 1035 * then we're not actually HyperThreaded. Read 1036 * "AMD CPUID Specification" for more details. 1037 */ 1038 if (cpi->cpi_vendor == X86_VENDOR_AMD && 1039 (feature & X86_HTT) && 1040 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 1041 feature &= ~X86_HTT; 1042 feature |= X86_CMP; 1043 } 1044 #if defined(__amd64) 1045 /* 1046 * It's really tricky to support syscall/sysret in 1047 * the i386 kernel; we rely on sysenter/sysexit 1048 * instead. In the amd64 kernel, things are -way- 1049 * better. 1050 */ 1051 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 1052 feature |= X86_ASYSC; 1053 1054 /* 1055 * While we're thinking about system calls, note 1056 * that AMD processors don't support sysenter 1057 * in long mode at all, so don't try to program them. 1058 */ 1059 if (x86_vendor == X86_VENDOR_AMD) 1060 feature &= ~X86_SEP; 1061 #endif 1062 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) 1063 feature |= X86_TSCP; 1064 break; 1065 default: 1066 break; 1067 } 1068 1069 /* 1070 * Get CPUID data about processor cores and hyperthreads. 1071 */ 1072 switch (cpi->cpi_vendor) { 1073 case X86_VENDOR_Intel: 1074 if (cpi->cpi_maxeax >= 4) { 1075 cp = &cpi->cpi_std[4]; 1076 cp->cp_eax = 4; 1077 cp->cp_ecx = 0; 1078 (void) __cpuid_insn(cp); 1079 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 1080 } 1081 /*FALLTHROUGH*/ 1082 case X86_VENDOR_AMD: 1083 if (cpi->cpi_xmaxeax < 0x80000008) 1084 break; 1085 cp = &cpi->cpi_extd[8]; 1086 cp->cp_eax = 0x80000008; 1087 (void) __cpuid_insn(cp); 1088 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 1089 1090 /* 1091 * Virtual and physical address limits from 1092 * cpuid override previously guessed values. 1093 */ 1094 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 1095 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 1096 break; 1097 default: 1098 break; 1099 } 1100 1101 /* 1102 * Derive the number of cores per chip 1103 */ 1104 switch (cpi->cpi_vendor) { 1105 case X86_VENDOR_Intel: 1106 if (cpi->cpi_maxeax < 4) { 1107 cpi->cpi_ncore_per_chip = 1; 1108 break; 1109 } else { 1110 cpi->cpi_ncore_per_chip = 1111 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 1112 } 1113 break; 1114 case X86_VENDOR_AMD: 1115 if (cpi->cpi_xmaxeax < 0x80000008) { 1116 cpi->cpi_ncore_per_chip = 1; 1117 break; 1118 } else { 1119 cpi->cpi_ncore_per_chip = 1120 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 1121 } 1122 break; 1123 default: 1124 cpi->cpi_ncore_per_chip = 1; 1125 break; 1126 } 1127 } else { 1128 cpi->cpi_ncore_per_chip = 1; 1129 } 1130 1131 /* 1132 * If more than one core, then this processor is CMP. 1133 */ 1134 if (cpi->cpi_ncore_per_chip > 1) 1135 feature |= X86_CMP; 1136 1137 /* 1138 * If the number of cores is the same as the number 1139 * of CPUs, then we cannot have HyperThreading. 1140 */ 1141 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 1142 feature &= ~X86_HTT; 1143 1144 if ((feature & (X86_HTT | X86_CMP)) == 0) { 1145 /* 1146 * Single-core single-threaded processors. 1147 */ 1148 cpi->cpi_chipid = -1; 1149 cpi->cpi_clogid = 0; 1150 cpi->cpi_coreid = cpu->cpu_id; 1151 } else if (cpi->cpi_ncpu_per_chip > 1) { 1152 uint_t i; 1153 uint_t chipid_shift = 0; 1154 uint_t coreid_shift = 0; 1155 uint_t apic_id = CPI_APIC_ID(cpi); 1156 1157 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 1158 chipid_shift++; 1159 cpi->cpi_chipid = apic_id >> chipid_shift; 1160 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 1161 1162 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 1163 if (feature & X86_CMP) { 1164 /* 1165 * Multi-core (and possibly multi-threaded) 1166 * processors. 1167 */ 1168 uint_t ncpu_per_core; 1169 if (cpi->cpi_ncore_per_chip == 1) 1170 ncpu_per_core = cpi->cpi_ncpu_per_chip; 1171 else if (cpi->cpi_ncore_per_chip > 1) 1172 ncpu_per_core = cpi->cpi_ncpu_per_chip / 1173 cpi->cpi_ncore_per_chip; 1174 /* 1175 * 8bit APIC IDs on dual core Pentiums 1176 * look like this: 1177 * 1178 * +-----------------------+------+------+ 1179 * | Physical Package ID | MC | HT | 1180 * +-----------------------+------+------+ 1181 * <------- chipid --------> 1182 * <------- coreid ---------------> 1183 * <--- clogid --> 1184 * 1185 * Where the number of bits necessary to 1186 * represent MC and HT fields together equals 1187 * to the minimum number of bits necessary to 1188 * store the value of cpi->cpi_ncpu_per_chip. 1189 * Of those bits, the MC part uses the number 1190 * of bits necessary to store the value of 1191 * cpi->cpi_ncore_per_chip. 1192 */ 1193 for (i = 1; i < ncpu_per_core; i <<= 1) 1194 coreid_shift++; 1195 cpi->cpi_coreid = apic_id >> coreid_shift; 1196 } else if (feature & X86_HTT) { 1197 /* 1198 * Single-core multi-threaded processors. 1199 */ 1200 cpi->cpi_coreid = cpi->cpi_chipid; 1201 } 1202 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 1203 /* 1204 * AMD currently only has dual-core processors with 1205 * single-threaded cores. If they ever release 1206 * multi-threaded processors, then this code 1207 * will have to be updated. 1208 */ 1209 cpi->cpi_coreid = cpu->cpu_id; 1210 } else { 1211 /* 1212 * All other processors are currently 1213 * assumed to have single cores. 1214 */ 1215 cpi->cpi_coreid = cpi->cpi_chipid; 1216 } 1217 } 1218 1219 /* 1220 * Synthesize chip "revision" and socket type 1221 */ 1222 synth_info(cpi); 1223 1224 pass1_done: 1225 cpi->cpi_pass = 1; 1226 return (feature); 1227 } 1228 1229 /* 1230 * Make copies of the cpuid table entries we depend on, in 1231 * part for ease of parsing now, in part so that we have only 1232 * one place to correct any of it, in part for ease of 1233 * later export to userland, and in part so we can look at 1234 * this stuff in a crash dump. 1235 */ 1236 1237 /*ARGSUSED*/ 1238 void 1239 cpuid_pass2(cpu_t *cpu) 1240 { 1241 uint_t n, nmax; 1242 int i; 1243 struct cpuid_regs *cp; 1244 uint8_t *dp; 1245 uint32_t *iptr; 1246 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1247 1248 ASSERT(cpi->cpi_pass == 1); 1249 1250 if (cpi->cpi_maxeax < 1) 1251 goto pass2_done; 1252 1253 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1254 nmax = NMAX_CPI_STD; 1255 /* 1256 * (We already handled n == 0 and n == 1 in pass 1) 1257 */ 1258 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1259 cp->cp_eax = n; 1260 1261 /* 1262 * CPUID function 4 expects %ecx to be initialized 1263 * with an index which indicates which cache to return 1264 * information about. The OS is expected to call function 4 1265 * with %ecx set to 0, 1, 2, ... until it returns with 1266 * EAX[4:0] set to 0, which indicates there are no more 1267 * caches. 1268 * 1269 * Here, populate cpi_std[4] with the information returned by 1270 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1271 * when dynamic memory allocation becomes available. 1272 * 1273 * Note: we need to explicitly initialize %ecx here, since 1274 * function 4 may have been previously invoked. 1275 */ 1276 if (n == 4) 1277 cp->cp_ecx = 0; 1278 1279 (void) __cpuid_insn(cp); 1280 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1281 switch (n) { 1282 case 2: 1283 /* 1284 * "the lower 8 bits of the %eax register 1285 * contain a value that identifies the number 1286 * of times the cpuid [instruction] has to be 1287 * executed to obtain a complete image of the 1288 * processor's caching systems." 1289 * 1290 * How *do* they make this stuff up? 1291 */ 1292 cpi->cpi_ncache = sizeof (*cp) * 1293 BITX(cp->cp_eax, 7, 0); 1294 if (cpi->cpi_ncache == 0) 1295 break; 1296 cpi->cpi_ncache--; /* skip count byte */ 1297 1298 /* 1299 * Well, for now, rather than attempt to implement 1300 * this slightly dubious algorithm, we just look 1301 * at the first 15 .. 1302 */ 1303 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1304 cpi->cpi_ncache = sizeof (*cp) - 1; 1305 1306 dp = cpi->cpi_cacheinfo; 1307 if (BITX(cp->cp_eax, 31, 31) == 0) { 1308 uint8_t *p = (void *)&cp->cp_eax; 1309 for (i = 1; i < 3; i++) 1310 if (p[i] != 0) 1311 *dp++ = p[i]; 1312 } 1313 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1314 uint8_t *p = (void *)&cp->cp_ebx; 1315 for (i = 0; i < 4; i++) 1316 if (p[i] != 0) 1317 *dp++ = p[i]; 1318 } 1319 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1320 uint8_t *p = (void *)&cp->cp_ecx; 1321 for (i = 0; i < 4; i++) 1322 if (p[i] != 0) 1323 *dp++ = p[i]; 1324 } 1325 if (BITX(cp->cp_edx, 31, 31) == 0) { 1326 uint8_t *p = (void *)&cp->cp_edx; 1327 for (i = 0; i < 4; i++) 1328 if (p[i] != 0) 1329 *dp++ = p[i]; 1330 } 1331 break; 1332 1333 case 3: /* Processor serial number, if PSN supported */ 1334 break; 1335 1336 case 4: /* Deterministic cache parameters */ 1337 break; 1338 1339 case 5: /* Monitor/Mwait parameters */ 1340 { 1341 size_t mwait_size; 1342 1343 /* 1344 * check cpi_mwait.support which was set in cpuid_pass1 1345 */ 1346 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1347 break; 1348 1349 /* 1350 * Protect ourself from insane mwait line size. 1351 * Workaround for incomplete hardware emulator(s). 1352 */ 1353 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); 1354 if (mwait_size < sizeof (uint32_t) || 1355 !ISP2(mwait_size)) { 1356 #if DEBUG 1357 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " 1358 "size %ld", 1359 cpu->cpu_id, (long)mwait_size); 1360 #endif 1361 break; 1362 } 1363 1364 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1365 cpi->cpi_mwait.mon_max = mwait_size; 1366 if (MWAIT_EXTENSION(cpi)) { 1367 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1368 if (MWAIT_INT_ENABLE(cpi)) 1369 cpi->cpi_mwait.support |= 1370 MWAIT_ECX_INT_ENABLE; 1371 } 1372 break; 1373 } 1374 default: 1375 break; 1376 } 1377 } 1378 1379 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 1380 goto pass2_done; 1381 1382 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 1383 nmax = NMAX_CPI_EXTD; 1384 /* 1385 * Copy the extended properties, fixing them as we go. 1386 * (We already handled n == 0 and n == 1 in pass 1) 1387 */ 1388 iptr = (void *)cpi->cpi_brandstr; 1389 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 1390 cp->cp_eax = 0x80000000 + n; 1391 (void) __cpuid_insn(cp); 1392 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 1393 switch (n) { 1394 case 2: 1395 case 3: 1396 case 4: 1397 /* 1398 * Extract the brand string 1399 */ 1400 *iptr++ = cp->cp_eax; 1401 *iptr++ = cp->cp_ebx; 1402 *iptr++ = cp->cp_ecx; 1403 *iptr++ = cp->cp_edx; 1404 break; 1405 case 5: 1406 switch (cpi->cpi_vendor) { 1407 case X86_VENDOR_AMD: 1408 /* 1409 * The Athlon and Duron were the first 1410 * parts to report the sizes of the 1411 * TLB for large pages. Before then, 1412 * we don't trust the data. 1413 */ 1414 if (cpi->cpi_family < 6 || 1415 (cpi->cpi_family == 6 && 1416 cpi->cpi_model < 1)) 1417 cp->cp_eax = 0; 1418 break; 1419 default: 1420 break; 1421 } 1422 break; 1423 case 6: 1424 switch (cpi->cpi_vendor) { 1425 case X86_VENDOR_AMD: 1426 /* 1427 * The Athlon and Duron were the first 1428 * AMD parts with L2 TLB's. 1429 * Before then, don't trust the data. 1430 */ 1431 if (cpi->cpi_family < 6 || 1432 cpi->cpi_family == 6 && 1433 cpi->cpi_model < 1) 1434 cp->cp_eax = cp->cp_ebx = 0; 1435 /* 1436 * AMD Duron rev A0 reports L2 1437 * cache size incorrectly as 1K 1438 * when it is really 64K 1439 */ 1440 if (cpi->cpi_family == 6 && 1441 cpi->cpi_model == 3 && 1442 cpi->cpi_step == 0) { 1443 cp->cp_ecx &= 0xffff; 1444 cp->cp_ecx |= 0x400000; 1445 } 1446 break; 1447 case X86_VENDOR_Cyrix: /* VIA C3 */ 1448 /* 1449 * VIA C3 processors are a bit messed 1450 * up w.r.t. encoding cache sizes in %ecx 1451 */ 1452 if (cpi->cpi_family != 6) 1453 break; 1454 /* 1455 * model 7 and 8 were incorrectly encoded 1456 * 1457 * xxx is model 8 really broken? 1458 */ 1459 if (cpi->cpi_model == 7 || 1460 cpi->cpi_model == 8) 1461 cp->cp_ecx = 1462 BITX(cp->cp_ecx, 31, 24) << 16 | 1463 BITX(cp->cp_ecx, 23, 16) << 12 | 1464 BITX(cp->cp_ecx, 15, 8) << 8 | 1465 BITX(cp->cp_ecx, 7, 0); 1466 /* 1467 * model 9 stepping 1 has wrong associativity 1468 */ 1469 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 1470 cp->cp_ecx |= 8 << 12; 1471 break; 1472 case X86_VENDOR_Intel: 1473 /* 1474 * Extended L2 Cache features function. 1475 * First appeared on Prescott. 1476 */ 1477 default: 1478 break; 1479 } 1480 break; 1481 default: 1482 break; 1483 } 1484 } 1485 1486 pass2_done: 1487 cpi->cpi_pass = 2; 1488 } 1489 1490 static const char * 1491 intel_cpubrand(const struct cpuid_info *cpi) 1492 { 1493 int i; 1494 1495 if ((x86_feature & X86_CPUID) == 0 || 1496 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1497 return ("i486"); 1498 1499 switch (cpi->cpi_family) { 1500 case 5: 1501 return ("Intel Pentium(r)"); 1502 case 6: 1503 switch (cpi->cpi_model) { 1504 uint_t celeron, xeon; 1505 const struct cpuid_regs *cp; 1506 case 0: 1507 case 1: 1508 case 2: 1509 return ("Intel Pentium(r) Pro"); 1510 case 3: 1511 case 4: 1512 return ("Intel Pentium(r) II"); 1513 case 6: 1514 return ("Intel Celeron(r)"); 1515 case 5: 1516 case 7: 1517 celeron = xeon = 0; 1518 cp = &cpi->cpi_std[2]; /* cache info */ 1519 1520 for (i = 1; i < 3; i++) { 1521 uint_t tmp; 1522 1523 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1524 if (tmp == 0x40) 1525 celeron++; 1526 if (tmp >= 0x44 && tmp <= 0x45) 1527 xeon++; 1528 } 1529 1530 for (i = 0; i < 2; i++) { 1531 uint_t tmp; 1532 1533 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1534 if (tmp == 0x40) 1535 celeron++; 1536 else if (tmp >= 0x44 && tmp <= 0x45) 1537 xeon++; 1538 } 1539 1540 for (i = 0; i < 4; i++) { 1541 uint_t tmp; 1542 1543 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1544 if (tmp == 0x40) 1545 celeron++; 1546 else if (tmp >= 0x44 && tmp <= 0x45) 1547 xeon++; 1548 } 1549 1550 for (i = 0; i < 4; i++) { 1551 uint_t tmp; 1552 1553 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1554 if (tmp == 0x40) 1555 celeron++; 1556 else if (tmp >= 0x44 && tmp <= 0x45) 1557 xeon++; 1558 } 1559 1560 if (celeron) 1561 return ("Intel Celeron(r)"); 1562 if (xeon) 1563 return (cpi->cpi_model == 5 ? 1564 "Intel Pentium(r) II Xeon(tm)" : 1565 "Intel Pentium(r) III Xeon(tm)"); 1566 return (cpi->cpi_model == 5 ? 1567 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1568 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1569 default: 1570 break; 1571 } 1572 default: 1573 break; 1574 } 1575 1576 /* BrandID is present if the field is nonzero */ 1577 if (cpi->cpi_brandid != 0) { 1578 static const struct { 1579 uint_t bt_bid; 1580 const char *bt_str; 1581 } brand_tbl[] = { 1582 { 0x1, "Intel(r) Celeron(r)" }, 1583 { 0x2, "Intel(r) Pentium(r) III" }, 1584 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1585 { 0x4, "Intel(r) Pentium(r) III" }, 1586 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1587 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1588 { 0x8, "Intel(r) Pentium(r) 4" }, 1589 { 0x9, "Intel(r) Pentium(r) 4" }, 1590 { 0xa, "Intel(r) Celeron(r)" }, 1591 { 0xb, "Intel(r) Xeon(tm)" }, 1592 { 0xc, "Intel(r) Xeon(tm) MP" }, 1593 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1594 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1595 { 0x11, "Mobile Genuine Intel(r)" }, 1596 { 0x12, "Intel(r) Celeron(r) M" }, 1597 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1598 { 0x14, "Intel(r) Celeron(r)" }, 1599 { 0x15, "Mobile Genuine Intel(r)" }, 1600 { 0x16, "Intel(r) Pentium(r) M" }, 1601 { 0x17, "Mobile Intel(r) Celeron(r)" } 1602 }; 1603 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1604 uint_t sgn; 1605 1606 sgn = (cpi->cpi_family << 8) | 1607 (cpi->cpi_model << 4) | cpi->cpi_step; 1608 1609 for (i = 0; i < btblmax; i++) 1610 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1611 break; 1612 if (i < btblmax) { 1613 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1614 return ("Intel(r) Celeron(r)"); 1615 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1616 return ("Intel(r) Xeon(tm) MP"); 1617 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1618 return ("Intel(r) Xeon(tm)"); 1619 return (brand_tbl[i].bt_str); 1620 } 1621 } 1622 1623 return (NULL); 1624 } 1625 1626 static const char * 1627 amd_cpubrand(const struct cpuid_info *cpi) 1628 { 1629 if ((x86_feature & X86_CPUID) == 0 || 1630 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1631 return ("i486 compatible"); 1632 1633 switch (cpi->cpi_family) { 1634 case 5: 1635 switch (cpi->cpi_model) { 1636 case 0: 1637 case 1: 1638 case 2: 1639 case 3: 1640 case 4: 1641 case 5: 1642 return ("AMD-K5(r)"); 1643 case 6: 1644 case 7: 1645 return ("AMD-K6(r)"); 1646 case 8: 1647 return ("AMD-K6(r)-2"); 1648 case 9: 1649 return ("AMD-K6(r)-III"); 1650 default: 1651 return ("AMD (family 5)"); 1652 } 1653 case 6: 1654 switch (cpi->cpi_model) { 1655 case 1: 1656 return ("AMD-K7(tm)"); 1657 case 0: 1658 case 2: 1659 case 4: 1660 return ("AMD Athlon(tm)"); 1661 case 3: 1662 case 7: 1663 return ("AMD Duron(tm)"); 1664 case 6: 1665 case 8: 1666 case 10: 1667 /* 1668 * Use the L2 cache size to distinguish 1669 */ 1670 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1671 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1672 default: 1673 return ("AMD (family 6)"); 1674 } 1675 default: 1676 break; 1677 } 1678 1679 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1680 cpi->cpi_brandid != 0) { 1681 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1682 case 3: 1683 return ("AMD Opteron(tm) UP 1xx"); 1684 case 4: 1685 return ("AMD Opteron(tm) DP 2xx"); 1686 case 5: 1687 return ("AMD Opteron(tm) MP 8xx"); 1688 default: 1689 return ("AMD Opteron(tm)"); 1690 } 1691 } 1692 1693 return (NULL); 1694 } 1695 1696 static const char * 1697 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1698 { 1699 if ((x86_feature & X86_CPUID) == 0 || 1700 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1701 type == X86_TYPE_CYRIX_486) 1702 return ("i486 compatible"); 1703 1704 switch (type) { 1705 case X86_TYPE_CYRIX_6x86: 1706 return ("Cyrix 6x86"); 1707 case X86_TYPE_CYRIX_6x86L: 1708 return ("Cyrix 6x86L"); 1709 case X86_TYPE_CYRIX_6x86MX: 1710 return ("Cyrix 6x86MX"); 1711 case X86_TYPE_CYRIX_GXm: 1712 return ("Cyrix GXm"); 1713 case X86_TYPE_CYRIX_MediaGX: 1714 return ("Cyrix MediaGX"); 1715 case X86_TYPE_CYRIX_MII: 1716 return ("Cyrix M2"); 1717 case X86_TYPE_VIA_CYRIX_III: 1718 return ("VIA Cyrix M3"); 1719 default: 1720 /* 1721 * Have another wild guess .. 1722 */ 1723 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1724 return ("Cyrix 5x86"); 1725 else if (cpi->cpi_family == 5) { 1726 switch (cpi->cpi_model) { 1727 case 2: 1728 return ("Cyrix 6x86"); /* Cyrix M1 */ 1729 case 4: 1730 return ("Cyrix MediaGX"); 1731 default: 1732 break; 1733 } 1734 } else if (cpi->cpi_family == 6) { 1735 switch (cpi->cpi_model) { 1736 case 0: 1737 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1738 case 5: 1739 case 6: 1740 case 7: 1741 case 8: 1742 case 9: 1743 return ("VIA C3"); 1744 default: 1745 break; 1746 } 1747 } 1748 break; 1749 } 1750 return (NULL); 1751 } 1752 1753 /* 1754 * This only gets called in the case that the CPU extended 1755 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1756 * aren't available, or contain null bytes for some reason. 1757 */ 1758 static void 1759 fabricate_brandstr(struct cpuid_info *cpi) 1760 { 1761 const char *brand = NULL; 1762 1763 switch (cpi->cpi_vendor) { 1764 case X86_VENDOR_Intel: 1765 brand = intel_cpubrand(cpi); 1766 break; 1767 case X86_VENDOR_AMD: 1768 brand = amd_cpubrand(cpi); 1769 break; 1770 case X86_VENDOR_Cyrix: 1771 brand = cyrix_cpubrand(cpi, x86_type); 1772 break; 1773 case X86_VENDOR_NexGen: 1774 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1775 brand = "NexGen Nx586"; 1776 break; 1777 case X86_VENDOR_Centaur: 1778 if (cpi->cpi_family == 5) 1779 switch (cpi->cpi_model) { 1780 case 4: 1781 brand = "Centaur C6"; 1782 break; 1783 case 8: 1784 brand = "Centaur C2"; 1785 break; 1786 case 9: 1787 brand = "Centaur C3"; 1788 break; 1789 default: 1790 break; 1791 } 1792 break; 1793 case X86_VENDOR_Rise: 1794 if (cpi->cpi_family == 5 && 1795 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1796 brand = "Rise mP6"; 1797 break; 1798 case X86_VENDOR_SiS: 1799 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1800 brand = "SiS 55x"; 1801 break; 1802 case X86_VENDOR_TM: 1803 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1804 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1805 break; 1806 case X86_VENDOR_NSC: 1807 case X86_VENDOR_UMC: 1808 default: 1809 break; 1810 } 1811 if (brand) { 1812 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1813 return; 1814 } 1815 1816 /* 1817 * If all else fails ... 1818 */ 1819 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1820 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1821 cpi->cpi_model, cpi->cpi_step); 1822 } 1823 1824 /* 1825 * This routine is called just after kernel memory allocation 1826 * becomes available on cpu0, and as part of mp_startup() on 1827 * the other cpus. 1828 * 1829 * Fixup the brand string, and collect any information from cpuid 1830 * that requires dynamicically allocated storage to represent. 1831 */ 1832 /*ARGSUSED*/ 1833 void 1834 cpuid_pass3(cpu_t *cpu) 1835 { 1836 int i, max, shft, level, size; 1837 struct cpuid_regs regs; 1838 struct cpuid_regs *cp; 1839 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1840 1841 ASSERT(cpi->cpi_pass == 2); 1842 1843 /* 1844 * Function 4: Deterministic cache parameters 1845 * 1846 * Take this opportunity to detect the number of threads 1847 * sharing the last level cache, and construct a corresponding 1848 * cache id. The respective cpuid_info members are initialized 1849 * to the default case of "no last level cache sharing". 1850 */ 1851 cpi->cpi_ncpu_shr_last_cache = 1; 1852 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 1853 1854 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 1855 1856 /* 1857 * Find the # of elements (size) returned by fn 4, and along 1858 * the way detect last level cache sharing details. 1859 */ 1860 bzero(®s, sizeof (regs)); 1861 cp = ®s; 1862 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 1863 cp->cp_eax = 4; 1864 cp->cp_ecx = i; 1865 1866 (void) __cpuid_insn(cp); 1867 1868 if (CPI_CACHE_TYPE(cp) == 0) 1869 break; 1870 level = CPI_CACHE_LVL(cp); 1871 if (level > max) { 1872 max = level; 1873 cpi->cpi_ncpu_shr_last_cache = 1874 CPI_NTHR_SHR_CACHE(cp) + 1; 1875 } 1876 } 1877 cpi->cpi_std_4_size = size = i; 1878 1879 /* 1880 * Allocate the cpi_std_4 array. The first element 1881 * references the regs for fn 4, %ecx == 0, which 1882 * cpuid_pass2() stashed in cpi->cpi_std[4]. 1883 */ 1884 if (size > 0) { 1885 cpi->cpi_std_4 = 1886 kmem_alloc(size * sizeof (cp), KM_SLEEP); 1887 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 1888 1889 /* 1890 * Allocate storage to hold the additional regs 1891 * for function 4, %ecx == 1 .. cpi_std_4_size. 1892 * 1893 * The regs for fn 4, %ecx == 0 has already 1894 * been allocated as indicated above. 1895 */ 1896 for (i = 1; i < size; i++) { 1897 cp = cpi->cpi_std_4[i] = 1898 kmem_zalloc(sizeof (regs), KM_SLEEP); 1899 cp->cp_eax = 4; 1900 cp->cp_ecx = i; 1901 1902 (void) __cpuid_insn(cp); 1903 } 1904 } 1905 /* 1906 * Determine the number of bits needed to represent 1907 * the number of CPUs sharing the last level cache. 1908 * 1909 * Shift off that number of bits from the APIC id to 1910 * derive the cache id. 1911 */ 1912 shft = 0; 1913 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 1914 shft++; 1915 cpi->cpi_last_lvl_cacheid = CPI_APIC_ID(cpi) >> shft; 1916 } 1917 1918 /* 1919 * Now fixup the brand string 1920 */ 1921 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1922 fabricate_brandstr(cpi); 1923 } else { 1924 1925 /* 1926 * If we successfully extracted a brand string from the cpuid 1927 * instruction, clean it up by removing leading spaces and 1928 * similar junk. 1929 */ 1930 if (cpi->cpi_brandstr[0]) { 1931 size_t maxlen = sizeof (cpi->cpi_brandstr); 1932 char *src, *dst; 1933 1934 dst = src = (char *)cpi->cpi_brandstr; 1935 src[maxlen - 1] = '\0'; 1936 /* 1937 * strip leading spaces 1938 */ 1939 while (*src == ' ') 1940 src++; 1941 /* 1942 * Remove any 'Genuine' or "Authentic" prefixes 1943 */ 1944 if (strncmp(src, "Genuine ", 8) == 0) 1945 src += 8; 1946 if (strncmp(src, "Authentic ", 10) == 0) 1947 src += 10; 1948 1949 /* 1950 * Now do an in-place copy. 1951 * Map (R) to (r) and (TM) to (tm). 1952 * The era of teletypes is long gone, and there's 1953 * -really- no need to shout. 1954 */ 1955 while (*src != '\0') { 1956 if (src[0] == '(') { 1957 if (strncmp(src + 1, "R)", 2) == 0) { 1958 (void) strncpy(dst, "(r)", 3); 1959 src += 3; 1960 dst += 3; 1961 continue; 1962 } 1963 if (strncmp(src + 1, "TM)", 3) == 0) { 1964 (void) strncpy(dst, "(tm)", 4); 1965 src += 4; 1966 dst += 4; 1967 continue; 1968 } 1969 } 1970 *dst++ = *src++; 1971 } 1972 *dst = '\0'; 1973 1974 /* 1975 * Finally, remove any trailing spaces 1976 */ 1977 while (--dst > cpi->cpi_brandstr) 1978 if (*dst == ' ') 1979 *dst = '\0'; 1980 else 1981 break; 1982 } else 1983 fabricate_brandstr(cpi); 1984 } 1985 cpi->cpi_pass = 3; 1986 } 1987 1988 /* 1989 * This routine is called out of bind_hwcap() much later in the life 1990 * of the kernel (post_startup()). The job of this routine is to resolve 1991 * the hardware feature support and kernel support for those features into 1992 * what we're actually going to tell applications via the aux vector. 1993 */ 1994 uint_t 1995 cpuid_pass4(cpu_t *cpu) 1996 { 1997 struct cpuid_info *cpi; 1998 uint_t hwcap_flags = 0; 1999 2000 if (cpu == NULL) 2001 cpu = CPU; 2002 cpi = cpu->cpu_m.mcpu_cpi; 2003 2004 ASSERT(cpi->cpi_pass == 3); 2005 2006 if (cpi->cpi_maxeax >= 1) { 2007 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 2008 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 2009 2010 *edx = CPI_FEATURES_EDX(cpi); 2011 *ecx = CPI_FEATURES_ECX(cpi); 2012 2013 /* 2014 * [these require explicit kernel support] 2015 */ 2016 if ((x86_feature & X86_SEP) == 0) 2017 *edx &= ~CPUID_INTC_EDX_SEP; 2018 2019 if ((x86_feature & X86_SSE) == 0) 2020 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 2021 if ((x86_feature & X86_SSE2) == 0) 2022 *edx &= ~CPUID_INTC_EDX_SSE2; 2023 2024 if ((x86_feature & X86_HTT) == 0) 2025 *edx &= ~CPUID_INTC_EDX_HTT; 2026 2027 if ((x86_feature & X86_SSE3) == 0) 2028 *ecx &= ~CPUID_INTC_ECX_SSE3; 2029 2030 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2031 if ((x86_feature & X86_SSSE3) == 0) 2032 *ecx &= ~CPUID_INTC_ECX_SSSE3; 2033 if ((x86_feature & X86_SSE4_1) == 0) 2034 *ecx &= ~CPUID_INTC_ECX_SSE4_1; 2035 if ((x86_feature & X86_SSE4_2) == 0) 2036 *ecx &= ~CPUID_INTC_ECX_SSE4_2; 2037 } 2038 2039 /* 2040 * [no explicit support required beyond x87 fp context] 2041 */ 2042 if (!fpu_exists) 2043 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 2044 2045 /* 2046 * Now map the supported feature vector to things that we 2047 * think userland will care about. 2048 */ 2049 if (*edx & CPUID_INTC_EDX_SEP) 2050 hwcap_flags |= AV_386_SEP; 2051 if (*edx & CPUID_INTC_EDX_SSE) 2052 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 2053 if (*edx & CPUID_INTC_EDX_SSE2) 2054 hwcap_flags |= AV_386_SSE2; 2055 if (*ecx & CPUID_INTC_ECX_SSE3) 2056 hwcap_flags |= AV_386_SSE3; 2057 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2058 if (*ecx & CPUID_INTC_ECX_SSSE3) 2059 hwcap_flags |= AV_386_SSSE3; 2060 if (*ecx & CPUID_INTC_ECX_SSE4_1) 2061 hwcap_flags |= AV_386_SSE4_1; 2062 if (*ecx & CPUID_INTC_ECX_SSE4_2) 2063 hwcap_flags |= AV_386_SSE4_2; 2064 } 2065 if (*ecx & CPUID_INTC_ECX_POPCNT) 2066 hwcap_flags |= AV_386_POPCNT; 2067 if (*edx & CPUID_INTC_EDX_FPU) 2068 hwcap_flags |= AV_386_FPU; 2069 if (*edx & CPUID_INTC_EDX_MMX) 2070 hwcap_flags |= AV_386_MMX; 2071 2072 if (*edx & CPUID_INTC_EDX_TSC) 2073 hwcap_flags |= AV_386_TSC; 2074 if (*edx & CPUID_INTC_EDX_CX8) 2075 hwcap_flags |= AV_386_CX8; 2076 if (*edx & CPUID_INTC_EDX_CMOV) 2077 hwcap_flags |= AV_386_CMOV; 2078 if (*ecx & CPUID_INTC_ECX_MON) 2079 hwcap_flags |= AV_386_MON; 2080 if (*ecx & CPUID_INTC_ECX_CX16) 2081 hwcap_flags |= AV_386_CX16; 2082 } 2083 2084 if (x86_feature & X86_HTT) 2085 hwcap_flags |= AV_386_PAUSE; 2086 2087 if (cpi->cpi_xmaxeax < 0x80000001) 2088 goto pass4_done; 2089 2090 switch (cpi->cpi_vendor) { 2091 struct cpuid_regs cp; 2092 uint32_t *edx, *ecx; 2093 2094 case X86_VENDOR_Intel: 2095 /* 2096 * Seems like Intel duplicated what we necessary 2097 * here to make the initial crop of 64-bit OS's work. 2098 * Hopefully, those are the only "extended" bits 2099 * they'll add. 2100 */ 2101 /*FALLTHROUGH*/ 2102 2103 case X86_VENDOR_AMD: 2104 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 2105 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 2106 2107 *edx = CPI_FEATURES_XTD_EDX(cpi); 2108 *ecx = CPI_FEATURES_XTD_ECX(cpi); 2109 2110 /* 2111 * [these features require explicit kernel support] 2112 */ 2113 switch (cpi->cpi_vendor) { 2114 case X86_VENDOR_Intel: 2115 break; 2116 2117 case X86_VENDOR_AMD: 2118 if ((x86_feature & X86_TSCP) == 0) 2119 *edx &= ~CPUID_AMD_EDX_TSCP; 2120 if ((x86_feature & X86_SSE4A) == 0) 2121 *ecx &= ~CPUID_AMD_ECX_SSE4A; 2122 break; 2123 2124 default: 2125 break; 2126 } 2127 2128 /* 2129 * [no explicit support required beyond 2130 * x87 fp context and exception handlers] 2131 */ 2132 if (!fpu_exists) 2133 *edx &= ~(CPUID_AMD_EDX_MMXamd | 2134 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 2135 2136 if ((x86_feature & X86_NX) == 0) 2137 *edx &= ~CPUID_AMD_EDX_NX; 2138 #if !defined(__amd64) 2139 *edx &= ~CPUID_AMD_EDX_LM; 2140 #endif 2141 /* 2142 * Now map the supported feature vector to 2143 * things that we think userland will care about. 2144 */ 2145 #if defined(__amd64) 2146 if (*edx & CPUID_AMD_EDX_SYSC) 2147 hwcap_flags |= AV_386_AMD_SYSC; 2148 #endif 2149 if (*edx & CPUID_AMD_EDX_MMXamd) 2150 hwcap_flags |= AV_386_AMD_MMX; 2151 if (*edx & CPUID_AMD_EDX_3DNow) 2152 hwcap_flags |= AV_386_AMD_3DNow; 2153 if (*edx & CPUID_AMD_EDX_3DNowx) 2154 hwcap_flags |= AV_386_AMD_3DNowx; 2155 2156 switch (cpi->cpi_vendor) { 2157 case X86_VENDOR_AMD: 2158 if (*edx & CPUID_AMD_EDX_TSCP) 2159 hwcap_flags |= AV_386_TSCP; 2160 if (*ecx & CPUID_AMD_ECX_AHF64) 2161 hwcap_flags |= AV_386_AHF; 2162 if (*ecx & CPUID_AMD_ECX_SSE4A) 2163 hwcap_flags |= AV_386_AMD_SSE4A; 2164 if (*ecx & CPUID_AMD_ECX_LZCNT) 2165 hwcap_flags |= AV_386_AMD_LZCNT; 2166 break; 2167 2168 case X86_VENDOR_Intel: 2169 /* 2170 * Aarrgh. 2171 * Intel uses a different bit in the same word. 2172 */ 2173 if (*ecx & CPUID_INTC_ECX_AHF64) 2174 hwcap_flags |= AV_386_AHF; 2175 break; 2176 2177 default: 2178 break; 2179 } 2180 break; 2181 2182 case X86_VENDOR_TM: 2183 cp.cp_eax = 0x80860001; 2184 (void) __cpuid_insn(&cp); 2185 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 2186 break; 2187 2188 default: 2189 break; 2190 } 2191 2192 pass4_done: 2193 cpi->cpi_pass = 4; 2194 return (hwcap_flags); 2195 } 2196 2197 2198 /* 2199 * Simulate the cpuid instruction using the data we previously 2200 * captured about this CPU. We try our best to return the truth 2201 * about the hardware, independently of kernel support. 2202 */ 2203 uint32_t 2204 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 2205 { 2206 struct cpuid_info *cpi; 2207 struct cpuid_regs *xcp; 2208 2209 if (cpu == NULL) 2210 cpu = CPU; 2211 cpi = cpu->cpu_m.mcpu_cpi; 2212 2213 ASSERT(cpuid_checkpass(cpu, 3)); 2214 2215 /* 2216 * CPUID data is cached in two separate places: cpi_std for standard 2217 * CPUID functions, and cpi_extd for extended CPUID functions. 2218 */ 2219 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 2220 xcp = &cpi->cpi_std[cp->cp_eax]; 2221 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 2222 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 2223 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 2224 else 2225 /* 2226 * The caller is asking for data from an input parameter which 2227 * the kernel has not cached. In this case we go fetch from 2228 * the hardware and return the data directly to the user. 2229 */ 2230 return (__cpuid_insn(cp)); 2231 2232 cp->cp_eax = xcp->cp_eax; 2233 cp->cp_ebx = xcp->cp_ebx; 2234 cp->cp_ecx = xcp->cp_ecx; 2235 cp->cp_edx = xcp->cp_edx; 2236 return (cp->cp_eax); 2237 } 2238 2239 int 2240 cpuid_checkpass(cpu_t *cpu, int pass) 2241 { 2242 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 2243 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 2244 } 2245 2246 int 2247 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 2248 { 2249 ASSERT(cpuid_checkpass(cpu, 3)); 2250 2251 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 2252 } 2253 2254 int 2255 cpuid_is_cmt(cpu_t *cpu) 2256 { 2257 if (cpu == NULL) 2258 cpu = CPU; 2259 2260 ASSERT(cpuid_checkpass(cpu, 1)); 2261 2262 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 2263 } 2264 2265 /* 2266 * AMD and Intel both implement the 64-bit variant of the syscall 2267 * instruction (syscallq), so if there's -any- support for syscall, 2268 * cpuid currently says "yes, we support this". 2269 * 2270 * However, Intel decided to -not- implement the 32-bit variant of the 2271 * syscall instruction, so we provide a predicate to allow our caller 2272 * to test that subtlety here. 2273 * 2274 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, 2275 * even in the case where the hardware would in fact support it. 2276 */ 2277 /*ARGSUSED*/ 2278 int 2279 cpuid_syscall32_insn(cpu_t *cpu) 2280 { 2281 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 2282 2283 #if !defined(__xpv) 2284 if (cpu == NULL) 2285 cpu = CPU; 2286 2287 /*CSTYLED*/ 2288 { 2289 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2290 2291 if (cpi->cpi_vendor == X86_VENDOR_AMD && 2292 cpi->cpi_xmaxeax >= 0x80000001 && 2293 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 2294 return (1); 2295 } 2296 #endif 2297 return (0); 2298 } 2299 2300 int 2301 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 2302 { 2303 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2304 2305 static const char fmt[] = 2306 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 2307 static const char fmt_ht[] = 2308 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 2309 2310 ASSERT(cpuid_checkpass(cpu, 1)); 2311 2312 if (cpuid_is_cmt(cpu)) 2313 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 2314 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2315 cpi->cpi_family, cpi->cpi_model, 2316 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2317 return (snprintf(s, n, fmt, 2318 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2319 cpi->cpi_family, cpi->cpi_model, 2320 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2321 } 2322 2323 const char * 2324 cpuid_getvendorstr(cpu_t *cpu) 2325 { 2326 ASSERT(cpuid_checkpass(cpu, 1)); 2327 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 2328 } 2329 2330 uint_t 2331 cpuid_getvendor(cpu_t *cpu) 2332 { 2333 ASSERT(cpuid_checkpass(cpu, 1)); 2334 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 2335 } 2336 2337 uint_t 2338 cpuid_getfamily(cpu_t *cpu) 2339 { 2340 ASSERT(cpuid_checkpass(cpu, 1)); 2341 return (cpu->cpu_m.mcpu_cpi->cpi_family); 2342 } 2343 2344 uint_t 2345 cpuid_getmodel(cpu_t *cpu) 2346 { 2347 ASSERT(cpuid_checkpass(cpu, 1)); 2348 return (cpu->cpu_m.mcpu_cpi->cpi_model); 2349 } 2350 2351 uint_t 2352 cpuid_get_ncpu_per_chip(cpu_t *cpu) 2353 { 2354 ASSERT(cpuid_checkpass(cpu, 1)); 2355 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 2356 } 2357 2358 uint_t 2359 cpuid_get_ncore_per_chip(cpu_t *cpu) 2360 { 2361 ASSERT(cpuid_checkpass(cpu, 1)); 2362 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 2363 } 2364 2365 uint_t 2366 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 2367 { 2368 ASSERT(cpuid_checkpass(cpu, 2)); 2369 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 2370 } 2371 2372 id_t 2373 cpuid_get_last_lvl_cacheid(cpu_t *cpu) 2374 { 2375 ASSERT(cpuid_checkpass(cpu, 2)); 2376 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 2377 } 2378 2379 uint_t 2380 cpuid_getstep(cpu_t *cpu) 2381 { 2382 ASSERT(cpuid_checkpass(cpu, 1)); 2383 return (cpu->cpu_m.mcpu_cpi->cpi_step); 2384 } 2385 2386 uint_t 2387 cpuid_getsig(struct cpu *cpu) 2388 { 2389 ASSERT(cpuid_checkpass(cpu, 1)); 2390 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 2391 } 2392 2393 uint32_t 2394 cpuid_getchiprev(struct cpu *cpu) 2395 { 2396 ASSERT(cpuid_checkpass(cpu, 1)); 2397 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 2398 } 2399 2400 const char * 2401 cpuid_getchiprevstr(struct cpu *cpu) 2402 { 2403 ASSERT(cpuid_checkpass(cpu, 1)); 2404 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 2405 } 2406 2407 uint32_t 2408 cpuid_getsockettype(struct cpu *cpu) 2409 { 2410 ASSERT(cpuid_checkpass(cpu, 1)); 2411 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 2412 } 2413 2414 int 2415 cpuid_get_chipid(cpu_t *cpu) 2416 { 2417 ASSERT(cpuid_checkpass(cpu, 1)); 2418 2419 if (cpuid_is_cmt(cpu)) 2420 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 2421 return (cpu->cpu_id); 2422 } 2423 2424 id_t 2425 cpuid_get_coreid(cpu_t *cpu) 2426 { 2427 ASSERT(cpuid_checkpass(cpu, 1)); 2428 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 2429 } 2430 2431 int 2432 cpuid_get_clogid(cpu_t *cpu) 2433 { 2434 ASSERT(cpuid_checkpass(cpu, 1)); 2435 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 2436 } 2437 2438 void 2439 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 2440 { 2441 struct cpuid_info *cpi; 2442 2443 if (cpu == NULL) 2444 cpu = CPU; 2445 cpi = cpu->cpu_m.mcpu_cpi; 2446 2447 ASSERT(cpuid_checkpass(cpu, 1)); 2448 2449 if (pabits) 2450 *pabits = cpi->cpi_pabits; 2451 if (vabits) 2452 *vabits = cpi->cpi_vabits; 2453 } 2454 2455 /* 2456 * Returns the number of data TLB entries for a corresponding 2457 * pagesize. If it can't be computed, or isn't known, the 2458 * routine returns zero. If you ask about an architecturally 2459 * impossible pagesize, the routine will panic (so that the 2460 * hat implementor knows that things are inconsistent.) 2461 */ 2462 uint_t 2463 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 2464 { 2465 struct cpuid_info *cpi; 2466 uint_t dtlb_nent = 0; 2467 2468 if (cpu == NULL) 2469 cpu = CPU; 2470 cpi = cpu->cpu_m.mcpu_cpi; 2471 2472 ASSERT(cpuid_checkpass(cpu, 1)); 2473 2474 /* 2475 * Check the L2 TLB info 2476 */ 2477 if (cpi->cpi_xmaxeax >= 0x80000006) { 2478 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 2479 2480 switch (pagesize) { 2481 2482 case 4 * 1024: 2483 /* 2484 * All zero in the top 16 bits of the register 2485 * indicates a unified TLB. Size is in low 16 bits. 2486 */ 2487 if ((cp->cp_ebx & 0xffff0000) == 0) 2488 dtlb_nent = cp->cp_ebx & 0x0000ffff; 2489 else 2490 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 2491 break; 2492 2493 case 2 * 1024 * 1024: 2494 if ((cp->cp_eax & 0xffff0000) == 0) 2495 dtlb_nent = cp->cp_eax & 0x0000ffff; 2496 else 2497 dtlb_nent = BITX(cp->cp_eax, 27, 16); 2498 break; 2499 2500 default: 2501 panic("unknown L2 pagesize"); 2502 /*NOTREACHED*/ 2503 } 2504 } 2505 2506 if (dtlb_nent != 0) 2507 return (dtlb_nent); 2508 2509 /* 2510 * No L2 TLB support for this size, try L1. 2511 */ 2512 if (cpi->cpi_xmaxeax >= 0x80000005) { 2513 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 2514 2515 switch (pagesize) { 2516 case 4 * 1024: 2517 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 2518 break; 2519 case 2 * 1024 * 1024: 2520 dtlb_nent = BITX(cp->cp_eax, 23, 16); 2521 break; 2522 default: 2523 panic("unknown L1 d-TLB pagesize"); 2524 /*NOTREACHED*/ 2525 } 2526 } 2527 2528 return (dtlb_nent); 2529 } 2530 2531 /* 2532 * Return 0 if the erratum is not present or not applicable, positive 2533 * if it is, and negative if the status of the erratum is unknown. 2534 * 2535 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 2536 * Processors" #25759, Rev 3.57, August 2005 2537 */ 2538 int 2539 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 2540 { 2541 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2542 uint_t eax; 2543 2544 /* 2545 * Bail out if this CPU isn't an AMD CPU, or if it's 2546 * a legacy (32-bit) AMD CPU. 2547 */ 2548 if (cpi->cpi_vendor != X86_VENDOR_AMD || 2549 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 2550 cpi->cpi_family == 6) 2551 2552 return (0); 2553 2554 eax = cpi->cpi_std[1].cp_eax; 2555 2556 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 2557 #define SH_B3(eax) (eax == 0xf51) 2558 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 2559 2560 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 2561 2562 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 2563 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 2564 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 2565 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 2566 2567 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 2568 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 2569 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 2570 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 2571 2572 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 2573 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 2574 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 2575 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 2576 #define BH_E4(eax) (eax == 0x20fb1) 2577 #define SH_E5(eax) (eax == 0x20f42) 2578 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 2579 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 2580 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 2581 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 2582 DH_E6(eax) || JH_E6(eax)) 2583 2584 switch (erratum) { 2585 case 1: 2586 return (cpi->cpi_family < 0x10); 2587 case 51: /* what does the asterisk mean? */ 2588 return (B(eax) || SH_C0(eax) || CG(eax)); 2589 case 52: 2590 return (B(eax)); 2591 case 57: 2592 return (cpi->cpi_family <= 0x10); 2593 case 58: 2594 return (B(eax)); 2595 case 60: 2596 return (cpi->cpi_family <= 0x10); 2597 case 61: 2598 case 62: 2599 case 63: 2600 case 64: 2601 case 65: 2602 case 66: 2603 case 68: 2604 case 69: 2605 case 70: 2606 case 71: 2607 return (B(eax)); 2608 case 72: 2609 return (SH_B0(eax)); 2610 case 74: 2611 return (B(eax)); 2612 case 75: 2613 return (cpi->cpi_family < 0x10); 2614 case 76: 2615 return (B(eax)); 2616 case 77: 2617 return (cpi->cpi_family <= 0x10); 2618 case 78: 2619 return (B(eax) || SH_C0(eax)); 2620 case 79: 2621 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2622 case 80: 2623 case 81: 2624 case 82: 2625 return (B(eax)); 2626 case 83: 2627 return (B(eax) || SH_C0(eax) || CG(eax)); 2628 case 85: 2629 return (cpi->cpi_family < 0x10); 2630 case 86: 2631 return (SH_C0(eax) || CG(eax)); 2632 case 88: 2633 #if !defined(__amd64) 2634 return (0); 2635 #else 2636 return (B(eax) || SH_C0(eax)); 2637 #endif 2638 case 89: 2639 return (cpi->cpi_family < 0x10); 2640 case 90: 2641 return (B(eax) || SH_C0(eax) || CG(eax)); 2642 case 91: 2643 case 92: 2644 return (B(eax) || SH_C0(eax)); 2645 case 93: 2646 return (SH_C0(eax)); 2647 case 94: 2648 return (B(eax) || SH_C0(eax) || CG(eax)); 2649 case 95: 2650 #if !defined(__amd64) 2651 return (0); 2652 #else 2653 return (B(eax) || SH_C0(eax)); 2654 #endif 2655 case 96: 2656 return (B(eax) || SH_C0(eax) || CG(eax)); 2657 case 97: 2658 case 98: 2659 return (SH_C0(eax) || CG(eax)); 2660 case 99: 2661 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2662 case 100: 2663 return (B(eax) || SH_C0(eax)); 2664 case 101: 2665 case 103: 2666 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2667 case 104: 2668 return (SH_C0(eax) || CG(eax) || D0(eax)); 2669 case 105: 2670 case 106: 2671 case 107: 2672 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2673 case 108: 2674 return (DH_CG(eax)); 2675 case 109: 2676 return (SH_C0(eax) || CG(eax) || D0(eax)); 2677 case 110: 2678 return (D0(eax) || EX(eax)); 2679 case 111: 2680 return (CG(eax)); 2681 case 112: 2682 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2683 case 113: 2684 return (eax == 0x20fc0); 2685 case 114: 2686 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2687 case 115: 2688 return (SH_E0(eax) || JH_E1(eax)); 2689 case 116: 2690 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2691 case 117: 2692 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2693 case 118: 2694 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 2695 JH_E6(eax)); 2696 case 121: 2697 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2698 case 122: 2699 return (cpi->cpi_family < 0x10); 2700 case 123: 2701 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2702 case 131: 2703 return (cpi->cpi_family < 0x10); 2704 case 6336786: 2705 /* 2706 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2707 * if this is a K8 family or newer processor 2708 */ 2709 if (CPI_FAMILY(cpi) == 0xf) { 2710 struct cpuid_regs regs; 2711 regs.cp_eax = 0x80000007; 2712 (void) __cpuid_insn(®s); 2713 return (!(regs.cp_edx & 0x100)); 2714 } 2715 return (0); 2716 case 6323525: 2717 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2718 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2719 2720 default: 2721 return (-1); 2722 } 2723 } 2724 2725 static const char assoc_str[] = "associativity"; 2726 static const char line_str[] = "line-size"; 2727 static const char size_str[] = "size"; 2728 2729 static void 2730 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2731 uint32_t val) 2732 { 2733 char buf[128]; 2734 2735 /* 2736 * ndi_prop_update_int() is used because it is desirable for 2737 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2738 */ 2739 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2740 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2741 } 2742 2743 /* 2744 * Intel-style cache/tlb description 2745 * 2746 * Standard cpuid level 2 gives a randomly ordered 2747 * selection of tags that index into a table that describes 2748 * cache and tlb properties. 2749 */ 2750 2751 static const char l1_icache_str[] = "l1-icache"; 2752 static const char l1_dcache_str[] = "l1-dcache"; 2753 static const char l2_cache_str[] = "l2-cache"; 2754 static const char l3_cache_str[] = "l3-cache"; 2755 static const char itlb4k_str[] = "itlb-4K"; 2756 static const char dtlb4k_str[] = "dtlb-4K"; 2757 static const char itlb4M_str[] = "itlb-4M"; 2758 static const char dtlb4M_str[] = "dtlb-4M"; 2759 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2760 static const char dtlb44_str[] = "dtlb-4K-4M"; 2761 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2762 static const char sl2_cache_str[] = "sectored-l2-cache"; 2763 static const char itrace_str[] = "itrace-cache"; 2764 static const char sl3_cache_str[] = "sectored-l3-cache"; 2765 2766 static const struct cachetab { 2767 uint8_t ct_code; 2768 uint8_t ct_assoc; 2769 uint16_t ct_line_size; 2770 size_t ct_size; 2771 const char *ct_label; 2772 } intel_ctab[] = { 2773 /* maintain descending order! */ 2774 { 0xb4, 4, 0, 256, dtlb4k_str }, 2775 { 0xb3, 4, 0, 128, dtlb4k_str }, 2776 { 0xb0, 4, 0, 128, itlb4k_str }, 2777 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2778 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2779 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2780 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2781 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2782 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2783 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2784 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2785 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2786 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2787 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2788 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2789 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2790 { 0x73, 8, 0, 64*1024, itrace_str}, 2791 { 0x72, 8, 0, 32*1024, itrace_str}, 2792 { 0x71, 8, 0, 16*1024, itrace_str}, 2793 { 0x70, 8, 0, 12*1024, itrace_str}, 2794 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2795 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2796 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2797 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2798 { 0x5d, 0, 0, 256, dtlb44_str}, 2799 { 0x5c, 0, 0, 128, dtlb44_str}, 2800 { 0x5b, 0, 0, 64, dtlb44_str}, 2801 { 0x52, 0, 0, 256, itlb424_str}, 2802 { 0x51, 0, 0, 128, itlb424_str}, 2803 { 0x50, 0, 0, 64, itlb424_str}, 2804 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 2805 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 2806 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 2807 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 2808 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 2809 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 2810 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 2811 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2812 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2813 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2814 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2815 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2816 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 2817 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 2818 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2819 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2820 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 2821 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2822 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2823 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2824 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2825 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2826 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2827 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2828 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2829 { 0x0b, 4, 0, 4, itlb4M_str}, 2830 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2831 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2832 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2833 { 0x04, 4, 0, 8, dtlb4M_str}, 2834 { 0x03, 4, 0, 64, dtlb4k_str}, 2835 { 0x02, 4, 0, 2, itlb4M_str}, 2836 { 0x01, 4, 0, 32, itlb4k_str}, 2837 { 0 } 2838 }; 2839 2840 static const struct cachetab cyrix_ctab[] = { 2841 { 0x70, 4, 0, 32, "tlb-4K" }, 2842 { 0x80, 4, 16, 16*1024, "l1-cache" }, 2843 { 0 } 2844 }; 2845 2846 /* 2847 * Search a cache table for a matching entry 2848 */ 2849 static const struct cachetab * 2850 find_cacheent(const struct cachetab *ct, uint_t code) 2851 { 2852 if (code != 0) { 2853 for (; ct->ct_code != 0; ct++) 2854 if (ct->ct_code <= code) 2855 break; 2856 if (ct->ct_code == code) 2857 return (ct); 2858 } 2859 return (NULL); 2860 } 2861 2862 /* 2863 * Walk the cacheinfo descriptor, applying 'func' to every valid element 2864 * The walk is terminated if the walker returns non-zero. 2865 */ 2866 static void 2867 intel_walk_cacheinfo(struct cpuid_info *cpi, 2868 void *arg, int (*func)(void *, const struct cachetab *)) 2869 { 2870 const struct cachetab *ct; 2871 uint8_t *dp; 2872 int i; 2873 2874 if ((dp = cpi->cpi_cacheinfo) == NULL) 2875 return; 2876 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2877 /* 2878 * For overloaded descriptor 0x49 we use cpuid function 4 2879 * if supported by the current processor, to update 2880 * cache information. 2881 */ 2882 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4) { 2883 intel_cpuid_4_cache_info(arg, cpi); 2884 continue; 2885 } 2886 2887 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2888 if (func(arg, ct) != 0) 2889 break; 2890 } 2891 } 2892 } 2893 2894 /* 2895 * (Like the Intel one, except for Cyrix CPUs) 2896 */ 2897 static void 2898 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 2899 void *arg, int (*func)(void *, const struct cachetab *)) 2900 { 2901 const struct cachetab *ct; 2902 uint8_t *dp; 2903 int i; 2904 2905 if ((dp = cpi->cpi_cacheinfo) == NULL) 2906 return; 2907 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 2908 /* 2909 * Search Cyrix-specific descriptor table first .. 2910 */ 2911 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 2912 if (func(arg, ct) != 0) 2913 break; 2914 continue; 2915 } 2916 /* 2917 * .. else fall back to the Intel one 2918 */ 2919 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 2920 if (func(arg, ct) != 0) 2921 break; 2922 continue; 2923 } 2924 } 2925 } 2926 2927 /* 2928 * A cacheinfo walker that adds associativity, line-size, and size properties 2929 * to the devinfo node it is passed as an argument. 2930 */ 2931 static int 2932 add_cacheent_props(void *arg, const struct cachetab *ct) 2933 { 2934 dev_info_t *devi = arg; 2935 2936 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 2937 if (ct->ct_line_size != 0) 2938 add_cache_prop(devi, ct->ct_label, line_str, 2939 ct->ct_line_size); 2940 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 2941 return (0); 2942 } 2943 2944 /* 2945 * Add L2 or L3 cache-information using cpuid function 4. This 2946 * function is called from intel_walk_cacheinfo() when descriptor 2947 * 0x49 is encountered. 2948 */ 2949 static void 2950 intel_cpuid_4_cache_info(void *arg, struct cpuid_info *cpi) 2951 { 2952 uint32_t level, i; 2953 2954 struct cachetab ct; 2955 2956 for (i = 0; i < cpi->cpi_std_4_size; i++) { 2957 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); 2958 2959 if (level == 2 || level == 3) { 2960 ct.ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; 2961 ct.ct_line_size = 2962 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; 2963 ct.ct_size = ct.ct_assoc * 2964 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * 2965 ct.ct_line_size * 2966 (cpi->cpi_std_4[i]->cp_ecx + 1); 2967 2968 if (level == 2) { 2969 ct.ct_label = l2_cache_str; 2970 } else if (level == 3) { 2971 ct.ct_label = l3_cache_str; 2972 } 2973 2974 (void) add_cacheent_props(arg, 2975 (const struct cachetab *) (&ct)); 2976 } 2977 } 2978 } 2979 2980 static const char fully_assoc[] = "fully-associative?"; 2981 2982 /* 2983 * AMD style cache/tlb description 2984 * 2985 * Extended functions 5 and 6 directly describe properties of 2986 * tlbs and various cache levels. 2987 */ 2988 static void 2989 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 2990 { 2991 switch (assoc) { 2992 case 0: /* reserved; ignore */ 2993 break; 2994 default: 2995 add_cache_prop(devi, label, assoc_str, assoc); 2996 break; 2997 case 0xff: 2998 add_cache_prop(devi, label, fully_assoc, 1); 2999 break; 3000 } 3001 } 3002 3003 static void 3004 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3005 { 3006 if (size == 0) 3007 return; 3008 add_cache_prop(devi, label, size_str, size); 3009 add_amd_assoc(devi, label, assoc); 3010 } 3011 3012 static void 3013 add_amd_cache(dev_info_t *devi, const char *label, 3014 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3015 { 3016 if (size == 0 || line_size == 0) 3017 return; 3018 add_amd_assoc(devi, label, assoc); 3019 /* 3020 * Most AMD parts have a sectored cache. Multiple cache lines are 3021 * associated with each tag. A sector consists of all cache lines 3022 * associated with a tag. For example, the AMD K6-III has a sector 3023 * size of 2 cache lines per tag. 3024 */ 3025 if (lines_per_tag != 0) 3026 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3027 add_cache_prop(devi, label, line_str, line_size); 3028 add_cache_prop(devi, label, size_str, size * 1024); 3029 } 3030 3031 static void 3032 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3033 { 3034 switch (assoc) { 3035 case 0: /* off */ 3036 break; 3037 case 1: 3038 case 2: 3039 case 4: 3040 add_cache_prop(devi, label, assoc_str, assoc); 3041 break; 3042 case 6: 3043 add_cache_prop(devi, label, assoc_str, 8); 3044 break; 3045 case 8: 3046 add_cache_prop(devi, label, assoc_str, 16); 3047 break; 3048 case 0xf: 3049 add_cache_prop(devi, label, fully_assoc, 1); 3050 break; 3051 default: /* reserved; ignore */ 3052 break; 3053 } 3054 } 3055 3056 static void 3057 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3058 { 3059 if (size == 0 || assoc == 0) 3060 return; 3061 add_amd_l2_assoc(devi, label, assoc); 3062 add_cache_prop(devi, label, size_str, size); 3063 } 3064 3065 static void 3066 add_amd_l2_cache(dev_info_t *devi, const char *label, 3067 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3068 { 3069 if (size == 0 || assoc == 0 || line_size == 0) 3070 return; 3071 add_amd_l2_assoc(devi, label, assoc); 3072 if (lines_per_tag != 0) 3073 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3074 add_cache_prop(devi, label, line_str, line_size); 3075 add_cache_prop(devi, label, size_str, size * 1024); 3076 } 3077 3078 static void 3079 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 3080 { 3081 struct cpuid_regs *cp; 3082 3083 if (cpi->cpi_xmaxeax < 0x80000005) 3084 return; 3085 cp = &cpi->cpi_extd[5]; 3086 3087 /* 3088 * 4M/2M L1 TLB configuration 3089 * 3090 * We report the size for 2M pages because AMD uses two 3091 * TLB entries for one 4M page. 3092 */ 3093 add_amd_tlb(devi, "dtlb-2M", 3094 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 3095 add_amd_tlb(devi, "itlb-2M", 3096 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 3097 3098 /* 3099 * 4K L1 TLB configuration 3100 */ 3101 3102 switch (cpi->cpi_vendor) { 3103 uint_t nentries; 3104 case X86_VENDOR_TM: 3105 if (cpi->cpi_family >= 5) { 3106 /* 3107 * Crusoe processors have 256 TLB entries, but 3108 * cpuid data format constrains them to only 3109 * reporting 255 of them. 3110 */ 3111 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 3112 nentries = 256; 3113 /* 3114 * Crusoe processors also have a unified TLB 3115 */ 3116 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 3117 nentries); 3118 break; 3119 } 3120 /*FALLTHROUGH*/ 3121 default: 3122 add_amd_tlb(devi, itlb4k_str, 3123 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 3124 add_amd_tlb(devi, dtlb4k_str, 3125 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 3126 break; 3127 } 3128 3129 /* 3130 * data L1 cache configuration 3131 */ 3132 3133 add_amd_cache(devi, l1_dcache_str, 3134 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 3135 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 3136 3137 /* 3138 * code L1 cache configuration 3139 */ 3140 3141 add_amd_cache(devi, l1_icache_str, 3142 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 3143 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 3144 3145 if (cpi->cpi_xmaxeax < 0x80000006) 3146 return; 3147 cp = &cpi->cpi_extd[6]; 3148 3149 /* Check for a unified L2 TLB for large pages */ 3150 3151 if (BITX(cp->cp_eax, 31, 16) == 0) 3152 add_amd_l2_tlb(devi, "l2-tlb-2M", 3153 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3154 else { 3155 add_amd_l2_tlb(devi, "l2-dtlb-2M", 3156 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3157 add_amd_l2_tlb(devi, "l2-itlb-2M", 3158 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3159 } 3160 3161 /* Check for a unified L2 TLB for 4K pages */ 3162 3163 if (BITX(cp->cp_ebx, 31, 16) == 0) { 3164 add_amd_l2_tlb(devi, "l2-tlb-4K", 3165 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3166 } else { 3167 add_amd_l2_tlb(devi, "l2-dtlb-4K", 3168 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3169 add_amd_l2_tlb(devi, "l2-itlb-4K", 3170 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3171 } 3172 3173 add_amd_l2_cache(devi, l2_cache_str, 3174 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 3175 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 3176 } 3177 3178 /* 3179 * There are two basic ways that the x86 world describes it cache 3180 * and tlb architecture - Intel's way and AMD's way. 3181 * 3182 * Return which flavor of cache architecture we should use 3183 */ 3184 static int 3185 x86_which_cacheinfo(struct cpuid_info *cpi) 3186 { 3187 switch (cpi->cpi_vendor) { 3188 case X86_VENDOR_Intel: 3189 if (cpi->cpi_maxeax >= 2) 3190 return (X86_VENDOR_Intel); 3191 break; 3192 case X86_VENDOR_AMD: 3193 /* 3194 * The K5 model 1 was the first part from AMD that reported 3195 * cache sizes via extended cpuid functions. 3196 */ 3197 if (cpi->cpi_family > 5 || 3198 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 3199 return (X86_VENDOR_AMD); 3200 break; 3201 case X86_VENDOR_TM: 3202 if (cpi->cpi_family >= 5) 3203 return (X86_VENDOR_AMD); 3204 /*FALLTHROUGH*/ 3205 default: 3206 /* 3207 * If they have extended CPU data for 0x80000005 3208 * then we assume they have AMD-format cache 3209 * information. 3210 * 3211 * If not, and the vendor happens to be Cyrix, 3212 * then try our-Cyrix specific handler. 3213 * 3214 * If we're not Cyrix, then assume we're using Intel's 3215 * table-driven format instead. 3216 */ 3217 if (cpi->cpi_xmaxeax >= 0x80000005) 3218 return (X86_VENDOR_AMD); 3219 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 3220 return (X86_VENDOR_Cyrix); 3221 else if (cpi->cpi_maxeax >= 2) 3222 return (X86_VENDOR_Intel); 3223 break; 3224 } 3225 return (-1); 3226 } 3227 3228 /* 3229 * create a node for the given cpu under the prom root node. 3230 * Also, create a cpu node in the device tree. 3231 */ 3232 static dev_info_t *cpu_nex_devi = NULL; 3233 static kmutex_t cpu_node_lock; 3234 3235 /* 3236 * Called from post_startup() and mp_startup() 3237 */ 3238 void 3239 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 3240 { 3241 dev_info_t *cpu_devi; 3242 int create; 3243 3244 mutex_enter(&cpu_node_lock); 3245 3246 /* 3247 * create a nexus node for all cpus identified as 'cpu_id' under 3248 * the root node. 3249 */ 3250 if (cpu_nex_devi == NULL) { 3251 if (ndi_devi_alloc(ddi_root_node(), "cpus", 3252 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 3253 mutex_exit(&cpu_node_lock); 3254 return; 3255 } 3256 (void) ndi_devi_online(cpu_nex_devi, 0); 3257 } 3258 3259 /* 3260 * create a child node for cpu identified as 'cpu_id' 3261 */ 3262 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 3263 cpu_id); 3264 if (cpu_devi == NULL) { 3265 mutex_exit(&cpu_node_lock); 3266 return; 3267 } 3268 3269 /* device_type */ 3270 3271 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3272 "device_type", "cpu"); 3273 3274 /* reg */ 3275 3276 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3277 "reg", cpu_id); 3278 3279 /* cpu-mhz, and clock-frequency */ 3280 3281 if (cpu_freq > 0) { 3282 long long mul; 3283 3284 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3285 "cpu-mhz", cpu_freq); 3286 3287 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 3288 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3289 "clock-frequency", (int)mul); 3290 } 3291 3292 (void) ndi_devi_online(cpu_devi, 0); 3293 3294 if ((x86_feature & X86_CPUID) == 0) { 3295 mutex_exit(&cpu_node_lock); 3296 return; 3297 } 3298 3299 /* vendor-id */ 3300 3301 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3302 "vendor-id", cpi->cpi_vendorstr); 3303 3304 if (cpi->cpi_maxeax == 0) { 3305 mutex_exit(&cpu_node_lock); 3306 return; 3307 } 3308 3309 /* 3310 * family, model, and step 3311 */ 3312 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3313 "family", CPI_FAMILY(cpi)); 3314 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3315 "cpu-model", CPI_MODEL(cpi)); 3316 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3317 "stepping-id", CPI_STEP(cpi)); 3318 3319 /* type */ 3320 3321 switch (cpi->cpi_vendor) { 3322 case X86_VENDOR_Intel: 3323 create = 1; 3324 break; 3325 default: 3326 create = 0; 3327 break; 3328 } 3329 if (create) 3330 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3331 "type", CPI_TYPE(cpi)); 3332 3333 /* ext-family */ 3334 3335 switch (cpi->cpi_vendor) { 3336 case X86_VENDOR_Intel: 3337 case X86_VENDOR_AMD: 3338 create = cpi->cpi_family >= 0xf; 3339 break; 3340 default: 3341 create = 0; 3342 break; 3343 } 3344 if (create) 3345 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3346 "ext-family", CPI_FAMILY_XTD(cpi)); 3347 3348 /* ext-model */ 3349 3350 switch (cpi->cpi_vendor) { 3351 case X86_VENDOR_Intel: 3352 create = CPI_MODEL(cpi) == 0xf; 3353 break; 3354 case X86_VENDOR_AMD: 3355 create = CPI_FAMILY(cpi) == 0xf; 3356 break; 3357 default: 3358 create = 0; 3359 break; 3360 } 3361 if (create) 3362 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3363 "ext-model", CPI_MODEL_XTD(cpi)); 3364 3365 /* generation */ 3366 3367 switch (cpi->cpi_vendor) { 3368 case X86_VENDOR_AMD: 3369 /* 3370 * AMD K5 model 1 was the first part to support this 3371 */ 3372 create = cpi->cpi_xmaxeax >= 0x80000001; 3373 break; 3374 default: 3375 create = 0; 3376 break; 3377 } 3378 if (create) 3379 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3380 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 3381 3382 /* brand-id */ 3383 3384 switch (cpi->cpi_vendor) { 3385 case X86_VENDOR_Intel: 3386 /* 3387 * brand id first appeared on Pentium III Xeon model 8, 3388 * and Celeron model 8 processors and Opteron 3389 */ 3390 create = cpi->cpi_family > 6 || 3391 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 3392 break; 3393 case X86_VENDOR_AMD: 3394 create = cpi->cpi_family >= 0xf; 3395 break; 3396 default: 3397 create = 0; 3398 break; 3399 } 3400 if (create && cpi->cpi_brandid != 0) { 3401 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3402 "brand-id", cpi->cpi_brandid); 3403 } 3404 3405 /* chunks, and apic-id */ 3406 3407 switch (cpi->cpi_vendor) { 3408 /* 3409 * first available on Pentium IV and Opteron (K8) 3410 */ 3411 case X86_VENDOR_Intel: 3412 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3413 break; 3414 case X86_VENDOR_AMD: 3415 create = cpi->cpi_family >= 0xf; 3416 break; 3417 default: 3418 create = 0; 3419 break; 3420 } 3421 if (create) { 3422 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3423 "chunks", CPI_CHUNKS(cpi)); 3424 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3425 "apic-id", CPI_APIC_ID(cpi)); 3426 if (cpi->cpi_chipid >= 0) { 3427 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3428 "chip#", cpi->cpi_chipid); 3429 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3430 "clog#", cpi->cpi_clogid); 3431 } 3432 } 3433 3434 /* cpuid-features */ 3435 3436 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3437 "cpuid-features", CPI_FEATURES_EDX(cpi)); 3438 3439 3440 /* cpuid-features-ecx */ 3441 3442 switch (cpi->cpi_vendor) { 3443 case X86_VENDOR_Intel: 3444 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3445 break; 3446 default: 3447 create = 0; 3448 break; 3449 } 3450 if (create) 3451 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3452 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 3453 3454 /* ext-cpuid-features */ 3455 3456 switch (cpi->cpi_vendor) { 3457 case X86_VENDOR_Intel: 3458 case X86_VENDOR_AMD: 3459 case X86_VENDOR_Cyrix: 3460 case X86_VENDOR_TM: 3461 case X86_VENDOR_Centaur: 3462 create = cpi->cpi_xmaxeax >= 0x80000001; 3463 break; 3464 default: 3465 create = 0; 3466 break; 3467 } 3468 if (create) { 3469 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3470 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 3471 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3472 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 3473 } 3474 3475 /* 3476 * Brand String first appeared in Intel Pentium IV, AMD K5 3477 * model 1, and Cyrix GXm. On earlier models we try and 3478 * simulate something similar .. so this string should always 3479 * same -something- about the processor, however lame. 3480 */ 3481 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3482 "brand-string", cpi->cpi_brandstr); 3483 3484 /* 3485 * Finally, cache and tlb information 3486 */ 3487 switch (x86_which_cacheinfo(cpi)) { 3488 case X86_VENDOR_Intel: 3489 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3490 break; 3491 case X86_VENDOR_Cyrix: 3492 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3493 break; 3494 case X86_VENDOR_AMD: 3495 amd_cache_info(cpi, cpu_devi); 3496 break; 3497 default: 3498 break; 3499 } 3500 3501 mutex_exit(&cpu_node_lock); 3502 } 3503 3504 struct l2info { 3505 int *l2i_csz; 3506 int *l2i_lsz; 3507 int *l2i_assoc; 3508 int l2i_ret; 3509 }; 3510 3511 /* 3512 * A cacheinfo walker that fetches the size, line-size and associativity 3513 * of the L2 cache 3514 */ 3515 static int 3516 intel_l2cinfo(void *arg, const struct cachetab *ct) 3517 { 3518 struct l2info *l2i = arg; 3519 int *ip; 3520 3521 if (ct->ct_label != l2_cache_str && 3522 ct->ct_label != sl2_cache_str) 3523 return (0); /* not an L2 -- keep walking */ 3524 3525 if ((ip = l2i->l2i_csz) != NULL) 3526 *ip = ct->ct_size; 3527 if ((ip = l2i->l2i_lsz) != NULL) 3528 *ip = ct->ct_line_size; 3529 if ((ip = l2i->l2i_assoc) != NULL) 3530 *ip = ct->ct_assoc; 3531 l2i->l2i_ret = ct->ct_size; 3532 return (1); /* was an L2 -- terminate walk */ 3533 } 3534 3535 /* 3536 * AMD L2/L3 Cache and TLB Associativity Field Definition: 3537 * 3538 * Unlike the associativity for the L1 cache and tlb where the 8 bit 3539 * value is the associativity, the associativity for the L2 cache and 3540 * tlb is encoded in the following table. The 4 bit L2 value serves as 3541 * an index into the amd_afd[] array to determine the associativity. 3542 * -1 is undefined. 0 is fully associative. 3543 */ 3544 3545 static int amd_afd[] = 3546 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; 3547 3548 static void 3549 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 3550 { 3551 struct cpuid_regs *cp; 3552 uint_t size, assoc; 3553 int i; 3554 int *ip; 3555 3556 if (cpi->cpi_xmaxeax < 0x80000006) 3557 return; 3558 cp = &cpi->cpi_extd[6]; 3559 3560 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && 3561 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 3562 uint_t cachesz = size * 1024; 3563 assoc = amd_afd[i]; 3564 3565 ASSERT(assoc != -1); 3566 3567 if ((ip = l2i->l2i_csz) != NULL) 3568 *ip = cachesz; 3569 if ((ip = l2i->l2i_lsz) != NULL) 3570 *ip = BITX(cp->cp_ecx, 7, 0); 3571 if ((ip = l2i->l2i_assoc) != NULL) 3572 *ip = assoc; 3573 l2i->l2i_ret = cachesz; 3574 } 3575 } 3576 3577 int 3578 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 3579 { 3580 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3581 struct l2info __l2info, *l2i = &__l2info; 3582 3583 l2i->l2i_csz = csz; 3584 l2i->l2i_lsz = lsz; 3585 l2i->l2i_assoc = assoc; 3586 l2i->l2i_ret = -1; 3587 3588 switch (x86_which_cacheinfo(cpi)) { 3589 case X86_VENDOR_Intel: 3590 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3591 break; 3592 case X86_VENDOR_Cyrix: 3593 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3594 break; 3595 case X86_VENDOR_AMD: 3596 amd_l2cacheinfo(cpi, l2i); 3597 break; 3598 default: 3599 break; 3600 } 3601 return (l2i->l2i_ret); 3602 } 3603 3604 #if !defined(__xpv) 3605 3606 uint32_t * 3607 cpuid_mwait_alloc(cpu_t *cpu) 3608 { 3609 uint32_t *ret; 3610 size_t mwait_size; 3611 3612 ASSERT(cpuid_checkpass(cpu, 2)); 3613 3614 mwait_size = cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max; 3615 if (mwait_size == 0) 3616 return (NULL); 3617 3618 /* 3619 * kmem_alloc() returns cache line size aligned data for mwait_size 3620 * allocations. mwait_size is currently cache line sized. Neither 3621 * of these implementation details are guarantied to be true in the 3622 * future. 3623 * 3624 * First try allocating mwait_size as kmem_alloc() currently returns 3625 * correctly aligned memory. If kmem_alloc() does not return 3626 * mwait_size aligned memory, then use mwait_size ROUNDUP. 3627 * 3628 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we 3629 * decide to free this memory. 3630 */ 3631 ret = kmem_zalloc(mwait_size, KM_SLEEP); 3632 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { 3633 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3634 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; 3635 *ret = MWAIT_RUNNING; 3636 return (ret); 3637 } else { 3638 kmem_free(ret, mwait_size); 3639 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); 3640 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3641 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; 3642 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); 3643 *ret = MWAIT_RUNNING; 3644 return (ret); 3645 } 3646 } 3647 3648 void 3649 cpuid_mwait_free(cpu_t *cpu) 3650 { 3651 ASSERT(cpuid_checkpass(cpu, 2)); 3652 3653 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && 3654 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { 3655 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, 3656 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); 3657 } 3658 3659 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; 3660 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; 3661 } 3662 3663 #endif /* !__xpv */ 3664