1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * Various routines to handle identification 28 * and classification of x86 processors. 29 */ 30 31 #include <sys/types.h> 32 #include <sys/archsystm.h> 33 #include <sys/x86_archext.h> 34 #include <sys/kmem.h> 35 #include <sys/systm.h> 36 #include <sys/cmn_err.h> 37 #include <sys/sunddi.h> 38 #include <sys/sunndi.h> 39 #include <sys/cpuvar.h> 40 #include <sys/processor.h> 41 #include <sys/sysmacros.h> 42 #include <sys/pg.h> 43 #include <sys/fp.h> 44 #include <sys/controlregs.h> 45 #include <sys/auxv_386.h> 46 #include <sys/bitmap.h> 47 #include <sys/memnode.h> 48 49 #ifdef __xpv 50 #include <sys/hypervisor.h> 51 #endif 52 53 /* 54 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 55 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 56 * them accordingly. For most modern processors, feature detection occurs here 57 * in pass 1. 58 * 59 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 60 * for the boot CPU and does the basic analysis that the early kernel needs. 61 * x86_feature is set based on the return value of cpuid_pass1() of the boot 62 * CPU. 63 * 64 * Pass 1 includes: 65 * 66 * o Determining vendor/model/family/stepping and setting x86_type and 67 * x86_vendor accordingly. 68 * o Processing the feature flags returned by the cpuid instruction while 69 * applying any workarounds or tricks for the specific processor. 70 * o Mapping the feature flags into Solaris feature bits (X86_*). 71 * o Processing extended feature flags if supported by the processor, 72 * again while applying specific processor knowledge. 73 * o Determining the CMT characteristics of the system. 74 * 75 * Pass 1 is done on non-boot CPUs during their initialization and the results 76 * are used only as a meager attempt at ensuring that all processors within the 77 * system support the same features. 78 * 79 * Pass 2 of cpuid feature analysis happens just at the beginning 80 * of startup(). It just copies in and corrects the remainder 81 * of the cpuid data we depend on: standard cpuid functions that we didn't 82 * need for pass1 feature analysis, and extended cpuid functions beyond the 83 * simple feature processing done in pass1. 84 * 85 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 86 * particular kernel memory allocation has been made available. It creates a 87 * readable brand string based on the data collected in the first two passes. 88 * 89 * Pass 4 of cpuid analysis is invoked after post_startup() when all 90 * the support infrastructure for various hardware features has been 91 * initialized. It determines which processor features will be reported 92 * to userland via the aux vector. 93 * 94 * All passes are executed on all CPUs, but only the boot CPU determines what 95 * features the kernel will use. 96 * 97 * Much of the worst junk in this file is for the support of processors 98 * that didn't really implement the cpuid instruction properly. 99 * 100 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 101 * the pass numbers. Accordingly, changes to the pass code may require changes 102 * to the accessor code. 103 */ 104 105 uint_t x86_feature = 0; 106 uint_t x86_vendor = X86_VENDOR_IntelClone; 107 uint_t x86_type = X86_TYPE_OTHER; 108 uint_t x86_clflush_size = 0; 109 110 uint_t pentiumpro_bug4046376; 111 uint_t pentiumpro_bug4064495; 112 113 uint_t enable486; 114 115 /* 116 * monitor/mwait info. 117 * 118 * size_actual and buf_actual are the real address and size allocated to get 119 * proper mwait_buf alignement. buf_actual and size_actual should be passed 120 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use 121 * processor cache-line alignment, but this is not guarantied in the furture. 122 */ 123 struct mwait_info { 124 size_t mon_min; /* min size to avoid missed wakeups */ 125 size_t mon_max; /* size to avoid false wakeups */ 126 size_t size_actual; /* size actually allocated */ 127 void *buf_actual; /* memory actually allocated */ 128 uint32_t support; /* processor support of monitor/mwait */ 129 }; 130 131 /* 132 * These constants determine how many of the elements of the 133 * cpuid we cache in the cpuid_info data structure; the 134 * remaining elements are accessible via the cpuid instruction. 135 */ 136 137 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 138 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 139 140 struct cpuid_info { 141 uint_t cpi_pass; /* last pass completed */ 142 /* 143 * standard function information 144 */ 145 uint_t cpi_maxeax; /* fn 0: %eax */ 146 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 147 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 148 149 uint_t cpi_family; /* fn 1: extended family */ 150 uint_t cpi_model; /* fn 1: extended model */ 151 uint_t cpi_step; /* fn 1: stepping */ 152 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 153 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 154 int cpi_clogid; /* fn 1: %ebx: thread # */ 155 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 156 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 157 uint_t cpi_ncache; /* fn 2: number of elements */ 158 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 159 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 160 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 161 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 162 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 163 /* 164 * extended function information 165 */ 166 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 167 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 168 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 169 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 170 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 171 id_t cpi_coreid; /* same coreid => strands share core */ 172 int cpi_pkgcoreid; /* core number within single package */ 173 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 174 /* Intel: fn 4: %eax[31-26] */ 175 /* 176 * supported feature information 177 */ 178 uint32_t cpi_support[5]; 179 #define STD_EDX_FEATURES 0 180 #define AMD_EDX_FEATURES 1 181 #define TM_EDX_FEATURES 2 182 #define STD_ECX_FEATURES 3 183 #define AMD_ECX_FEATURES 4 184 /* 185 * Synthesized information, where known. 186 */ 187 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 188 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 189 uint32_t cpi_socket; /* Chip package/socket type */ 190 191 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 192 uint32_t cpi_apicid; 193 }; 194 195 196 static struct cpuid_info cpuid_info0; 197 198 /* 199 * These bit fields are defined by the Intel Application Note AP-485 200 * "Intel Processor Identification and the CPUID Instruction" 201 */ 202 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 203 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 204 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 205 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 206 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 207 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 208 209 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 210 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 211 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 212 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 213 214 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 215 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 216 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 217 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 218 219 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 220 #define CPI_XMAXEAX_MAX 0x80000100 221 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 222 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */ 223 224 /* 225 * Function 4 (Deterministic Cache Parameters) macros 226 * Defined by Intel Application Note AP-485 227 */ 228 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 229 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 230 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 231 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 232 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 233 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 234 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8) 235 236 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 237 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 238 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 239 240 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 241 242 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 243 244 245 /* 246 * A couple of shorthand macros to identify "later" P6-family chips 247 * like the Pentium M and Core. First, the "older" P6-based stuff 248 * (loosely defined as "pre-Pentium-4"): 249 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 250 */ 251 252 #define IS_LEGACY_P6(cpi) ( \ 253 cpi->cpi_family == 6 && \ 254 (cpi->cpi_model == 1 || \ 255 cpi->cpi_model == 3 || \ 256 cpi->cpi_model == 5 || \ 257 cpi->cpi_model == 6 || \ 258 cpi->cpi_model == 7 || \ 259 cpi->cpi_model == 8 || \ 260 cpi->cpi_model == 0xA || \ 261 cpi->cpi_model == 0xB) \ 262 ) 263 264 /* A "new F6" is everything with family 6 that's not the above */ 265 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 266 267 /* Extended family/model support */ 268 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ 269 cpi->cpi_family >= 0xf) 270 271 /* 272 * Info for monitor/mwait idle loop. 273 * 274 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 275 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 276 * 2006. 277 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 278 * Documentation Updates" #33633, Rev 2.05, December 2006. 279 */ 280 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 281 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 282 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 283 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 284 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 285 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 286 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 287 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 288 /* 289 * Number of sub-cstates for a given c-state. 290 */ 291 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 292 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 293 294 /* 295 * Functions we consune from cpuid_subr.c; don't publish these in a header 296 * file to try and keep people using the expected cpuid_* interfaces. 297 */ 298 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t); 299 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t); 300 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t); 301 extern uint_t _cpuid_vendorstr_to_vendorcode(char *); 302 303 /* 304 * Apply up various platform-dependent restrictions where the 305 * underlying platform restrictions mean the CPU can be marked 306 * as less capable than its cpuid instruction would imply. 307 */ 308 #if defined(__xpv) 309 static void 310 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) 311 { 312 switch (eax) { 313 case 1: { 314 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ? 315 0 : CPUID_INTC_EDX_MCA; 316 cp->cp_edx &= 317 ~(mcamask | 318 CPUID_INTC_EDX_PSE | 319 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 320 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | 321 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | 322 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 323 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); 324 break; 325 } 326 327 case 0x80000001: 328 cp->cp_edx &= 329 ~(CPUID_AMD_EDX_PSE | 330 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 331 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | 332 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | 333 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 334 CPUID_AMD_EDX_TSCP); 335 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; 336 break; 337 default: 338 break; 339 } 340 341 switch (vendor) { 342 case X86_VENDOR_Intel: 343 switch (eax) { 344 case 4: 345 /* 346 * Zero out the (ncores-per-chip - 1) field 347 */ 348 cp->cp_eax &= 0x03fffffff; 349 break; 350 default: 351 break; 352 } 353 break; 354 case X86_VENDOR_AMD: 355 switch (eax) { 356 case 0x80000008: 357 /* 358 * Zero out the (ncores-per-chip - 1) field 359 */ 360 cp->cp_ecx &= 0xffffff00; 361 break; 362 default: 363 break; 364 } 365 break; 366 default: 367 break; 368 } 369 } 370 #else 371 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 372 #endif 373 374 /* 375 * Some undocumented ways of patching the results of the cpuid 376 * instruction to permit running Solaris 10 on future cpus that 377 * we don't currently support. Could be set to non-zero values 378 * via settings in eeprom. 379 */ 380 381 uint32_t cpuid_feature_ecx_include; 382 uint32_t cpuid_feature_ecx_exclude; 383 uint32_t cpuid_feature_edx_include; 384 uint32_t cpuid_feature_edx_exclude; 385 386 void 387 cpuid_alloc_space(cpu_t *cpu) 388 { 389 /* 390 * By convention, cpu0 is the boot cpu, which is set up 391 * before memory allocation is available. All other cpus get 392 * their cpuid_info struct allocated here. 393 */ 394 ASSERT(cpu->cpu_id != 0); 395 cpu->cpu_m.mcpu_cpi = 396 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 397 } 398 399 void 400 cpuid_free_space(cpu_t *cpu) 401 { 402 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 403 int i; 404 405 ASSERT(cpu->cpu_id != 0); 406 407 /* 408 * Free up any function 4 related dynamic storage 409 */ 410 for (i = 1; i < cpi->cpi_std_4_size; i++) 411 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 412 if (cpi->cpi_std_4_size > 0) 413 kmem_free(cpi->cpi_std_4, 414 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 415 416 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); 417 } 418 419 #if !defined(__xpv) 420 421 static void 422 check_for_hvm() 423 { 424 struct cpuid_regs cp; 425 char *xen_str; 426 uint32_t xen_signature[4]; 427 extern int xpv_is_hvm; 428 429 /* 430 * In a fully virtualized domain, Xen's pseudo-cpuid function 431 * 0x40000000 returns a string representing the Xen signature in 432 * %ebx, %ecx, and %edx. %eax contains the maximum supported cpuid 433 * function. 434 */ 435 cp.cp_eax = 0x40000000; 436 (void) __cpuid_insn(&cp); 437 xen_signature[0] = cp.cp_ebx; 438 xen_signature[1] = cp.cp_ecx; 439 xen_signature[2] = cp.cp_edx; 440 xen_signature[3] = 0; 441 xen_str = (char *)xen_signature; 442 if (strcmp("XenVMMXenVMM", xen_str) == 0 && cp.cp_eax <= 0x40000002) 443 xpv_is_hvm = 1; 444 } 445 #endif /* __xpv */ 446 447 uint_t 448 cpuid_pass1(cpu_t *cpu) 449 { 450 uint32_t mask_ecx, mask_edx; 451 uint_t feature = X86_CPUID; 452 struct cpuid_info *cpi; 453 struct cpuid_regs *cp; 454 int xcpuid; 455 #if !defined(__xpv) 456 extern int idle_cpu_prefer_mwait; 457 #endif 458 459 /* 460 * Space statically allocated for cpu0, ensure pointer is set 461 */ 462 if (cpu->cpu_id == 0) 463 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 464 cpi = cpu->cpu_m.mcpu_cpi; 465 ASSERT(cpi != NULL); 466 cp = &cpi->cpi_std[0]; 467 cp->cp_eax = 0; 468 cpi->cpi_maxeax = __cpuid_insn(cp); 469 { 470 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 471 *iptr++ = cp->cp_ebx; 472 *iptr++ = cp->cp_edx; 473 *iptr++ = cp->cp_ecx; 474 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 475 } 476 477 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr); 478 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 479 480 /* 481 * Limit the range in case of weird hardware 482 */ 483 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 484 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 485 if (cpi->cpi_maxeax < 1) 486 goto pass1_done; 487 488 cp = &cpi->cpi_std[1]; 489 cp->cp_eax = 1; 490 (void) __cpuid_insn(cp); 491 492 /* 493 * Extract identifying constants for easy access. 494 */ 495 cpi->cpi_model = CPI_MODEL(cpi); 496 cpi->cpi_family = CPI_FAMILY(cpi); 497 498 if (cpi->cpi_family == 0xf) 499 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 500 501 /* 502 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 503 * Intel, and presumably everyone else, uses model == 0xf, as 504 * one would expect (max value means possible overflow). Sigh. 505 */ 506 507 switch (cpi->cpi_vendor) { 508 case X86_VENDOR_Intel: 509 if (IS_EXTENDED_MODEL_INTEL(cpi)) 510 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 511 break; 512 case X86_VENDOR_AMD: 513 if (CPI_FAMILY(cpi) == 0xf) 514 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 515 break; 516 default: 517 if (cpi->cpi_model == 0xf) 518 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 519 break; 520 } 521 522 cpi->cpi_step = CPI_STEP(cpi); 523 cpi->cpi_brandid = CPI_BRANDID(cpi); 524 525 /* 526 * *default* assumptions: 527 * - believe %edx feature word 528 * - ignore %ecx feature word 529 * - 32-bit virtual and physical addressing 530 */ 531 mask_edx = 0xffffffff; 532 mask_ecx = 0; 533 534 cpi->cpi_pabits = cpi->cpi_vabits = 32; 535 536 switch (cpi->cpi_vendor) { 537 case X86_VENDOR_Intel: 538 if (cpi->cpi_family == 5) 539 x86_type = X86_TYPE_P5; 540 else if (IS_LEGACY_P6(cpi)) { 541 x86_type = X86_TYPE_P6; 542 pentiumpro_bug4046376 = 1; 543 pentiumpro_bug4064495 = 1; 544 /* 545 * Clear the SEP bit when it was set erroneously 546 */ 547 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 548 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 549 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 550 x86_type = X86_TYPE_P4; 551 /* 552 * We don't currently depend on any of the %ecx 553 * features until Prescott, so we'll only check 554 * this from P4 onwards. We might want to revisit 555 * that idea later. 556 */ 557 mask_ecx = 0xffffffff; 558 } else if (cpi->cpi_family > 0xf) 559 mask_ecx = 0xffffffff; 560 /* 561 * We don't support MONITOR/MWAIT if leaf 5 is not available 562 * to obtain the monitor linesize. 563 */ 564 if (cpi->cpi_maxeax < 5) 565 mask_ecx &= ~CPUID_INTC_ECX_MON; 566 break; 567 case X86_VENDOR_IntelClone: 568 default: 569 break; 570 case X86_VENDOR_AMD: 571 #if defined(OPTERON_ERRATUM_108) 572 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 573 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 574 cpi->cpi_model = 0xc; 575 } else 576 #endif 577 if (cpi->cpi_family == 5) { 578 /* 579 * AMD K5 and K6 580 * 581 * These CPUs have an incomplete implementation 582 * of MCA/MCE which we mask away. 583 */ 584 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 585 586 /* 587 * Model 0 uses the wrong (APIC) bit 588 * to indicate PGE. Fix it here. 589 */ 590 if (cpi->cpi_model == 0) { 591 if (cp->cp_edx & 0x200) { 592 cp->cp_edx &= ~0x200; 593 cp->cp_edx |= CPUID_INTC_EDX_PGE; 594 } 595 } 596 597 /* 598 * Early models had problems w/ MMX; disable. 599 */ 600 if (cpi->cpi_model < 6) 601 mask_edx &= ~CPUID_INTC_EDX_MMX; 602 } 603 604 /* 605 * For newer families, SSE3 and CX16, at least, are valid; 606 * enable all 607 */ 608 if (cpi->cpi_family >= 0xf) 609 mask_ecx = 0xffffffff; 610 /* 611 * We don't support MONITOR/MWAIT if leaf 5 is not available 612 * to obtain the monitor linesize. 613 */ 614 if (cpi->cpi_maxeax < 5) 615 mask_ecx &= ~CPUID_INTC_ECX_MON; 616 617 #if !defined(__xpv) 618 /* 619 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD 620 * processors. AMD does not intend MWAIT to be used in the cpu 621 * idle loop on current and future processors. 10h and future 622 * AMD processors use more power in MWAIT than HLT. 623 * Pre-family-10h Opterons do not have the MWAIT instruction. 624 */ 625 idle_cpu_prefer_mwait = 0; 626 #endif 627 628 break; 629 case X86_VENDOR_TM: 630 /* 631 * workaround the NT workaround in CMS 4.1 632 */ 633 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 634 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 635 cp->cp_edx |= CPUID_INTC_EDX_CX8; 636 break; 637 case X86_VENDOR_Centaur: 638 /* 639 * workaround the NT workarounds again 640 */ 641 if (cpi->cpi_family == 6) 642 cp->cp_edx |= CPUID_INTC_EDX_CX8; 643 break; 644 case X86_VENDOR_Cyrix: 645 /* 646 * We rely heavily on the probing in locore 647 * to actually figure out what parts, if any, 648 * of the Cyrix cpuid instruction to believe. 649 */ 650 switch (x86_type) { 651 case X86_TYPE_CYRIX_486: 652 mask_edx = 0; 653 break; 654 case X86_TYPE_CYRIX_6x86: 655 mask_edx = 0; 656 break; 657 case X86_TYPE_CYRIX_6x86L: 658 mask_edx = 659 CPUID_INTC_EDX_DE | 660 CPUID_INTC_EDX_CX8; 661 break; 662 case X86_TYPE_CYRIX_6x86MX: 663 mask_edx = 664 CPUID_INTC_EDX_DE | 665 CPUID_INTC_EDX_MSR | 666 CPUID_INTC_EDX_CX8 | 667 CPUID_INTC_EDX_PGE | 668 CPUID_INTC_EDX_CMOV | 669 CPUID_INTC_EDX_MMX; 670 break; 671 case X86_TYPE_CYRIX_GXm: 672 mask_edx = 673 CPUID_INTC_EDX_MSR | 674 CPUID_INTC_EDX_CX8 | 675 CPUID_INTC_EDX_CMOV | 676 CPUID_INTC_EDX_MMX; 677 break; 678 case X86_TYPE_CYRIX_MediaGX: 679 break; 680 case X86_TYPE_CYRIX_MII: 681 case X86_TYPE_VIA_CYRIX_III: 682 mask_edx = 683 CPUID_INTC_EDX_DE | 684 CPUID_INTC_EDX_TSC | 685 CPUID_INTC_EDX_MSR | 686 CPUID_INTC_EDX_CX8 | 687 CPUID_INTC_EDX_PGE | 688 CPUID_INTC_EDX_CMOV | 689 CPUID_INTC_EDX_MMX; 690 break; 691 default: 692 break; 693 } 694 break; 695 } 696 697 #if defined(__xpv) 698 /* 699 * Do not support MONITOR/MWAIT under a hypervisor 700 */ 701 mask_ecx &= ~CPUID_INTC_ECX_MON; 702 #endif /* __xpv */ 703 704 /* 705 * Now we've figured out the masks that determine 706 * which bits we choose to believe, apply the masks 707 * to the feature words, then map the kernel's view 708 * of these feature words into its feature word. 709 */ 710 cp->cp_edx &= mask_edx; 711 cp->cp_ecx &= mask_ecx; 712 713 /* 714 * apply any platform restrictions (we don't call this 715 * immediately after __cpuid_insn here, because we need the 716 * workarounds applied above first) 717 */ 718 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 719 720 /* 721 * fold in overrides from the "eeprom" mechanism 722 */ 723 cp->cp_edx |= cpuid_feature_edx_include; 724 cp->cp_edx &= ~cpuid_feature_edx_exclude; 725 726 cp->cp_ecx |= cpuid_feature_ecx_include; 727 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 728 729 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 730 feature |= X86_LARGEPAGE; 731 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 732 feature |= X86_TSC; 733 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 734 feature |= X86_MSR; 735 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 736 feature |= X86_MTRR; 737 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 738 feature |= X86_PGE; 739 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 740 feature |= X86_CMOV; 741 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 742 feature |= X86_MMX; 743 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 744 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 745 feature |= X86_MCA; 746 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 747 feature |= X86_PAE; 748 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 749 feature |= X86_CX8; 750 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 751 feature |= X86_CX16; 752 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 753 feature |= X86_PAT; 754 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 755 feature |= X86_SEP; 756 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 757 /* 758 * In our implementation, fxsave/fxrstor 759 * are prerequisites before we'll even 760 * try and do SSE things. 761 */ 762 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 763 feature |= X86_SSE; 764 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 765 feature |= X86_SSE2; 766 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 767 feature |= X86_SSE3; 768 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 769 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) 770 feature |= X86_SSSE3; 771 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) 772 feature |= X86_SSE4_1; 773 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) 774 feature |= X86_SSE4_2; 775 } 776 } 777 if (cp->cp_edx & CPUID_INTC_EDX_DE) 778 feature |= X86_DE; 779 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 780 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 781 feature |= X86_MWAIT; 782 } 783 784 /* 785 * Only need it first time, rest of the cpus would follow suite. 786 * we only capture this for the bootcpu. 787 */ 788 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 789 feature |= X86_CLFSH; 790 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8); 791 } 792 793 if (feature & X86_PAE) 794 cpi->cpi_pabits = 36; 795 796 /* 797 * Hyperthreading configuration is slightly tricky on Intel 798 * and pure clones, and even trickier on AMD. 799 * 800 * (AMD chose to set the HTT bit on their CMP processors, 801 * even though they're not actually hyperthreaded. Thus it 802 * takes a bit more work to figure out what's really going 803 * on ... see the handling of the CMP_LGCY bit below) 804 */ 805 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 806 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 807 if (cpi->cpi_ncpu_per_chip > 1) 808 feature |= X86_HTT; 809 } else { 810 cpi->cpi_ncpu_per_chip = 1; 811 } 812 813 /* 814 * Work on the "extended" feature information, doing 815 * some basic initialization for cpuid_pass2() 816 */ 817 xcpuid = 0; 818 switch (cpi->cpi_vendor) { 819 case X86_VENDOR_Intel: 820 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 821 xcpuid++; 822 break; 823 case X86_VENDOR_AMD: 824 if (cpi->cpi_family > 5 || 825 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 826 xcpuid++; 827 break; 828 case X86_VENDOR_Cyrix: 829 /* 830 * Only these Cyrix CPUs are -known- to support 831 * extended cpuid operations. 832 */ 833 if (x86_type == X86_TYPE_VIA_CYRIX_III || 834 x86_type == X86_TYPE_CYRIX_GXm) 835 xcpuid++; 836 break; 837 case X86_VENDOR_Centaur: 838 case X86_VENDOR_TM: 839 default: 840 xcpuid++; 841 break; 842 } 843 844 if (xcpuid) { 845 cp = &cpi->cpi_extd[0]; 846 cp->cp_eax = 0x80000000; 847 cpi->cpi_xmaxeax = __cpuid_insn(cp); 848 } 849 850 if (cpi->cpi_xmaxeax & 0x80000000) { 851 852 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 853 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 854 855 switch (cpi->cpi_vendor) { 856 case X86_VENDOR_Intel: 857 case X86_VENDOR_AMD: 858 if (cpi->cpi_xmaxeax < 0x80000001) 859 break; 860 cp = &cpi->cpi_extd[1]; 861 cp->cp_eax = 0x80000001; 862 (void) __cpuid_insn(cp); 863 864 if (cpi->cpi_vendor == X86_VENDOR_AMD && 865 cpi->cpi_family == 5 && 866 cpi->cpi_model == 6 && 867 cpi->cpi_step == 6) { 868 /* 869 * K6 model 6 uses bit 10 to indicate SYSC 870 * Later models use bit 11. Fix it here. 871 */ 872 if (cp->cp_edx & 0x400) { 873 cp->cp_edx &= ~0x400; 874 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 875 } 876 } 877 878 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 879 880 /* 881 * Compute the additions to the kernel's feature word. 882 */ 883 if (cp->cp_edx & CPUID_AMD_EDX_NX) 884 feature |= X86_NX; 885 886 /* 887 * Regardless whether or not we boot 64-bit, 888 * we should have a way to identify whether 889 * the CPU is capable of running 64-bit. 890 */ 891 if (cp->cp_edx & CPUID_AMD_EDX_LM) 892 feature |= X86_64; 893 894 #if defined(__amd64) 895 /* 1 GB large page - enable only for 64 bit kernel */ 896 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) 897 feature |= X86_1GPG; 898 #endif 899 900 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 901 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 902 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) 903 feature |= X86_SSE4A; 904 905 /* 906 * If both the HTT and CMP_LGCY bits are set, 907 * then we're not actually HyperThreaded. Read 908 * "AMD CPUID Specification" for more details. 909 */ 910 if (cpi->cpi_vendor == X86_VENDOR_AMD && 911 (feature & X86_HTT) && 912 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 913 feature &= ~X86_HTT; 914 feature |= X86_CMP; 915 } 916 #if defined(__amd64) 917 /* 918 * It's really tricky to support syscall/sysret in 919 * the i386 kernel; we rely on sysenter/sysexit 920 * instead. In the amd64 kernel, things are -way- 921 * better. 922 */ 923 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 924 feature |= X86_ASYSC; 925 926 /* 927 * While we're thinking about system calls, note 928 * that AMD processors don't support sysenter 929 * in long mode at all, so don't try to program them. 930 */ 931 if (x86_vendor == X86_VENDOR_AMD) 932 feature &= ~X86_SEP; 933 #endif 934 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) 935 feature |= X86_TSCP; 936 break; 937 default: 938 break; 939 } 940 941 /* 942 * Get CPUID data about processor cores and hyperthreads. 943 */ 944 switch (cpi->cpi_vendor) { 945 case X86_VENDOR_Intel: 946 if (cpi->cpi_maxeax >= 4) { 947 cp = &cpi->cpi_std[4]; 948 cp->cp_eax = 4; 949 cp->cp_ecx = 0; 950 (void) __cpuid_insn(cp); 951 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 952 } 953 /*FALLTHROUGH*/ 954 case X86_VENDOR_AMD: 955 if (cpi->cpi_xmaxeax < 0x80000008) 956 break; 957 cp = &cpi->cpi_extd[8]; 958 cp->cp_eax = 0x80000008; 959 (void) __cpuid_insn(cp); 960 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 961 962 /* 963 * Virtual and physical address limits from 964 * cpuid override previously guessed values. 965 */ 966 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 967 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 968 break; 969 default: 970 break; 971 } 972 973 /* 974 * Derive the number of cores per chip 975 */ 976 switch (cpi->cpi_vendor) { 977 case X86_VENDOR_Intel: 978 if (cpi->cpi_maxeax < 4) { 979 cpi->cpi_ncore_per_chip = 1; 980 break; 981 } else { 982 cpi->cpi_ncore_per_chip = 983 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 984 } 985 break; 986 case X86_VENDOR_AMD: 987 if (cpi->cpi_xmaxeax < 0x80000008) { 988 cpi->cpi_ncore_per_chip = 1; 989 break; 990 } else { 991 /* 992 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is 993 * 1 less than the number of physical cores on 994 * the chip. In family 0x10 this value can 995 * be affected by "downcoring" - it reflects 996 * 1 less than the number of cores actually 997 * enabled on this node. 998 */ 999 cpi->cpi_ncore_per_chip = 1000 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 1001 } 1002 break; 1003 default: 1004 cpi->cpi_ncore_per_chip = 1; 1005 break; 1006 } 1007 } else { 1008 cpi->cpi_ncore_per_chip = 1; 1009 } 1010 1011 /* 1012 * If more than one core, then this processor is CMP. 1013 */ 1014 if (cpi->cpi_ncore_per_chip > 1) 1015 feature |= X86_CMP; 1016 1017 /* 1018 * If the number of cores is the same as the number 1019 * of CPUs, then we cannot have HyperThreading. 1020 */ 1021 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 1022 feature &= ~X86_HTT; 1023 1024 if ((feature & (X86_HTT | X86_CMP)) == 0) { 1025 /* 1026 * Single-core single-threaded processors. 1027 */ 1028 cpi->cpi_chipid = -1; 1029 cpi->cpi_clogid = 0; 1030 cpi->cpi_coreid = cpu->cpu_id; 1031 cpi->cpi_pkgcoreid = 0; 1032 } else if (cpi->cpi_ncpu_per_chip > 1) { 1033 uint_t i; 1034 uint_t chipid_shift = 0; 1035 uint_t coreid_shift = 0; 1036 uint_t apic_id = CPI_APIC_ID(cpi); 1037 1038 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 1039 chipid_shift++; 1040 cpi->cpi_chipid = apic_id >> chipid_shift; 1041 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 1042 1043 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 1044 if (feature & X86_CMP) { 1045 /* 1046 * Multi-core (and possibly multi-threaded) 1047 * processors. 1048 */ 1049 uint_t ncpu_per_core; 1050 if (cpi->cpi_ncore_per_chip == 1) 1051 ncpu_per_core = cpi->cpi_ncpu_per_chip; 1052 else if (cpi->cpi_ncore_per_chip > 1) 1053 ncpu_per_core = cpi->cpi_ncpu_per_chip / 1054 cpi->cpi_ncore_per_chip; 1055 /* 1056 * 8bit APIC IDs on dual core Pentiums 1057 * look like this: 1058 * 1059 * +-----------------------+------+------+ 1060 * | Physical Package ID | MC | HT | 1061 * +-----------------------+------+------+ 1062 * <------- chipid --------> 1063 * <------- coreid ---------------> 1064 * <--- clogid --> 1065 * <------> 1066 * pkgcoreid 1067 * 1068 * Where the number of bits necessary to 1069 * represent MC and HT fields together equals 1070 * to the minimum number of bits necessary to 1071 * store the value of cpi->cpi_ncpu_per_chip. 1072 * Of those bits, the MC part uses the number 1073 * of bits necessary to store the value of 1074 * cpi->cpi_ncore_per_chip. 1075 */ 1076 for (i = 1; i < ncpu_per_core; i <<= 1) 1077 coreid_shift++; 1078 cpi->cpi_coreid = apic_id >> coreid_shift; 1079 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> 1080 coreid_shift; 1081 } else if (feature & X86_HTT) { 1082 /* 1083 * Single-core multi-threaded processors. 1084 */ 1085 cpi->cpi_coreid = cpi->cpi_chipid; 1086 cpi->cpi_pkgcoreid = 0; 1087 } 1088 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 1089 /* 1090 * AMD CMP chips currently have a single thread per 1091 * core, with 2 cores on family 0xf and 2, 3 or 4 1092 * cores on family 0x10. 1093 * 1094 * Since no two cpus share a core we must assign a 1095 * distinct coreid per cpu, and we do this by using 1096 * the cpu_id. This scheme does not, however, 1097 * guarantee that sibling cores of a chip will have 1098 * sequential coreids starting at a multiple of the 1099 * number of cores per chip - that is usually the 1100 * case, but if the ACPI MADT table is presented 1101 * in a different order then we need to perform a 1102 * few more gymnastics for the pkgcoreid. 1103 * 1104 * In family 0xf CMPs there are 2 cores on all nodes 1105 * present - no mixing of single and dual core parts. 1106 * 1107 * In family 0x10 CMPs cpuid fn 2 ECX[15:12] 1108 * "ApicIdCoreIdSize[3:0]" tells us how 1109 * many least-significant bits in the ApicId 1110 * are used to represent the core number 1111 * within the node. Cores are always 1112 * numbered sequentially from 0 regardless 1113 * of how many or which are disabled, and 1114 * there seems to be no way to discover the 1115 * real core id when some are disabled. 1116 */ 1117 cpi->cpi_coreid = cpu->cpu_id; 1118 1119 if (cpi->cpi_family == 0x10 && 1120 cpi->cpi_xmaxeax >= 0x80000008) { 1121 int coreidsz = 1122 BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12); 1123 1124 cpi->cpi_pkgcoreid = 1125 apic_id & ((1 << coreidsz) - 1); 1126 } else { 1127 cpi->cpi_pkgcoreid = cpi->cpi_clogid; 1128 } 1129 } else { 1130 /* 1131 * All other processors are currently 1132 * assumed to have single cores. 1133 */ 1134 cpi->cpi_coreid = cpi->cpi_chipid; 1135 cpi->cpi_pkgcoreid = 0; 1136 } 1137 } 1138 1139 cpi->cpi_apicid = CPI_APIC_ID(cpi); 1140 1141 /* 1142 * Synthesize chip "revision" and socket type 1143 */ 1144 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family, 1145 cpi->cpi_model, cpi->cpi_step); 1146 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor, 1147 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step); 1148 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family, 1149 cpi->cpi_model, cpi->cpi_step); 1150 1151 pass1_done: 1152 #if !defined(__xpv) 1153 check_for_hvm(); 1154 #endif 1155 cpi->cpi_pass = 1; 1156 return (feature); 1157 } 1158 1159 /* 1160 * Make copies of the cpuid table entries we depend on, in 1161 * part for ease of parsing now, in part so that we have only 1162 * one place to correct any of it, in part for ease of 1163 * later export to userland, and in part so we can look at 1164 * this stuff in a crash dump. 1165 */ 1166 1167 /*ARGSUSED*/ 1168 void 1169 cpuid_pass2(cpu_t *cpu) 1170 { 1171 uint_t n, nmax; 1172 int i; 1173 struct cpuid_regs *cp; 1174 uint8_t *dp; 1175 uint32_t *iptr; 1176 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1177 1178 ASSERT(cpi->cpi_pass == 1); 1179 1180 if (cpi->cpi_maxeax < 1) 1181 goto pass2_done; 1182 1183 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1184 nmax = NMAX_CPI_STD; 1185 /* 1186 * (We already handled n == 0 and n == 1 in pass 1) 1187 */ 1188 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1189 cp->cp_eax = n; 1190 1191 /* 1192 * CPUID function 4 expects %ecx to be initialized 1193 * with an index which indicates which cache to return 1194 * information about. The OS is expected to call function 4 1195 * with %ecx set to 0, 1, 2, ... until it returns with 1196 * EAX[4:0] set to 0, which indicates there are no more 1197 * caches. 1198 * 1199 * Here, populate cpi_std[4] with the information returned by 1200 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1201 * when dynamic memory allocation becomes available. 1202 * 1203 * Note: we need to explicitly initialize %ecx here, since 1204 * function 4 may have been previously invoked. 1205 */ 1206 if (n == 4) 1207 cp->cp_ecx = 0; 1208 1209 (void) __cpuid_insn(cp); 1210 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1211 switch (n) { 1212 case 2: 1213 /* 1214 * "the lower 8 bits of the %eax register 1215 * contain a value that identifies the number 1216 * of times the cpuid [instruction] has to be 1217 * executed to obtain a complete image of the 1218 * processor's caching systems." 1219 * 1220 * How *do* they make this stuff up? 1221 */ 1222 cpi->cpi_ncache = sizeof (*cp) * 1223 BITX(cp->cp_eax, 7, 0); 1224 if (cpi->cpi_ncache == 0) 1225 break; 1226 cpi->cpi_ncache--; /* skip count byte */ 1227 1228 /* 1229 * Well, for now, rather than attempt to implement 1230 * this slightly dubious algorithm, we just look 1231 * at the first 15 .. 1232 */ 1233 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1234 cpi->cpi_ncache = sizeof (*cp) - 1; 1235 1236 dp = cpi->cpi_cacheinfo; 1237 if (BITX(cp->cp_eax, 31, 31) == 0) { 1238 uint8_t *p = (void *)&cp->cp_eax; 1239 for (i = 1; i < 4; i++) 1240 if (p[i] != 0) 1241 *dp++ = p[i]; 1242 } 1243 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1244 uint8_t *p = (void *)&cp->cp_ebx; 1245 for (i = 0; i < 4; i++) 1246 if (p[i] != 0) 1247 *dp++ = p[i]; 1248 } 1249 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1250 uint8_t *p = (void *)&cp->cp_ecx; 1251 for (i = 0; i < 4; i++) 1252 if (p[i] != 0) 1253 *dp++ = p[i]; 1254 } 1255 if (BITX(cp->cp_edx, 31, 31) == 0) { 1256 uint8_t *p = (void *)&cp->cp_edx; 1257 for (i = 0; i < 4; i++) 1258 if (p[i] != 0) 1259 *dp++ = p[i]; 1260 } 1261 break; 1262 1263 case 3: /* Processor serial number, if PSN supported */ 1264 break; 1265 1266 case 4: /* Deterministic cache parameters */ 1267 break; 1268 1269 case 5: /* Monitor/Mwait parameters */ 1270 { 1271 size_t mwait_size; 1272 1273 /* 1274 * check cpi_mwait.support which was set in cpuid_pass1 1275 */ 1276 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1277 break; 1278 1279 /* 1280 * Protect ourself from insane mwait line size. 1281 * Workaround for incomplete hardware emulator(s). 1282 */ 1283 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); 1284 if (mwait_size < sizeof (uint32_t) || 1285 !ISP2(mwait_size)) { 1286 #if DEBUG 1287 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " 1288 "size %ld", 1289 cpu->cpu_id, (long)mwait_size); 1290 #endif 1291 break; 1292 } 1293 1294 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1295 cpi->cpi_mwait.mon_max = mwait_size; 1296 if (MWAIT_EXTENSION(cpi)) { 1297 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1298 if (MWAIT_INT_ENABLE(cpi)) 1299 cpi->cpi_mwait.support |= 1300 MWAIT_ECX_INT_ENABLE; 1301 } 1302 break; 1303 } 1304 default: 1305 break; 1306 } 1307 } 1308 1309 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) { 1310 cp->cp_eax = 0xB; 1311 cp->cp_ecx = 0; 1312 1313 (void) __cpuid_insn(cp); 1314 1315 /* 1316 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which 1317 * indicates that the extended topology enumeration leaf is 1318 * available. 1319 */ 1320 if (cp->cp_ebx) { 1321 uint32_t x2apic_id; 1322 uint_t coreid_shift = 0; 1323 uint_t ncpu_per_core = 1; 1324 uint_t chipid_shift = 0; 1325 uint_t ncpu_per_chip = 1; 1326 uint_t i; 1327 uint_t level; 1328 1329 for (i = 0; i < CPI_FNB_ECX_MAX; i++) { 1330 cp->cp_eax = 0xB; 1331 cp->cp_ecx = i; 1332 1333 (void) __cpuid_insn(cp); 1334 level = CPI_CPU_LEVEL_TYPE(cp); 1335 1336 if (level == 1) { 1337 x2apic_id = cp->cp_edx; 1338 coreid_shift = BITX(cp->cp_eax, 4, 0); 1339 ncpu_per_core = BITX(cp->cp_ebx, 15, 0); 1340 } else if (level == 2) { 1341 x2apic_id = cp->cp_edx; 1342 chipid_shift = BITX(cp->cp_eax, 4, 0); 1343 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0); 1344 } 1345 } 1346 1347 cpi->cpi_apicid = x2apic_id; 1348 cpi->cpi_ncpu_per_chip = ncpu_per_chip; 1349 cpi->cpi_ncore_per_chip = ncpu_per_chip / 1350 ncpu_per_core; 1351 cpi->cpi_chipid = x2apic_id >> chipid_shift; 1352 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1); 1353 cpi->cpi_coreid = x2apic_id >> coreid_shift; 1354 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; 1355 } 1356 } 1357 1358 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 1359 goto pass2_done; 1360 1361 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 1362 nmax = NMAX_CPI_EXTD; 1363 /* 1364 * Copy the extended properties, fixing them as we go. 1365 * (We already handled n == 0 and n == 1 in pass 1) 1366 */ 1367 iptr = (void *)cpi->cpi_brandstr; 1368 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 1369 cp->cp_eax = 0x80000000 + n; 1370 (void) __cpuid_insn(cp); 1371 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 1372 switch (n) { 1373 case 2: 1374 case 3: 1375 case 4: 1376 /* 1377 * Extract the brand string 1378 */ 1379 *iptr++ = cp->cp_eax; 1380 *iptr++ = cp->cp_ebx; 1381 *iptr++ = cp->cp_ecx; 1382 *iptr++ = cp->cp_edx; 1383 break; 1384 case 5: 1385 switch (cpi->cpi_vendor) { 1386 case X86_VENDOR_AMD: 1387 /* 1388 * The Athlon and Duron were the first 1389 * parts to report the sizes of the 1390 * TLB for large pages. Before then, 1391 * we don't trust the data. 1392 */ 1393 if (cpi->cpi_family < 6 || 1394 (cpi->cpi_family == 6 && 1395 cpi->cpi_model < 1)) 1396 cp->cp_eax = 0; 1397 break; 1398 default: 1399 break; 1400 } 1401 break; 1402 case 6: 1403 switch (cpi->cpi_vendor) { 1404 case X86_VENDOR_AMD: 1405 /* 1406 * The Athlon and Duron were the first 1407 * AMD parts with L2 TLB's. 1408 * Before then, don't trust the data. 1409 */ 1410 if (cpi->cpi_family < 6 || 1411 cpi->cpi_family == 6 && 1412 cpi->cpi_model < 1) 1413 cp->cp_eax = cp->cp_ebx = 0; 1414 /* 1415 * AMD Duron rev A0 reports L2 1416 * cache size incorrectly as 1K 1417 * when it is really 64K 1418 */ 1419 if (cpi->cpi_family == 6 && 1420 cpi->cpi_model == 3 && 1421 cpi->cpi_step == 0) { 1422 cp->cp_ecx &= 0xffff; 1423 cp->cp_ecx |= 0x400000; 1424 } 1425 break; 1426 case X86_VENDOR_Cyrix: /* VIA C3 */ 1427 /* 1428 * VIA C3 processors are a bit messed 1429 * up w.r.t. encoding cache sizes in %ecx 1430 */ 1431 if (cpi->cpi_family != 6) 1432 break; 1433 /* 1434 * model 7 and 8 were incorrectly encoded 1435 * 1436 * xxx is model 8 really broken? 1437 */ 1438 if (cpi->cpi_model == 7 || 1439 cpi->cpi_model == 8) 1440 cp->cp_ecx = 1441 BITX(cp->cp_ecx, 31, 24) << 16 | 1442 BITX(cp->cp_ecx, 23, 16) << 12 | 1443 BITX(cp->cp_ecx, 15, 8) << 8 | 1444 BITX(cp->cp_ecx, 7, 0); 1445 /* 1446 * model 9 stepping 1 has wrong associativity 1447 */ 1448 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 1449 cp->cp_ecx |= 8 << 12; 1450 break; 1451 case X86_VENDOR_Intel: 1452 /* 1453 * Extended L2 Cache features function. 1454 * First appeared on Prescott. 1455 */ 1456 default: 1457 break; 1458 } 1459 break; 1460 default: 1461 break; 1462 } 1463 } 1464 1465 pass2_done: 1466 cpi->cpi_pass = 2; 1467 } 1468 1469 static const char * 1470 intel_cpubrand(const struct cpuid_info *cpi) 1471 { 1472 int i; 1473 1474 if ((x86_feature & X86_CPUID) == 0 || 1475 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1476 return ("i486"); 1477 1478 switch (cpi->cpi_family) { 1479 case 5: 1480 return ("Intel Pentium(r)"); 1481 case 6: 1482 switch (cpi->cpi_model) { 1483 uint_t celeron, xeon; 1484 const struct cpuid_regs *cp; 1485 case 0: 1486 case 1: 1487 case 2: 1488 return ("Intel Pentium(r) Pro"); 1489 case 3: 1490 case 4: 1491 return ("Intel Pentium(r) II"); 1492 case 6: 1493 return ("Intel Celeron(r)"); 1494 case 5: 1495 case 7: 1496 celeron = xeon = 0; 1497 cp = &cpi->cpi_std[2]; /* cache info */ 1498 1499 for (i = 1; i < 4; i++) { 1500 uint_t tmp; 1501 1502 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1503 if (tmp == 0x40) 1504 celeron++; 1505 if (tmp >= 0x44 && tmp <= 0x45) 1506 xeon++; 1507 } 1508 1509 for (i = 0; i < 2; i++) { 1510 uint_t tmp; 1511 1512 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1513 if (tmp == 0x40) 1514 celeron++; 1515 else if (tmp >= 0x44 && tmp <= 0x45) 1516 xeon++; 1517 } 1518 1519 for (i = 0; i < 4; i++) { 1520 uint_t tmp; 1521 1522 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1523 if (tmp == 0x40) 1524 celeron++; 1525 else if (tmp >= 0x44 && tmp <= 0x45) 1526 xeon++; 1527 } 1528 1529 for (i = 0; i < 4; i++) { 1530 uint_t tmp; 1531 1532 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1533 if (tmp == 0x40) 1534 celeron++; 1535 else if (tmp >= 0x44 && tmp <= 0x45) 1536 xeon++; 1537 } 1538 1539 if (celeron) 1540 return ("Intel Celeron(r)"); 1541 if (xeon) 1542 return (cpi->cpi_model == 5 ? 1543 "Intel Pentium(r) II Xeon(tm)" : 1544 "Intel Pentium(r) III Xeon(tm)"); 1545 return (cpi->cpi_model == 5 ? 1546 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1547 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1548 default: 1549 break; 1550 } 1551 default: 1552 break; 1553 } 1554 1555 /* BrandID is present if the field is nonzero */ 1556 if (cpi->cpi_brandid != 0) { 1557 static const struct { 1558 uint_t bt_bid; 1559 const char *bt_str; 1560 } brand_tbl[] = { 1561 { 0x1, "Intel(r) Celeron(r)" }, 1562 { 0x2, "Intel(r) Pentium(r) III" }, 1563 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1564 { 0x4, "Intel(r) Pentium(r) III" }, 1565 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1566 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1567 { 0x8, "Intel(r) Pentium(r) 4" }, 1568 { 0x9, "Intel(r) Pentium(r) 4" }, 1569 { 0xa, "Intel(r) Celeron(r)" }, 1570 { 0xb, "Intel(r) Xeon(tm)" }, 1571 { 0xc, "Intel(r) Xeon(tm) MP" }, 1572 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1573 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1574 { 0x11, "Mobile Genuine Intel(r)" }, 1575 { 0x12, "Intel(r) Celeron(r) M" }, 1576 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1577 { 0x14, "Intel(r) Celeron(r)" }, 1578 { 0x15, "Mobile Genuine Intel(r)" }, 1579 { 0x16, "Intel(r) Pentium(r) M" }, 1580 { 0x17, "Mobile Intel(r) Celeron(r)" } 1581 }; 1582 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1583 uint_t sgn; 1584 1585 sgn = (cpi->cpi_family << 8) | 1586 (cpi->cpi_model << 4) | cpi->cpi_step; 1587 1588 for (i = 0; i < btblmax; i++) 1589 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1590 break; 1591 if (i < btblmax) { 1592 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1593 return ("Intel(r) Celeron(r)"); 1594 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1595 return ("Intel(r) Xeon(tm) MP"); 1596 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1597 return ("Intel(r) Xeon(tm)"); 1598 return (brand_tbl[i].bt_str); 1599 } 1600 } 1601 1602 return (NULL); 1603 } 1604 1605 static const char * 1606 amd_cpubrand(const struct cpuid_info *cpi) 1607 { 1608 if ((x86_feature & X86_CPUID) == 0 || 1609 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1610 return ("i486 compatible"); 1611 1612 switch (cpi->cpi_family) { 1613 case 5: 1614 switch (cpi->cpi_model) { 1615 case 0: 1616 case 1: 1617 case 2: 1618 case 3: 1619 case 4: 1620 case 5: 1621 return ("AMD-K5(r)"); 1622 case 6: 1623 case 7: 1624 return ("AMD-K6(r)"); 1625 case 8: 1626 return ("AMD-K6(r)-2"); 1627 case 9: 1628 return ("AMD-K6(r)-III"); 1629 default: 1630 return ("AMD (family 5)"); 1631 } 1632 case 6: 1633 switch (cpi->cpi_model) { 1634 case 1: 1635 return ("AMD-K7(tm)"); 1636 case 0: 1637 case 2: 1638 case 4: 1639 return ("AMD Athlon(tm)"); 1640 case 3: 1641 case 7: 1642 return ("AMD Duron(tm)"); 1643 case 6: 1644 case 8: 1645 case 10: 1646 /* 1647 * Use the L2 cache size to distinguish 1648 */ 1649 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1650 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1651 default: 1652 return ("AMD (family 6)"); 1653 } 1654 default: 1655 break; 1656 } 1657 1658 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1659 cpi->cpi_brandid != 0) { 1660 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1661 case 3: 1662 return ("AMD Opteron(tm) UP 1xx"); 1663 case 4: 1664 return ("AMD Opteron(tm) DP 2xx"); 1665 case 5: 1666 return ("AMD Opteron(tm) MP 8xx"); 1667 default: 1668 return ("AMD Opteron(tm)"); 1669 } 1670 } 1671 1672 return (NULL); 1673 } 1674 1675 static const char * 1676 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1677 { 1678 if ((x86_feature & X86_CPUID) == 0 || 1679 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1680 type == X86_TYPE_CYRIX_486) 1681 return ("i486 compatible"); 1682 1683 switch (type) { 1684 case X86_TYPE_CYRIX_6x86: 1685 return ("Cyrix 6x86"); 1686 case X86_TYPE_CYRIX_6x86L: 1687 return ("Cyrix 6x86L"); 1688 case X86_TYPE_CYRIX_6x86MX: 1689 return ("Cyrix 6x86MX"); 1690 case X86_TYPE_CYRIX_GXm: 1691 return ("Cyrix GXm"); 1692 case X86_TYPE_CYRIX_MediaGX: 1693 return ("Cyrix MediaGX"); 1694 case X86_TYPE_CYRIX_MII: 1695 return ("Cyrix M2"); 1696 case X86_TYPE_VIA_CYRIX_III: 1697 return ("VIA Cyrix M3"); 1698 default: 1699 /* 1700 * Have another wild guess .. 1701 */ 1702 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1703 return ("Cyrix 5x86"); 1704 else if (cpi->cpi_family == 5) { 1705 switch (cpi->cpi_model) { 1706 case 2: 1707 return ("Cyrix 6x86"); /* Cyrix M1 */ 1708 case 4: 1709 return ("Cyrix MediaGX"); 1710 default: 1711 break; 1712 } 1713 } else if (cpi->cpi_family == 6) { 1714 switch (cpi->cpi_model) { 1715 case 0: 1716 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1717 case 5: 1718 case 6: 1719 case 7: 1720 case 8: 1721 case 9: 1722 return ("VIA C3"); 1723 default: 1724 break; 1725 } 1726 } 1727 break; 1728 } 1729 return (NULL); 1730 } 1731 1732 /* 1733 * This only gets called in the case that the CPU extended 1734 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1735 * aren't available, or contain null bytes for some reason. 1736 */ 1737 static void 1738 fabricate_brandstr(struct cpuid_info *cpi) 1739 { 1740 const char *brand = NULL; 1741 1742 switch (cpi->cpi_vendor) { 1743 case X86_VENDOR_Intel: 1744 brand = intel_cpubrand(cpi); 1745 break; 1746 case X86_VENDOR_AMD: 1747 brand = amd_cpubrand(cpi); 1748 break; 1749 case X86_VENDOR_Cyrix: 1750 brand = cyrix_cpubrand(cpi, x86_type); 1751 break; 1752 case X86_VENDOR_NexGen: 1753 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1754 brand = "NexGen Nx586"; 1755 break; 1756 case X86_VENDOR_Centaur: 1757 if (cpi->cpi_family == 5) 1758 switch (cpi->cpi_model) { 1759 case 4: 1760 brand = "Centaur C6"; 1761 break; 1762 case 8: 1763 brand = "Centaur C2"; 1764 break; 1765 case 9: 1766 brand = "Centaur C3"; 1767 break; 1768 default: 1769 break; 1770 } 1771 break; 1772 case X86_VENDOR_Rise: 1773 if (cpi->cpi_family == 5 && 1774 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1775 brand = "Rise mP6"; 1776 break; 1777 case X86_VENDOR_SiS: 1778 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1779 brand = "SiS 55x"; 1780 break; 1781 case X86_VENDOR_TM: 1782 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1783 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1784 break; 1785 case X86_VENDOR_NSC: 1786 case X86_VENDOR_UMC: 1787 default: 1788 break; 1789 } 1790 if (brand) { 1791 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1792 return; 1793 } 1794 1795 /* 1796 * If all else fails ... 1797 */ 1798 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1799 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1800 cpi->cpi_model, cpi->cpi_step); 1801 } 1802 1803 /* 1804 * This routine is called just after kernel memory allocation 1805 * becomes available on cpu0, and as part of mp_startup() on 1806 * the other cpus. 1807 * 1808 * Fixup the brand string, and collect any information from cpuid 1809 * that requires dynamicically allocated storage to represent. 1810 */ 1811 /*ARGSUSED*/ 1812 void 1813 cpuid_pass3(cpu_t *cpu) 1814 { 1815 int i, max, shft, level, size; 1816 struct cpuid_regs regs; 1817 struct cpuid_regs *cp; 1818 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1819 1820 ASSERT(cpi->cpi_pass == 2); 1821 1822 /* 1823 * Function 4: Deterministic cache parameters 1824 * 1825 * Take this opportunity to detect the number of threads 1826 * sharing the last level cache, and construct a corresponding 1827 * cache id. The respective cpuid_info members are initialized 1828 * to the default case of "no last level cache sharing". 1829 */ 1830 cpi->cpi_ncpu_shr_last_cache = 1; 1831 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 1832 1833 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 1834 1835 /* 1836 * Find the # of elements (size) returned by fn 4, and along 1837 * the way detect last level cache sharing details. 1838 */ 1839 bzero(®s, sizeof (regs)); 1840 cp = ®s; 1841 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 1842 cp->cp_eax = 4; 1843 cp->cp_ecx = i; 1844 1845 (void) __cpuid_insn(cp); 1846 1847 if (CPI_CACHE_TYPE(cp) == 0) 1848 break; 1849 level = CPI_CACHE_LVL(cp); 1850 if (level > max) { 1851 max = level; 1852 cpi->cpi_ncpu_shr_last_cache = 1853 CPI_NTHR_SHR_CACHE(cp) + 1; 1854 } 1855 } 1856 cpi->cpi_std_4_size = size = i; 1857 1858 /* 1859 * Allocate the cpi_std_4 array. The first element 1860 * references the regs for fn 4, %ecx == 0, which 1861 * cpuid_pass2() stashed in cpi->cpi_std[4]. 1862 */ 1863 if (size > 0) { 1864 cpi->cpi_std_4 = 1865 kmem_alloc(size * sizeof (cp), KM_SLEEP); 1866 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 1867 1868 /* 1869 * Allocate storage to hold the additional regs 1870 * for function 4, %ecx == 1 .. cpi_std_4_size. 1871 * 1872 * The regs for fn 4, %ecx == 0 has already 1873 * been allocated as indicated above. 1874 */ 1875 for (i = 1; i < size; i++) { 1876 cp = cpi->cpi_std_4[i] = 1877 kmem_zalloc(sizeof (regs), KM_SLEEP); 1878 cp->cp_eax = 4; 1879 cp->cp_ecx = i; 1880 1881 (void) __cpuid_insn(cp); 1882 } 1883 } 1884 /* 1885 * Determine the number of bits needed to represent 1886 * the number of CPUs sharing the last level cache. 1887 * 1888 * Shift off that number of bits from the APIC id to 1889 * derive the cache id. 1890 */ 1891 shft = 0; 1892 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 1893 shft++; 1894 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft; 1895 } 1896 1897 /* 1898 * Now fixup the brand string 1899 */ 1900 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1901 fabricate_brandstr(cpi); 1902 } else { 1903 1904 /* 1905 * If we successfully extracted a brand string from the cpuid 1906 * instruction, clean it up by removing leading spaces and 1907 * similar junk. 1908 */ 1909 if (cpi->cpi_brandstr[0]) { 1910 size_t maxlen = sizeof (cpi->cpi_brandstr); 1911 char *src, *dst; 1912 1913 dst = src = (char *)cpi->cpi_brandstr; 1914 src[maxlen - 1] = '\0'; 1915 /* 1916 * strip leading spaces 1917 */ 1918 while (*src == ' ') 1919 src++; 1920 /* 1921 * Remove any 'Genuine' or "Authentic" prefixes 1922 */ 1923 if (strncmp(src, "Genuine ", 8) == 0) 1924 src += 8; 1925 if (strncmp(src, "Authentic ", 10) == 0) 1926 src += 10; 1927 1928 /* 1929 * Now do an in-place copy. 1930 * Map (R) to (r) and (TM) to (tm). 1931 * The era of teletypes is long gone, and there's 1932 * -really- no need to shout. 1933 */ 1934 while (*src != '\0') { 1935 if (src[0] == '(') { 1936 if (strncmp(src + 1, "R)", 2) == 0) { 1937 (void) strncpy(dst, "(r)", 3); 1938 src += 3; 1939 dst += 3; 1940 continue; 1941 } 1942 if (strncmp(src + 1, "TM)", 3) == 0) { 1943 (void) strncpy(dst, "(tm)", 4); 1944 src += 4; 1945 dst += 4; 1946 continue; 1947 } 1948 } 1949 *dst++ = *src++; 1950 } 1951 *dst = '\0'; 1952 1953 /* 1954 * Finally, remove any trailing spaces 1955 */ 1956 while (--dst > cpi->cpi_brandstr) 1957 if (*dst == ' ') 1958 *dst = '\0'; 1959 else 1960 break; 1961 } else 1962 fabricate_brandstr(cpi); 1963 } 1964 cpi->cpi_pass = 3; 1965 } 1966 1967 /* 1968 * This routine is called out of bind_hwcap() much later in the life 1969 * of the kernel (post_startup()). The job of this routine is to resolve 1970 * the hardware feature support and kernel support for those features into 1971 * what we're actually going to tell applications via the aux vector. 1972 */ 1973 uint_t 1974 cpuid_pass4(cpu_t *cpu) 1975 { 1976 struct cpuid_info *cpi; 1977 uint_t hwcap_flags = 0; 1978 1979 if (cpu == NULL) 1980 cpu = CPU; 1981 cpi = cpu->cpu_m.mcpu_cpi; 1982 1983 ASSERT(cpi->cpi_pass == 3); 1984 1985 if (cpi->cpi_maxeax >= 1) { 1986 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 1987 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 1988 1989 *edx = CPI_FEATURES_EDX(cpi); 1990 *ecx = CPI_FEATURES_ECX(cpi); 1991 1992 /* 1993 * [these require explicit kernel support] 1994 */ 1995 if ((x86_feature & X86_SEP) == 0) 1996 *edx &= ~CPUID_INTC_EDX_SEP; 1997 1998 if ((x86_feature & X86_SSE) == 0) 1999 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 2000 if ((x86_feature & X86_SSE2) == 0) 2001 *edx &= ~CPUID_INTC_EDX_SSE2; 2002 2003 if ((x86_feature & X86_HTT) == 0) 2004 *edx &= ~CPUID_INTC_EDX_HTT; 2005 2006 if ((x86_feature & X86_SSE3) == 0) 2007 *ecx &= ~CPUID_INTC_ECX_SSE3; 2008 2009 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2010 if ((x86_feature & X86_SSSE3) == 0) 2011 *ecx &= ~CPUID_INTC_ECX_SSSE3; 2012 if ((x86_feature & X86_SSE4_1) == 0) 2013 *ecx &= ~CPUID_INTC_ECX_SSE4_1; 2014 if ((x86_feature & X86_SSE4_2) == 0) 2015 *ecx &= ~CPUID_INTC_ECX_SSE4_2; 2016 } 2017 2018 /* 2019 * [no explicit support required beyond x87 fp context] 2020 */ 2021 if (!fpu_exists) 2022 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 2023 2024 /* 2025 * Now map the supported feature vector to things that we 2026 * think userland will care about. 2027 */ 2028 if (*edx & CPUID_INTC_EDX_SEP) 2029 hwcap_flags |= AV_386_SEP; 2030 if (*edx & CPUID_INTC_EDX_SSE) 2031 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 2032 if (*edx & CPUID_INTC_EDX_SSE2) 2033 hwcap_flags |= AV_386_SSE2; 2034 if (*ecx & CPUID_INTC_ECX_SSE3) 2035 hwcap_flags |= AV_386_SSE3; 2036 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2037 if (*ecx & CPUID_INTC_ECX_SSSE3) 2038 hwcap_flags |= AV_386_SSSE3; 2039 if (*ecx & CPUID_INTC_ECX_SSE4_1) 2040 hwcap_flags |= AV_386_SSE4_1; 2041 if (*ecx & CPUID_INTC_ECX_SSE4_2) 2042 hwcap_flags |= AV_386_SSE4_2; 2043 } 2044 if (*ecx & CPUID_INTC_ECX_POPCNT) 2045 hwcap_flags |= AV_386_POPCNT; 2046 if (*edx & CPUID_INTC_EDX_FPU) 2047 hwcap_flags |= AV_386_FPU; 2048 if (*edx & CPUID_INTC_EDX_MMX) 2049 hwcap_flags |= AV_386_MMX; 2050 2051 if (*edx & CPUID_INTC_EDX_TSC) 2052 hwcap_flags |= AV_386_TSC; 2053 if (*edx & CPUID_INTC_EDX_CX8) 2054 hwcap_flags |= AV_386_CX8; 2055 if (*edx & CPUID_INTC_EDX_CMOV) 2056 hwcap_flags |= AV_386_CMOV; 2057 if (*ecx & CPUID_INTC_ECX_MON) 2058 hwcap_flags |= AV_386_MON; 2059 if (*ecx & CPUID_INTC_ECX_CX16) 2060 hwcap_flags |= AV_386_CX16; 2061 } 2062 2063 if (x86_feature & X86_HTT) 2064 hwcap_flags |= AV_386_PAUSE; 2065 2066 if (cpi->cpi_xmaxeax < 0x80000001) 2067 goto pass4_done; 2068 2069 switch (cpi->cpi_vendor) { 2070 struct cpuid_regs cp; 2071 uint32_t *edx, *ecx; 2072 2073 case X86_VENDOR_Intel: 2074 /* 2075 * Seems like Intel duplicated what we necessary 2076 * here to make the initial crop of 64-bit OS's work. 2077 * Hopefully, those are the only "extended" bits 2078 * they'll add. 2079 */ 2080 /*FALLTHROUGH*/ 2081 2082 case X86_VENDOR_AMD: 2083 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 2084 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 2085 2086 *edx = CPI_FEATURES_XTD_EDX(cpi); 2087 *ecx = CPI_FEATURES_XTD_ECX(cpi); 2088 2089 /* 2090 * [these features require explicit kernel support] 2091 */ 2092 switch (cpi->cpi_vendor) { 2093 case X86_VENDOR_Intel: 2094 if ((x86_feature & X86_TSCP) == 0) 2095 *edx &= ~CPUID_AMD_EDX_TSCP; 2096 break; 2097 2098 case X86_VENDOR_AMD: 2099 if ((x86_feature & X86_TSCP) == 0) 2100 *edx &= ~CPUID_AMD_EDX_TSCP; 2101 if ((x86_feature & X86_SSE4A) == 0) 2102 *ecx &= ~CPUID_AMD_ECX_SSE4A; 2103 break; 2104 2105 default: 2106 break; 2107 } 2108 2109 /* 2110 * [no explicit support required beyond 2111 * x87 fp context and exception handlers] 2112 */ 2113 if (!fpu_exists) 2114 *edx &= ~(CPUID_AMD_EDX_MMXamd | 2115 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 2116 2117 if ((x86_feature & X86_NX) == 0) 2118 *edx &= ~CPUID_AMD_EDX_NX; 2119 #if !defined(__amd64) 2120 *edx &= ~CPUID_AMD_EDX_LM; 2121 #endif 2122 /* 2123 * Now map the supported feature vector to 2124 * things that we think userland will care about. 2125 */ 2126 #if defined(__amd64) 2127 if (*edx & CPUID_AMD_EDX_SYSC) 2128 hwcap_flags |= AV_386_AMD_SYSC; 2129 #endif 2130 if (*edx & CPUID_AMD_EDX_MMXamd) 2131 hwcap_flags |= AV_386_AMD_MMX; 2132 if (*edx & CPUID_AMD_EDX_3DNow) 2133 hwcap_flags |= AV_386_AMD_3DNow; 2134 if (*edx & CPUID_AMD_EDX_3DNowx) 2135 hwcap_flags |= AV_386_AMD_3DNowx; 2136 2137 switch (cpi->cpi_vendor) { 2138 case X86_VENDOR_AMD: 2139 if (*edx & CPUID_AMD_EDX_TSCP) 2140 hwcap_flags |= AV_386_TSCP; 2141 if (*ecx & CPUID_AMD_ECX_AHF64) 2142 hwcap_flags |= AV_386_AHF; 2143 if (*ecx & CPUID_AMD_ECX_SSE4A) 2144 hwcap_flags |= AV_386_AMD_SSE4A; 2145 if (*ecx & CPUID_AMD_ECX_LZCNT) 2146 hwcap_flags |= AV_386_AMD_LZCNT; 2147 break; 2148 2149 case X86_VENDOR_Intel: 2150 if (*edx & CPUID_AMD_EDX_TSCP) 2151 hwcap_flags |= AV_386_TSCP; 2152 /* 2153 * Aarrgh. 2154 * Intel uses a different bit in the same word. 2155 */ 2156 if (*ecx & CPUID_INTC_ECX_AHF64) 2157 hwcap_flags |= AV_386_AHF; 2158 break; 2159 2160 default: 2161 break; 2162 } 2163 break; 2164 2165 case X86_VENDOR_TM: 2166 cp.cp_eax = 0x80860001; 2167 (void) __cpuid_insn(&cp); 2168 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 2169 break; 2170 2171 default: 2172 break; 2173 } 2174 2175 pass4_done: 2176 cpi->cpi_pass = 4; 2177 return (hwcap_flags); 2178 } 2179 2180 2181 /* 2182 * Simulate the cpuid instruction using the data we previously 2183 * captured about this CPU. We try our best to return the truth 2184 * about the hardware, independently of kernel support. 2185 */ 2186 uint32_t 2187 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 2188 { 2189 struct cpuid_info *cpi; 2190 struct cpuid_regs *xcp; 2191 2192 if (cpu == NULL) 2193 cpu = CPU; 2194 cpi = cpu->cpu_m.mcpu_cpi; 2195 2196 ASSERT(cpuid_checkpass(cpu, 3)); 2197 2198 /* 2199 * CPUID data is cached in two separate places: cpi_std for standard 2200 * CPUID functions, and cpi_extd for extended CPUID functions. 2201 */ 2202 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 2203 xcp = &cpi->cpi_std[cp->cp_eax]; 2204 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 2205 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 2206 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 2207 else 2208 /* 2209 * The caller is asking for data from an input parameter which 2210 * the kernel has not cached. In this case we go fetch from 2211 * the hardware and return the data directly to the user. 2212 */ 2213 return (__cpuid_insn(cp)); 2214 2215 cp->cp_eax = xcp->cp_eax; 2216 cp->cp_ebx = xcp->cp_ebx; 2217 cp->cp_ecx = xcp->cp_ecx; 2218 cp->cp_edx = xcp->cp_edx; 2219 return (cp->cp_eax); 2220 } 2221 2222 int 2223 cpuid_checkpass(cpu_t *cpu, int pass) 2224 { 2225 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 2226 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 2227 } 2228 2229 int 2230 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 2231 { 2232 ASSERT(cpuid_checkpass(cpu, 3)); 2233 2234 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 2235 } 2236 2237 int 2238 cpuid_is_cmt(cpu_t *cpu) 2239 { 2240 if (cpu == NULL) 2241 cpu = CPU; 2242 2243 ASSERT(cpuid_checkpass(cpu, 1)); 2244 2245 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 2246 } 2247 2248 /* 2249 * AMD and Intel both implement the 64-bit variant of the syscall 2250 * instruction (syscallq), so if there's -any- support for syscall, 2251 * cpuid currently says "yes, we support this". 2252 * 2253 * However, Intel decided to -not- implement the 32-bit variant of the 2254 * syscall instruction, so we provide a predicate to allow our caller 2255 * to test that subtlety here. 2256 * 2257 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, 2258 * even in the case where the hardware would in fact support it. 2259 */ 2260 /*ARGSUSED*/ 2261 int 2262 cpuid_syscall32_insn(cpu_t *cpu) 2263 { 2264 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 2265 2266 #if !defined(__xpv) 2267 if (cpu == NULL) 2268 cpu = CPU; 2269 2270 /*CSTYLED*/ 2271 { 2272 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2273 2274 if (cpi->cpi_vendor == X86_VENDOR_AMD && 2275 cpi->cpi_xmaxeax >= 0x80000001 && 2276 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 2277 return (1); 2278 } 2279 #endif 2280 return (0); 2281 } 2282 2283 int 2284 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 2285 { 2286 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2287 2288 static const char fmt[] = 2289 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 2290 static const char fmt_ht[] = 2291 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 2292 2293 ASSERT(cpuid_checkpass(cpu, 1)); 2294 2295 if (cpuid_is_cmt(cpu)) 2296 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 2297 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2298 cpi->cpi_family, cpi->cpi_model, 2299 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2300 return (snprintf(s, n, fmt, 2301 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2302 cpi->cpi_family, cpi->cpi_model, 2303 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2304 } 2305 2306 const char * 2307 cpuid_getvendorstr(cpu_t *cpu) 2308 { 2309 ASSERT(cpuid_checkpass(cpu, 1)); 2310 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 2311 } 2312 2313 uint_t 2314 cpuid_getvendor(cpu_t *cpu) 2315 { 2316 ASSERT(cpuid_checkpass(cpu, 1)); 2317 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 2318 } 2319 2320 uint_t 2321 cpuid_getfamily(cpu_t *cpu) 2322 { 2323 ASSERT(cpuid_checkpass(cpu, 1)); 2324 return (cpu->cpu_m.mcpu_cpi->cpi_family); 2325 } 2326 2327 uint_t 2328 cpuid_getmodel(cpu_t *cpu) 2329 { 2330 ASSERT(cpuid_checkpass(cpu, 1)); 2331 return (cpu->cpu_m.mcpu_cpi->cpi_model); 2332 } 2333 2334 uint_t 2335 cpuid_get_ncpu_per_chip(cpu_t *cpu) 2336 { 2337 ASSERT(cpuid_checkpass(cpu, 1)); 2338 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 2339 } 2340 2341 uint_t 2342 cpuid_get_ncore_per_chip(cpu_t *cpu) 2343 { 2344 ASSERT(cpuid_checkpass(cpu, 1)); 2345 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 2346 } 2347 2348 uint_t 2349 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 2350 { 2351 ASSERT(cpuid_checkpass(cpu, 2)); 2352 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 2353 } 2354 2355 id_t 2356 cpuid_get_last_lvl_cacheid(cpu_t *cpu) 2357 { 2358 ASSERT(cpuid_checkpass(cpu, 2)); 2359 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 2360 } 2361 2362 uint_t 2363 cpuid_getstep(cpu_t *cpu) 2364 { 2365 ASSERT(cpuid_checkpass(cpu, 1)); 2366 return (cpu->cpu_m.mcpu_cpi->cpi_step); 2367 } 2368 2369 uint_t 2370 cpuid_getsig(struct cpu *cpu) 2371 { 2372 ASSERT(cpuid_checkpass(cpu, 1)); 2373 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 2374 } 2375 2376 uint32_t 2377 cpuid_getchiprev(struct cpu *cpu) 2378 { 2379 ASSERT(cpuid_checkpass(cpu, 1)); 2380 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 2381 } 2382 2383 const char * 2384 cpuid_getchiprevstr(struct cpu *cpu) 2385 { 2386 ASSERT(cpuid_checkpass(cpu, 1)); 2387 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 2388 } 2389 2390 uint32_t 2391 cpuid_getsockettype(struct cpu *cpu) 2392 { 2393 ASSERT(cpuid_checkpass(cpu, 1)); 2394 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 2395 } 2396 2397 int 2398 cpuid_get_chipid(cpu_t *cpu) 2399 { 2400 ASSERT(cpuid_checkpass(cpu, 1)); 2401 2402 if (cpuid_is_cmt(cpu)) 2403 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 2404 return (cpu->cpu_id); 2405 } 2406 2407 id_t 2408 cpuid_get_coreid(cpu_t *cpu) 2409 { 2410 ASSERT(cpuid_checkpass(cpu, 1)); 2411 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 2412 } 2413 2414 int 2415 cpuid_get_pkgcoreid(cpu_t *cpu) 2416 { 2417 ASSERT(cpuid_checkpass(cpu, 1)); 2418 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid); 2419 } 2420 2421 int 2422 cpuid_get_clogid(cpu_t *cpu) 2423 { 2424 ASSERT(cpuid_checkpass(cpu, 1)); 2425 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 2426 } 2427 2428 void 2429 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 2430 { 2431 struct cpuid_info *cpi; 2432 2433 if (cpu == NULL) 2434 cpu = CPU; 2435 cpi = cpu->cpu_m.mcpu_cpi; 2436 2437 ASSERT(cpuid_checkpass(cpu, 1)); 2438 2439 if (pabits) 2440 *pabits = cpi->cpi_pabits; 2441 if (vabits) 2442 *vabits = cpi->cpi_vabits; 2443 } 2444 2445 /* 2446 * Returns the number of data TLB entries for a corresponding 2447 * pagesize. If it can't be computed, or isn't known, the 2448 * routine returns zero. If you ask about an architecturally 2449 * impossible pagesize, the routine will panic (so that the 2450 * hat implementor knows that things are inconsistent.) 2451 */ 2452 uint_t 2453 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 2454 { 2455 struct cpuid_info *cpi; 2456 uint_t dtlb_nent = 0; 2457 2458 if (cpu == NULL) 2459 cpu = CPU; 2460 cpi = cpu->cpu_m.mcpu_cpi; 2461 2462 ASSERT(cpuid_checkpass(cpu, 1)); 2463 2464 /* 2465 * Check the L2 TLB info 2466 */ 2467 if (cpi->cpi_xmaxeax >= 0x80000006) { 2468 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 2469 2470 switch (pagesize) { 2471 2472 case 4 * 1024: 2473 /* 2474 * All zero in the top 16 bits of the register 2475 * indicates a unified TLB. Size is in low 16 bits. 2476 */ 2477 if ((cp->cp_ebx & 0xffff0000) == 0) 2478 dtlb_nent = cp->cp_ebx & 0x0000ffff; 2479 else 2480 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 2481 break; 2482 2483 case 2 * 1024 * 1024: 2484 if ((cp->cp_eax & 0xffff0000) == 0) 2485 dtlb_nent = cp->cp_eax & 0x0000ffff; 2486 else 2487 dtlb_nent = BITX(cp->cp_eax, 27, 16); 2488 break; 2489 2490 default: 2491 panic("unknown L2 pagesize"); 2492 /*NOTREACHED*/ 2493 } 2494 } 2495 2496 if (dtlb_nent != 0) 2497 return (dtlb_nent); 2498 2499 /* 2500 * No L2 TLB support for this size, try L1. 2501 */ 2502 if (cpi->cpi_xmaxeax >= 0x80000005) { 2503 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 2504 2505 switch (pagesize) { 2506 case 4 * 1024: 2507 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 2508 break; 2509 case 2 * 1024 * 1024: 2510 dtlb_nent = BITX(cp->cp_eax, 23, 16); 2511 break; 2512 default: 2513 panic("unknown L1 d-TLB pagesize"); 2514 /*NOTREACHED*/ 2515 } 2516 } 2517 2518 return (dtlb_nent); 2519 } 2520 2521 /* 2522 * Return 0 if the erratum is not present or not applicable, positive 2523 * if it is, and negative if the status of the erratum is unknown. 2524 * 2525 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 2526 * Processors" #25759, Rev 3.57, August 2005 2527 */ 2528 int 2529 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 2530 { 2531 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2532 uint_t eax; 2533 2534 /* 2535 * Bail out if this CPU isn't an AMD CPU, or if it's 2536 * a legacy (32-bit) AMD CPU. 2537 */ 2538 if (cpi->cpi_vendor != X86_VENDOR_AMD || 2539 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 2540 cpi->cpi_family == 6) 2541 2542 return (0); 2543 2544 eax = cpi->cpi_std[1].cp_eax; 2545 2546 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 2547 #define SH_B3(eax) (eax == 0xf51) 2548 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 2549 2550 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 2551 2552 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 2553 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 2554 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 2555 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 2556 2557 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 2558 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 2559 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 2560 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 2561 2562 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 2563 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 2564 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 2565 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 2566 #define BH_E4(eax) (eax == 0x20fb1) 2567 #define SH_E5(eax) (eax == 0x20f42) 2568 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 2569 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 2570 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 2571 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 2572 DH_E6(eax) || JH_E6(eax)) 2573 2574 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02) 2575 #define DR_B0(eax) (eax == 0x100f20) 2576 #define DR_B1(eax) (eax == 0x100f21) 2577 #define DR_BA(eax) (eax == 0x100f2a) 2578 #define DR_B2(eax) (eax == 0x100f22) 2579 #define DR_B3(eax) (eax == 0x100f23) 2580 #define RB_C0(eax) (eax == 0x100f40) 2581 2582 switch (erratum) { 2583 case 1: 2584 return (cpi->cpi_family < 0x10); 2585 case 51: /* what does the asterisk mean? */ 2586 return (B(eax) || SH_C0(eax) || CG(eax)); 2587 case 52: 2588 return (B(eax)); 2589 case 57: 2590 return (cpi->cpi_family <= 0x11); 2591 case 58: 2592 return (B(eax)); 2593 case 60: 2594 return (cpi->cpi_family <= 0x11); 2595 case 61: 2596 case 62: 2597 case 63: 2598 case 64: 2599 case 65: 2600 case 66: 2601 case 68: 2602 case 69: 2603 case 70: 2604 case 71: 2605 return (B(eax)); 2606 case 72: 2607 return (SH_B0(eax)); 2608 case 74: 2609 return (B(eax)); 2610 case 75: 2611 return (cpi->cpi_family < 0x10); 2612 case 76: 2613 return (B(eax)); 2614 case 77: 2615 return (cpi->cpi_family <= 0x11); 2616 case 78: 2617 return (B(eax) || SH_C0(eax)); 2618 case 79: 2619 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2620 case 80: 2621 case 81: 2622 case 82: 2623 return (B(eax)); 2624 case 83: 2625 return (B(eax) || SH_C0(eax) || CG(eax)); 2626 case 85: 2627 return (cpi->cpi_family < 0x10); 2628 case 86: 2629 return (SH_C0(eax) || CG(eax)); 2630 case 88: 2631 #if !defined(__amd64) 2632 return (0); 2633 #else 2634 return (B(eax) || SH_C0(eax)); 2635 #endif 2636 case 89: 2637 return (cpi->cpi_family < 0x10); 2638 case 90: 2639 return (B(eax) || SH_C0(eax) || CG(eax)); 2640 case 91: 2641 case 92: 2642 return (B(eax) || SH_C0(eax)); 2643 case 93: 2644 return (SH_C0(eax)); 2645 case 94: 2646 return (B(eax) || SH_C0(eax) || CG(eax)); 2647 case 95: 2648 #if !defined(__amd64) 2649 return (0); 2650 #else 2651 return (B(eax) || SH_C0(eax)); 2652 #endif 2653 case 96: 2654 return (B(eax) || SH_C0(eax) || CG(eax)); 2655 case 97: 2656 case 98: 2657 return (SH_C0(eax) || CG(eax)); 2658 case 99: 2659 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2660 case 100: 2661 return (B(eax) || SH_C0(eax)); 2662 case 101: 2663 case 103: 2664 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2665 case 104: 2666 return (SH_C0(eax) || CG(eax) || D0(eax)); 2667 case 105: 2668 case 106: 2669 case 107: 2670 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2671 case 108: 2672 return (DH_CG(eax)); 2673 case 109: 2674 return (SH_C0(eax) || CG(eax) || D0(eax)); 2675 case 110: 2676 return (D0(eax) || EX(eax)); 2677 case 111: 2678 return (CG(eax)); 2679 case 112: 2680 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2681 case 113: 2682 return (eax == 0x20fc0); 2683 case 114: 2684 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2685 case 115: 2686 return (SH_E0(eax) || JH_E1(eax)); 2687 case 116: 2688 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2689 case 117: 2690 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2691 case 118: 2692 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 2693 JH_E6(eax)); 2694 case 121: 2695 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2696 case 122: 2697 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11); 2698 case 123: 2699 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2700 case 131: 2701 return (cpi->cpi_family < 0x10); 2702 case 6336786: 2703 /* 2704 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2705 * if this is a K8 family or newer processor 2706 */ 2707 if (CPI_FAMILY(cpi) == 0xf) { 2708 struct cpuid_regs regs; 2709 regs.cp_eax = 0x80000007; 2710 (void) __cpuid_insn(®s); 2711 return (!(regs.cp_edx & 0x100)); 2712 } 2713 return (0); 2714 case 6323525: 2715 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2716 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2717 2718 case 6671130: 2719 /* 2720 * check for processors (pre-Shanghai) that do not provide 2721 * optimal management of 1gb ptes in its tlb. 2722 */ 2723 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4); 2724 2725 case 298: 2726 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) || 2727 DR_B2(eax) || RB_C0(eax)); 2728 2729 default: 2730 return (-1); 2731 2732 } 2733 } 2734 2735 /* 2736 * Determine if specified erratum is present via OSVW (OS Visible Workaround). 2737 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate. 2738 */ 2739 int 2740 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum) 2741 { 2742 struct cpuid_info *cpi; 2743 uint_t osvwid; 2744 static int osvwfeature = -1; 2745 uint64_t osvwlength; 2746 2747 2748 cpi = cpu->cpu_m.mcpu_cpi; 2749 2750 /* confirm OSVW supported */ 2751 if (osvwfeature == -1) { 2752 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW; 2753 } else { 2754 /* assert that osvw feature setting is consistent on all cpus */ 2755 ASSERT(osvwfeature == 2756 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW)); 2757 } 2758 if (!osvwfeature) 2759 return (-1); 2760 2761 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK; 2762 2763 switch (erratum) { 2764 case 298: /* osvwid is 0 */ 2765 osvwid = 0; 2766 if (osvwlength <= (uint64_t)osvwid) { 2767 /* osvwid 0 is unknown */ 2768 return (-1); 2769 } 2770 2771 /* 2772 * Check the OSVW STATUS MSR to determine the state 2773 * of the erratum where: 2774 * 0 - fixed by HW 2775 * 1 - BIOS has applied the workaround when BIOS 2776 * workaround is available. (Or for other errata, 2777 * OS workaround is required.) 2778 * For a value of 1, caller will confirm that the 2779 * erratum 298 workaround has indeed been applied by BIOS. 2780 * 2781 * A 1 may be set in cpus that have a HW fix 2782 * in a mixed cpu system. Regarding erratum 298: 2783 * In a multiprocessor platform, the workaround above 2784 * should be applied to all processors regardless of 2785 * silicon revision when an affected processor is 2786 * present. 2787 */ 2788 2789 return (rdmsr(MSR_AMD_OSVW_STATUS + 2790 (osvwid / OSVW_ID_CNT_PER_MSR)) & 2791 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR))); 2792 2793 default: 2794 return (-1); 2795 } 2796 } 2797 2798 static const char assoc_str[] = "associativity"; 2799 static const char line_str[] = "line-size"; 2800 static const char size_str[] = "size"; 2801 2802 static void 2803 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2804 uint32_t val) 2805 { 2806 char buf[128]; 2807 2808 /* 2809 * ndi_prop_update_int() is used because it is desirable for 2810 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2811 */ 2812 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2813 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2814 } 2815 2816 /* 2817 * Intel-style cache/tlb description 2818 * 2819 * Standard cpuid level 2 gives a randomly ordered 2820 * selection of tags that index into a table that describes 2821 * cache and tlb properties. 2822 */ 2823 2824 static const char l1_icache_str[] = "l1-icache"; 2825 static const char l1_dcache_str[] = "l1-dcache"; 2826 static const char l2_cache_str[] = "l2-cache"; 2827 static const char l3_cache_str[] = "l3-cache"; 2828 static const char itlb4k_str[] = "itlb-4K"; 2829 static const char dtlb4k_str[] = "dtlb-4K"; 2830 static const char itlb2M_str[] = "itlb-2M"; 2831 static const char itlb4M_str[] = "itlb-4M"; 2832 static const char dtlb4M_str[] = "dtlb-4M"; 2833 static const char dtlb24_str[] = "dtlb0-2M-4M"; 2834 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2835 static const char itlb24_str[] = "itlb-2M-4M"; 2836 static const char dtlb44_str[] = "dtlb-4K-4M"; 2837 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2838 static const char sl2_cache_str[] = "sectored-l2-cache"; 2839 static const char itrace_str[] = "itrace-cache"; 2840 static const char sl3_cache_str[] = "sectored-l3-cache"; 2841 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k"; 2842 2843 static const struct cachetab { 2844 uint8_t ct_code; 2845 uint8_t ct_assoc; 2846 uint16_t ct_line_size; 2847 size_t ct_size; 2848 const char *ct_label; 2849 } intel_ctab[] = { 2850 /* 2851 * maintain descending order! 2852 * 2853 * Codes ignored - Reason 2854 * ---------------------- 2855 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache 2856 * f0H/f1H - Currently we do not interpret prefetch size by design 2857 */ 2858 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str}, 2859 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str}, 2860 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str}, 2861 { 0xde, 12, 64, 6*1024*1024, l3_cache_str}, 2862 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str}, 2863 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str}, 2864 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str}, 2865 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str}, 2866 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str}, 2867 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str}, 2868 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str}, 2869 { 0xd0, 4, 64, 512*1024, l3_cache_str}, 2870 { 0xca, 4, 0, 512, sh_l2_tlb4k_str}, 2871 { 0xc0, 4, 0, 8, dtlb44_str }, 2872 { 0xba, 4, 0, 64, dtlb4k_str }, 2873 { 0xb4, 4, 0, 256, dtlb4k_str }, 2874 { 0xb3, 4, 0, 128, dtlb4k_str }, 2875 { 0xb2, 4, 0, 64, itlb4k_str }, 2876 { 0xb0, 4, 0, 128, itlb4k_str }, 2877 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2878 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2879 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2880 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2881 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2882 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2883 { 0x80, 8, 64, 512*1024, l2_cache_str}, 2884 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2885 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2886 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2887 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2888 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2889 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2890 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2891 { 0x73, 8, 0, 64*1024, itrace_str}, 2892 { 0x72, 8, 0, 32*1024, itrace_str}, 2893 { 0x71, 8, 0, 16*1024, itrace_str}, 2894 { 0x70, 8, 0, 12*1024, itrace_str}, 2895 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2896 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2897 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2898 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2899 { 0x5d, 0, 0, 256, dtlb44_str}, 2900 { 0x5c, 0, 0, 128, dtlb44_str}, 2901 { 0x5b, 0, 0, 64, dtlb44_str}, 2902 { 0x5a, 4, 0, 32, dtlb24_str}, 2903 { 0x59, 0, 0, 16, dtlb4k_str}, 2904 { 0x57, 4, 0, 16, dtlb4k_str}, 2905 { 0x56, 4, 0, 16, dtlb4M_str}, 2906 { 0x55, 0, 0, 7, itlb24_str}, 2907 { 0x52, 0, 0, 256, itlb424_str}, 2908 { 0x51, 0, 0, 128, itlb424_str}, 2909 { 0x50, 0, 0, 64, itlb424_str}, 2910 { 0x4f, 0, 0, 32, itlb4k_str}, 2911 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str}, 2912 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 2913 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 2914 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 2915 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 2916 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 2917 { 0x48, 12, 64, 3*1024*1024, l2_cache_str}, 2918 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 2919 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 2920 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2921 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2922 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2923 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2924 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2925 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 2926 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 2927 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2928 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2929 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 2930 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2931 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2932 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2933 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2934 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2935 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2936 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2937 { 0x0e, 6, 64, 24*1024, l1_dcache_str}, 2938 { 0x0d, 4, 32, 16*1024, l1_dcache_str}, 2939 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2940 { 0x0b, 4, 0, 4, itlb4M_str}, 2941 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2942 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2943 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2944 { 0x05, 4, 0, 32, dtlb4M_str}, 2945 { 0x04, 4, 0, 8, dtlb4M_str}, 2946 { 0x03, 4, 0, 64, dtlb4k_str}, 2947 { 0x02, 4, 0, 2, itlb4M_str}, 2948 { 0x01, 4, 0, 32, itlb4k_str}, 2949 { 0 } 2950 }; 2951 2952 static const struct cachetab cyrix_ctab[] = { 2953 { 0x70, 4, 0, 32, "tlb-4K" }, 2954 { 0x80, 4, 16, 16*1024, "l1-cache" }, 2955 { 0 } 2956 }; 2957 2958 /* 2959 * Search a cache table for a matching entry 2960 */ 2961 static const struct cachetab * 2962 find_cacheent(const struct cachetab *ct, uint_t code) 2963 { 2964 if (code != 0) { 2965 for (; ct->ct_code != 0; ct++) 2966 if (ct->ct_code <= code) 2967 break; 2968 if (ct->ct_code == code) 2969 return (ct); 2970 } 2971 return (NULL); 2972 } 2973 2974 /* 2975 * Populate cachetab entry with L2 or L3 cache-information using 2976 * cpuid function 4. This function is called from intel_walk_cacheinfo() 2977 * when descriptor 0x49 is encountered. It returns 0 if no such cache 2978 * information is found. 2979 */ 2980 static int 2981 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi) 2982 { 2983 uint32_t level, i; 2984 int ret = 0; 2985 2986 for (i = 0; i < cpi->cpi_std_4_size; i++) { 2987 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); 2988 2989 if (level == 2 || level == 3) { 2990 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; 2991 ct->ct_line_size = 2992 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; 2993 ct->ct_size = ct->ct_assoc * 2994 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * 2995 ct->ct_line_size * 2996 (cpi->cpi_std_4[i]->cp_ecx + 1); 2997 2998 if (level == 2) { 2999 ct->ct_label = l2_cache_str; 3000 } else if (level == 3) { 3001 ct->ct_label = l3_cache_str; 3002 } 3003 ret = 1; 3004 } 3005 } 3006 3007 return (ret); 3008 } 3009 3010 /* 3011 * Walk the cacheinfo descriptor, applying 'func' to every valid element 3012 * The walk is terminated if the walker returns non-zero. 3013 */ 3014 static void 3015 intel_walk_cacheinfo(struct cpuid_info *cpi, 3016 void *arg, int (*func)(void *, const struct cachetab *)) 3017 { 3018 const struct cachetab *ct; 3019 struct cachetab des_49_ct, des_b1_ct; 3020 uint8_t *dp; 3021 int i; 3022 3023 if ((dp = cpi->cpi_cacheinfo) == NULL) 3024 return; 3025 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3026 /* 3027 * For overloaded descriptor 0x49 we use cpuid function 4 3028 * if supported by the current processor, to create 3029 * cache information. 3030 * For overloaded descriptor 0xb1 we use X86_PAE flag 3031 * to disambiguate the cache information. 3032 */ 3033 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 && 3034 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) { 3035 ct = &des_49_ct; 3036 } else if (*dp == 0xb1) { 3037 des_b1_ct.ct_code = 0xb1; 3038 des_b1_ct.ct_assoc = 4; 3039 des_b1_ct.ct_line_size = 0; 3040 if (x86_feature & X86_PAE) { 3041 des_b1_ct.ct_size = 8; 3042 des_b1_ct.ct_label = itlb2M_str; 3043 } else { 3044 des_b1_ct.ct_size = 4; 3045 des_b1_ct.ct_label = itlb4M_str; 3046 } 3047 ct = &des_b1_ct; 3048 } else { 3049 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) { 3050 continue; 3051 } 3052 } 3053 3054 if (func(arg, ct) != 0) { 3055 break; 3056 } 3057 } 3058 } 3059 3060 /* 3061 * (Like the Intel one, except for Cyrix CPUs) 3062 */ 3063 static void 3064 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 3065 void *arg, int (*func)(void *, const struct cachetab *)) 3066 { 3067 const struct cachetab *ct; 3068 uint8_t *dp; 3069 int i; 3070 3071 if ((dp = cpi->cpi_cacheinfo) == NULL) 3072 return; 3073 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3074 /* 3075 * Search Cyrix-specific descriptor table first .. 3076 */ 3077 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 3078 if (func(arg, ct) != 0) 3079 break; 3080 continue; 3081 } 3082 /* 3083 * .. else fall back to the Intel one 3084 */ 3085 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 3086 if (func(arg, ct) != 0) 3087 break; 3088 continue; 3089 } 3090 } 3091 } 3092 3093 /* 3094 * A cacheinfo walker that adds associativity, line-size, and size properties 3095 * to the devinfo node it is passed as an argument. 3096 */ 3097 static int 3098 add_cacheent_props(void *arg, const struct cachetab *ct) 3099 { 3100 dev_info_t *devi = arg; 3101 3102 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 3103 if (ct->ct_line_size != 0) 3104 add_cache_prop(devi, ct->ct_label, line_str, 3105 ct->ct_line_size); 3106 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 3107 return (0); 3108 } 3109 3110 3111 static const char fully_assoc[] = "fully-associative?"; 3112 3113 /* 3114 * AMD style cache/tlb description 3115 * 3116 * Extended functions 5 and 6 directly describe properties of 3117 * tlbs and various cache levels. 3118 */ 3119 static void 3120 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3121 { 3122 switch (assoc) { 3123 case 0: /* reserved; ignore */ 3124 break; 3125 default: 3126 add_cache_prop(devi, label, assoc_str, assoc); 3127 break; 3128 case 0xff: 3129 add_cache_prop(devi, label, fully_assoc, 1); 3130 break; 3131 } 3132 } 3133 3134 static void 3135 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3136 { 3137 if (size == 0) 3138 return; 3139 add_cache_prop(devi, label, size_str, size); 3140 add_amd_assoc(devi, label, assoc); 3141 } 3142 3143 static void 3144 add_amd_cache(dev_info_t *devi, const char *label, 3145 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3146 { 3147 if (size == 0 || line_size == 0) 3148 return; 3149 add_amd_assoc(devi, label, assoc); 3150 /* 3151 * Most AMD parts have a sectored cache. Multiple cache lines are 3152 * associated with each tag. A sector consists of all cache lines 3153 * associated with a tag. For example, the AMD K6-III has a sector 3154 * size of 2 cache lines per tag. 3155 */ 3156 if (lines_per_tag != 0) 3157 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3158 add_cache_prop(devi, label, line_str, line_size); 3159 add_cache_prop(devi, label, size_str, size * 1024); 3160 } 3161 3162 static void 3163 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3164 { 3165 switch (assoc) { 3166 case 0: /* off */ 3167 break; 3168 case 1: 3169 case 2: 3170 case 4: 3171 add_cache_prop(devi, label, assoc_str, assoc); 3172 break; 3173 case 6: 3174 add_cache_prop(devi, label, assoc_str, 8); 3175 break; 3176 case 8: 3177 add_cache_prop(devi, label, assoc_str, 16); 3178 break; 3179 case 0xf: 3180 add_cache_prop(devi, label, fully_assoc, 1); 3181 break; 3182 default: /* reserved; ignore */ 3183 break; 3184 } 3185 } 3186 3187 static void 3188 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3189 { 3190 if (size == 0 || assoc == 0) 3191 return; 3192 add_amd_l2_assoc(devi, label, assoc); 3193 add_cache_prop(devi, label, size_str, size); 3194 } 3195 3196 static void 3197 add_amd_l2_cache(dev_info_t *devi, const char *label, 3198 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3199 { 3200 if (size == 0 || assoc == 0 || line_size == 0) 3201 return; 3202 add_amd_l2_assoc(devi, label, assoc); 3203 if (lines_per_tag != 0) 3204 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3205 add_cache_prop(devi, label, line_str, line_size); 3206 add_cache_prop(devi, label, size_str, size * 1024); 3207 } 3208 3209 static void 3210 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 3211 { 3212 struct cpuid_regs *cp; 3213 3214 if (cpi->cpi_xmaxeax < 0x80000005) 3215 return; 3216 cp = &cpi->cpi_extd[5]; 3217 3218 /* 3219 * 4M/2M L1 TLB configuration 3220 * 3221 * We report the size for 2M pages because AMD uses two 3222 * TLB entries for one 4M page. 3223 */ 3224 add_amd_tlb(devi, "dtlb-2M", 3225 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 3226 add_amd_tlb(devi, "itlb-2M", 3227 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 3228 3229 /* 3230 * 4K L1 TLB configuration 3231 */ 3232 3233 switch (cpi->cpi_vendor) { 3234 uint_t nentries; 3235 case X86_VENDOR_TM: 3236 if (cpi->cpi_family >= 5) { 3237 /* 3238 * Crusoe processors have 256 TLB entries, but 3239 * cpuid data format constrains them to only 3240 * reporting 255 of them. 3241 */ 3242 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 3243 nentries = 256; 3244 /* 3245 * Crusoe processors also have a unified TLB 3246 */ 3247 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 3248 nentries); 3249 break; 3250 } 3251 /*FALLTHROUGH*/ 3252 default: 3253 add_amd_tlb(devi, itlb4k_str, 3254 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 3255 add_amd_tlb(devi, dtlb4k_str, 3256 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 3257 break; 3258 } 3259 3260 /* 3261 * data L1 cache configuration 3262 */ 3263 3264 add_amd_cache(devi, l1_dcache_str, 3265 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 3266 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 3267 3268 /* 3269 * code L1 cache configuration 3270 */ 3271 3272 add_amd_cache(devi, l1_icache_str, 3273 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 3274 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 3275 3276 if (cpi->cpi_xmaxeax < 0x80000006) 3277 return; 3278 cp = &cpi->cpi_extd[6]; 3279 3280 /* Check for a unified L2 TLB for large pages */ 3281 3282 if (BITX(cp->cp_eax, 31, 16) == 0) 3283 add_amd_l2_tlb(devi, "l2-tlb-2M", 3284 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3285 else { 3286 add_amd_l2_tlb(devi, "l2-dtlb-2M", 3287 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3288 add_amd_l2_tlb(devi, "l2-itlb-2M", 3289 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3290 } 3291 3292 /* Check for a unified L2 TLB for 4K pages */ 3293 3294 if (BITX(cp->cp_ebx, 31, 16) == 0) { 3295 add_amd_l2_tlb(devi, "l2-tlb-4K", 3296 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3297 } else { 3298 add_amd_l2_tlb(devi, "l2-dtlb-4K", 3299 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3300 add_amd_l2_tlb(devi, "l2-itlb-4K", 3301 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3302 } 3303 3304 add_amd_l2_cache(devi, l2_cache_str, 3305 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 3306 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 3307 } 3308 3309 /* 3310 * There are two basic ways that the x86 world describes it cache 3311 * and tlb architecture - Intel's way and AMD's way. 3312 * 3313 * Return which flavor of cache architecture we should use 3314 */ 3315 static int 3316 x86_which_cacheinfo(struct cpuid_info *cpi) 3317 { 3318 switch (cpi->cpi_vendor) { 3319 case X86_VENDOR_Intel: 3320 if (cpi->cpi_maxeax >= 2) 3321 return (X86_VENDOR_Intel); 3322 break; 3323 case X86_VENDOR_AMD: 3324 /* 3325 * The K5 model 1 was the first part from AMD that reported 3326 * cache sizes via extended cpuid functions. 3327 */ 3328 if (cpi->cpi_family > 5 || 3329 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 3330 return (X86_VENDOR_AMD); 3331 break; 3332 case X86_VENDOR_TM: 3333 if (cpi->cpi_family >= 5) 3334 return (X86_VENDOR_AMD); 3335 /*FALLTHROUGH*/ 3336 default: 3337 /* 3338 * If they have extended CPU data for 0x80000005 3339 * then we assume they have AMD-format cache 3340 * information. 3341 * 3342 * If not, and the vendor happens to be Cyrix, 3343 * then try our-Cyrix specific handler. 3344 * 3345 * If we're not Cyrix, then assume we're using Intel's 3346 * table-driven format instead. 3347 */ 3348 if (cpi->cpi_xmaxeax >= 0x80000005) 3349 return (X86_VENDOR_AMD); 3350 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 3351 return (X86_VENDOR_Cyrix); 3352 else if (cpi->cpi_maxeax >= 2) 3353 return (X86_VENDOR_Intel); 3354 break; 3355 } 3356 return (-1); 3357 } 3358 3359 /* 3360 * create a node for the given cpu under the prom root node. 3361 * Also, create a cpu node in the device tree. 3362 */ 3363 static dev_info_t *cpu_nex_devi = NULL; 3364 static kmutex_t cpu_node_lock; 3365 3366 /* 3367 * Called from post_startup() and mp_startup() 3368 */ 3369 void 3370 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 3371 { 3372 dev_info_t *cpu_devi; 3373 int create; 3374 3375 mutex_enter(&cpu_node_lock); 3376 3377 /* 3378 * create a nexus node for all cpus identified as 'cpu_id' under 3379 * the root node. 3380 */ 3381 if (cpu_nex_devi == NULL) { 3382 if (ndi_devi_alloc(ddi_root_node(), "cpus", 3383 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 3384 mutex_exit(&cpu_node_lock); 3385 return; 3386 } 3387 (void) ndi_devi_online(cpu_nex_devi, 0); 3388 } 3389 3390 /* 3391 * create a child node for cpu identified as 'cpu_id' 3392 */ 3393 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 3394 cpu_id); 3395 if (cpu_devi == NULL) { 3396 mutex_exit(&cpu_node_lock); 3397 return; 3398 } 3399 3400 /* device_type */ 3401 3402 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3403 "device_type", "cpu"); 3404 3405 /* reg */ 3406 3407 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3408 "reg", cpu_id); 3409 3410 /* cpu-mhz, and clock-frequency */ 3411 3412 if (cpu_freq > 0) { 3413 long long mul; 3414 3415 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3416 "cpu-mhz", cpu_freq); 3417 3418 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 3419 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3420 "clock-frequency", (int)mul); 3421 } 3422 3423 (void) ndi_devi_online(cpu_devi, 0); 3424 3425 if ((x86_feature & X86_CPUID) == 0) { 3426 mutex_exit(&cpu_node_lock); 3427 return; 3428 } 3429 3430 /* vendor-id */ 3431 3432 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3433 "vendor-id", cpi->cpi_vendorstr); 3434 3435 if (cpi->cpi_maxeax == 0) { 3436 mutex_exit(&cpu_node_lock); 3437 return; 3438 } 3439 3440 /* 3441 * family, model, and step 3442 */ 3443 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3444 "family", CPI_FAMILY(cpi)); 3445 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3446 "cpu-model", CPI_MODEL(cpi)); 3447 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3448 "stepping-id", CPI_STEP(cpi)); 3449 3450 /* type */ 3451 3452 switch (cpi->cpi_vendor) { 3453 case X86_VENDOR_Intel: 3454 create = 1; 3455 break; 3456 default: 3457 create = 0; 3458 break; 3459 } 3460 if (create) 3461 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3462 "type", CPI_TYPE(cpi)); 3463 3464 /* ext-family */ 3465 3466 switch (cpi->cpi_vendor) { 3467 case X86_VENDOR_Intel: 3468 case X86_VENDOR_AMD: 3469 create = cpi->cpi_family >= 0xf; 3470 break; 3471 default: 3472 create = 0; 3473 break; 3474 } 3475 if (create) 3476 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3477 "ext-family", CPI_FAMILY_XTD(cpi)); 3478 3479 /* ext-model */ 3480 3481 switch (cpi->cpi_vendor) { 3482 case X86_VENDOR_Intel: 3483 create = IS_EXTENDED_MODEL_INTEL(cpi); 3484 break; 3485 case X86_VENDOR_AMD: 3486 create = CPI_FAMILY(cpi) == 0xf; 3487 break; 3488 default: 3489 create = 0; 3490 break; 3491 } 3492 if (create) 3493 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3494 "ext-model", CPI_MODEL_XTD(cpi)); 3495 3496 /* generation */ 3497 3498 switch (cpi->cpi_vendor) { 3499 case X86_VENDOR_AMD: 3500 /* 3501 * AMD K5 model 1 was the first part to support this 3502 */ 3503 create = cpi->cpi_xmaxeax >= 0x80000001; 3504 break; 3505 default: 3506 create = 0; 3507 break; 3508 } 3509 if (create) 3510 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3511 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 3512 3513 /* brand-id */ 3514 3515 switch (cpi->cpi_vendor) { 3516 case X86_VENDOR_Intel: 3517 /* 3518 * brand id first appeared on Pentium III Xeon model 8, 3519 * and Celeron model 8 processors and Opteron 3520 */ 3521 create = cpi->cpi_family > 6 || 3522 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 3523 break; 3524 case X86_VENDOR_AMD: 3525 create = cpi->cpi_family >= 0xf; 3526 break; 3527 default: 3528 create = 0; 3529 break; 3530 } 3531 if (create && cpi->cpi_brandid != 0) { 3532 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3533 "brand-id", cpi->cpi_brandid); 3534 } 3535 3536 /* chunks, and apic-id */ 3537 3538 switch (cpi->cpi_vendor) { 3539 /* 3540 * first available on Pentium IV and Opteron (K8) 3541 */ 3542 case X86_VENDOR_Intel: 3543 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3544 break; 3545 case X86_VENDOR_AMD: 3546 create = cpi->cpi_family >= 0xf; 3547 break; 3548 default: 3549 create = 0; 3550 break; 3551 } 3552 if (create) { 3553 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3554 "chunks", CPI_CHUNKS(cpi)); 3555 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3556 "apic-id", cpi->cpi_apicid); 3557 if (cpi->cpi_chipid >= 0) { 3558 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3559 "chip#", cpi->cpi_chipid); 3560 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3561 "clog#", cpi->cpi_clogid); 3562 } 3563 } 3564 3565 /* cpuid-features */ 3566 3567 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3568 "cpuid-features", CPI_FEATURES_EDX(cpi)); 3569 3570 3571 /* cpuid-features-ecx */ 3572 3573 switch (cpi->cpi_vendor) { 3574 case X86_VENDOR_Intel: 3575 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3576 break; 3577 default: 3578 create = 0; 3579 break; 3580 } 3581 if (create) 3582 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3583 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 3584 3585 /* ext-cpuid-features */ 3586 3587 switch (cpi->cpi_vendor) { 3588 case X86_VENDOR_Intel: 3589 case X86_VENDOR_AMD: 3590 case X86_VENDOR_Cyrix: 3591 case X86_VENDOR_TM: 3592 case X86_VENDOR_Centaur: 3593 create = cpi->cpi_xmaxeax >= 0x80000001; 3594 break; 3595 default: 3596 create = 0; 3597 break; 3598 } 3599 if (create) { 3600 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3601 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 3602 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3603 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 3604 } 3605 3606 /* 3607 * Brand String first appeared in Intel Pentium IV, AMD K5 3608 * model 1, and Cyrix GXm. On earlier models we try and 3609 * simulate something similar .. so this string should always 3610 * same -something- about the processor, however lame. 3611 */ 3612 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3613 "brand-string", cpi->cpi_brandstr); 3614 3615 /* 3616 * Finally, cache and tlb information 3617 */ 3618 switch (x86_which_cacheinfo(cpi)) { 3619 case X86_VENDOR_Intel: 3620 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3621 break; 3622 case X86_VENDOR_Cyrix: 3623 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3624 break; 3625 case X86_VENDOR_AMD: 3626 amd_cache_info(cpi, cpu_devi); 3627 break; 3628 default: 3629 break; 3630 } 3631 3632 mutex_exit(&cpu_node_lock); 3633 } 3634 3635 struct l2info { 3636 int *l2i_csz; 3637 int *l2i_lsz; 3638 int *l2i_assoc; 3639 int l2i_ret; 3640 }; 3641 3642 /* 3643 * A cacheinfo walker that fetches the size, line-size and associativity 3644 * of the L2 cache 3645 */ 3646 static int 3647 intel_l2cinfo(void *arg, const struct cachetab *ct) 3648 { 3649 struct l2info *l2i = arg; 3650 int *ip; 3651 3652 if (ct->ct_label != l2_cache_str && 3653 ct->ct_label != sl2_cache_str) 3654 return (0); /* not an L2 -- keep walking */ 3655 3656 if ((ip = l2i->l2i_csz) != NULL) 3657 *ip = ct->ct_size; 3658 if ((ip = l2i->l2i_lsz) != NULL) 3659 *ip = ct->ct_line_size; 3660 if ((ip = l2i->l2i_assoc) != NULL) 3661 *ip = ct->ct_assoc; 3662 l2i->l2i_ret = ct->ct_size; 3663 return (1); /* was an L2 -- terminate walk */ 3664 } 3665 3666 /* 3667 * AMD L2/L3 Cache and TLB Associativity Field Definition: 3668 * 3669 * Unlike the associativity for the L1 cache and tlb where the 8 bit 3670 * value is the associativity, the associativity for the L2 cache and 3671 * tlb is encoded in the following table. The 4 bit L2 value serves as 3672 * an index into the amd_afd[] array to determine the associativity. 3673 * -1 is undefined. 0 is fully associative. 3674 */ 3675 3676 static int amd_afd[] = 3677 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; 3678 3679 static void 3680 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 3681 { 3682 struct cpuid_regs *cp; 3683 uint_t size, assoc; 3684 int i; 3685 int *ip; 3686 3687 if (cpi->cpi_xmaxeax < 0x80000006) 3688 return; 3689 cp = &cpi->cpi_extd[6]; 3690 3691 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && 3692 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 3693 uint_t cachesz = size * 1024; 3694 assoc = amd_afd[i]; 3695 3696 ASSERT(assoc != -1); 3697 3698 if ((ip = l2i->l2i_csz) != NULL) 3699 *ip = cachesz; 3700 if ((ip = l2i->l2i_lsz) != NULL) 3701 *ip = BITX(cp->cp_ecx, 7, 0); 3702 if ((ip = l2i->l2i_assoc) != NULL) 3703 *ip = assoc; 3704 l2i->l2i_ret = cachesz; 3705 } 3706 } 3707 3708 int 3709 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 3710 { 3711 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3712 struct l2info __l2info, *l2i = &__l2info; 3713 3714 l2i->l2i_csz = csz; 3715 l2i->l2i_lsz = lsz; 3716 l2i->l2i_assoc = assoc; 3717 l2i->l2i_ret = -1; 3718 3719 switch (x86_which_cacheinfo(cpi)) { 3720 case X86_VENDOR_Intel: 3721 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3722 break; 3723 case X86_VENDOR_Cyrix: 3724 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3725 break; 3726 case X86_VENDOR_AMD: 3727 amd_l2cacheinfo(cpi, l2i); 3728 break; 3729 default: 3730 break; 3731 } 3732 return (l2i->l2i_ret); 3733 } 3734 3735 #if !defined(__xpv) 3736 3737 uint32_t * 3738 cpuid_mwait_alloc(cpu_t *cpu) 3739 { 3740 uint32_t *ret; 3741 size_t mwait_size; 3742 3743 ASSERT(cpuid_checkpass(cpu, 2)); 3744 3745 mwait_size = cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max; 3746 if (mwait_size == 0) 3747 return (NULL); 3748 3749 /* 3750 * kmem_alloc() returns cache line size aligned data for mwait_size 3751 * allocations. mwait_size is currently cache line sized. Neither 3752 * of these implementation details are guarantied to be true in the 3753 * future. 3754 * 3755 * First try allocating mwait_size as kmem_alloc() currently returns 3756 * correctly aligned memory. If kmem_alloc() does not return 3757 * mwait_size aligned memory, then use mwait_size ROUNDUP. 3758 * 3759 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we 3760 * decide to free this memory. 3761 */ 3762 ret = kmem_zalloc(mwait_size, KM_SLEEP); 3763 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { 3764 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3765 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; 3766 *ret = MWAIT_RUNNING; 3767 return (ret); 3768 } else { 3769 kmem_free(ret, mwait_size); 3770 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); 3771 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3772 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; 3773 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); 3774 *ret = MWAIT_RUNNING; 3775 return (ret); 3776 } 3777 } 3778 3779 void 3780 cpuid_mwait_free(cpu_t *cpu) 3781 { 3782 ASSERT(cpuid_checkpass(cpu, 2)); 3783 3784 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && 3785 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { 3786 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, 3787 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); 3788 } 3789 3790 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; 3791 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; 3792 } 3793 3794 void 3795 patch_tsc_read(int flag) 3796 { 3797 size_t cnt; 3798 3799 switch (flag) { 3800 case X86_NO_TSC: 3801 cnt = &_no_rdtsc_end - &_no_rdtsc_start; 3802 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt); 3803 break; 3804 case X86_HAVE_TSCP: 3805 cnt = &_tscp_end - &_tscp_start; 3806 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt); 3807 break; 3808 case X86_TSC_MFENCE: 3809 cnt = &_tsc_mfence_end - &_tsc_mfence_start; 3810 (void) memcpy((void *)tsc_read, 3811 (void *)&_tsc_mfence_start, cnt); 3812 break; 3813 case X86_TSC_LFENCE: 3814 cnt = &_tsc_lfence_end - &_tsc_lfence_start; 3815 (void) memcpy((void *)tsc_read, 3816 (void *)&_tsc_lfence_start, cnt); 3817 break; 3818 default: 3819 break; 3820 } 3821 } 3822 3823 #endif /* !__xpv */ 3824